Planarization method of semiconductor structure

Abstract

The invention provides a planarization method of a semiconductor structure. Preliminary leveling can be carried out on the surface undulation, namely the first height difference, of a film layer through a first ion beam etching process. A second ion beam etching process is utilized, and by means of film layers, structures and density differences, new surface undulation differences and height differences are created among different areas of a second semiconductor structure again, namely, more obvious protrusions and recesses are formed on the surface, so that a height difference window is provided for leveling in a global range, and the flatness of the second semiconductor structure is improved. And performing trimming treatment again by using a third ion beam etching process to realize global planarization, namely, considering the flatness of the pattern surface in a local region and the flatness between different regions in a global range, so that the surface of the semiconductor structure has no obvious height difference. Through the ion beam etching technology, the surface difference of the film layers at different positions of the semiconductor structure can be controlled, and the surface fluctuation degree and fluctuation frequency are reduced, so that the height difference of the film layers at different positions is eliminated, and global planarization is realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for planarizing a semiconductor structure. Background Technology

[0002] As the feature size of VLSI manufacturing shrinks and the depth of focus of lithography equipment decreases, the precision requirements for semiconductor surface planarization are constantly increasing (at the nanometer and even molecular level) to meet the requirements of key processes such as repeated lithography, etching, thin film and doping.

[0003] The core requirement of planarization is to achieve global planarization of the semiconductor structure, overcoming material differences, pattern density, and differences between pattern structures at different locations, and ultimately achieving nanoscale planarization of the surface. Currently, chemical mechanical planarization (CMP) is generally used to achieve planarization. However, during the planarization process, the planarization loading effect and dishing effect are still quite significant and cannot be overcome. CMP can only provide planarization and uniformity correction down to a few centimeters, making it extremely difficult to locally distinguish the thickness or morphology between adjacent chips and correct the non-uniformity of all chips on a 300mm wafer to the range of a few nanometers.

[0004] The loading effect refers to the difference in etching rates caused by material differences, pattern density differences, and pattern structure differences at different locations on the same semiconductor structure. This results in height / undulation differences at different locations after planarization, leading to uneven film surfaces during the fabrication process and affecting device performance and stability. The dishing effect, on the other hand, refers to the behavior of central bulges and edge depressions caused by mechanical forces and differences in chemical polishing rates at different locations during CMP, resulting in height differences between the central and edge regions of the semiconductor structure. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a method for planarizing semiconductor structures, improving the surface flatness of semiconductor structures, and achieving global planarization. The specific solution is as follows:

[0006] On the one hand, this application provides a method for planarizing a semiconductor structure, including:

[0007] A first semiconductor structure is provided; the first semiconductor structure includes a substrate, a first film layer located on one side of the substrate, and a second film layer located on the side of the first film layer away from the substrate; the first semiconductor structure includes a first region and a second region arranged along a target direction perpendicular to the direction of the substrate pointing towards the first film layer, and a first height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region;

[0008] The second film layer is planarized using a first ion beam etching process to obtain a second semiconductor structure; in the second semiconductor structure, there is a second height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and the second height difference is smaller than the first height difference.

[0009] The second semiconductor structure is subjected to a second ion beam etching process to perform undulation treatment to obtain a third semiconductor structure; in the third semiconductor structure, there is a third height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and the third height difference is greater than the second height difference.

[0010] The third semiconductor structure is planarized using a third ion beam etching process to obtain a fourth semiconductor structure. The surface flatness of the fourth semiconductor structure meets the flatness requirements. In the fourth semiconductor structure, there is a fourth height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region. The fourth height difference is smaller than the second height difference.

[0011] Optionally, the first film layer and the second film layer are made of the same material;

[0012] or,

[0013] The first membrane layer and the second membrane layer are made of different materials, and the second membrane layer includes at least one sub-membrane layer.

[0014] Optionally, the first height difference is the difference in film growth undulation caused by the difference in pattern density between the first region and the second region.

[0015] Optionally, the patterned structure of the first film layer differs in the first region and the second region, and the patterned structure includes a pin structure, a via structure, or a trench structure.

[0016] Optionally, the number of patterns in the first film layer differs between the first region and the second region.

[0017] Optionally, the first height difference is the difference in film growth undulation caused by the material difference between the first region and the second region.

[0018] Optionally, the first height difference originates from the loading effect during the chemical mechanical polishing process of the first region and the second region.

[0019] Optionally, the first semiconductor structure is a logic device, a memory device, a microelectromechanical system, or an optical device.

[0020] Optionally, in the first ion beam etching process, the incident angle of the first ion beam is greater than or equal to 0° and less than or equal to 80°, wherein the incident angle is the angle between the incident direction of the ion beam and the stacking direction of the first semiconductor structure, and the first etching gas forming the first ion beam includes an inert gas.

[0021] Optionally, in the first semiconductor structure, when the surface undulation of the second film layer is greater than a preset undulation, the incident angle of the first ion beam is greater than or equal to 0° and less than or equal to 60°.

[0022] When the surface undulation of the second film layer is less than or equal to the preset undulation, the incident angle of the first ion beam is greater than or equal to 60° and less than or equal to 80°.

[0023] Optionally, in the second ion beam etching process, the incident angle of the second ion beam is greater than or equal to 0° and less than or equal to 80°, and the etching rate of the second etching gas forming the second ion beam on the second film layer is greater than the etching rate on the first film layer.

[0024] Optionally, in the second ion beam etching process, the undulation is processed through a high-energy inert ion modification path, and the second etching gas includes an inert gas. 13. The method according to claim 12, characterized in that, in the second ion beam etching process, based on the high-energy inert ion modification path, the voltage of the screen gate is greater than or equal to 800V and less than or equal to 1500V, the current of the screen gate is greater than or equal to 0.6A and less than or equal to 1.5A, and the voltage of the accelerating gate is greater than or equal to 400V and less than or equal to 1500V.

[0025] Optionally, in the second ion beam etching process, the undulation is processed through a chemical ion modification path, and the second etching gas includes a reactive gas, which includes at least one of fluorine-based gas and chlorine-based gas.

[0026] Optionally, the fluorine-based gas includes C x F yThe chlorine-based gas includes at least one of NF3, SF6, WF6, CHF3, and CH2F2, and the chlorine-based gas includes at least one of Cl2, BCl3, CCl4, and SiCl4.

[0027] Optionally, in the second ion beam etching process, based on the chemical ion modification path, the voltage of the screen gate is greater than or equal to 200V and less than or equal to 1200V, the current of the screen gate is greater than or equal to 0.1A and less than or equal to 1.2A, and the voltage of the acceleration gate is greater than or equal to 200V and less than or equal to 1200V.

[0028] Optionally, in the third ion beam etching process, the incident angle of the third ion beam is greater than or equal to 60° and less than or equal to 90°, and the third etching gas forming the third ion beam includes an inert gas.

[0029] Optionally, the inert gas used in the ion beam etching process includes at least one of He, Ne, Ar, Kr, and Xe.

[0030] Optionally, in the first ion beam etching process, the voltage of the screen gate is greater than or equal to 200V and less than or equal to 1500V, the current of the screen gate is greater than or equal to 0.1A and less than or equal to 1.5A, and the voltage of the acceleration gate is greater than or equal to 100V and less than or equal to 1500V.

[0031] Optionally, in the third ion beam etching process, the voltage of the screen grid is greater than or equal to 75V and less than or equal to 400V, the current of the screen grid is greater than or equal to 0.1A and less than or equal to 0.5A, and the voltage of the acceleration gate is greater than or equal to 100V and less than or equal to 800V.

[0032] Optionally, in the first ion beam etching process, the second ion beam etching process, or the third ion beam etching process, the cavity pressure is greater than or equal to 0.05 mT and less than or equal to 5 mT.

[0033] This application provides a planarization method for a semiconductor structure, providing a first semiconductor structure. The first semiconductor structure includes a substrate, a first film layer located on one side of the substrate, and a second film layer located on the side of the first film layer away from the substrate. The first semiconductor structure includes a first region and a second region arranged along a target direction, the target direction being perpendicular to the direction from the substrate to the first film layer. A first height difference exists between the surface of the second film layer in the first region and the surface of the second film layer in the second region. The second film layer is planarized using a first ion beam etching process to obtain the second semiconductor structure. In the second semiconductor structure, a second height difference exists between the surface of the second film layer in the first region and the surface of the second film layer in the second region. The second semiconductor structure is subjected to a second ion beam etching process to process its surface relief, resulting in a third semiconductor structure. In the third semiconductor structure, there is a third height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and this third height difference is greater than the second height difference. The third semiconductor structure is then subjected to a third ion beam etching process to process its surface flatness, resulting in a fourth semiconductor structure. The surface flatness of the fourth semiconductor structure meets the flatness requirements. In the fourth semiconductor structure, there is a fourth height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and this fourth height difference is less than the second height difference.

[0034] Therefore, the first ion beam etching process can initially smooth out the surface undulations of the film layer, i.e., the first height difference, achieving preliminary optimization of the loading and dishing effects. Its core principle lies in the difference in etching rates produced by the ion beam on different undulating surfaces; the higher the surface undulation height and frequency, the faster the equivalent etching rate, achieved by leveraging the surface differences in different regions of the film layer. Next, the second ion beam etching process can be used to recreate new surface undulation differences between different regions of the second semiconductor structure, increasing the height difference and forming more pronounced protrusions and depressions on the surface, resulting in a third height difference. This provides a height difference window for further smoothing out the height differences between different regions globally. Then, the third ion beam etching process is used for further smoothing, further optimizing the loading and dishing effects, thereby improving the surface flatness of the semiconductor structure and achieving global flattening. This means considering both the flatness of the patterned surface in local areas and the flatness between different regions globally, resulting in a semiconductor structure surface without significant height differences. In summary, this application utilizes ion beam etching technology to control the surface differences of film layers at different locations in a semiconductor structure, thereby reducing surface undulation and undulation frequency, eliminating height differences between film layers at different locations, and achieving global planarization. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of a typical semiconductor structure in the related technology is shown;

[0037] Figure 2 A schematic flowchart of a semiconductor structure planarization method provided in an embodiment of this application is shown;

[0038] Figure 3 A schematic diagram of a first semiconductor structure provided in an embodiment of this application is shown;

[0039] Figure 4 A schematic diagram of an ion beam etching method provided in an embodiment of this application is shown;

[0040] Figure 5 A schematic diagram of an ion beam trimming method provided in an embodiment of this application is shown;

[0041] Figure 6 This illustration shows a schematic diagram of an ion beam planarization provided in an embodiment of this application;

[0042] Figure 7 This illustration shows a schematic diagram of a semiconductor structure planarization process provided in an embodiment of this application;

[0043] Figure 8 A schematic diagram of a first semiconductor structure provided in an embodiment of this application is shown. Detailed Implementation

[0044] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0045] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0046] As described in the background section, the flattening load effect and dishing effect are still quite significant and cannot be overcome during the flattening process.

[0047] Specifically, refer to Figure 1 The diagram shows a typical semiconductor structure in the related technology. In this semiconductor structure, there is a patterned dense region A and a patterned sparse region B. After planarization, due to the difference in pattern density between the two regions, there will be a certain height difference (step height) between the film layers of the two regions, that is, a loading effect occurs.

[0048] Semiconductor dishing refers to the phenomenon in semiconductor manufacturing where, when external forces increase, the central region of a thin film bulges while the surrounding region sinks. This is primarily due to the greater frictional force exerted by mechanical forces on the film surface, creating pressure. At the surface, this mechanical force causes greater pressure in the central region, resulting in a bulge, while the surrounding area experiences relatively less mechanical force, leading to a sinking. Secondly, during the planarization process, the difference in the degree of chemical polishing fluid contact between the central and edge regions also causes a difference in etching rates. Typically, the central region of the wafer has relatively limited contact space with the chemical polishing fluid due to the surrounding pattern, resulting in a relatively controllable etching rate. Conversely, the edge regions, with sufficient contact with the chemical polishing fluid, usually have a higher etching rate than the central region, thus causing a significant difference between the central and edge regions.

[0049] Especially in the architecture of Dynamic Random Access Memory (DRAM) below 14nm, the memory cell area is filled with memory capacitors, while the peripheral area only has scattered peripheral circuits. The difference in pattern structure and density between the two is enormous. These characteristics put the fabrication process of this memory under severe test during planarization. Components in the high pattern density areas that are over-etched may be damaged, inducing electrical failure of the device.

[0050] Based on the above technical problems, this application provides a method for planarizing a semiconductor structure. A first ion beam etching process can initially smooth the surface undulations of the film layer, i.e., the first height difference, achieving preliminary optimization of the loading and dishing effects. The core principle lies in the difference in etching rates generated by the ion beam on different undulating surfaces; the higher the surface undulation height and frequency, the faster the equivalent etching rate, achieved by leveraging the surface differences in different regions of the film layer. Next, a second ion beam etching process can be used to recreate new surface undulation differences between different regions of the second semiconductor structure, increasing the height difference. This results in more pronounced protrusions and depressions on the surface, obtaining a third height difference. This provides a height difference window for further smoothing the height difference between different regions globally. Then, a third ion beam etching process is used for further smoothing, further optimizing the loading and dishing effects, thereby improving the surface flatness of the semiconductor structure and achieving global planarization. This balances the flatness of the patterned surface in local areas and the flatness between different regions globally, resulting in a semiconductor structure surface without significant height differences. In summary, this application utilizes ion beam etching technology to control the surface differences of film layers at different locations in a semiconductor structure, thereby reducing surface undulation and undulation frequency, eliminating height differences between film layers at different locations, and achieving global planarization.

[0051] For ease of understanding, the planarization method for a semiconductor structure provided in this application will be described in detail below with reference to the accompanying drawings.

[0052] refer to Figure 1 The diagram shown is a schematic flowchart of a semiconductor structure planarization method provided in an embodiment of this application. The method may include the following steps.

[0053] S101, a first semiconductor structure is provided; the first semiconductor structure includes a substrate, a first film layer located on one side of the substrate, and a second film layer located on the side of the first film layer away from the substrate; the first semiconductor structure includes a first region and a second region arranged along a target direction, the target direction being perpendicular to the direction of the substrate pointing to the first film layer, and a first height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region.

[0054] In this embodiment, a first semiconductor structure can be provided to planarize its surface. The first semiconductor structure may include a first film layer 101 and a second film layer 102 sequentially stacked on a substrate 100, with the first film layer 101 in contact with the substrate 100. The direction from the substrate 100 to the first film layer 101 can be considered vertical, and the target direction can be horizontal. In the target direction, the first semiconductor structure can be divided into a first region and a second region. The upper surfaces of the first region and the second region have different heights. The height of the second film layer in the first region differs from its height in the second region. This height difference between the first region and the second region can be denoted as the first height difference. This height difference can be caused by various reasons, such as different pattern densities.

[0055] refer to Figure 3 The diagram shown is a schematic diagram of a first semiconductor structure provided in an embodiment of this application, including a substrate 100, a first film layer 101 and a second film layer 102 stacked sequentially. The first region has fewer patterns and is a sparse region, while the second region has more patterns and is a dense region. The pattern density in the first region is less than that in the second region, which causes the upper surface of the second film layer 102 to have undulations and is not horizontal.

[0056] In one possible implementation, the first height difference is the difference in film growth undulation caused by the difference in pattern density between the first region and the second region.

[0057] Specifically, the first region and the second region can have different pattern densities. For example, the first region has a high pattern density and the second region has a low pattern density. Due to the different pattern densities, the upper surface of the second film layer will have undulations and be uneven when the second film layer is formed.

[0058] For example Figure 3 As shown, the first film layer 101 can be a patterned film layer, which can be formed by methods such as development and exposure. That is, some areas of the first film layer 101 are retained, while some areas are removed. For the unevenness of the second film layer caused by the difference in pattern density, the method provided in this application can be used to eliminate the unevenness caused by the difference in pattern density, making the surface of the second film layer 102 flat.

[0059] In one possible implementation, the first film layer has different patterned structures in the first and second regions, including pad structures, via structures, or trench structures.

[0060] Specifically, the difference in pattern density can be caused by different pattern structures, that is, the pattern structures in the first region and the second region are different. For example, the first film layer in the first region has a pin structure, while the first film layer in the second region has a through-hole structure. Due to the different pattern structures, this will also cause undulations when forming the second film layer 102.

[0061] Similarly, for the unevenness of the second film layer caused by different pattern structures, the method provided in this application can be used to process it, thereby eliminating the unevenness caused by the difference in pattern structure and making the surface of the second film layer 102 flat.

[0062] In one possible implementation, the number of patterns in the first film layer differs between the first and second regions.

[0063] Specifically, the first film layer 101 is a patterned film layer, but the number of patterns may vary in different regions; some regions have a larger and denser number of patterns, while others have a smaller and sparser number. For example... Figure 3 The first region has fewer patterns, while the second region has more patterns, which causes the surface of the second film layer 102 to have undulations.

[0064] In one possible implementation, the first height difference is the difference in film growth undulation caused by the material difference between the first region and the second region.

[0065] Specifically, there may be material differences between the first region and the second region, which may cause the second film layer 102 to have undulations during the formation process, forming a first height difference. For example, the first film layer 101 may have different materials in the first region and the second region, or the second region may have other film layers compared to the first region.

[0066] The unevenness of the second film layer caused by the difference in materials can be addressed by the method provided in this application, thereby eliminating the unevenness caused by the material difference and making the surface of the second film layer 102 flat.

[0067] In one possible implementation, the first height difference arises from the loading effect during the chemical mechanical polishing process of the first and second regions.

[0068] Specifically, during the chemical mechanical polishing of the first semiconductor structure, inconsistencies in the surface height of the film layer between different regions may occur due to the loading effect, resulting in a first height difference. For the undulations in the second film layer caused by this loading effect, the method provided in this application can be used to eliminate the undulations caused by the loading effect, thereby making the surface of the second film layer 102 flat.

[0069] In summary, the height difference can originate from the difference in film growth undulation caused by the difference in pattern density at different locations, the difference in film growth undulation caused by the difference in materials at different locations, the load effect in chemical mechanical polishing, and the difference in pattern structure at different locations, such as the difference in Pad, Via, Trench. That is, the height difference of the film layer originates from the differences in pattern structure, material, and pattern density at different locations of the first film layer, as well as the load effect of the coating process and chemical mechanical polishing itself.

[0070] Optionally, Figure 3 The following example illustrates a typical case of pattern density difference. The first film layer 101 is a patterned film layer, and the second film layer 102 is located inside the groove and also on the surface of the first film layer 101 away from the substrate. That is, when the second film layer 102 is deposited on the first film layer 101, the second film layer 102 can fall into the groove or be formed above the surface of the first film layer 101.

[0071] S102, the second film layer is planarized using the first ion beam etching process to obtain a second semiconductor structure; in the second semiconductor structure, there is a second height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and the second height difference is smaller than the first height difference.

[0072] In this embodiment, ion beam etching (IBE) involves bombarding the wafer surface with neutral gas ions of a certain energy, removing surface material through a physical sputtering effect. Ion beam etching is an atomically precise surface processing technology that uses a collimated neutral ion beam to planarize the wafer surface. By controlling the trajectory of colliding particles using parameters such as incident angle, energy, and beam current density, it optimizes processes such as surface roughness, undulation, and height differences between regions, ultimately achieving nanometer-level wafer-level thickness control.

[0073] refer to Figure 4 The diagram shown is a schematic of an ion beam etching process provided in an embodiment of this application. Etching gas can be introduced into the chamber, and the etching gas is excited to form plasma. The plasma, i.e., neutral particles, passes through the screen grid, acceleration grid, and deceleration grid and is incident on the sample surface at a certain angle.

[0074] In this embodiment, the second film layer located on the surface can be planarized. The ion beam etching process used is referred to as the first ion beam etching process, and a second semiconductor structure is obtained after the process. In the second semiconductor structure, there is still a certain height difference between the surface of the second film layer and the first and second regions. This height difference can be referred to as the second height difference, which is smaller than the first height difference.

[0075] In this embodiment of the application, when performing etching using an ion beam etching process, it is necessary to reasonably determine the incident angle of the ion beam. The incident angle of the ion beam can be defined as the angle between the incident direction of the ion beam and the stacking direction of the semiconductor structure, that is, the angle between the incident direction and the normal to the plane where the film layer is located. Figure 4 θ in the equation.

[0076] When determining the incident angle of the ion beam, it is necessary to comprehensively consider the effects of the surface undulation of the semiconductor structure film, the equivalent incident angle, and the etching rate. The equivalent incident angle can be understood as the actual incident angle of the film surface at a specific location within the semiconductor structure, given a given ion beam incident angle; that is, the angle between the ion beam and the normal to the film at that location. Because the film surface has undulations, some locations are convex while others are concave. Therefore, at the same ion beam incident angle, the equivalent incident angles corresponding to convex and concave locations are different.

[0077] For example, refer to Figure 5 As shown in (a), the same ion beam incident angle is applied to the film surface at different locations. The first and second locations both have vertically downward-incident ion beams with an incident angle of 0°. However, the equivalent incident angles at these two locations are different: S' at the first location and S' at the second. Furthermore, the incident angles of the ion beams at the third and fourth locations are the same, but the equivalent incident angle at the third location is L, and at the fourth location it is L'.

[0078] Furthermore, under the same ion beam incident angle, different locations on the film surface have corresponding equivalent incident angles. Different equivalent incident angles may result in different etching rates; that is, there is a certain correlation between the equivalent incident angle and the etching rate. (Reference) Figure 5 (b) shows the relationship between the equivalent incident angle and the etching rate. The etching rate corresponding to the equivalent incident angle S' at the first position point is greater than the etching rate corresponding to the equivalent incident angle S at the second position point. The etching rate corresponding to the equivalent incident angle L' at the fourth position point is greater than the etching rate corresponding to the equivalent incident angle L at the third position point.

[0079] Therefore, when determining the incident angle of the ion beam, it is necessary to comprehensively consider the degree of undulation at different positions on the film surface, the equivalent incident angle corresponding to each position, and the etching rate at each position, so as to determine a suitable incident angle, so as to achieve a faster etching rate for protruding areas and a lower etching rate for recessed areas during the film surface smoothing process, and to minimize the height difference between areas with different degrees of undulation.

[0080] In one possible implementation, when planarizing the second film layer 102 using a first ion beam etching process, the incident angle of the first ion beam may not exceed 80°. This is because, in Figure 5 As shown in (b), the etching rate curve is generally near parabolic, with the highest etching rate occurring near a moderate equivalent incident angle. Larger equivalent incident angles correspond to lower etching rates. Based on this characteristic, a smaller equivalent incident angle can be used to achieve a higher etching rate, thus eliminating the etching rate difference between raised and recessed regions. Furthermore, the smaller the incident angle of the ion beam, the smaller the corresponding equivalent incident angle. Therefore, by utilizing low-angle incident (no more than 80°), the etching rate difference between raised and recessed regions (undulating regions > flat regions) during ion-non-smooth surface interaction, and by controlling the average sputtering yield dependent on the ion incident angle, a surface smoothing effect can be achieved.

[0081] Based on the characteristics of directional etching with ion beams, the higher the undulation frequency, the higher the total proportion of undulation regions within the ion beam irradiation range, and consequently, the higher the overall etching rate. This allows for the adjustment and smoothing of height differences between different undulation regions, providing a fundamental solution to the height difference problem between different locations. (Reference) Figure 6 As shown in Figure (a), the height difference between two regions is shown. After ion beam etching, the structure shown in Figure (b) can be obtained. By performing ion beam etching, the height difference between different regions can be reduced. For a single region, the unevenness of the local surface of the film is also smoothed out accordingly.

[0082] refer to Figure 7As shown, (a) and (b) represent two different regions with a height difference. The height difference of the film layer originates from the differences in the pattern structure, material, and pattern density of the film layer at different locations, as well as the loading effect introduced by the coating process and chemical mechanical polishing. In a typical case, as shown in the figure, there are differences in pattern density at different locations, divided into pattern-dense regions and pattern-sparse regions. There is a large height difference h1 between the pattern-dense regions and the pattern-sparse regions. For each region, the surface of the second film layer 102 also has a certain degree of undulation. After the first ion beam etching process (first etching process), the etching results are shown in (c) and (d). The height difference between the two regions is denoted as h2. h2 is less than h1, which reduces the height difference between the two regions. At the same time, the surface undulation of a single region is also improved.

[0083] In other words, after the first ion beam etching process, the height difference between different dense regions in the resulting second semiconductor structure is significantly reduced, and is generally lower than the height difference between different dense regions in the first semiconductor structure. This application does not limit the height difference between two specific dense regions in the second semiconductor structure to less than the height difference in the first semiconductor structure; rather, it refers to the overall height difference of the semiconductor structure. That is, from a global perspective, the global flatness of the second semiconductor structure surface is better than that of the first semiconductor structure surface, thereby reducing the height difference of the film surface between different regions and optimizing the loading effect.

[0084] The first etching gas can be excited to form a first plasma to etch the first semiconductor structure. The first etching gas may include an inert gas, which may include at least one of He, Ne, Ar, Kr and Xe, thereby reducing process costs and improving planarization effect.

[0085] In one possible implementation, to further improve the flatness, different incident angles can be used for the first semiconductor structure with different undulations.

[0086] Specifically, the surface roughness of the film layer can be defined as the height difference between the highest and lowest points on the film layer surface. The greater the height difference, the greater the roughness; the smaller the height difference, the smaller the roughness. In the first semiconductor structure, if the roughness of the outer surface of the second film layer 102 is relatively large, exceeding the preset roughness, it can be considered to have high roughness, and it is necessary to reduce the roughness as soon as possible. Therefore, the incident angle of the first ion beam can be greater than or equal to 0° and less than or equal to 60°. In this way, for a film layer surface with high roughness, by selecting a smaller ion beam incident angle, the angle between the ion beam and the film layer surface is larger, which can make the etching rate at various positions on the film layer surface larger, thereby smoothing the film layer surface as quickly as possible and achieving the optimal roughness smoothing effect. The preset roughness can be selected according to the process conditions. If the undulation of the outer surface of the second film layer 102 is less than or equal to the preset undulation, it means that the undulation of the film surface is small. In this case, the film surface needs to be refined more finely. The incident angle of the first ion beam can be greater than or equal to 60° and less than or equal to 80°. By selecting a larger incident angle, the ion beam can be closer to the film surface, so that the etching rate at each position of the film is relatively small, and more fine etching is achieved. That is, controlling the low divergence of the ion beam can achieve higher recognition of the undulating surface and finally achieve smoothing.

[0087] In one possible implementation, in the first ion beam etching process, the grid voltage BMV can be greater than or equal to 200V and less than or equal to 1500V. This avoids the initial kinetic energy of the ion beam being too low and the collimation of the ion beam being poor due to the grid voltage being too low. In this application, by selecting a higher grid voltage (i.e., 200V-1500V), the ion beam has a higher initial kinetic energy, which in turn gives the ion beam higher collimation and a higher etching rate.

[0088] The voltage ACV of the accelerating gate can be greater than or equal to 100V and less than or equal to 1500V. ACV can affect the beam divergence angle of the ion beam. By adjusting this parameter, different locations on the semiconductor structure surface, such as the center, middle, and edge regions, can have different ion beam irradiation capabilities. For wafer-level height differences, a suitable voltage can be selected within this voltage range to adaptively adjust the ion beam distribution and etching rate of the corresponding regions, thereby balancing the differences in performance of each region and ultimately achieving global high-precision planarization.

[0089] Specifically, in the first ion beam process, by selecting an ACV between 100V and 1500V, a higher ACV can be ensured when the surface undulation of the first semiconductor structure is relatively large. This reduces the beam divergence angle of the ion beam, making the ion beam more concentrated, eliminating height differences as quickly as possible, and smoothing out the undulations. If the surface undulation of the first semiconductor structure is relatively small, a smaller ACV can be selected to provide a higher ion beam divergence angle, thereby performing global fine-tuning of the surface with insignificant undulations and further reducing height differences.

[0090] The current BMI of the grid can affect the ion beam density. The current BMI of the grid can be greater than or equal to 0.1A and less than or equal to 1.5A. By selecting a lower BMI, a lower ion density can be achieved, which can reduce direct collisions between ion beams, enhance beam collimation, and the number of fewer ions can lead to a lower etching rate, thus providing sufficient time for surface finishing. The specific selection depends on the process requirements (the degree of optimization of capacity and height difference).

[0091] S103, the second semiconductor structure is subjected to undulation processing using a second ion beam etching process to obtain a third semiconductor structure; in the third semiconductor structure, there is a third height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and the third height difference is greater than the second height difference.

[0092] In this embodiment, since the undulation of the second semiconductor structure has been improved to a certain extent, the height difference between the highest points of the film layer has been reduced to a certain extent, and the height difference between the dense and sparse regions of the pattern has also been reduced. However, in order to further eliminate the height difference, it is necessary to continue to planarize the surface of the second semiconductor structure.

[0093] Since ion beam etching is mainly used to planarize surfaces with protrusions and depressions, the local surface undulation of the second semiconductor structure is low, and the difference in the interface information between different regions of the film layer is low, which is not conducive to further planarization. Therefore, it is necessary to recreate a higher undulation so that planarization can be performed again.

[0094] In other words, the second ion beam etching process can be used to process the undulation of the second semiconductor structure. Specifically, the incident angle of the second ion beam can also be within the range of 0°-80°, so that the ion beam can form a certain angle with the film surface, enabling effective etching of the second semiconductor structure at a higher etching rate, thereby creating a more obvious undulation. Furthermore, during the second ion beam etching process, etching gases with significant differences in etching rate at different locations can be selected. Different etching gases correspond to different etching rate change curves, further increasing the etching rate difference between different film layers and creating a more pronounced height difference between the first and second film layers.

[0095] By ionizing the second etching gas, a second ion beam can be formed for etching, thereby creating a film surface with greater undulation. In other words, in the third semiconductor structure, the third height difference between different regions is greater than the second height difference in the second semiconductor structure. By increasing the film height difference, the surface undulation difference between different pattern regions is recreated, providing a window of undulation difference for further smoothing the surface of different regions.

[0096] The second etching gas can etch both the first film layer 101 and the second film layer 102, and has a high etching selectivity. This allows the etching rate of the second film layer 102 to be greater than that of the first film layer 101. In other words, the overall height of the second film layer 102 can be lower than that of the first film layer 101. Furthermore, a certain degree of undulation is created for each individual film layer (either the first film layer 101 or the second film layer 102), and there is also a difference in undulation between the first film layer 101 and the second film layer 102. (Reference) Figure 7 As shown, after the second ion beam etching (second etching process), the structure shown in (e) and (f) is obtained. The height difference between the two regions is h3, which is greater than h2. For a single region, the overall height of the second film layer 102 is slightly lower than the overall height of the first film layer 101.

[0097] In other words, during the second ion beam etching process, the differences in etching performance between materials can be adjusted based on angle, energy, and gas selection to modify the surface film undulation, creating differences in surface undulation between different regions, and providing a window of undulation difference for further smoothing the surface of different regions.

[0098] In one possible implementation, the second etching gas can be determined based on the material difference between the first and second films, and / or the density difference between the films, and / or the structural difference between the films.

[0099] Specifically, a suitable second etching gas can be selected based on differences in the material, pattern density, and structure of the film layers. This ensures that the etching rate of the second film layer is greater than that of the first film layer, preferentially removing the second film layer and creating a height difference. Alternatively, the second etching gas can be selected based on the density differences between different regions, thereby creating height differences between different regions.

[0100] In one possible implementation, the undulation is processed by modifying the path with high-energy inert ions in the second ion beam etching process, and the second etching gas includes an inert gas.

[0101] In one possible implementation, the second ion beam etching process involves surface undulation treatment via a chemical ion modification path. The second etching gas includes a reactive gas, which comprises at least one of a fluorine-based gas and a chlorine-based gas. In other words, the second etching process can create surface undulations through high-energy inert ion ionization or chemical ion ionization modification, resulting in a third semiconductor structure with a surface morphology undulation difference greater than the height difference between different regions in the second semiconductor structure.

[0102] In one possible implementation, the second etching gas may include at least one of fluorine-based gas and chlorine-based gas. The fluorine-based gas or chlorine-based gas can chemically react with the film material, that is, to perform reactive ion beam etching (RIBE). This not only retains the physical etching capability of the ion beam, but also increases the chemical reaction capability of the fluorine-based gas or chlorine-based gas on the sample after ionization, which can significantly improve the etching rate, improve the etching quality, and improve the planarization degree.

[0103] When specifically selecting an etching gas, it can be selected based on the materials of the first film layer 101 and the second film layer 102 to provide a larger etching selectivity. That is, the etching rate of the second film layer 102 can be greater than the etching rate of the first film layer 101, so that the overall height of the second film layer is lower than the overall height of the first film layer.

[0104] In one possible implementation, the fluorine-based gas may include C x F y The etching gas can be at least one of NF3, SF6, WF6, CHF3, and CH2F2, where x and y are positive integers. The chlorine-based gas can include at least one of Cl2, BCl3, CCl4, and SiCl4. The second etching gas can also include an inert gas, for example, the inert gas can account for 10% of the total flow rate of the second etching gas. By selecting a suitable etching gas, the planarization degree can be further improved.

[0105] In one possible implementation, in the second ion beam etching process, based on the high-energy inert gas path, the voltage of the screen gate can be greater than or equal to 800V and less than or equal to 1500V, the current of the screen gate can be greater than or equal to 0.6A and less than or equal to 1.5A, and the voltage of the accelerating gate can be greater than or equal to 400V and less than or equal to 1500V.

[0106] This is because, when etching using plasma generated from inert gas, the inert gas does not chemically react with the film layer; the etching relies primarily on the physical etching effect of the high-energy plasma. Therefore, the parameters for the gate voltage, gate current, and accelerating gate voltage must be set based on providing a high-energy ion beam. Thus, setting a higher gate voltage allows the ion beam to have higher energy and initial kinetic energy, resulting in better beam collimation. Setting a higher gate current (0.6A-1.5A) provides a higher ion density, increasing the number of ions and accelerating the etching rate. This facilitates creating greater surface undulation differences in the film layer, providing a wider process window for subsequent height difference optimization. A larger accelerating gate voltage reduces the beam divergence angle of the ion beam, allowing it to etch different regions of the film surface at different rates, thus facilitating the creation of height differences on the film surface.

[0107] In the second ion beam etching process, based on the chemical ion modification path, the voltage of the gate is greater than or equal to 200V and less than or equal to 1200V, the current of the gate is greater than or equal to 0.1A and less than or equal to 1.2A, and the voltage of the accelerating gate is greater than or equal to 200V and less than or equal to 1200V. This is because the etching gas used in the chemical ion modification path is a chemical gas that can chemically react with the film layer to achieve etching. Furthermore, different film layers react with the etching gas at different rates, thus allowing for different etching rates in the first and second film layers for the same etching gas; that is, different etching selectivity for different film layers. In this way, since the chemical gas can have corresponding etching rates for different material film layers, differences in surface undulation can be created through the selection of the chemical gas, thereby eliminating the need to provide high energy to the ion beam and reducing process costs.

[0108] In other words, the parameters of the grid voltage, grid current, and accelerating grid voltage are all in a relatively low range. By setting the grid voltage in the range of 200V-1200V, a lower ion beam energy can be provided. By setting the grid current in the range of 0.1A-1.2A, the value of the grid current can be relatively small, thereby reducing the number of ions. By setting the range of the accelerating grid voltage to be lower, the beam divergence angle of the ion beam can be increased, reducing the etching difference in different regions. Thus, new surface undulation differences can be created by relying on the selection of etching gas.

[0109] S104, the third semiconductor structure is planarized using a third ion beam etching process to obtain a fourth semiconductor structure; the surface flatness of the fourth semiconductor structure meets the flatness requirements; in the fourth semiconductor structure, there is a fourth height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and the fourth height difference is smaller than the second height difference.

[0110] In this embodiment, the third semiconductor structure already has a certain degree of undulation, so it can be planarized using a third ion beam etching process to obtain the fourth semiconductor structure. The surface flatness of the fourth semiconductor structure is sufficiently high to meet the flatness requirements. (Reference) Figure 7 As shown, (g) and (h) are schematic diagrams of the dense and sparse pattern regions obtained after the third etching. The heights of the first film layer 101 and the second film layer 102 are basically the same, and there are no obvious undulations on the film surface. That is to say, after recreating and then eliminating the undulations, the height difference between different regions is significantly reduced compared to the height difference before the undulations were created, thus meeting the flatness requirements.

[0111] In one possible implementation, during the third ion beam etching process, the incident angle of the third ion beam can be between 60° and 90°, and the incident direction of the ion beam can be closer to the surface of the third semiconductor structure. By using near-parallel incident, controlling the low divergence of the ion beam can achieve fine smoothing of the surface undulations, thereby improving the flattening degree of the first film layer 101 and the second film layer 102.

[0112] Furthermore, although there is a certain height difference h3 between the dense and sparse patterned regions, the etching rate of the dense patterned regions during ion beam etching is greater than that of the sparse patterned regions. This allows for the smoothing of the height difference between different patterned regions, essentially eliminating the height difference between the first film layer 101 and the second film layer 102. Consequently, the height difference in the resulting fourth semiconductor structure is significantly reduced. In other words, the fourth height difference can be smaller than the second height difference, thus achieving the smoothing of the height difference in the second semiconductor structure. This not only enables the flatness of the patterned surface within a single local area but also the flatness between different patterned regions globally, without significant height differences. This achieves secondary optimization of the loading effect and ultimately realizes nanoscale cross-wafer uniformity and flatness control.

[0113] In summary, this solution can eliminate the height difference of film layers between different locations on the wafer, achieve global planarization of the entire wafer, and also achieve surface planarization of local areas of a single pattern.

[0114] Therefore, the first ion beam etching process can initially smooth out the surface undulations of the film layer, i.e., the first height difference, achieving preliminary optimization of the loading and dishing effects. Its core principle lies in the difference in etching rates produced by the ion beam on different undulating surfaces; the higher the surface undulation height and frequency, the faster the equivalent etching rate, achieved by leveraging the surface differences in different regions of the film layer. Next, the second ion beam etching process can be used to recreate new surface undulation differences between different regions of the second semiconductor structure, increasing the height difference and forming more pronounced protrusions and depressions on the surface, resulting in a third height difference. This provides a height difference window for further smoothing out the height differences between different regions globally. Then, the third ion beam etching process is used for further smoothing, further optimizing the loading and dishing effects, thereby improving the surface flatness of the semiconductor structure and achieving global flattening. This means considering both the flatness of the patterned surface in local areas and the flatness between different regions globally, resulting in a semiconductor structure surface without significant height differences. In summary, this application utilizes ion beam etching technology to control the surface differences of film layers at different locations in a semiconductor structure, thereby reducing surface undulation and undulation frequency, eliminating height differences between film layers at different locations, and achieving global planarization.

[0115] In one possible implementation, during the third ion beam etching process, the gate voltage can be greater than or equal to 75V and less than or equal to 400V, the gate current can be greater than or equal to 0.1A and less than or equal to 0.5A, and the accelerating gate voltage can be greater than or equal to 100V and less than or equal to 800V. It can be observed that the maximum values ​​of parameters such as gate voltage, gate current, and accelerating gate voltage are significantly reduced, placing them within a lower range. The lower gate voltage allows for fine modification of the film surface of the third semiconductor structure, while the lower accelerating gate voltage provides a higher ion beam divergence angle, thus achieving global wafer modification. The lower gate current enables lower ion density, reducing collisions between ion beams, enhancing beam collimation, achieving better directional removal capability, and, due to the smaller number of ions, reducing the etching rate, thus achieving fine smoothing of the film surface.

[0116] In one possible implementation, in the first ion beam etching process, the second ion beam etching process, or the third ion beam etching process, the cavity pressure can be greater than or equal to 0.05 mT and less than or equal to 5 mT, and the total gas flow rate can be 10 sccm to 100 sccm. The low cavity pressure is beneficial to increase the molecular free path, improve ion collimation, and achieve process modification with higher uniformity, thereby meeting the process requirements.

[0117] Furthermore, the modification time of the third etching process can depend on the surface undulation height and the optimization amount of the final loading. After the third etching process, the loading problem is further optimized, and there is no significant height difference between the film layers at different locations on the wafer. The height difference can be less than 50 angstroms, ultimately achieving global planarization of the wafer film layers and improving the performance of the final device.

[0118] In one possible implementation, the first film layer 101 and the second film layer 102 are made of the same material. That is, the first film layer 101 and the second film layer 102 can be considered as a single film layer, thereby achieving the elimination of unevenness of a single film layer.

[0119] In one possible implementation, the first film layer 101 and the second film layer 102 can be made of different materials, and the second film layer 102 includes at least one sub-film layer. That is, the first film layer 101 and the second film layer 102 can be multilayer films, and the second film layer 102 can also include multiple sub-film layers, thereby achieving the elimination of unevenness in multilayer films.

[0120] In the embodiments of this application, the first semiconductor structure can be any type of structure, and the second film layer 102 can be a photoresist material, a dielectric material, a metal material, or a combination of these materials, and is not limited to single film layer structures such as photoresist (PR), spin-on carbon (SOC), SOH, silicon nitride Si3N4, silicon oxynitride SiON, silicon oxide (SiO2), polysilicon, low-temperature oxide (LTO), Ta, W, TiN, TaN, Al, etc., wherein SOH refers to highly doped H element in SOC.

[0121] Specifically, the first semiconductor structure can be a first-layer / second-layer structure, such as Poly / SiO2 (the first layer is Poly, and the second layer is SiO2), Si3N4 / SiO2, SOC / SiO2, SiO2 / Ta, SiO2 / W, Ta / W, etc., bilayer structures. It can also be a multi-layer combination structure such as SiO2 / Si3N4 / W, SiO2 / W / TiN / HfO2. In the SiO2 / SiN / W structure, the first layer 101 can be understood as SiO2, with SiN covering the surface of the first layer 101, and then W is used as the second layer 102 to fill the trench. Similarly, the SiO2 / W / TiN / HfO2 structure can be understood as SiO2, with TiN and HfO2 covering the surface of the first layer 101, and then W is used as the second layer 102 to fill the trench. (Reference) Figure 8As shown, the first semiconductor structure shown in (a) and (b) is a single film layer, that is, the first film layer and the second film layer are made of the same material; the first semiconductor structure shown in (c) and (d) is a double film layer; and the first semiconductor structure shown in (e) and (f) is a multi-film layer combination.

[0122] In one possible implementation, the first semiconductor structure can be a logic device, a memory device, a micro-electro-mechanical system (MEMS), or an optical device. The memory device can be a dynamic random access memory (DRAM), a NAND flash memory, or a novel memory device, etc., and the optical device can be, for example, a light-emitting diode (LED). That is, the semiconductor structure in this application can be any type of structure in the semiconductor field.

[0123] In this embodiment, the first semiconductor structure can be a SOC / LTO film structure, with the first film being LTO and the second film being SOC. During the first etching process, the incident angle of the ion beam can be 0°. This incident angle maximizes the etching rate difference between the undulating and flat regions, achieving maximum smoothing capability for highly undulating surfaces. The gate voltage (BMV) can be selected as 800V, the accelerating gate voltage (ACV) as 1000V, and the gate current (BMI) range as 0.8A. High-energy conditions are suitable for high-difference performance, and a high ACV is beneficial for divergence angle convergence, improving the ion beam's recognition and irradiation capability of undulating surfaces. A BMI of 0.8A can control a moderate ion beam density, coordinating beam collimation and etching rate, and improving throughput. In the first etching process, the etching chamber pressure range can be 0.5mT, the total gas flow rate can be 20sccm, and the etching gas is the inert gas Ar. The height difference after etching can be optimized from 80nm to 20nm.

[0124] A second ion beam etching process is performed, with an incident angle of 60°. At this angle, the etching rate difference between LTO and SOC is greatest, maximizing the re-enhancing of surface roughness differences and providing a window for further smoothing of height variations. The chamber pressure range is 1 mT, the total gas flow rate is 20 sccm, and the etching gas uses a combination of inert and fluorine-based gases, with Ar as the inert gas and CHF3 as the fluorine-based gas. The gate voltage (BMV) can be 600 V, the accelerating gate voltage (ACV) can be 800 V, and the gate current (BMI) can range from 0.6 A. Higher energy and higher ion density are beneficial for creating greater surface roughness differences in the film, thus providing a wider process window for loading optimization. After process modification, the height difference can be increased to 40 nm, while the surface roughness frequency difference increases, with densely patterned regions becoming even denser and sparse regions maintaining low-frequency fluctuations.

[0125] In the third etching process, the ion beam incident angle can be 80°, the gate voltage BMV can be 200V, the gate current BMI can be 0.2A, the ion acceleration bias voltage ACV can be 200V, the cavity pressure can be 0.3mT, the etching gas can be the inert gas Ar, and the total gas flow rate is 10sccm. The low cavity pressure is conducive to increasing the molecular free path, improving ion collimation, and achieving higher uniformity in the process modification. The height difference between each region can be less than 5nm, ultimately achieving global planarization of the wafer film surface.

[0126] In this embodiment, the first semiconductor structure can be a W / Oxide film structure, where the first film is Oxide and the second film is W. There is a height difference between the film layers at different locations, but in this scenario, the height difference between densely patterned and sparsely patterned regions is relatively small, greater than 20 nm. For this low height difference scenario, a two-stage etching process can be performed. The first etching process creates the unevenness height difference, and the second etching process performs a secondary leveling of the film surface, ultimately achieving planarization.

[0127] During the first etching process, the incident angle of the ion beam can be 50°. At this angle, the difference in etching rates between Oxide and W is greatest, which can maximize the restoration of the height and frequency differences of the material surface undulations, providing a window for further smoothing and expanding the height differences between different regions. The chamber pressure range can be 2 mT, the total gas flow rate is 30 sccm, and the etching gas adopts an inert gas combined with a chlorine-based gas path, where Ar is selected as the inert gas and Cl2 is selected as the chlorine-based gas.

[0128] The gate voltage (BMV) can be 400V, the accelerating gate voltage (ACV) can be 600V, and the gate current (BMI) ranges from 0.40A. The mixed gas of Ar and Cl2 allows for a higher etching rate in the physical-chemical etching path compared to a purely physical etching path. The relatively low energy required at this stage contributes to higher process precision and controllability. After this process modification, the height difference between different locations increases to 30nm, while the frequency difference of surface undulations increases, resulting in further densification in densely patterned areas and maintaining low-frequency undulations in sparse areas.

[0129] In the second etching process, the ion beam incident angle can be 85°. Near-parallel incident light allows for better control of the low divergence of the ion beam, enabling fine smoothing of low surface undulations. The ion gate voltage (BMV) can be 100V, the gate current (BMI) can be 0.1A, and the ion acceleration bias voltage (ACV) can be 200V. Low-energy modification provides fine-tuning of film undulations under conditions of low height difference. The low ion beam divergence angle improves the ion beam's ability to identify and irradiate undulating surfaces, achieving better height difference optimization.

[0130] The cavity pressure can be 0.5 mT, and the etching gas is a combination of inert gas Ar and chlorine-based gas Cl2. The total gas flow rate can be 30 sccm. The low cavity pressure is beneficial for increasing the molecular free path, improving ion collimation, achieving better process modification, further optimizing the loading problem, and ensuring no significant difference in film height between different locations on the wafer (<5 nm). Ultimately, global planarization of the wafer film is achieved, improving the performance of the final device.

[0131] This application provides a method for planarizing a semiconductor structure. A first ion beam etching process can initially smooth out the surface undulations of the film layer, i.e., the first height difference, achieving preliminary optimization of the loading and dishing effects. The core principle lies in the difference in etching rates generated by the ion beam on different undulating surfaces; the higher the surface undulation height and frequency, the faster the equivalent etching rate, achieved by leveraging the surface differences in different regions of the film layer. Next, a second ion beam etching process can be used to recreate new surface undulation differences between different regions of the second semiconductor structure, increasing the height difference. This results in more pronounced protrusions and depressions on the surface, creating a third height difference. This provides a height difference window for further smoothing the height difference between different regions globally. Then, a third ion beam etching process is used for further smoothing, further optimizing the loading and dishing effects, thereby improving the surface flatness of the semiconductor structure and achieving global planarization. This balances the flatness of the patterned surface in local areas and the flatness between different regions globally, resulting in a semiconductor structure surface without significant height differences. In summary, this application utilizes ion beam etching technology to control the surface differences of film layers at different locations in a semiconductor structure, thereby reducing surface undulation and undulation frequency, eliminating height differences between film layers at different locations, and achieving global planarization.

[0132] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0133] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for planarizing a semiconductor structure, characterized in that, include: Provide a first semiconductor structure; The first semiconductor structure includes a substrate, a first film layer located on one side of the substrate, and a second film layer located on the side of the first film layer away from the substrate; the first semiconductor structure includes a first region and a second region arranged along a target direction, the target direction being perpendicular to the direction of the substrate pointing towards the first film layer, and a first height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region; The second film layer is planarized using a first ion beam etching process to obtain a second semiconductor structure; in the second semiconductor structure, there is a second height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and the second height difference is smaller than the first height difference. The second semiconductor structure is subjected to a second ion beam etching process to perform undulation treatment to obtain a third semiconductor structure; in the third semiconductor structure, there is a third height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region, and the third height difference is greater than the second height difference. The third semiconductor structure is planarized using a third ion beam etching process to obtain a fourth semiconductor structure. The surface flatness of the fourth semiconductor structure meets the flatness requirements. In the fourth semiconductor structure, there is a fourth height difference between the surface of the second film layer in the first region and the surface of the second film layer in the second region. The fourth height difference is smaller than the second height difference.

2. The method according to claim 1, characterized in that, The first film layer and the second film layer are made of the same material; or, The first membrane layer and the second membrane layer are made of different materials, and the second membrane layer includes at least one sub-membrane layer.

3. The method according to claim 1, characterized in that, The first height difference is the difference in film growth undulation caused by the difference in pattern density between the first region and the second region.

4. The method according to claim 3, characterized in that, The first film layer has different pattern structures in the first region and the second region, and the pattern structures include pin structures, through-hole structures or trench structures.

5. The method according to claim 3, characterized in that, The number of patterns in the first film layer differs between the first region and the second region.

6. The method according to claim 1, characterized in that, The first height difference is the difference in film growth undulation caused by the material difference between the first region and the second region.

7. The method according to claim 1, characterized in that, The first height difference is due to the load effect during the chemical mechanical polishing process of the first region and the second region.

8. The method according to claim 1, characterized in that, The first semiconductor structure is a logic device, a memory device, a microelectromechanical system, or an optical device.

9. The method according to claim 1, characterized in that, In the first ion beam etching process, the incident angle of the first ion beam is greater than or equal to 0° and less than or equal to 80°, the incident angle being the angle between the incident direction of the ion beam and the stacking direction of the first semiconductor structure, and the first etching gas forming the first ion beam includes an inert gas.

10. The method according to claim 9, characterized in that, In the first semiconductor structure, when the surface undulation of the second film layer is greater than a preset undulation, the incident angle of the first ion beam is greater than or equal to 0° and less than or equal to 60°. When the surface undulation of the second film layer is less than or equal to the preset undulation, the incident angle of the first ion beam is greater than or equal to 60° and less than or equal to 80°.

11. The method according to claim 1, characterized in that, In the second ion beam etching process, the incident angle of the second ion beam is greater than or equal to 0° and less than or equal to 80°, and the etching rate of the second etching gas forming the second ion beam on the second film layer is greater than the etching rate on the first film layer.

12. The method according to claim 11, characterized in that, In the second ion beam etching process, the undulation is processed by modifying the path with high-energy inert ions, and the second etching gas includes an inert gas.

13. The method according to claim 12, characterized in that, In the second ion beam etching process, based on the high-energy inert ion modification path, the voltage of the screen gate is greater than or equal to 800V and less than or equal to 1500V, the current of the screen gate is greater than or equal to 0.6A and less than or equal to 1.5A, and the voltage of the acceleration gate is greater than or equal to 400V and less than or equal to 1500V.

14. The method according to claim 11, characterized in that, In the second ion beam etching process, the undulation is processed through a chemical ion modification path. The second etching gas includes a reactive gas, which includes at least one of fluorine-based gas and chlorine-based gas.

15. The method according to claim 14, characterized in that, The fluorine-based gas includes C x F y The chlorine-based gas includes at least one of NF3, SF6, WF6, CHF3, and CH2F2, and the chlorine-based gas includes at least one of Cl2, BCl3, CCl4, and SiCl4.

16. The method according to claim 14, characterized in that, In the second ion beam etching process, based on the chemical ion modification path, the voltage of the screen gate is greater than or equal to 200V and less than or equal to 1200V, the current of the screen gate is greater than or equal to 0.1A and less than or equal to 1.2A, and the voltage of the acceleration gate is greater than or equal to 200V and less than or equal to 1200V.

17. The method according to claim 1, characterized in that, In the third ion beam etching process, the incident angle of the third ion beam is greater than or equal to 60° and less than or equal to 90°, and the third etching gas forming the third ion beam includes an inert gas.

18. The method according to claim 1, characterized in that, The inert gases used in ion beam etching processes include at least one of He, Ne, Ar, Kr, and Xe.

19. The method according to claim 1, characterized in that, In the first ion beam etching process, the voltage of the screen gate is greater than or equal to 200V and less than or equal to 1500V, the current of the screen gate is greater than or equal to 0.1A and less than or equal to 1.5A, and the voltage of the acceleration gate is greater than or equal to 100V and less than or equal to 1500V.

20. The method according to any one of claims 1, characterized in that, In the third ion beam etching process, the voltage of the screen gate is greater than or equal to 75V and less than or equal to 400V, the current of the screen gate is greater than or equal to 0.1A and less than or equal to 0.5A, and the voltage of the acceleration gate is greater than or equal to 100V and less than or equal to 800V.

21. The method according to any one of claims 1, characterized in that, In the first ion beam etching process, the second ion beam etching process, or the third ion beam etching process, the cavity pressure is greater than or equal to 0.05 mT and less than or equal to 5 mT.

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