Low dropout regulator for Hall sensor front-end circuit

Abstract

The invention provides a low-dropout voltage stabilizer for a Hall sensor front-end circuit. The low-dropout voltage stabilizer comprises a closed-loop control system, a voltage input end and a voltage output end, the closed-loop control system comprises a bias sub-circuit, a charge pump and a feedback sub-circuit; the bias sub-circuit generates initial bias voltage, the charge pump generates multiple bias voltage according to the initial bias voltage and outputs the multiple bias voltage, and the feedback sub-circuit monitors the multiple bias voltage and feeds back the multiple bias voltage to the bias sub-circuit. A closed-loop control system feeds back and regulates the gate-source voltage of a cascaded N-type power tube in real time when the power supply voltage fluctuates or external interference occurs, so that the output voltage of a voltage output end Vout is kept stable, accurate control over the multiple bias voltage output by a charge pump is achieved, the power supply rejection ratio is increased, the anti-jamming capability of the LDO is improved, and the power supply rejection ratio of the LDO is increased. Especially under the condition of large power supply fluctuation, the stability of the output voltage can be maintained, and then the reliability and the anti-interference capability of the Hall sensor front-end circuit are ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, and in particular to a low dropout regulator for a Hall sensor front-end circuit. TECHNICAL BACKGROUND

[0002] Currently, the rapid development of system-on-chip has made it possible to integrate low dropout regulators and their load circuits on the same chip. This integration technology brings significant advantages, including a reduction in module size and a reduction in non-ideal noise caused by bond wires and printed circuit board traces. In particular, in noise-sensitive circuit applications, such as Hall sensor analog front-end circuits, a well-regulated voltage is required to have a high degree of immunity to switching ripple and noise-induced power variations in power management. In addition, in complex electromagnetic environments, such as automotive application scenarios, sensing elements and signal conditioning circuits are susceptible to crosstalk and ripple interference. Therefore, the high power supply rejection of the on-chip LDO (Low Dropout Regulator) has become a research hotspot. The power supply rejection ratio of the LDO is mainly related to the bandwidth of the feedback path, the DC gain of the gain stage, and the output transconductance of the transistor. Typically, an LDO with a typical input voltage range has an input voltage close to the output voltage, which means that it has a small voltage drop to improve power efficiency. However, typical automotive applications require the LDO to adapt to an input voltage range from 6V to 30V, while operating in a temperature range of -40℃ to 150℃. Therefore, designing an LDO that meets these requirements is crucial for automotive applications.

[0003] A conventional low dropout regulator chip includes an input voltage, an output voltage, and a ground, where the input voltage provides power for the error amplifier, the reference circuit, and the power transistor. The chip peripheral circuit includes a load at the output end. The error amplifier and the power transistor are the core modules of the LDO chip, and they form a negative feedback system through a resistive feedback network. When the output voltage drops, the resistive feedback network sends the signal change to the non-inverting terminal of the error amplifier, causing the input voltage of the error amplifier to rise, and then the error amplifier outputs an adjustment signal to drive the power transistor to provide more current, thereby increasing the output voltage of the LDO. Conversely, when the output voltage rises, the input voltage of the error amplifier will drop, and the adjustment signal output by the error amplifier will cause the power transistor to provide less current, thereby reducing the output voltage of the LDO. This process ensures that the LDO can maintain a stable output voltage even if the load conditions change. In this way, the LDO can effectively suppress external interference and internal changes to maintain the stability of the output voltage.

[0004] However, the aforementioned traditional low-dropout regulators have weak power supply rejection capabilities because the power supply needs to power the error amplifier, reference circuit, and power transistors. This makes the gate-source voltage of the power transistors susceptible to external interference. To overcome these problems, existing low-dropout regulators need to be improved to enhance their interference immunity and power supply rejection performance. Summary of the Invention

[0005] This invention provides a low-dropout regulator for the front-end circuit of a Hall sensor, designed to enhance anti-interference capability and improve power supply suppression performance.

[0006] This invention provides a low dropout voltage regulator for the front-end circuit of a Hall sensor, including a closed-loop control system, cascaded N-type power transistors, a voltage input terminal, and a voltage output terminal; The closed-loop control system includes a bias sub-circuit, a charge pump, and a feedback sub-circuit. The input terminal of the bias sub-circuit is connected to the voltage input terminal to generate an initial bias voltage and output it. The input terminal of the charge pump is connected to the output terminal of the bias sub-circuit, and is used to generate and output a multiple bias voltage based on the initial bias voltage. The input terminal of the feedback sub-circuit is connected to the output terminal of the charge pump, and the output terminal is connected to the bias sub-circuit. It is used to monitor the multiple bias voltage output by the charge pump and feed it back to the bias sub-circuit. The control terminal of the cascaded N-type power transistor is connected to the output terminal of the charge pump, and the output terminal is connected to the voltage output terminal, for outputting the gate-source voltage according to the multiple bias voltage; The closed-loop control system adjusts the gate-source voltage of the cascaded N-type power transistors in real time to maintain the voltage output V in response to power supply voltage fluctuations or external interference. out The output voltage is stable.

[0007] Optionally, the closed-loop control system further includes an oscillator; the input terminal of the oscillator is connected to the output terminal of the bias sub-circuit, and the output terminal of the oscillator is connected to the input terminal of the charge pump, for receiving the initial bias voltage and generating a clock signal according to the initial bias voltage to adjust the operating frequency of the charge pump.

[0008] Optionally, the feedback sub-circuit includes a cascaded feedback MOSFET and a control MOSFET; In this configuration, the drain of the first feedback MOS transistor in the cascaded feedback MOS transistors is connected to the output terminal of the charge pump, and the source is connected to the drain of the next feedback MOS transistor; the drain of the last feedback MOS transistor in the cascaded feedback MOS transistors is connected to the source of the previous feedback MOS transistor, and the source is grounded; the gate of each feedback MOS transistor in the cascaded feedback MOS transistors is shorted to its drain. The gate of the control MOS transistor is connected to the gate of the last feedback MOS transistor in the cascaded feedback MOS transistors, the drain is connected to the bias sub-circuit, and the source is grounded, which is used to transmit the multiple bias voltage to the bias sub-circuit.

[0009] Optionally, the cascaded N-type power transistors include a first NMOS transistor and a second NMOS transistor, wherein the drain of the first NMOS transistor is connected to the voltage input terminal and the gate is connected to the output terminal of the charge pump; the drain of the second NMOS transistor is connected to the source of the first NMOS transistor, the gate is connected to the output terminal of the charge pump, and the source is connected to the voltage output terminal. The cascaded N-type power transistors stabilize the multiple bias voltage output by the charge pump through the first NMOS transistor and the second NMOS transistor.

[0010] Optionally, the low dropout regulator further includes a feedback control loop, which is connected to the voltage output terminal, the output terminal of the charge pump, and the cascaded N-type power transistor. The feedback control loop is used to generate a feedback control voltage and control the gate-source voltage rise and fall of the cascaded N-type power transistor according to the multiple bias voltage.

[0011] Optionally, the feedback control loop includes: A resistor feedback sub-circuit, connected to the cascaded N-type power transistor, is used to divide the gate-source voltage output by the cascaded N-type power transistor to generate a feedback voltage divider signal; A voltage reference sub-circuit, connected to the cascaded N-type power transistor and the voltage output terminal, is used to generate a reference voltage signal based on the feedback voltage divider signal; The feedback gain stage sub-circuit, connected to the voltage reference sub-circuit, the charge pump, and the cascaded N-type power transistor, is used to generate a feedback control voltage signal based on the reference voltage signal and to control the rise and fall of the gate-source voltage of the cascaded N-type power transistor based on the multiple bias voltage.

[0012] Optionally, the resistor feedback sub-circuit includes a first feedback resistor and a second feedback resistor connected in series. One end of the first feedback resistor is connected to the output terminal of the cascaded N-type power transistor and the voltage output terminal, and the other end is connected to the voltage reference sub-circuit and one end of the second feedback resistor. The other end of the second feedback resistor is grounded.

[0013] Optionally, the voltage reference sub-circuit includes a first transistor, a first resistor, a second resistor, a second transistor, a third transistor, and a third resistor; wherein, the collector of the first transistor is connected to the voltage output terminal, the base is connected between the first feedback resistor and the second feedback resistor, and the emitter is connected to one end of the first resistor and one end of the second resistor; the other end of the first resistor is connected to the collector of the second transistor; the other end of the second resistor is connected to the collector of the third transistor; the base of the second transistor is connected to the base of the third transistor, and the emitter is grounded through the third resistor; the emitter of the third transistor is grounded, and the base and collector of the third transistor are short-circuited.

[0014] Optionally, the cascaded N-type power transistors include a first NMOS transistor and a second NMOS transistor; the feedback gain stage circuit includes a fourth transistor, a fourth resistor, a first capacitor, and a fifth resistor; wherein, the base of the fourth transistor is connected between the first resistor and the collector of the second transistor, the collector is connected to the gate of the second NMOS transistor, and the emitter is grounded; the fourth resistor and the first capacitor are connected in series between the collector and the base of the fourth transistor; one end of the fifth resistor is connected between the output of the charge pump and the gate of the first NMOS transistor, and the other end is connected between the gate of the second NMOS transistor and the collector of the fourth transistor.

[0015] Optionally, after the gate-source voltage of the cascaded N-type power transistor is adjusted by the feedback control loop, the output voltage at the voltage output terminal is calculated using the following formula: (1) (2) (3) From formulas (1), (2), and (3), we get: Wherein, Vout represents the output voltage of the voltage output terminal; R F1 This indicates the resistance value of the first feedback resistor; R F2 This indicates the resistance value of the second feedback resistor; V BE1 This indicates the voltage value between the base and emitter of the second transistor; V BE2 This indicates the voltage value between the base and emitter of the third transistor; V BE4 This indicates the voltage between the base and emitter of the first transistor; R W1 This indicates the resistance value of the third resistor; R W3 This indicates the resistance value of the second resistor; V T Indicates the thermal voltage coefficient; n represents the ratio of the emitter area of ​​the third transistor to the emitter area of ​​the second transistor.

[0016] The beneficial effects of this invention are: A low-dropout regulator for a Hall sensor front-end circuit is provided. The regulator includes a voltage input terminal, a voltage output terminal, a closed-loop control system, and a cascaded N-type power transistor. The closed-loop control system includes a bias sub-circuit, a charge pump, and a feedback sub-circuit. The bias sub-circuit generates a bias voltage. The charge pump generates and outputs a multiple of the bias voltage. The feedback sub-circuit monitors the multiple bias voltage output by the charge pump and feeds it back to the bias sub-circuit. The control terminal of the cascaded N-type power transistor is connected to the output terminal of the charge pump, and its output terminal is connected to the voltage output terminal. The closed-loop control system adjusts the gate-source voltage of the cascaded N-type power transistor in real time to maintain the voltage output V when the power supply voltage fluctuates or external interference occurs, thereby maintaining the voltage output V. out The output voltage is stable.

[0017] Thus, by integrating a closed-loop control system, precise control of the charge pump output bias voltage is achieved, thereby enabling precise control of the gate-source voltage of the cascaded N-type power transistor. This enhances the power supply rejection ratio and improves the anti-interference capability of the LDO. Especially under conditions of large power supply fluctuations, it can maintain the stability of the output voltage, thereby ensuring the reliability and anti-interference capability of the Hall sensor front-end circuit.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0019] Figure 1 This invention provides a structural block diagram of a low-dropout regulator for the front-end circuit of a Hall sensor.

[0020] Figure 2 This invention provides a structural block diagram of another low-dropout regulator for the front-end circuit of a Hall sensor.

[0021] Figure 3 for Figure 2 The diagram shows a specific circuit diagram of a low-dropout regulator used in the front-end circuit of a Hall sensor. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses consistent with some aspects of the invention as detailed in the appended claims.

[0023] The terminology used in this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. Unless otherwise defined, the technical or scientific terms used in this invention should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. If only "an" is referred to, it will be separately stated. "A plurality" or "several" indicates two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are for illustrative purposes only and are not limited to a location or spatial orientation. Terms such as "comprising" or "including" mean that the elements or objects preceding "comprising" encompass the elements or objects listed following "comprising" or "including" and their equivalents, but do not exclude other elements or objects. The terms “connection” or “link” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0024] like Figure 1 As shown, the low-dropout regulator 1 for the front-end circuit of a Hall sensor provided by the present invention includes a voltage input terminal Vin for providing power supply voltage and a voltage output terminal V. outThe system comprises a closed-loop control system 2 and a cascaded N-type power transistor 3. The closed-loop control system 2 includes a bias sub-circuit 4, a charge pump 5, and a feedback sub-circuit 6. The input terminal of the bias sub-circuit 4 is connected to the voltage input terminal Vin, used to generate and output an initial bias voltage based on the power supply voltage. The input terminal of the charge pump 5 is connected to the output terminal of the bias sub-circuit 4, used to generate and output a voltage multiple of the initial bias voltage (i.e., a multiple bias voltage). The input terminal of the feedback sub-circuit 6 is connected to the output terminal of the charge pump 5, and its output terminal is connected to the input terminal of the bias sub-circuit 4, used to monitor the multiple bias voltage output by the charge pump 5 and feed it back to the bias sub-circuit 4. The control terminal of the cascaded N-type power transistor 3 is connected to the output terminal of the charge pump 5, and its output terminal is connected to the voltage output terminal V. out This is used to output the gate-source voltage based on a multiple bias voltage. The closed-loop control system 2 adjusts the gate-source voltage of the cascaded N-type power transistor 3 in real time to maintain the voltage output V when the power supply voltage fluctuates or external interference occurs. out The output voltage is stable. This means that the feedback sub-circuit 6 monitors the multiple bias voltage output by the charge pump 5. If the multiple bias voltage is higher than a preset value, the feedback signal triggers the bias sub-circuit 4 to reduce the initial bias voltage, thereby reducing the multiple bias voltage output by the charge pump 5 and ultimately decreasing the gate-source voltage of the cascaded N-type power transistor 3. Conversely, the opposite is true. Thus, through the integrated closed-loop control system 2, precise control of the multiple bias voltage output by the charge pump 5 is achieved, thereby achieving precise control of the gate-source voltage of the cascaded N-type power transistor 3. This enhances the power supply rejection ratio and improves the LDO's anti-interference capability, especially under conditions of large power supply fluctuations, maintaining the stability of the output voltage and ensuring the reliability and anti-interference capability of the Hall sensor front-end circuit.

[0025] Because the voltage input of the low-dropout regulator needs to power the internal error amplifier, reference circuit, and P-type power transistor, the gate-source voltage of the power transistor is easily affected by external interference, resulting in weak power supply rejection ratio. To overcome these problems, this embodiment uses a closed-loop control system 2 to achieve precise control of the gate-source voltage of the cascaded N-type power transistor 3, thus avoiding large changes in the gate-source voltage of the cascaded N-type power transistor 3 caused by fluctuations in the power supply voltage input at the voltage input terminal Vin. Specifically, the feedback sub-circuit 6 of the closed-loop control system 2 monitors the multiple bias voltage output by the charge pump 5 in real time and feeds it back to the bias sub-circuit 4. When the detected multiple bias voltage change is large, it indicates that the initial bias voltage is large, which indicates large power supply voltage fluctuations. Therefore, by adjusting the initial bias voltage, the multiple bias voltage output by the charge pump 5 can be stabilized, thereby achieving precise control of the gate-source voltage of the cascaded N-type power transistor 3, ensuring a constant gate-source voltage of the cascaded N-type power transistor 3, and enhancing the power supply rejection ratio. In addition, the multiple bias voltage output by charge pump 5 is used as the gate control voltage of cascaded N-type power transistor 3, thus avoiding the problem that cascaded N-type power transistor 3 and its subsequent external circuits may not work properly when the power supply voltage is low.

[0026] like Figure 2 As shown, in some embodiments, the closed-loop control system 2 further includes an oscillator 7; the input terminal of the oscillator 7 is connected to the output terminal of the bias sub-circuit 4, and the output terminal is connected to the input terminal of the charge pump 5, for receiving an initial bias voltage and generating a clock signal according to the initial bias voltage to adjust the operating frequency of the charge pump 5.

[0027] In this embodiment, the main function of oscillator 7 is to adjust the operating frequency of the charge pump according to a clock signal. During this process, oscillator 7 uses the initial bias voltage and initial bias current provided by bias sub-circuit 4 to generate a clock signal. This clock signal is then transmitted to charge pump 5 to adjust its operating frequency. Specifically, during adjustment, oscillator 7 adjusts the frequency according to the multiple bias voltage required by charge pump 5. In this way, oscillator 7 ensures that charge pump 5 operates at the required frequency, thereby effectively and precisely adjusting the multiple bias voltage output by charge pump 5. This interaction ensures that charge pump 5 can stably provide the required voltage, which is crucial for the stability and performance of the entire circuit system. By precisely controlling the operating frequency of charge pump 5, oscillator 7 and bias sub-circuit 4 jointly maintain the efficient operation of the circuit and the stable voltage output.

[0028] It should also be noted that oscillator 7 generates a clock signal based on the initial bias voltage provided by bias sub-circuit 4, and the clock signal frequency is positively correlated with the initial bias voltage: when V INWhen the initial bias voltage increases, the clock frequency increases, the boost efficiency of charge pump 5 improves, and the bias voltage is reduced by multiple times due to V. IN Increases excessively; when V IN When the clock frequency decreases, the charge pump 5 maintains the basic boost capability, ensuring that the multiple bias voltage is not lower than the conduction threshold of the cascaded N-type power transistor 3.

[0029] Combination Figure 2 , Figure 3As shown, in some embodiments, the bias sub-circuit 4 includes a first MOSFET MB1, a second MOSFET MB2, a third MOSFET MB3, a fourth MOSFET MB4, a fifth MOSFET MB5, a sixth MOSFET MB6, a seventh MOSFET MB7, an eighth MOSFET MH1, a ninth MOSFET MH2, a tenth MOSFET MH3, an eleventh MOSFET MH4, a twelfth MOSFET MH5, a thirteenth MOSFET MH6, a fourteenth MOSFET MH7, and a sixth resistor RB1, a seventh resistor RB2, and an eighth resistor RF3. The gate of the first MOSFET MB1 is grounded through the sixth resistor RB1, its source is grounded, and its drain is connected to the gate of the second MOSFET MB2. The source of the second MOSFET MB2 is connected to the gate of the first MOSFET MB1. The third MOSFET MB3 and the fourth MOSFET MB4 form a current mirror, and their gates are interconnected. Furthermore, the drain of the third MOSFET MB3 is connected to the gate of the second MOSFET MB2, and its source is connected to the voltage input terminal Vin; the drain of the fourth MOSFET MB4 is shorted to its gate and connected to the drain of the second MOSFET MB2, and its source is connected to the voltage input terminal Vin. The gate and source of the fifth MOSFET MB5 are both connected between the gates of the third MOSFET MB3 and the fourth MOSFET MB4, and its drain is grounded. This fifth MOSFET MB5 serves as a key component in the startup circuit during initial power-up, raising its gate-source voltage to move the circuit away from the degeneracy point, thus improving circuit reliability. The gate of the sixth MOSFET MB6 is connected to the gate of the fifth MOSFET MB5, and its source is connected to the voltage input terminal Vin. The gate of the seventh MOSFET MB7 is connected to the gate of the fifth MOSFET MB5, its source is connected to the voltage input terminal Vin, and its drain is grounded. The gate of the eighth MOSFET MH1 is shorted to its drain, and its source is grounded. The source of the ninth MOSFET MH2 is connected to the drain of the eighth MOSFET MH1, its gate is shorted to its drain, and its drain is connected to the drain of the sixth MOSFET MB6. The source of the tenth MOSFET MH3 is grounded, its gate is connected to feedback sub-circuit 6, and it is also connected to the gate of the ninth MOSFET MH2. Its drain is connected to the drain of the eleventh MOSFET MH4. Eleventh MOSFET MH4 and twelfth MOSFET MH5 form a current mirror, with their gates interconnected. Furthermore, the gate of eleventh MOSFET MH4 is shorted to its drain, and its source is connected to the voltage input terminal Vin. The source of twelfth MOSFET MH5 is connected to the voltage input terminal Vin, and its drain is connected to the drain of thirteenth MOSFET MH6 via the seventh resistor RB2, and is also connected to the input terminal of charge pump 5. In this embodiment, the bias sub-circuit 4 outputs a bias voltage to charge pump 5 through the drain of twelfth MOSFET MH5. Thirteenth MOSFET MH6 and fourteenth MOSFET MH7 form a current mirror, with their gates interconnected. Furthermore, the gate of thirteenth MOSFET MH6 is shorted to its drain, and its source is grounded. The drain of fourteenth MOSFET MH7 is connected to the input terminal of oscillator 7, and its source is grounded.In this embodiment, the bias sub-circuit 4 outputs a bias voltage and bias current to the oscillator 7 through the drain of the fourteenth MOSFET MH7. One end of the eighth resistor RF3 is connected to the gate of the ninth MOSFET MH2, and the other end is connected to the gate of the tenth MOSFET MH3 and the feedback sub-circuit 6. This eighth resistor RF3 is used to dynamically adjust the bias voltage. Specifically, if the bias voltage output by the charge pump 5 is higher than the bias voltage, the voltage output by the feedback sub-circuit 6 increases, and the corresponding current output increases. At this time, the voltage drop of the eighth resistor RF3 increases, which in turn reduces the bias voltage input to the charge pump 5.

[0030] like Figure 3 As shown, in some embodiments, the feedback sub-circuit 6 includes a cascaded feedback MOS transistor and a control MOS transistor MF1; wherein, the drain of the first feedback MOS transistor in the cascaded feedback MOS transistor is connected to the output terminal of the charge pump 5, and the source is connected to the drain of the next feedback MOS transistor; the drain of the last feedback MOS transistor in the cascaded feedback MOS transistor is connected to the source of the previous feedback MOS transistor, and the source is grounded; the gate of each feedback MOS transistor in the cascaded feedback MOS transistor is shorted to its drain; the gate of the control MOS transistor MF1 is connected to the gate of the last feedback MOS transistor in the cascaded feedback MOS transistor, the drain is connected between the eighth resistor RF3 and the gate of the tenth MOS transistor MH3 in the bias sub-circuit 4, and the source is grounded.

[0031] Specifically, the cascaded feedback MOSFETs are formed by at least seven diode-connected feedback MOSFETs, namely, the first feedback MOSFET MD1 to the seventh feedback MOSFET MD7 connected in series. The first feedback MOSFET MD1 is the first feedback MOSFET mentioned above, and the seventh feedback MOSFET MD7 is the last feedback MOSFET mentioned above. The cascaded feedback MOSFETs are used to ensure the overall stability of the feedback sub-circuit 6 when the system operates in constant current mode. Thus, by constructing a feedback network consisting of cascaded feedback MOSFETs and a control MOSFET MF1, the multiple bias voltage output by the charge pump 5 can be monitored in real time. The design of this feedback network allows the monitored multiple bias voltage to be fed back to the bias sub-circuit 4 in a timely manner. When the power supply voltage fluctuates, this feedback mechanism allows the bias sub-circuit 4 to dynamically adjust its initial output bias voltage. This adjustment is to maintain the stability of the multiple bias voltage output by the charge pump 5, even when the power supply voltage changes. In this way, the bias sub-circuit 4 can react quickly to power supply voltage fluctuations, ensuring that the charge pump 5 continues to operate at predetermined performance parameters, thereby maintaining the stability and reliability of the entire circuit system. In short, the feedback network formed by the cascaded feedback MOSFET and the control MOSFET MF1 is crucial to ensuring that the charge pump 5 continues to operate stably when the power supply voltage changes. The dynamic adjustment of the bias sub-circuit 4 based on the feedback information is an important step in achieving stable voltage output.

[0032] In some embodiments, the cascaded N-type power transistors 3 specifically include a first NMOS transistor MPH1 and a second NMOS transistor MP1, wherein the drain of the first NMOS transistor MPH1 is connected to the voltage input terminal Vin, and the gate is connected to the output terminal of the charge pump 5; the drain of the second NMOS transistor MP1 is connected to the source of the first NMOS transistor MPH1, the gate is connected to the output terminal of the charge pump 5, and the source is connected to the voltage output terminal V. out The cascaded N-type power transistors stabilize the multiple bias voltage output by the charge pump through the first NMOS transistor and the second NMOS transistor.

[0033] In some embodiments, the cascaded N-type power transistor 3 adjusts its conduction state according to the multiple bias voltage output by the charge pump 5, and through the cascaded structure of the first NMOS transistor MPH1 and the second NMOS transistor MP1, the voltage input terminal V... IN After voltage reduction, the output is stabilized to V. OUT .

[0034] In this embodiment, to achieve the voltage reduction and regulation function of the circuit, a cascaded N-type power transistor 3, consisting of a first NMOS transistor MPH1 and a second NMOS transistor MP1, is designed. This configuration utilizes the characteristics of NMOS transistors, achieving voltage reduction and regulation through their cascading connection. In this configuration, the first NMOS transistor MPH1 and the second NMOS transistor MP1 cooperate, adjusting the output voltage by controlling the current flow between them. This invention utilizes the low on-resistance of NMOS transistors, effectively reducing the voltage drop in the circuit during conduction, thereby achieving voltage reduction and regulation. Through the parameters and connection method of these two NMOS transistors, the cascaded N-type power transistor 3 can provide a stable output voltage while reducing energy loss. This design not only improves the circuit efficiency but also ensures the stability and reliability of the circuit under various load conditions. Therefore, this cascaded N-type power transistor 3, consisting of the first NMOS transistor MPH1 and the second NMOS transistor MP1, is an important component for achieving efficient voltage reduction and regulation.

[0035] like Figure 1 As shown, in some embodiments, the low-dropout regulator 1 further includes a feedback control loop 8, which is connected to the voltage output terminal V. outThe output terminal of the charge pump 5 and the cascaded N-type power transistor 3 are used to generate a feedback control voltage signal and control the gate-source voltage of the cascaded N-type power transistor 3 to decrease or increase according to the multiple bias voltage. In this embodiment, the feedback control loop 8 is used to stably regulate the gate-source voltage output by the cascaded N-type power transistor 3. When the gate-source voltage output by the cascaded N-type power transistor 3 is high, the feedback control loop 8 generates a lower feedback control voltage signal, which in turn lowers the gate voltage of the cascaded N-type power transistor 3, thereby lowering the output gate-source voltage; conversely, when the gate-source voltage output by the cascaded N-type power transistor 3 is low, the feedback control loop 8 generates a higher feedback control voltage signal, which in turn raises the gate voltage of the cascaded N-type power transistor 3, thereby raising the output gate-source voltage.

[0036] The stable regulation of the gate-source voltage of the cascaded N-type power transistor 3 means that even under fluctuations in the power supply voltage, the cascaded N-type power transistor 3 can maintain its constant operating point, thereby ensuring the voltage output V. out The voltage output is undisturbed. In this embodiment, this is achieved through a feedback control loop 8, which monitors changes in the output voltage and adjusts the gate-source voltage of the cascaded N-type power transistor 3 accordingly to maintain a constant output voltage. In this way, efficient management of the gate-source voltage of the cascaded N-type power transistor 3 is achieved, ensuring the voltage output V remains constant. out Output voltage stability and reliability are crucial. This is essential for electronic devices and systems that require stable power supplies, as they rely on stable voltages for normal operation and performance. Furthermore, in this invention, the multiple bias voltage output by charge pump 5 provides the base gate voltage for the cascaded N-type power transistor, ensuring its operation in the conduction region. The feedback control voltage generated by feedback control loop 8 is superimposed on the base gate voltage. When the voltage output Vout fluctuates, the feedback control voltage finely adjusts the gate voltage in real time. When Vout increases, the feedback control voltage decreases, and the gate voltage decreases accordingly, weakening the conduction of the cascaded N-type power transistor and reducing the output current to pull down Vout. When Vout decreases, the reverse adjustment is applied to achieve output voltage stability.

[0037] Combination Figure 2 , Figure 3 As shown, in some embodiments, the feedback control loop 8 specifically includes a resistor feedback sub-circuit 9, a voltage reference sub-circuit 10, and a feedback gain stage sub-circuit 11. The resistor feedback sub-circuit 9 is connected to the output terminal of the cascaded N-type power transistor 3 and is used to accurately divide the gate-source voltage output by the cascaded N-type power transistor 3 to generate a feedback voltage divider signal; the voltage reference sub-circuit 10 is connected to the cascaded N-type power transistor 3 and the voltage output terminal V. outThe feedback gain stage sub-circuit 11 is used to generate a reference voltage signal based on the feedback voltage divider signal. The feedback gain stage sub-circuit 11 is connected to the voltage reference sub-circuit 10, the charge pump 5, and the cascaded N-type power transistor 3. It is used to generate the feedback control voltage signal based on the reference voltage signal and to control the gate-source voltage rise and fall of the cascaded N-type power transistor 3 based on the multiple bias voltage to stabilize the output voltage. That is, the multiple bias voltage output by the charge pump 5 provides the base gate voltage for the cascaded N-type power transistor 3, and the feedback control voltage generated by the feedback gain stage sub-circuit 11 and the base gate voltage are superimposed on the gate voltage: when V... OUT When the voltage increases, the feedback control voltage decreases, resulting in an overall decrease in the gate voltage after the voltage is increased. This weakens the conduction of the cascaded N-type power transistor 3, reducing the output current and pulling down V. OUT When V OUT When the voltage decreases, the feedback control voltage increases, and the overall gate voltage increases after the voltage is increased, the conduction is enhanced, and the output current increases to raise V. OUT The two work together to achieve V OUT Stablize.

[0038] In this embodiment, the resistive feedback sub-circuit 9 is connected to the cascaded N-type power transistor 3. Its main function is to perform precise voltage division on the gate-source voltage output by the cascaded N-type power transistor 3. Through resistive voltage division, the resistive feedback sub-circuit 9 can generate a feedback voltage divider, which is used to monitor and adjust the gate-source voltage of the cascaded N-type power transistor 3, i.e., the voltage output terminal V. out The output voltage. Specifically, the resistive feedback sub-circuit 9 divides the gate-source voltage through its internal resistor network to generate a feedback voltage proportional to the output voltage. This feedback voltage facilitates the stable regulation of the output of the cascaded N-type power transistor 3. When the voltage output terminal V... out When changes occur, the feedback voltage divider will also change accordingly. The system will adjust the operating state of the cascaded N-type power transistor 3 based on this change to ensure that the output voltage returns to the expected stable level. This ensures that the voltage output terminal V... out It can provide a stable voltage output, remaining stable even when the power supply voltage fluctuates. The introduction of resistive feedback sub-circuit 9 enhances the robustness and reliability of the circuit. In this way, the circuit can continuously provide a stable voltage output, meeting the power supply stability requirements of electronic devices.

[0039] like Figure 3 As shown, in some embodiments, the resistive feedback sub-circuit 9 includes a first feedback resistor RF1 and a second feedback resistor RF2 connected in series, wherein one end of the first feedback resistor RF1 is connected to the output terminal of the cascaded N-type power transistor 3 and the voltage output terminal V. outThe other end is connected to the voltage reference sub-circuit 10 and one end of the second feedback resistor RF2; the other end of the second feedback resistor RF2 is grounded.

[0040] In this embodiment, a first feedback resistor RF1 and a second feedback resistor RF2 are used to monitor and regulate the gate-source voltage output of the cascaded N-type power transistor 3. These two feedback resistors are configured as a resistor divider network to divide the gate-source voltage of the cascaded N-type power transistor 3. When the gate-source voltage passes through this resistor divider network, a voltage drop proportional to the original gate-source voltage is generated between the two feedback resistors; this is the feedback voltage divider. This feedback voltage divider is then used as a feedback signal in the feedback control system to monitor and adjust the output voltage of the cascaded N-type power transistor 3 in real time. The combination of the first feedback resistor RF1 and the second feedback resistor RF2 allows the system to dynamically adjust the operating state of the cascaded N-type power transistor 3 according to the actual output voltage. This adjustment mechanism helps maintain a stable output voltage. It should be noted that the feedback voltage divider ratio is determined by the resistance values ​​of the first feedback resistor RF1 and the second feedback resistor RF2. Those skilled in the art should consider the range of the output voltage and the system stability when designing the system.

[0041] Voltage reference sub-circuit 10 connects the cascaded N-type power transistor 3 and the voltage output terminal V. out This voltage reference circuit outputs voltage V. out The provided voltage powers the circuit, and a stable reference voltage is generated by a feedback voltage divider obtained by dividing the gate-source voltage output from the cascaded N-type power transistor 3. The voltage reference sub-circuit 10 receives voltage from the voltage output terminal V. out By taking the voltage and combining it with feedback voltage division, a constant reference voltage signal unaffected by power supply voltage fluctuations can be generated. This reference voltage signal is then used in the feedback gain stage sub-circuit 11 as a reference for gate-source voltage regulation and control.

[0042] In some embodiments, such as Figure 3As shown, the voltage reference sub-circuit 10 includes a first transistor Q1, a first resistor RW2, a second resistor RW3, a second transistor Q2, a third transistor Q3, and a third resistor RW1. The collector of the first transistor Q1 is connected to the voltage output terminal VOUT, its base is connected between the first feedback resistor RF1 and the second feedback resistor RF2, and its emitter is connected between one end of the first resistor RW2 and one end of the second resistor RW3. The other end of the first resistor RW2 is connected to the collector of the second transistor Q2. The other end of the second resistor RW3 is connected to the collector of the third transistor Q3. The base of the second transistor Q2 is connected to the base of the third transistor Q3, and its emitter is grounded through the third resistor RW1. The emitter of the third transistor Q3 is grounded, and the base and collector of the third transistor Q3 are short-circuited. The second transistor Q2 and the third transistor Q3 form a current mirror structure to ensure current matching, thereby stabilizing the reference voltage signal. In this embodiment, the first transistor Q1, the first resistor RW2, the second resistor RW3, the second transistor Q2, the third transistor Q3, and the third resistor RW1 are used to ensure that the voltage reference sub-circuit 10 can generate a stable reference voltage signal.

[0043] The feedback gain stage sub-circuit 11 is connected to the voltage reference sub-circuit 10, the charge pump 5, and the cascaded N-type power transistor 3. It generates a feedback control voltage based on the reference voltage signal and controls the gate-source voltage of the cascaded N-type power transistor to decrease or increase based on the multiple bias voltage, thereby stabilizing the output voltage. The feedback gain stage sub-circuit 11 ensures that the cascaded N-type power transistor 3 can automatically adjust and maintain a stable gate-source voltage, even under varying power supply voltage conditions.

[0044] In some embodiments, such as Figure 3As shown, the feedback gain stage sub-circuit 11 includes a fourth transistor Q4, a fourth resistor RM, a first capacitor CM, and a fifth resistor RG. The base of the fourth transistor Q4 is connected between the first resistor RM and the collector of the second transistor Q2, the collector is connected to the gate of the second NMOS transistor MP1, and the emitter is grounded. The fourth resistor RM and the first capacitor CM are connected in series between the collector and base of the fourth transistor Q4. One end of the fifth resistor RG is connected between the output terminal of the charge pump 5 and the gate of the first NMOS transistor MPH1, and the other end is connected between the gate of the second NMOS transistor MP1 and the collector of the fourth transistor Q4. In this embodiment, through the fourth transistor Q4, the fourth resistor RM, the first capacitor CM, and the fifth resistor RG, the feedback gain stage sub-circuit 11 can effectively generate a feedback control voltage based on the reference voltage and adjust the gate-source voltage of the cascaded N-type power transistor 3 according to the multiple bias voltage to maintain a stable output at the voltage output terminal VOUT.

[0045] In this invention, through the synergistic effect of the resistor feedback sub-circuit 9, the voltage reference sub-circuit 10, and the feedback gain stage sub-circuit 11, the feedback control loop 8 can not only stably regulate the gate-source voltage of the cascaded N-type power transistor 3, but also reduce the impact of output ripple on other parts of the circuit, which is beneficial to the reliability of the circuit.

[0046] In some embodiments, after the gate-source voltage of the cascaded N-type power transistor 3 is adjusted by the feedback control loop 8, the voltage output terminal V out The formula for calculating the output voltage is: (1) (2) (3) From formulas (1), (2), and (3), we get: Wherein, Vout represents the output voltage of the voltage output terminal; R F1 This indicates the resistance value of the first feedback resistor RF1; R F2 This indicates the resistance value of the second feedback resistor RF2; V BE1 This indicates the voltage between the base and emitter of transistor Q2. V BE2 This indicates the voltage between the base and emitter of the third transistor Q3; V BE4 This represents the voltage between the base and emitter of the first transistor Q1; RW1 This indicates the resistance value of the third resistor, RW1. R W3 This indicates the resistance value of the second resistor, RW3. V T It represents the thermal voltage coefficient, a commonly used temperature-voltage equivalent in electrical engineering; n represents the ratio of the emitter area of ​​the third transistor to the emitter area of ​​the second transistor.

[0047] From the above formula, it can be seen that the voltage output terminal V out The output voltage is independent of the power supply voltage input to the voltage input terminal Vin. This means that regardless of any changes or fluctuations in the power supply voltage Vin, the output voltage V will remain constant. out Both can stably output voltage, thus effectively isolating the voltage fluctuations at the input terminal Vin from the voltage output terminal V. out In short, the circuit design of this invention ensures the stability and independence of the output voltage, making it unaffected by power supply voltage fluctuations at the voltage input terminal Vin, and guaranteeing the voltage output terminal V. out The output voltage is constant. This characteristic is especially important in power supply design because it ensures that electronic devices or systems can still operate normally and perform as expected when faced with unstable power supply voltages.

[0048] In some embodiments, the low-dropout regulator 1 further includes a load resistor RL and a load capacitor RC. Specifically, the load resistor RL and the load capacitor RC are connected in parallel and connected to the voltage output terminal V. out Between and ground. By setting the load resistor RL and load capacitor RC in the low dropout regulator 1, it serves as the voltage output terminal V. out The equivalent load ensures that it can maintain a stable voltage output when faced with various load changes in actual applications.

[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A low-dropout regulator for the front-end circuit of a Hall sensor, characterized in that, Includes a closed-loop control system, cascaded N-type power transistors, voltage input terminals, and voltage output terminals; The closed-loop control system includes a bias sub-circuit, a charge pump, and a feedback sub-circuit. The input terminal of the bias sub-circuit is connected to the voltage input terminal to generate and output an initial bias voltage; The input terminal of the charge pump is connected to the output terminal of the bias sub-circuit, and is used to generate and output a multiple bias voltage based on the initial bias voltage. The input terminal of the feedback sub-circuit is connected to the output terminal of the charge pump, and the output terminal is connected to the bias sub-circuit. It is used to monitor the multiple bias voltage output by the charge pump and feed it back to the bias sub-circuit. A cascaded N-type power transistor is used, wherein the control terminal of the cascaded N-type power transistor is connected to the output terminal of the charge pump, and the output terminal is connected to the voltage output terminal. The closed-loop control system adjusts the gate-source voltage of the cascaded N-type power transistors in real time to maintain a stable output voltage when the power supply voltage fluctuates or external interference occurs.

2. The low-dropout voltage regulator according to claim 1, characterized in that, The closed-loop control system further includes an oscillator; the input terminal of the oscillator is connected to the output terminal of the bias sub-circuit, and the output terminal of the oscillator is connected to the input terminal of the charge pump, for receiving the initial bias voltage and generating a clock signal according to the initial bias voltage to adjust the operating frequency of the charge pump.

3. The low-dropout voltage regulator according to claim 1, characterized in that, The feedback sub-circuit includes a cascaded feedback MOSFET and a control MOSFET, wherein: The drain of the first feedback MOS transistor in the cascaded feedback MOS transistors is connected to the output terminal of the charge pump, and the source is connected to the drain of the next feedback MOS transistor; the drain of the last feedback MOS transistor in the cascaded feedback MOS transistors is connected to the source of the previous feedback MOS transistor, and the source is grounded; the gate of each feedback MOS transistor in the cascaded feedback MOS transistors is shorted to its drain. The gate of the control MOS transistor is connected to the gate of the last feedback MOS transistor in the cascaded feedback MOS transistors, the drain is connected to the bias sub-circuit, and the source is grounded, which is used to transmit the multiple bias voltage to the bias sub-circuit.

4. The low-dropout voltage regulator according to claim 1, characterized in that, The cascaded N-type power transistors include a first NMOS transistor and a second NMOS transistor, wherein: The drain of the first NMOS transistor is connected to the voltage input terminal, and the gate is connected to the output terminal of the charge pump; The drain of the second NMOS transistor is connected to the source of the first NMOS transistor, the gate is connected to the output terminal of the charge pump, and the source is connected to the voltage output terminal V. out ; The cascaded N-type power transistors stabilize the multiple bias voltage output by the charge pump through the first NMOS transistor and the second NMOS transistor.

5. The low-dropout voltage regulator according to claim 1, characterized in that, The low dropout regulator also includes a feedback control loop, which is connected to the voltage output terminal, the output terminal of the charge pump, and the cascaded N-type power transistor. The feedback control loop is used to generate a feedback control voltage signal and control the gate-source voltage rise and fall of the cascaded N-type power transistor according to the multiple bias voltage.

6. The low-dropout voltage regulator according to claim 5, characterized in that, The feedback control loop includes: A resistor feedback sub-circuit, connected to the output terminal of the cascaded N-type power transistor, is used to divide the gate-source voltage output by the cascaded N-type power transistor to generate a feedback voltage divider signal; A voltage reference sub-circuit, connected to the cascaded N-type power transistor and the voltage output terminal, is used to generate a reference voltage signal based on the feedback voltage divider signal; The feedback gain stage sub-circuit, connected to the voltage reference sub-circuit, the charge pump, and the cascaded N-type power transistor, is used to generate the feedback control voltage signal based on the reference voltage signal and to control the gate-source voltage rise and fall of the cascaded N-type power transistor based on the multiple bias voltage.

7. The low-dropout voltage regulator according to claim 6, characterized in that, The resistor feedback sub-circuit includes a first feedback resistor and a second feedback resistor connected in series. One end of the first feedback resistor is connected to the output terminal of the cascaded N-type power transistor and the voltage output terminal, and the other end is connected to the voltage reference sub-circuit and one end of the second feedback resistor. The other end of the second feedback resistor is grounded.

8. The low-dropout voltage regulator according to claim 7, characterized in that, The voltage reference sub-circuit includes a first transistor, a first resistor, a second resistor, a second transistor, a third transistor, and a third resistor; wherein, the collector of the first transistor is connected to the voltage output terminal, the base is connected between the first feedback resistor and the second feedback resistor, and the emitter is connected between one end of the first resistor and one end of the second resistor; the other end of the first resistor is connected to the collector of the second transistor; the other end of the second resistor is connected to the collector of the third transistor; the base of the second transistor is connected to the base of the third transistor, and the emitter is grounded through the third resistor; the emitter of the third transistor is grounded, and the base and collector of the third transistor are short-circuited.

9. The low-dropout voltage regulator according to claim 8, characterized in that, The cascaded N-type power transistors include a first NMOS transistor and a second NMOS transistor; the feedback gain stage circuit includes a fourth transistor, a fourth resistor, a first capacitor, and a fifth resistor; wherein, the base of the fourth transistor is connected between the first resistor and the collector of the second transistor, the collector is connected to the gate of the second NMOS transistor, and the emitter is grounded; the fourth resistor and the first capacitor are connected in series between the collector and the base of the fourth transistor; one end of the fifth resistor is connected between the output of the charge pump and the gate of the first NMOS transistor, and the other end is connected between the gate of the second NMOS transistor and the collector of the fourth transistor.

10. The low-dropout voltage regulator according to claim 9, characterized in that, After the gate-source voltage of the cascaded N-type power transistor is adjusted by the feedback control loop, the formula for calculating the output voltage at the voltage output terminal is: ;(1) ; (2) ; (3) From formulas (1), (2), and (3), we get: Wherein, Vout represents the output voltage of the voltage output terminal; R F1 This indicates the resistance value of the first feedback resistor; R F2 This indicates the resistance value of the second feedback resistor; V BE1 This indicates the voltage value between the base and emitter of the second transistor; V BE2 This indicates the voltage value between the base and emitter of the third transistor; V BE4 This indicates the voltage between the base and emitter of the first transistor; R W1 This indicates the resistance value of the third resistor; R W3 This indicates the resistance value of the second resistor; V T Indicates the thermal voltage coefficient; n represents the ratio of the emitter area of ​​the third transistor to the emitter area of ​​the second transistor.

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