Curvature correction band gap reference device

Abstract

The invention discloses a curvature correction band-gap reference device, and the device comprises a band-gap reference core unit which is used for generating a reference current according to a bias voltage, and generating a reference voltage through the reference current; the curvature compensation unit is used for generating a positive temperature current and a zero temperature current based on the reference voltage, determining the magnitude of a compensation current according to the positive temperature current and the zero temperature current, and extracting a current with a corresponding magnitude from the reference current of the band-gap reference core unit as the compensation current; and the curvature error introduced by a high-order temperature term of the base-emitter voltage in the reference voltage is counteracted. Through the innovative high-order curvature compensation technology, the curvature error introduced by a triode base-emitter voltage high-order temperature item in traditional band-gap reference voltage is successfully eliminated, and the compensated reference voltage shows excellent temperature stability in a wide temperature range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a curvature correction bandgap reference device. Background Technology

[0002] Bandgap reference sources are widely used in various chips such as low-dropout linear regulators (LDOs), analog-to-digital converters (ADCs), and phase-locked loops (PLLs) to provide reference voltage and bias. As a core module in analog integrated circuits, the stability of the bandgap reference source's output voltage directly affects the overall performance and accuracy of the system. With the development of high-precision circuits, such as high-precision analog-to-digital converters and voltage regulators, higher requirements are placed on the temperature drift characteristics and anti-interference capabilities of bandgap references.

[0003] Traditional first-order temperature compensation is limited by the base-emitter voltage V of a transistor (BJT). BE The nonlinear term in the temperature coefficient makes it difficult to achieve a temperature drift below 10 ppm / ℃. To achieve a low temperature drift coefficient over a wide temperature range, researchers have proposed many compensation methods. One method involves using polycrystalline resistors and diffusion resistors with different temperature coefficients for curvature compensation. Some studies have focused on V... BE (T) Compensation for higher-order terms in the second-order Taylor expansion. Researchers employed a 5-segment piecewise curvature compensation to eliminate nonlinear terms. A combination of low-temperature exponential curvature compensation and high-temperature logarithmic curvature compensation was used to achieve a temperature drift of 5 ppm / ℃.

[0004] In the above compensation methods, V BE The nonlinear term Tln(T) in the measurement is not completely eliminated, resulting in an unsatisfactory temperature drift coefficient, which fails to meet the accuracy and temperature drift requirements in high-precision measurement. Summary of the Invention

[0005] To address the shortcomings of the prior art, the technical problem to be solved by the present invention is: to provide a method capable of eliminating V BE The higher-order temperature terms in the bandgap reference reduce the temperature drift coefficient of the bandgap reference and the curvature correction bandgap reference device.

[0006] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is: to provide a curvature correction bandgap reference device, comprising: The bandgap reference core unit is used to generate a reference current based on the bias voltage and to generate a reference voltage through the reference current. The curvature compensation unit is used to generate a positive temperature current and a zero temperature current based on the reference voltage, and to determine the magnitude of the compensation current according to the positive temperature current and the zero temperature current. It extracts a corresponding current from the reference current of the bandgap reference core unit as the compensation current to offset the curvature error introduced by the higher-order temperature term of the base-emitter voltage in the reference voltage.

[0007] Furthermore, the curvature compensation unit includes: A positive temperature current generating subunit is used to generate a positive temperature current based on the reference voltage; A zero-temperature current generating subunit is used to generate a zero-temperature current based on the reference voltage; The compensation subunit is used to receive the positive temperature current and the zero temperature current, determine the magnitude of the compensation current with high-order temperature characteristics based on the positive temperature current and the zero temperature current, and extract a corresponding current from the reference current in the bandgap reference core unit as the compensation current.

[0008] Furthermore, it also includes: The common-mode feedback unit is used to provide a stable bias voltage for the bandgap reference core unit, detect and stabilize the DC common-mode level in the bandgap reference core unit, and improve the power supply rejection ratio and output stability of the reference voltage source.

[0009] Furthermore, the bandgap reference core unit includes a first MOSFET M1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a first amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; the gate of the first MOSFET M1 is connected to a bias voltage V. F The source of the first MOSFET M1 is connected to the supply voltage AVDD. The drain of the first MOSFET M1 is electrically connected to the collector of the first transistor Q1 through the third resistor R3. The drain of the MOSFET M1 is also electrically connected to the collector of the second transistor through the fourth resistor R4. The base of the first transistor Q1 and the base of the second transistor Q2 are electrically connected as the output terminal of the bandgap reference core unit to output the reference voltage. The emitter of the first transistor Q1 is grounded through the first resistor R1 and the second resistor R2. The emitter of the second transistor Q2 is electrically connected between the first resistor R1 and the second resistor R2. The non-inverting input terminal of the first amplifier U1 is electrically connected to the collector of the second transistor Q2. The inverting input terminal of the first amplifier U1 is electrically connected to the collector of the first transistor Q1. The output terminal of the first amplifier U1 is electrically connected to the base of the first transistor Q1. Node Vc is electrically connected to the compensation current extraction terminal of the compensation subunit.

[0010] Furthermore, the positive temperature current generating subunit includes a sixth transistor Q6, a sixth resistor R6, a thirteenth MOSFET M13, and a fourteenth MOSFET M14. The base of the sixth transistor Q6 serves as the input terminal of the positive temperature current generating subunit, receiving the reference voltage. The emitter of the sixth transistor Q6 is grounded through the sixth resistor R6. The collector of the sixth transistor Q6 is electrically connected to the drain of the thirteenth MOSFET M13. The source of the thirteenth MOSFET M13 is connected to the supply voltage AVDD, and the gate of the thirteenth MOSFET M13 is electrically connected to the gate of the fourteenth MOSFET M14. The source of the fourteenth MOSFET M14 is connected to the supply voltage AVDD, and the drain of the fourteenth MOSFET M14 serves as the output terminal of the positive temperature current generating subunit, outputting a positive temperature current.

[0011] Furthermore, the zero-temperature current generating subunit includes a second amplifier U2, a seventh resistor R7, a fifteenth MOSFET M15, and a sixteenth MOSFET M16. The non-inverting input terminal of the second amplifier U2 serves as the input terminal of the zero-temperature current generating subunit, inputting the reference voltage. The inverting input terminal of the second amplifier U2 is electrically connected to the drain of the fifteenth MOSFET M15, and the output terminal of the second amplifier U2 is electrically connected to the gate of the fifteenth MOSFET M15. The source of the fifteenth MOSFET M15 is connected to the supply voltage AVDD, and the drain of the fifteenth MOSFET M15 is grounded through the seventh resistor R7. The gate of the sixteenth MOSFET M16 is electrically connected to the output terminal of the second amplifier U2, the source of the sixteenth MOSFET M16 is connected to the supply voltage AVDD, and the drain of the sixteenth MOSFET M16 serves as the output terminal of the zero-temperature current generating subunit, outputting a zero-temperature current.

[0012] Furthermore, the compensation subunit includes a fourth transistor Q4, a fifth transistor Q5, a third amplifier U3, a fifth resistor R5, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, and a twelfth MOSFET M12. The base and collector of the fourth transistor Q4 are electrically connected as the first input terminal of the compensation subunit, receiving a positive temperature current. The emitters of the fourth transistor Q4 and the fifth transistor Q5 are both grounded. The base and collector of the fifth transistor Q5 are electrically connected as the second input terminal of the compensation subunit, receiving a zero temperature current. The inverting input terminal of the third amplifier U3 is electrically connected to the collector of the fourth transistor Q4 through the fifth resistor R5. The non-inverting input terminal of the third amplifier U3 is electrically connected to the collector of the fifth transistor Q5. The output terminal of the third amplifier U3 is electrically connected to... A current mirror is formed between the gate of the sixth MOSFET M6 and the gate of the eighth MOSFET M8. The drain of the sixth MOSFET M6 is electrically connected to the source of the fifth MOSFET M5, and the source of the sixth MOSFET M6 is connected to the supply voltage AVDD. The drain of the fifth MOSFET M5 is electrically connected to the inverting input terminal of the third amplifier U3. The gate of the fifth MOSFET M5 is electrically connected to the gate of the seventh MOSFET M7. The drain of the seventh MOSFET M7 is electrically connected to the drain of the ninth MOSFET M9. The source of the seventh MOSFET M7 is electrically connected to the drain of the eighth MOSFET M8, and the source of the eighth MOSFET M8 is connected to the supply voltage AVDD. The ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, and the twelfth MOSFET M12 form a current mirror. The drain of the eleventh MOSFET serves as the compensation current extraction terminal of the compensation subunit and is electrically connected to the node Vc.

[0013] Furthermore, the common-mode feedback unit includes a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a seventh transistor Q7, an eighth transistor Q8, and a ninth transistor Q9. The source of the second MOSFET M2 is connected to the supply voltage AVDD, the drain of the second MOSFET M2 is electrically connected to the collectors of the seventh transistor Q7 and the eighth transistor Q8, and the gate of the second MOSFET M2 is electrically connected to the gate of the third MOSFET M3. The source of the third MOSFET M3 is connected to the supply voltage AVDD, and the drain of the third MOSFET M3 is electrically connected to the collector of the ninth transistor Q9, serving as the output terminal of the common-mode feedback unit to output the bias voltage V. FThe base of the seventh transistor Q7 is connected to the first sampling voltage as the first input terminal of the common-mode feedback unit, the base of the eighth transistor Q8 is connected to the second sampling voltage as the second input terminal of the common-mode feedback unit, the base of the ninth transistor Q9 is connected to the reference voltage, the emitters of the seventh transistor Q7, the eighth transistor Q8, and the ninth transistor Q9 are all electrically connected to the drain of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4 is connected to an external bias voltage, and the source of the fourth MOS transistor M4 is grounded.

[0014] Furthermore, it also includes: The adjustment unit is used to inject or extract an adjustable adjustment current into the bandgap reference core unit to correct the temperature coefficient deviation of the reference voltage.

[0015] Furthermore, the bandgap reference core unit is also provided with an eighth resistor R8 and a ninth resistor R9. The eighth resistor R8 is disposed between the drain of the first MOS transistor M1 and the first end of the third resistor R3, and the ninth resistor R9 is disposed between the drain of the first MOS transistor M1 and the first end of the fourth resistor R4. The adjustment unit is used to inject or extract adjustment current between the first end of the third resistor R3 and the second end of the eighth resistor R8, and between the first end of the fourth resistor R4 and the second end of the ninth resistor R9.

[0016] The curvature correction bandgap reference device of the present invention has at least the following beneficial effects: The present invention, through innovative high-order curvature compensation technology, successfully eliminates the curvature error introduced by the high-order temperature term of the transistor base-emitter voltage in traditional bandgap reference voltages. The compensated reference voltage exhibits excellent temperature stability over a wide temperature range, providing bias for precision systems such as data converters, low-dropout linear regulators, and phase-locked loops. Addressing the inherent process deviation problem in semiconductor manufacturing, the present invention introduces a trimming unit for trimming. By injecting or extracting an adjustable trimming current into the bandgap reference core unit, it can dynamically correct temperature coefficient deviations caused by process angle changes, improving performance consistency and production yield under different process conditions. The common-mode feedback unit, by detecting and stabilizing the DC common-mode level in the core unit, provides a stable bias voltage and operating point for the entire system, significantly improving the power supply rejection ratio and output stability of the reference voltage source, enabling it to effectively resist power supply noise and environmental interference, ensuring reliable operation in complex application scenarios. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a schematic diagram of an embodiment of the curvature correction bandgap reference device of the present invention.

[0018] Figure 2 This is a circuit diagram of one embodiment of the curvature correction bandgap reference device of the present invention.

[0019] Figure 3 The circuit diagram is for the positive temperature current generation sub-unit.

[0020] Figure 4 Circuit diagram of the zero-temperature current generation sub-unit.

[0021] Figure 5 This is a temperature characteristic curve of the reference voltage output by the bandgap reference core unit under different process angles before adjustment.

[0022] Figure 6 This is a temperature characteristic curve of the reference voltage output by the bandgap reference core unit under different process angles after adjustment. Detailed Implementation

[0023] The invention will now be further described with reference to the accompanying drawings.

[0024] A bandgap reference is obtained by weighted summation of two voltages with opposite temperature coefficients, resulting in a reference voltage with zero temperature coefficient. Typically, a negative temperature coefficient can be obtained from the base-emitter voltage of a transistor. Provided, however The temperature characteristic expression contains higher-order temperature terms. The temperature characteristic expression is as follows:

[0025] in, This represents the band gap energy of silicon at absolute zero (0 K). Represents thermodynamic temperature. This represents a specific temperature, and b is the logarithmic fitting coefficient. This represents a constant related to the process carrier mobility. This indicates the temperature dependence order of the transistor's collector current. When the collector current has a positive temperature coefficient... =1, when the collector current has a zero temperature coefficient. =0. In Since it contains first-order terms and logarithmic terms, this invention proposes a method for Tln(T) curvature compensation, namely, eliminating higher-order temperature terms.

[0026] Please see Figure 1 and Figure 2The curvature correction bandgap reference device of the present invention includes a bandgap reference core unit 100, a common-mode feedback unit 200, and a curvature compensation unit 300. The bandgap reference core unit 100 is used to generate a reference current based on a bias voltage, and to generate a reference voltage with first-order temperature compensation through the reference current. The common-mode feedback unit 200 is used to provide a stable bias voltage to the bandgap reference core unit 100, detect and stabilize the DC common-mode level in the bandgap reference core unit 100, and improve the power supply rejection ratio and output stability of the reference voltage source. The curvature compensation unit 300 is used to compensate for the reference voltage. Generate positive temperature current and zero-temperature current And based on the positive temperature current and zero-temperature current Determine the compensation current The magnitude of the current is determined by extracting a corresponding current from the reference current of the bandgap reference core unit 100 as a compensation current. To offset the reference voltage The curvature error is introduced by the higher-order temperature term of the base-emitter voltage.

[0027] Specifically, the bandgap reference core unit 100 may include a first MOSFET M1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a first amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first MOSFET M1 is a P-type MOSFET. The third resistor R3 and the fourth resistor R4 can be the same; in this embodiment, the third resistor R3 and the fourth resistor R4 are the same. The gate of the first MOSFET M1 is connected to a bias voltage V. F The source of the first MOSFET M1 is connected to the supply voltage AVDD. The drain of the first MOSFET M1 is electrically connected to the collector of the first transistor Q1 through a third resistor R3. The drain of the MOSFET M1 is also electrically connected to the collector of the second transistor through a fourth resistor R4. The base of the first transistor Q1 and the base of the second transistor Q2 are electrically connected, serving as the output terminal of the bandgap reference core unit 100 to output a reference voltage. The emitter of the first transistor Q1 is grounded through a first resistor R1 and a second resistor R2. The emitter of the second transistor Q2 is electrically connected between the first resistor R1 and the second resistor R2. The non-inverting input of the first amplifier U1 is electrically connected to the collector of the second transistor Q2, the inverting input of the first amplifier U1 is electrically connected to the collector of the first transistor Q1, the output of the first amplifier U1 is electrically connected to the base of the first transistor Q1, and node Vc is electrically connected to the compensation current extraction terminal of the compensation subunit 330. In this embodiment, a startup current flows into the base of the first transistor Q1. At that time, the bandgap reference core unit 100 starts to work.

[0028] Specifically, the common-mode feedback unit 200 may include a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a seventh transistor Q7, an eighth transistor Q8, and a ninth transistor Q9. Among them, the second MOSFET M2 and the third MOSFET M3 are P-type MOSFETs. The source of the second MOSFET M2 is connected to the supply voltage AVDD, the drain of the second MOSFET M2 is electrically connected to the collectors of the seventh transistor Q7 and the eighth transistor Q8, and the gate of the second MOSFET M2 is electrically connected to the gate of the third MOSFET M3. The source of the third MOSFET M3 is connected to the supply voltage AVDD, and the drain of the third MOSFET M3 is electrically connected to the collector of the ninth transistor Q9, serving as the output terminal of the common-mode feedback unit 200 to output a bias voltage V. F The base of the seventh transistor Q7 is electrically connected to node a as the first input terminal of the common-mode feedback unit 200 to receive the first sampling voltage VA (i.e., the voltage of node a). The base of the eighth transistor Q8 is electrically connected to node b as the second input terminal of the common-mode feedback unit 200 to receive the second sampling voltage VB (i.e., the voltage of node b). The base of the ninth transistor Q9 is connected to a reference voltage. The emitters of the seventh transistor Q7, the eighth transistor Q8, and the ninth transistor Q9 are all electrically connected to the drain of the fourth MOS transistor M4. The gate of the fourth MOS transistor M4 is connected to an external bias voltage, and the source of the fourth MOS transistor M4 is grounded.

[0029] The common-mode feedback unit 200 detects the DC common-mode level of key signal nodes (i.e., node a and node b) in the bandgap reference core unit 100 and compares it with the reference voltage connected to the base of the ninth transistor Q9. By comparing the values, the bias voltage V of the output can be dynamically adjusted. F This stabilizes the common-mode level of nodes a and b at a level determined by... At the set expected value, the drain output of the third MOSFET M3 is the bias voltage V. F When the common-mode level of VA and VB (VA+VB) / 2 drifts, if a high common-mode level is detected, the common-mode feedback unit 200 will reduce V. F Conversely, if the common-mode level is too low, V will increase. F Bias voltage V F The current is fed back to the gate of the first MOS transistor M1 in the bandgap reference core unit 100, which adjusts its current output, thereby acting on the voltage of node a and node b to counteract the initial drift.

[0030] In this embodiment, the emitter area ratio of the first transistor Q1 and the second transistor Q2 in the bandgap reference core unit 100 is n:1, which is used to generate a voltage difference proportional to temperature; by setting the ratio of the second resistor R2 to the first resistor R1, the reference voltage can be eliminated. The first-order temperature term in [the text]. The specific principle is as follows: Since the emitter area ratio of the first transistor Q1 to the second transistor Q2 is n:1, under the same collector current, they generate base-emitter... Different voltages result in a voltage difference. = ,this The voltage exhibits a positive temperature coefficient (PTAT). When applied across the first resistor R1, it generates a current that also has a positive temperature coefficient.

[0031] The first amplifier U1 clamps the node voltages VA and VB to the same value, therefore the current flowing through the first transistor Q1 and the second transistor Q2 is equal, twice the current. The current flows through the second resistor R2 and Forming a reference voltage with first-order compensation Substituting the above into the context Temperature characteristic expression replacement The obtained reference voltage as follows:

[0032] Therefore, the reference resistor It is a high-order polynomial related to temperature. By adjusting the ratio of the first resistor R1 to the second resistor R2, the problem can be eliminated. The first-order term in, at this time There is still a higher-order term Tln(T) in the equation, so a higher-order curvature compensation circuit (i.e., the curvature compensation unit 300 designed in this scheme) is needed to eliminate it.

[0033] The curvature compensation unit 300 may include a positive temperature current generating subunit 310, a zero temperature current generating subunit 320, and a compensation subunit 330. The positive temperature current generating subunit 310 is used to generate current based on the reference voltage. Generate positive temperature current The zero-temperature current generation subunit 320 is used to generate current based on the reference voltage. Generating zero-temperature current The compensation subunit 330 is used to receive the positive temperature current. and zero-temperature current According to the positive temperature current and zero-temperature current Determine the compensation current with high-order temperature characteristics (i.e., with a Tln(T) term). The size of the current is determined, and a corresponding current is drawn from the bandgap reference core unit 100 as a compensation current. .

[0034] For details, please refer to Figure 3 The positive temperature current generating subunit 310 may include a sixth transistor Q6, a sixth resistor R6, a thirteenth MOSFET M13, and a fourteenth MOSFET M14. The thirteenth MOSFET M13 and the fourteenth MOSFET M14 are P-type MOSFETs. The base of the sixth transistor Q6 serves as the input terminal of the positive temperature current generating subunit 310, where the reference voltage is input. The emitter of the sixth transistor Q6 is grounded through the sixth resistor R6, and the collector of the sixth transistor Q6 is electrically connected to the drain of the thirteenth MOSFET M13. The source of the thirteenth MOSFET M13 is connected to the supply voltage AVDD, and the gate of the thirteenth MOSFET M13 is electrically connected to the gate of the fourteenth MOSFET M14. The source of the fourteenth MOSFET M14 is connected to the supply voltage AVDD, and the drain of the fourteenth MOSFET M14 serves as the output terminal of the positive temperature current generating subunit 310, outputting a positive temperature current. .

[0035] For details, please refer to Figure 4 The zero-temperature current generating subunit 320 may include a second amplifier U2, a seventh resistor R7, a fifteenth MOSFET M15, and a sixteenth MOSFET M16. The fifteenth MOSFET M15 and the sixteenth MOSFET are P-type MOSFETs. The non-inverting input terminal of the second amplifier U2, M16, serves as the input terminal of the zero-temperature current generating subunit 320, where the reference voltage is input. The inverting input terminal of the second amplifier U2 is electrically connected to the drain of the fifteenth MOSFET M15, and the output terminal of the second amplifier U2 is electrically connected to the gate of the fifteenth MOSFET M15. The source of the fifteenth MOSFET M15 is connected to the supply voltage AVDD, and the drain of the fifteenth MOSFET M15 is grounded through the seventh resistor R7. The gate of the sixteenth MOSFET M16 is electrically connected to the output terminal of the second amplifier U2, the source of the sixteenth MOSFET M16 is connected to the supply voltage AVDD, and the drain of the sixteenth MOSFET M16 serves as the output terminal of the zero-temperature current generating subunit 320, outputting zero-temperature current. .

[0036] Specifically, the compensation subunit 330 may include a fourth transistor Q4, a fifth transistor Q5, a third amplifier U3, a fifth resistor R5, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, and a twelfth MOSFET M12. Among these, the fifth MOSFET M5, sixth MOSFET M6, seventh MOSFET M7, and eighth MOSFET M8 are P-type MOSFETs, while the ninth MOSFET M9, tenth MOSFET M10, eleventh MOSFET M11, and twelfth MOSFET M12 are N-type MOSFETs. The fourth transistor Q4 and the fifth transistor Q5 have the same emitter area. The base and collector of the fourth transistor Q4 are electrically connected, serving as the first input terminal of the compensation subunit 330, into which a positive temperature current is applied. The emitters of the fourth transistor Q4 and the fifth transistor Q5 are both grounded. The base and collector of the fifth transistor Q5 are electrically connected as the second input terminal of the compensation subunit 330, which is connected to a zero-temperature current. The inverting input of the third amplifier U3 is electrically connected to the collector of the fourth transistor Q4 through the fifth resistor R5. The non-inverting input of the third amplifier U3 is electrically connected to the collector of the fifth transistor Q5. The output of the third amplifier U3 is electrically connected between the gate of the sixth MOSFET M6 and the gate of the eighth MOSFET M8. The drain of the sixth MOSFET M6 is electrically connected to the source of the fifth MOSFET M5, and the source of the sixth MOSFET M6 is connected to the supply voltage AVDD. The drain of the fifth MOSFET M5 is electrically connected to the inverting input of the third amplifier U3. The gate of the fifth MOSFET M5 is electrically connected to the gate of the seventh MOSFET M7. The drain of the seventh MOSFET M7 is electrically connected to the drain of the ninth MOSFET M9. The source of the seventh MOSFET M7 is electrically connected to the drain of the eighth MOSFET M8, and the source of the eighth MOSFET M8 is connected to the supply voltage AVDD. The ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 form a current mirror. The drain of the eleventh MOS transistor serves as the compensation current extraction terminal of the compensation subunit 330 and is electrically connected to the node Vc. The current mirror structure is specifically as follows: the drain of the ninth MOS transistor M9 is electrically connected between the gate of the tenth MOS transistor M10 and the gate of the twelfth MOS transistor M12; the gate of the ninth MOS transistor M9 is electrically connected to the gate of the eleventh MOS transistor M11; and the source of the ninth MOS transistor M9 is electrically connected to the drain of the tenth MOS transistor M10. The source of the tenth MOS transistor M10 is grounded, and its gate is electrically connected to the gate of the twelfth MOS transistor M12. The source of the twelfth MOS transistor M12 is grounded, and its drain is electrically connected to the source of the eleventh MOS transistor M11. The drain of the eleventh MOS transistor M11 serves as the compensation current extraction terminal of the compensation subunit 330 and is electrically connected to node Vc to extract the compensation current. .

[0037] The working principle of the curvature compensation unit 300 is as follows: Zero-temperature current By using the reference voltage This current, generated when applied across a seventh resistor R7 with a very small temperature coefficient, can be approximated as a zero-temperature-coefficient current. Positive temperature current. By using the reference voltage The current generated is applied to the path formed by the sixth transistor Q6 and the sixth resistor R6, and has a positive temperature coefficient. The current flowing through the fourth transistor Q4 is approximately a positive temperature current. The current flowing through the fifth transistor Q5 is the zero-temperature current. Because the current-temperature characteristics of transistors Q4 and Q5, which have the same current-to-emitter area, are different, their base-emitter voltages are also different. The base-emitter voltage of transistor Q4 is expressed as:

[0038] The base-emitter voltage of transistor Q5 is expressed as:

[0039] V is transmitted through the third amplifier U3 D Voltage clamping of the node Therefore, the voltage difference generated across the fifth resistor R5 is:

[0040] A compensation current with Tln(T) is formed across the resistor. The compensation current is then extracted from node Vc of the bandgap reference core unit 100 after being replicated via a current mirror. ,offset Higher-order terms of neutral negative. Compensation current. The calculation formula is as follows:

[0041] Compensated reference voltage for:

[0042] Therefore, by properly setting the ratio of the first resistor R1 to the second resistor R2, the problem can be eliminated. The first-order term in the equation can be eliminated by setting mR2 / R5, thus eliminating the Tln(T) term. Therefore, this scheme utilizes the voltage difference generated by currents flowing through the bipolar transistor at different temperature coefficients to generate a Tln(T) term as compensation, which is achieved by adjusting the positive temperature current. Zero-temperature current The relative magnitudes of the current and the current mirror are used to adjust the shape of the compensation current curve. The compensation current is adjusted by changing the ratio m of the fifth resistor R5 and the current mirror. Size.

[0043] Due to the compensation There exists a first-order term Furthermore, due to process deviations and mismatch errors, transistors and resistors exhibit deviations, thus requiring the introduction of adjustment strategies to achieve the optimal temperature coefficient compensation point.

[0044] Based on the above analysis, in order to achieve the optimal temperature coefficient compensation point, as a preferred embodiment, the curvature correction bandgap reference device further includes a trimming unit 400, which is used to inject or extract an adjustable trimming current into the bandgap reference core unit 100. Correcting the reference voltage Temperature coefficient deviation. In this embodiment, the bandgap reference core unit 100 is further provided with an eighth resistor R8 and a ninth resistor R9, wherein the resistance values ​​of the eighth resistor R8 and the ninth resistor R9 can be the same. In this embodiment, the resistance values ​​of the eighth resistor R8 and the ninth resistor R9 are the same. The eighth resistor R8 is disposed between the drain of the first MOS transistor M1 and the first end of the third resistor R3, and the ninth resistor R9 is disposed between the drain of the first MOS transistor M1 and the first end of the fourth resistor R4. The trimming unit 400 is used to inject or extract trimming current between the first end of the third resistor R3 and the second end of the eighth resistor R8, and between the first end of the fourth resistor R4 and the second end of the ninth resistor R9, respectively. The adjustment unit 400 is an existing circuit structure, which will not be described in detail here.

[0045] This invention injects or extracts a trimming current with a positive temperature coefficient between the third resistor R3 and the eighth resistor R8, and between the fourth resistor R4 and the ninth resistor R9. The first-order coefficients are adjusted. Since the voltage VA at node a and the voltage VB at node b are clamped to the same potential, the two resistors on the two branches have the same voltage drop. For example, an adjustment current is injected into the left branch. , so that:

[0046] Solving the above equation yields... Thus, the adjusted version was obtained. :

[0047] Therefore, the current is adjusted by digital logic control. The magnitude and direction of the coefficients can be used to adjust the first-order coefficients. Characteristic tests were performed on the circuit with high-order curvature compensation completed before and after adjustment. With a supply voltage AVDD of 5V, the output voltage curves under different process angles before adjustment, within the range of -40~125℃, are shown below. Figure 5As shown, the temperature coefficient is 1.16 ppm / ℃ under the TT process angle; 3.66 ppm / ℃ under the SS process angle; and 3.07 ppm / ℃ under the FF process angle. This indicates that the compensated output voltage has high-order temperature compensation characteristics. The temperature coefficient is relatively small under TT, but requires adjustment under SS and FF process angles. The temperature drift curves after digital adjustment for different process angles are shown below. Figure 6 As shown, the temperature coefficient is 1.16 ppm / ℃ under the TT process angle; 1.33 ppm / ℃ under the SS process angle; and 1.16 ppm / ℃ under the FF process angle, indicating that the adjusted output voltage has a temperature coefficient of less than 1.4 ppm / ℃.

[0048] This invention successfully eliminates the curvature error introduced by the high-order temperature term of the transistor base-emitter voltage in traditional bandgap reference voltages through innovative high-order curvature compensation technology. The compensated reference voltage exhibits excellent temperature stability over a wide temperature range, providing bias for precision systems such as data converters, low-dropout linear regulators, and phase-locked loops. Addressing the inherent process deviations in semiconductor manufacturing, this invention introduces a trimming unit. By injecting or extracting an adjustable trimming current into the bandgap reference core unit, it dynamically corrects temperature coefficient deviations caused by process angle variations, improving performance consistency and production yield under different process conditions. The common-mode feedback unit detects and stabilizes the DC common-mode level in the core unit, providing a stable bias voltage and operating point for the entire system. This significantly improves the power supply rejection ratio and output stability of the reference voltage source, enabling it to effectively resist power supply noise and environmental interference, ensuring reliable operation in complex application scenarios.

[0049] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A curvature correction bandgap reference device, characterized in that, include: The bandgap reference core unit is used to generate a reference current based on the bias voltage and to generate a reference voltage through the reference current. The curvature compensation unit is used to generate a positive temperature current and a zero temperature current based on the reference voltage, and to determine the magnitude of the compensation current according to the positive temperature current and the zero temperature current. It extracts a corresponding current from the reference current of the bandgap reference core unit as the compensation current to offset the curvature error introduced by the higher-order temperature term of the base-emitter voltage in the reference voltage.

2. The curvature correction bandgap reference device as described in claim 1, characterized in that, The curvature compensation unit includes: A positive temperature current generating subunit is used to generate a positive temperature current based on the reference voltage; A zero-temperature current generating subunit is used to generate a zero-temperature current based on the reference voltage; The compensation subunit is used to receive the positive temperature current and the zero temperature current, determine the magnitude of the compensation current with high-order temperature characteristics based on the positive temperature current and the zero temperature current, and extract a corresponding current from the reference current in the bandgap reference core unit as the compensation current.

3. The curvature correction bandgap reference device as described in claim 1, characterized in that, Also includes: The common-mode feedback unit is used to provide a stable bias voltage for the bandgap reference core unit, detect and stabilize the DC common-mode level in the bandgap reference core unit, and improve the power supply rejection ratio and output stability of the reference voltage source.

4. The curvature correction bandgap reference device as described in claim 2, characterized in that: The bandgap reference core unit includes a first MOSFET M1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a first amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; the gate of the first MOSFET M1 is connected to a bias voltage V. F The source of the first MOSFET M1 is connected to the supply voltage AVDD. The drain of the first MOSFET M1 is electrically connected to the collector of the first transistor Q1 through the third resistor R3. The drain of the MOSFET M1 is also electrically connected to the collector of the second transistor through the fourth resistor R4. The base of the first transistor Q1 and the base of the second transistor Q2 are electrically connected as the output terminal of the bandgap reference core unit to output the reference voltage. The emitter of the first transistor Q1 is grounded through the first resistor R1 and the second resistor R2. The emitter of the second transistor Q2 is electrically connected between the first resistor R1 and the second resistor R2. The non-inverting input terminal of the first amplifier U1 is electrically connected to the collector of the second transistor Q2. The inverting input terminal of the first amplifier U1 is electrically connected to the collector of the first transistor Q1. The output terminal of the first amplifier U1 is electrically connected to the base of the first transistor Q1. Node Vc is electrically connected to the compensation current extraction terminal of the compensation subunit.

5. The curvature correction bandgap reference device as described in claim 2, characterized in that: The positive temperature current generating subunit includes a sixth transistor Q6, a sixth resistor R6, a thirteenth MOSFET M13, and a fourteenth MOSFET M14. The base of the sixth transistor Q6 serves as the input terminal of the positive temperature current generating subunit, receiving the reference voltage. The emitter of the sixth transistor Q6 is grounded through the sixth resistor R6. The collector of the sixth transistor Q6 is electrically connected to the drain of the thirteenth MOSFET M13. The source of the thirteenth MOSFET M13 is connected to the supply voltage AVDD, and the gate of the thirteenth MOSFET M13 is electrically connected to the gate of the fourteenth MOSFET M14. The source of the fourteenth MOSFET M14 is connected to the supply voltage AVDD, and the drain of the fourteenth MOSFET M14 serves as the output terminal of the positive temperature current generating subunit, outputting a positive temperature current.

6. The curvature correction bandgap reference device as described in claim 2, characterized in that: The zero-temperature current generating subunit includes a second amplifier U2, a seventh resistor R7, a fifteenth MOSFET M15, and a sixteenth MOSFET M16. The non-inverting input of the second amplifier U2 serves as the input of the zero-temperature current generating subunit, inputting the reference voltage. The inverting input of the second amplifier U2 is electrically connected to the drain of the fifteenth MOSFET M15, and the output of the second amplifier U2 is electrically connected to the gate of the fifteenth MOSFET M15. The source of the fifteenth MOSFET M15 is connected to the supply voltage AVDD, and the drain of the fifteenth MOSFET M15 is grounded through the seventh resistor R7. The gate of the sixteenth MOSFET M16 is electrically connected to the output of the second amplifier U2, the source of the sixteenth MOSFET M16 is connected to the supply voltage AVDD, and the drain of the sixteenth MOSFET M16 serves as the output of the zero-temperature current generating subunit, outputting a zero-temperature current.

7. The curvature correction bandgap reference device as described in claim 4, characterized in that: The compensation subunit includes a fourth transistor Q4, a fifth transistor Q5, a third amplifier U3, a fifth resistor R5, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, and a twelfth MOSFET M12. The base and collector of the fourth transistor Q4 are electrically connected as the first input terminal of the compensation subunit, receiving a positive temperature current. The emitters of both the fourth and fifth transistors Q4 and Q5 are grounded. The base and collector of the fifth transistor Q5 are electrically connected as the second input terminal of the compensation subunit, receiving a zero temperature current. The inverting input terminal of the third amplifier U3 is electrically connected to the collector of the fourth transistor Q4 through the fifth resistor R5. The non-inverting input terminal of the third amplifier U3 is electrically connected to the collector of the fifth transistor Q5. The output terminal of the third amplifier U3 is electrically connected to... The gate of the sixth MOS transistor M6 is connected to the gate of the eighth MOS transistor M8, and the drain of the sixth MOS transistor M6 is electrically connected to the source of the fifth MOS transistor M5. The source of the sixth MOS transistor M6 is connected to the supply voltage AVDD. The drain of the fifth MOS transistor M5 is electrically connected to the inverting input terminal of the third amplifier U3. The gate of the fifth MOS transistor M5 is electrically connected to the gate of the seventh MOS transistor M7. The drain of the seventh MOS transistor M7 is electrically connected to the drain of the ninth MOS transistor M9. The source of the seventh MOS transistor M7 is electrically connected to the drain of the eighth MOS transistor M8. The source of the eighth MOS transistor M8 is connected to the supply voltage AVDD. The ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, and the twelfth MOS transistor M12 form a current mirror. The drain of the eleventh MOS transistor serves as the compensation current extraction terminal of the compensation subunit and is electrically connected to the node Vc.

8. The curvature correction bandgap reference device as described in claim 3, characterized in that: The common-mode feedback unit includes a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a seventh transistor Q7, an eighth transistor Q8, and a ninth transistor Q9. The source of the second MOSFET M2 is connected to the power supply voltage AVDD. The drain of the second MOSFET M2 is electrically connected to the collectors of the seventh transistor Q7 and the eighth transistor Q8. The gate of the second MOSFET M2 is electrically connected to the gate of the third MOSFET M3. The source of the third MOSFET M3 is connected to the power supply voltage AVDD. The drain of the third MOSFET M3 is electrically connected to the collector of the ninth transistor Q9, serving as the output terminal of the common-mode feedback unit, which outputs a bias voltage V. F The base of the seventh transistor Q7 is connected to the first sampling voltage as the first input terminal of the common-mode feedback unit, the base of the eighth transistor Q8 is connected to the second sampling voltage as the second input terminal of the common-mode feedback unit, the base of the ninth transistor Q9 is connected to the reference voltage, the emitters of the seventh transistor Q7, the eighth transistor Q8, and the ninth transistor Q9 are all electrically connected to the drain of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4 is connected to an external bias voltage, and the source of the fourth MOS transistor M4 is grounded.

9. The curvature correction bandgap reference device as described in claim 4, characterized in that, Also includes: The adjustment unit is used to inject or extract an adjustable adjustment current into the bandgap reference core unit to correct the temperature coefficient deviation of the reference voltage.

10. The curvature correction bandgap reference device as described in claim 9, characterized in that: The bandgap reference core unit is also provided with an eighth resistor R8 and a ninth resistor R9. The eighth resistor R8 is disposed between the drain of the first MOS transistor M1 and the first end of the third resistor R3, and the ninth resistor R9 is disposed between the drain of the first MOS transistor M1 and the first end of the fourth resistor R4. The adjustment unit is used to inject or extract adjustment current between the first end of the third resistor R3 and the second end of the eighth resistor R8, and between the first end of the fourth resistor R4 and the second end of the ninth resistor R9.

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