Operational structure, processor, chip, data processing method and electronic equipment

Abstract

The invention relates to an operation structure, a processor, a chip, a data processing method and electronic equipment, belongs to the technical field of chips, can be compatible with multiplication and addition operation processing of integer data and floating point type data, and saves the layout area. The format processing module is used for performing format processing on integer or floating point type input data according to the data type of the input data to be processed; a multiply-add operation unit for performing multiply-add operations in response to different types of input data; wherein for floating point type input data, multiplication and addition operation processing is carried out through the multiplier unit, the adder unit and the floating point special operation unit; for integer input data, carrying out multiplication and addition operation processing through a multiplier unit and an adder unit, and forbidding a floating point special operation unit; and the data output unit is used for outputting a multiply-add operation result when the input data is integer, and outputting an operation result after adjusting the multiply-add operation result to be adaptive to a floating point type data format when the input data is floating point type.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the chip technical field, and in particular to an operation structure, a processor, a chip, a data processing method and an electronic device. BACKGROUND

[0002] In the field of high-performance computing such as scientific computing (such as celestial motion simulation, physical calculation, chemical calculation, weather prediction, etc.), artificial intelligence calculation or modeling, computer image processing, engineering calculation and financial data processing, a large number and high frequency of multiplication and addition operations of floating point and integer type data are one of the core requirements of chip computing power.

[0003] Taking an INT64 multiplication and addition operation corresponding to multiplication of two 32-bit integer (INT32) data and addition of 64-bit integer data, and an FP64 multiplication and addition operation corresponding to multiplication of two 64-bit floating point (FP64) data and addition of 64-bit floating point data as examples, in the related art, two independent operation architectures, an INT64 integer operation unit and an FP64 floating point operation unit, are usually set in a chip for the INT64 multiplication and addition operation and the FP64 multiplication and addition operation, respectively, each of which is configured with a dedicated multiplier, an adder and other core components. The multiplier and the adder are the largest part of the area in the calculation module, and in the case of increasing computing power demand, many independent operation units are usually instantiated in the chip to meet the high computing power demand of the chip, resulting in an increasing area of the chip, causing a series of problems such as high cost and low yield. SUMMARY

[0004] In order to at least solve the technical problem of a large area caused by the need to set independent operation units for processing integer and floating point data respectively in the related art, embodiments of the present disclosure provide an operation structure, a processor, a chip, a data processing method and an electronic device to compatibly process integer and floating point data based on the same operation structure, saving the layout area.

[0005] In a first aspect, embodiments of the present disclosure provide an operation structure, comprising: an input data processing unit, a multiply-add operation unit, and a data output unit. The input data processing unit is configured to perform format processing on input data to be processed according to a data type of the input data, the data type being an integer type or a floating-point type. The multiply-add operation unit is configured to perform multiply-add operation in response to input data of different types; wherein for floating-point input data, multiply-add operation processing is performed by a multiplier unit, an adder unit, and a floating-point dedicated operation unit; for integer input data, multiply-add operation processing is performed by the multiplier unit and the adder unit, and the floating-point dedicated operation unit is disabled. The data output unit is configured to output the multiply-add operation result when the input data is of the integer type, and to output the operation result after adjusting the multiply-add operation result to adapt to the floating-point data format when the input data is of the floating-point type.

[0006] In some embodiments, the input data processing unit is configured to perform sign bit extension on the input data of the integer type when the data type of the input data is the integer type, and to perform split sign bit, exponent bit, and mantissa bit processing on the input data of the floating-point type when the data type of the input data is the floating-point type.

[0007] In some embodiments, the input data to be processed includes a floating-point first input, a floating-point second input, and a floating-point third input, and the floating-point dedicated operation unit includes an exponent alignment unit and a normalization and rounding unit. The multiply-add operation processing by the multiplier unit, the adder unit, and the floating-point dedicated operation unit includes: The multiplier unit and the exponent alignment unit are configured to perform multiplication operation processing on the floating-point first input and the floating-point second input to obtain a floating-point multiplication operation result. The adder unit is configured to perform addition operation processing on the floating-point multiplication operation result and the floating-point third input to obtain a floating-point addition operation result. The normalization and rounding unit is configured to perform at least one of mantissa normalization processing and rounding processing on the floating-point addition operation result to obtain a floating-point operation result.

[0008] In some embodiments, the multiplier unit is configured to perform multiplication operation processing on a mantissa part of the floating-point first input and a mantissa part of the floating-point second input to obtain a floating-point mantissa multiplication result. The aforementioned exponent alignment unit is used to perform addition operations on the exponent portions of the first floating-point input and the second floating-point input to obtain a floating-point exponent addition result; and to perform alignment operations on the floating-point exponent addition result and the exponent portion of the third floating-point input to obtain an exponent alignment operation result; the alignment operation is based on aligning the larger of the floating-point exponent addition result and the exponent portion of the third input. The adder unit described above is used to perform mantissa shift adjustment on the mantissa portion corresponding to the smaller of the above floating-point exponent addition result and the exponent portion of the above floating-point third input, based on the above exponent alignment operation result, and to perform addition operation processing on the mantissa portion corresponding to the larger one to obtain a floating-point addition operation result; wherein, the mantissa portion corresponding to the smaller one is the mantissa portion of the above floating-point mantissa multiplication result or the third input.

[0009] In some embodiments, the multiply-add unit further includes: a sign bit operation unit and a representation conversion unit; The aforementioned sign bit operation unit is used to perform an XOR operation on the sign bits of the first floating-point input and the second floating-point input when the first floating-point input, the second floating-point input, and the third floating-point input are all signed data and are all represented using binary sign-magnitude representation, to obtain the sign bit multiplication result; and to concatenate the sign bit multiplication result with the floating-point mantissa multiplication result to obtain the signed floating-point mantissa multiplication result. The aforementioned representation conversion unit is used to convert the signed floating-point mantissa multiplication result and the floating-point third input into two's complement form and then input them to the adder unit for corresponding processing when the aforementioned floating-point first input, the aforementioned floating-point second input and the aforementioned floating-point third input are all signed data and are all represented using binary sign-magnitude representation.

[0010] In some embodiments, the multiply-add unit further includes a bit selection unit, which is used to select a corresponding input bit segment according to a first control signal and input it to the multiplier unit, the adder unit and the exponent alignment unit. The step of selecting the corresponding input bit segment according to the first control signal and inputting it into the multiplier unit, the adder unit, and the exponent alignment unit includes: responding to the first control signal generated based on the floating-point data type, selecting the first input bit segment corresponding to the mantissa portion of the floating-point first input and the mantissa portion of the floating-point second input and inputting it into the multiplier unit; selecting the second input bit segment corresponding to the mantissa portion of the floating-point third input and inputting it into the adder unit; and selecting the third input bit segment corresponding to the exponent portion of each of the floating-point first input, the floating-point second input, and the floating-point third input and inputting it into the exponent alignment unit.

[0011] In some embodiments, the above-described arithmetic structure further includes an input adjustment unit, which is used to perform at least one operation of negation and absolute value calculation on at least one of the floating-point first input, floating-point second input, and floating-point third input to obtain an adjusted result, and input the adjusted result as input data to the above-described multiply-accumulate arithmetic unit.

[0012] In some embodiments, the input data to be processed includes: a first integer input, a second integer input, and a third integer input. The multiplication-addition operation performed by the multiplier unit and the adder unit includes: Based on the multiplier unit, the first integer input and the second integer input are multiplied to obtain the integer multiplication result; based on the adder unit, the integer multiplication result and the third integer input are added to obtain the integer operation result.

[0013] In some embodiments, the multiply-add unit further includes: a sign bit operation unit and a representation conversion unit; The aforementioned sign bit operation unit is used to perform an XOR operation on the sign bits of the first integer input and the second integer input when the first integer input, the second integer input, and the third integer input are all signed data and are all represented using binary original code, to obtain the sign bit multiplication result; and to concatenate the sign bit multiplication result with the integer multiplication result to obtain the signed integer multiplication result. The aforementioned representation conversion unit is used to convert the signed integer multiplication result and the third integer input into two's complement form and then input them to the adder unit for corresponding processing when the first integer input, the second integer input, and the third integer input are all signed data and are all represented using binary sign-magnitude representation.

[0014] In some embodiments, the multiply-add unit further includes a bit selection unit, which is used to select a corresponding input bit segment according to the second control signal and input it to the multiplier unit and the adder unit. Selecting the corresponding input bit segment according to the second control signal and inputting it into the multiplier unit and the adder unit includes: in response to the second control signal generated based on the integer data type, selecting the fourth input bit segment corresponding to all data of the first integer input and the second integer input or all other data without the sign bit and inputting it into the multiplier unit, and selecting the fifth input bit segment corresponding to the third integer input and inputting it into the adder unit.

[0015] In some embodiments, the above-described arithmetic structure further includes: an input adjustment unit, configured to perform at least one operation of negation and absolute value calculation on at least one of the integer first input, integer second input, and integer third input to obtain an adjusted result, and input the adjusted result as input data to the above-described multiply-accumulate arithmetic unit.

[0016] In some embodiments, for input data compatible with both integer and floating-point types, the above-described arithmetic structure further includes: a shared cache unit; The aforementioned shared cache unit supports the storage of integer and floating-point data, including: after the first type of data is read from the storage unit of the aforementioned shared cache unit, the second type of data is allowed to be written to the same storage unit; the first type and the second type are different types, and are either integer or floating-point; the index information of the aforementioned shared cache unit includes: the mapping relationship between the address where the data is located, the data type, and the data identifier; The aforementioned input data processing unit is also used to read data from the aforementioned shared cache unit to obtain the input data to be processed; When the input data processing unit reads data from the shared cache unit, it determines the data identifier and corresponding target data type of the target data to be processed in the current processing cycle according to the processing sequence indicated by the scheduling module that interacts with the above-mentioned computing structure, determines the target address corresponding to the data identifier and the target data type according to the index information, and reads the corresponding target data from the shared cache unit according to the target address, and uses the target data as the input data to be processed.

[0017] In some embodiments, in the above-described arithmetic structure, both the multiplier unit and the adder unit are time-division multiplexed, and for the same multiplier unit or the same adder unit, the processing of different types of inputs is distributed in different time periods.

[0018] In some embodiments, multiple input data groups are sequentially input into the above-described arithmetic structure for processing; In the aforementioned multiply-add unit, the aforementioned time-division multiplexing exists in at least one of the following situations: within the same time period, the multiplier unit processes data of the first type, and the adder unit processes data of the second type; the first type and the second type are different, and are either integer or floating-point; or, within the same time period, the multiplier unit processes data corresponding to the first input data group, and the adder unit processes data corresponding to the second input data group, wherein the data corresponding to the first input data group and the data corresponding to the second input data group have the same data type but different input data groups.

[0019] In some embodiments, the above-described arithmetic structure further includes a control unit, which is configured to receive scheduling information from the scheduling module and control the multiply-accumulate unit and the data output unit to execute corresponding data processing timing based on the scheduling information. The scheduling information is generated based on the acquisition timing of different input data groups, the current processing status of each unit in the above-mentioned operational structure, and the processing priority information. The processing priority information is used to indicate at least one of the following: the processing priority of a certain group in different input data groups for all units in the above-mentioned operational structure is set to the highest; the preset priority order of the processing priorities of each group in different input data groups for at least some units in the operational structure. The strategy for generating the aforementioned scheduling information includes: determining the input timing of the first unit following the input data processing unit in the aforementioned operational structure corresponding to different input data groups based on the timing of the input data processing unit's acquisition of different input data groups. The first unit can be one of the following: an input adjustment unit, a bit selection unit, or a multiplier unit. For each subsequent unit after the first unit, the timing of the input of the relevant operation output result of the previous unit is determined by analyzing the processing completion time of the previous unit for one or more input data groups, whether the current unit is idle or occupied, and the processing priority information, under the condition that the sum of the processing interval duration of each unit and the idle time within the unit is minimized or the processing priority information is satisfied.

[0020] Secondly, embodiments of this disclosure provide a data processing method applied to the computational structure provided in the first aspect embodiment, the method comprising: Based on the input data processing unit, the input data is formatted according to the data type of the input data to be processed, wherein the data type of the input data is integer or floating-point. Based on the multiply-accumulate unit, multiply-accumulate operations are performed on different types of input data; for floating-point input data, multiply-accumulate operations are performed through the multiplier unit, the adder unit, and the dedicated floating-point arithmetic unit; for integer input data, multiply-accumulate operations are performed through the aforementioned multiplier unit and the aforementioned adder unit, and the aforementioned dedicated floating-point arithmetic unit is disabled. Based on the data output unit, when the input data is an integer, the result of the multiplication and addition operation is output; when the input data is a floating-point number, the result of the multiplication and addition operation is adjusted to adapt to the floating-point data format before the operation result is output.

[0021] In some embodiments, the above data processing method further includes: Based on the control unit, the above scheduling information is received, and based on the above scheduling information, the above multiply-accumulate operation unit and the above data output unit are controlled to execute the corresponding data processing timing sequence; The above scheduling information is generated based on the acquisition timing of different input data groups, the current processing status of each unit in the above operation structure, and the processing priority information. The processing priority information is used to indicate at least one of the following: the processing priority of a certain group in different input data groups for all units in the above operation structure is set to the highest; the preset priority order of the processing priorities of each group in different input data groups for at least some units in the operation structure. The strategy for generating the aforementioned scheduling information includes: determining the input timing of the first unit following the input data processing unit in the aforementioned operational structure corresponding to different input data groups based on the timing of the input data processing unit's acquisition of different input data groups. The first unit can be one of the following: an input adjustment unit, a bit selection unit, or a multiplier unit. For each subsequent unit after the first unit, the timing of the input of the relevant operation output result of the previous unit is determined by analyzing the processing completion time of the previous unit for one or more input data groups, whether the current unit is idle or occupied, and the processing priority information, under the condition that the sum of the processing interval duration of each unit and the idle time within the unit is minimized or the processing priority information is satisfied.

[0022] Thirdly, embodiments of this disclosure provide a processor. The processor includes the operational structure provided in the first aspect embodiment or is used to execute the data processing method provided in the second aspect embodiment.

[0023] Fourthly, embodiments of this disclosure provide a chip. The processor described above includes the arithmetic structure provided in the first aspect embodiment, or is used to execute the data processing method provided in the second aspect embodiment, or includes the processor provided in the third aspect embodiment.

[0024] Fifthly, embodiments of this disclosure provide an electronic device. The electronic device includes the computational structure provided in the first aspect embodiment, or is used to execute the data processing method provided in the second aspect embodiment, or includes a processor provided in the third aspect embodiment, or includes a chip provided in the fourth aspect embodiment.

[0025] The technical solutions provided in the embodiments of this disclosure have at least some or all of the following advantages: In the aforementioned arithmetic structures, processors, chips, and electronic devices, by setting up an input data processing unit, a multiply-accumulate unit, and a data output unit in the arithmetic structure, the input data processing unit is used to format integer or floating-point input data according to the data type of the input data to be processed, so that the processed input data is adapted to the arithmetic logic of the multiply-accumulate unit; the multiply-accumulate unit is used to perform multiply-accumulate operations in response to different types of input data; wherein, for floating-point input data, multiply-accumulate operations are performed through a multiplier unit, an adder unit, and a dedicated floating-point arithmetic unit; for integer input data, multiply-accumulate operations are performed through the above... The multiplier unit and the adder unit perform multiplication and addition operations, and the floating-point dedicated arithmetic unit is disabled. By setting up a data output unit, the operation result can be output that is adapted to the data type of the input data. In the multiplication and addition unit, the adder unit and the multiplier unit are reused, and control logic is set to enable or disable the floating-point dedicated unit according to different data types of input data. This enables the above-mentioned arithmetic structure, processor, chip and electronic device to be effectively compatible with the processing of integer data and floating-point data, without the need to set up two parallel processing units as in related technologies, thus saving the required hardware layout area.

[0026] The technical solutions provided in the embodiments of this disclosure have at least some or all of the following advantages: In the above data processing method, based on the input data processing unit, the integer or floating-point input data is formatted according to the data type of the input data to be processed, so that the processed input data is adapted to the operation logic of the multiplication-addition unit; based on the multiplication-addition unit, multiplication-addition operations are performed on different types of input data; specifically, for floating-point input data, multiplication-addition operations are performed through a multiplier unit, an adder unit, and a dedicated floating-point operation unit; for integer input data, multiplication-addition operations are performed through the aforementioned multiplier unit and the aforementioned adder unit, and the aforementioned dedicated floating-point operation unit is disabled; in the multiplication-addition unit, the adder unit and the multiplier unit are reused, and different settings are configured for different input data. The control logic for enabling or disabling the dedicated floating-point unit based on data type adaptability allows the aforementioned arithmetic structures, processors, chips, and electronic devices to effectively process both integer and floating-point data. Based on the data output unit, when the input data is integer, the result of a multiplication-accumulation operation is output; when the input data is floating-point, the result of the multiplication-accumulation operation is adjusted to adapt to the floating-point data format before being output, thus enabling the output of operation results adapted to the data type of the input data. This allows the corresponding arithmetic structures, processors, chips, and electronic devices to effectively process both integer and floating-point data without the need for two separate parallel processing units as required by related technologies, saving the required hardware footprint. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of an operational structure compatible with integer and floating-point processing according to an embodiment of the present disclosure is shown.

[0030] Figure 2 The diagram illustrates the structure of an arithmetic structure and the processing flow diagram of a process that is compatible with integer and floating-point processing according to an embodiment of the present disclosure.

[0031] Figure 3 A schematic diagram of the structure and a schematic diagram of the processing procedure of the arithmetic structure compatible with integer and floating-point processing according to another embodiment of the present disclosure are shown.

[0032] Figure 4The diagram illustrates the structure and processing flow of an arithmetic structure compatible with integer and floating-point processing according to yet another embodiment of the present disclosure.

[0033] Figure 5 The diagram illustrates the structure and process of an arithmetic structure compatible with integer and floating-point processing according to another embodiment of the present disclosure.

[0034] Figure 6 The diagram illustrates the interaction between the arithmetic structure and the scheduling module that are compatible with integer and floating-point processing according to an embodiment of the present disclosure.

[0035] Figure 7 The diagram illustrates the timing distribution of the processing of three sets of input data (a) data set 1, (b) data set 2 and (c) data set 3 under the scheduling of a scheduling module according to an embodiment of the present disclosure. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the specification, " / " indicates "or", and "A and / or B" means A alone, B alone, or both A and B.

[0037] Terminology The terminology used in the embodiments of this disclosure is described below.

[0038] INT / int: Represents integer data. The number following it indicates the number of bits to store the data. The value can be changed.

[0039] For example, INT32 / int32 represents 32-bit integer data, using 32 bits for data storage. It belongs to a type of data representation and storage format in computers.

[0040] INT64 / int64: Represents 64-bit integer data, which is stored in 8 bytes (64 bits in total).

[0041] FP / float: Represents floating-point data. The number following it indicates the number of bits of data to be stored, and the value can be changed.

[0042] For example, FP64 / float64 represents 64-bit floating-point data, using 8 bytes (64 bits in total) for data storage. It belongs to another type of data representation and storage format in computers. The difference between FP64 and INT64 is that it is based on scientific notation and includes: a sign bit (also described as the sign part), an exponent bit (or exponent part, exponent portion, etc.), and a mantissa bit (also described as the mantissa portion).

[0043] Normalization: In computers, to ensure the uniqueness of floating-point representations, floating-point numbers are stored in normalized form. For IEEE 754 standard floating-point numbers, this means the mantissa must be in the form of 1.M (where M represents the data of the following bits).

[0044] Rounding: Truncation or approximation of the lower digits of a calculation result that exceed the range of the mantissa is called rounding. Specific rounding methods include one of the following: round to nearest, round to +∞, round to -∞, and round to 0.

[0045] Pipeline / Processing Flow: Represents the processing procedure corresponding to a data processing operation. There can be one or more processing operations within a processing flow. The logic between these processing operations can be parallel execution, interleaved execution, sequential execution, etc. The timing of the process from one processing flow to the next is executed according to the scheduling information of the scheduling module.

[0046] The first exemplary embodiment of this disclosure provides an operational structure that is compatible with both integer and floating-point multiplication and addition operations.

[0047] In related technologies, taking the INT64 multiply-add operation (multiplying two 32-bit integer (INT32) data and adding them to a 64-bit integer data) and the FP64 multiply-add operation (multiplying two 64-bit floating-point (FP64) data and adding them to a 64-bit floating-point data) as examples, in related technologies, two independent operation architectures are usually set up in the chip for the INT64 multiply-add operation and the FP64 multiply-add operation: the INT64 integer operation unit and the FP64 floating-point operation unit, each configured with dedicated multipliers, adders and other core components.

[0048] For example, in a 64-bit integer (INT64) multiplication-addition operation, A and B are INT32 (32-bit integer) data, and C is INT64 (64-bit integer) data. These are input to the INT64 integer arithmetic unit for the multiplication-addition operation A×B+C. Similarly, in a 64-bit floating-point (FP64) data multiplication-addition operation, A and B are FP64 (64-bit floating-point) data, and C is input to the FP64 floating-point arithmetic unit for processing. Since multipliers and adders occupy the largest area of ​​the computing module, and with increasing computing power demands, many independent arithmetic units are typically instantiated within the chip to meet these high computing power requirements. This leads to a significant increase in chip area, resulting in higher costs, lower yields, and a series of other problems.

[0049] The operational structure provided in this embodiment can be compatible with multiplication and addition operations of integer and floating-point data based on the same multiplication and addition unit, saving deployment area.

[0050] Figure 1 A schematic diagram of an operational structure compatible with integer and floating-point processing according to an embodiment of the present disclosure is shown. Figure 2 The diagram illustrates the structure of an arithmetic structure and the processing flow diagram of a process that is compatible with integer and floating-point processing according to an embodiment of the present disclosure.

[0051] Reference Figure 1 and Figure 2 As shown, the above-mentioned arithmetic structure 100 includes: an input data processing unit 110, a multiplication and addition arithmetic unit 120, and a data output unit 130.

[0052] The input data processing unit 110 is used to format the input data according to the data type of the input data to be processed, wherein the data type of the input data is integer or floating-point. For multiplication-addition operations, the input data to be processed is in the form of an input data group, including a first input and a second input for performing the multiplication operation to obtain the multiplication result, and a third input for performing the addition operation with the multiplication result. For example, in... Figure 2The example provides two input data sets: {A1, B1, C1} and {A2, B2, C2}. Parentheses are used after each data set to indicate its data type. For instance, A1 and B1 are of data type int32 (32-bit integer), and C1 is of data type int64. The multiplication-addition operation A1 × B1 + C1 is described as an INT64 multiplication-addition operation. A2, B2, and C2 are all of data type float64 (64-bit floating-point), and the multiplication-addition operation A2 × B2 + C2 is described as an FP64 multiplication-addition operation. The input data processing unit 110 performs format processing on the integer or floating-point input data to adapt it to the operation logic of the multiplication-addition unit 120.

[0053] The multiply-add unit 120 contains a multiplier unit 121, an adder unit 123, and a dedicated floating-point arithmetic unit 1201, and also has built-in control logic. Figure 2 The internal structure of the floating-point dedicated arithmetic unit is illustrated using a single-dot dashed box. For example, the floating-point dedicated arithmetic unit 1201 mentioned above includes: an exponent alignment unit 122 and a normalization and rounding unit 124.

[0054] The multiply-accumulate unit 120 described above is used to perform multiply-accumulate operations in response to different types of input data; wherein, referring to Figure 1 The processing flow, indicated by the double arrows, performs multiplication and addition operations on floating-point input data through multiplier unit 121, adder unit 123, and a dedicated floating-point arithmetic unit; see reference... Figure 1 The processing flow indicated by the single arrow in the middle performs multiplication and addition operations on integer input data through the multiplier unit 121 and the adder unit 123, and disables the floating-point dedicated arithmetic unit.

[0055] Data output unit 130 is used to output the result of multiplication and addition operation when the input data is an integer, for example, referring to Figure 1 As shown by the single arrow in the processing flow, the second multiplication-accumulation operation result is output. When the input data is floating-point, the multiplication-accumulation operation result is adjusted to adapt to the floating-point data format before being output. For example, refer to... Figure 1 The processing flow indicated by the double arrows in the middle outputs the result of the first multiplication-addition operation.

[0056] By incorporating an input data processing unit, a multiply-accumulate unit, and a data output unit into the operational structure, the input data processing unit formats integer or floating-point input data according to its data type, ensuring the processed input data is compatible with the operational logic of the multiply-accumulate unit. The multiply-accumulate unit performs multiply-accumulate operations in response to different types of input data. Specifically, for floating-point input data, multiply-accumulate operations are performed using a multiplier unit, an adder unit, and a dedicated floating-point arithmetic unit. For integer input data, multiply-accumulate operations are performed using the multiplier unit and the adder unit, while the dedicated floating-point arithmetic unit is disabled. The data output unit outputs the operational result compatible with the data type of the input data. By multiplexing the adder and multiplier units within the multiply-accumulate unit and configuring control logic to enable or disable the dedicated floating-point unit based on different input data types, the operational structure, processor, chip, and electronic device can effectively handle both integer and floating-point data processing without requiring two separate parallel processing units as in related technologies, thus saving hardware footprint.

[0057] The aforementioned computational structures can be applied to various fields, including scientific computing (such as celestial motion simulation, physical calculations, chemical calculations, and weather forecasting), artificial intelligence calculations or modeling, computer image processing, engineering calculations, and financial data processing. For example, training machine learning models requires numerous matrix operations, including addition and multiplication of integer and floating-point data. In computer-simulated fluid flow in fluid mechanics, extensive mathematical calculations are needed for physical quantities such as velocity and pressure. These physical quantities are typically stored as floating-point data, and the fluid state is updated through addition and multiplication. Image scaling, rotation, and color adjustment operations utilize integer and floating-point data operations. For instance, image scaling requires multiplication of pixel coordinates (integer data) based on the scaling ratio (floating-point data) to obtain the new pixel position; color adjustment involves multiplication and addition of the RGB (red, green, and blue) values ​​(integer data) to change the image's brightness, contrast, etc.

[0058] In some embodiments, the multiply-accumulate unit 120 is a 64-bit multiply-accumulate unit, wherein the multiplier unit adopts a 53-bit × 53-bit multiplier circuit without a sign bit, or a 54-bit × 54-bit multiplier circuit with a sign bit.

[0059] By constructing multiplier units based on wide-bit multiplier circuits (such as 53-bit × 53-bit multiplier circuits, or 54-bit × 54-bit multiplier circuits including sign bits), it is possible to simultaneously support FP64 multiply-add operations (multiplying two FP64-bit data and adding them to an FP64-bit data) and INT64 multiply-add operations (multiplying two INT32-bit data and adding them to an INT64-bit data). It is also backward compatible with related multiply-add operations on integer or floating-point data with fewer bits. Moreover, the number of bits of the three original data in an input data group can differ; for example, it supports multiplying two FP64-bit data and adding them to lower-bit data such as FP32-bit data or FP16-bit data, or it supports multiplying two FP32-bit data and adding them to FP64-bit data. During the operation, the lower-bit data can be padded to meet the bit requirements of the input format of the multiplier unit and the adder unit. For example, it also supports floating-point operations such as FP32 multiply-accumulate (multiplying two FP32 data and adding them to an FP32 data), FP16 multiply-accumulate (multiplying two FP32 data and adding them to an FP32 data), and integer operations such as INT32 multiply-accumulate (INT32 multiply-accumulate is multiplying two INT16 data and adding them to an INT32 data, and so on), INT16 multiply-accumulate, and INT8 multiply-accumulate. FP16 can be either the half-precision floating-point number FP16 conforming to the IEEE 754 standard, or BFloat16, a 16-bit floating-point format specific to Google's Tensor Processing Unit (TPU), which is compatible with the IEEE 754 standard but optimizes computational efficiency.

[0060] Based on the aforementioned 64-bit multiply-accumulate unit, the operational structure 100 of this embodiment only needs to pad the lower-bit data (e.g., perform bit padding operation based on the input data processing unit 110) before processing data with fewer bits, and then use it as the input of the multiply-accumulate unit for corresponding processing. Unlike related technologies that use narrow-bit circuits, it does not require data bit splitting and result reassembly, simplifying the processing and saving processing time in the corresponding splitting and result reassembly stages.

[0061] It is understood that in other embodiments, depending on the actual application scenario of the arithmetic structure, a multiply-accumulate unit with an appropriate number of bits can be selected, without being limited to the number of bits of the multiplier circuit in the example above. The number of bits of the adder circuit used in the specific adder unit can be selected according to actual needs. For example, in some embodiments, the adder unit uses an adder circuit with more than 100 bits.

[0062] In some embodiments, the input data processing unit 110 is configured to perform sign bit extension on the integer input data when the data type of the input data is integer, and to perform splitting of the sign bit, exponent bit, and mantissa bit on the floating-point input data when the data type of the input data is floating-point.

[0063] For example, both INT64 multiply-accumulate and FP64 multiply-accumulate operations require three input operands of the same type. For INT64 multiply-accumulate operations, the input data processing unit 110 performs sign bit extension processing on at least some of the input operands, including: extending the sign bit of two 32-bit or lower integer input operands (e.g., C1 and C2) for the product operation (for lower integer operands, bit padding is required) to obtain 33-bit signed integer input operands. The multiplier unit 121 then performs the multiplication operation on the two 33-bit integer input operands to obtain the integer multiplication result. Finally, the adder unit performs the addition operation on the integer multiplication result and another 64-bit integer input operand.

[0064] For FP64 multiply-accumulate operations, the input data processing unit 110 performs bit padding on non-FP64 bit input operands (such as floating-point data with lower bit depth, FP32, FP16, etc.) and splits the FP64 bit input operands into 1 sign bit, 11 exponent bits and 53 mantissa bits, where the 53 mantissa bits include 1 leading hidden bit and 52 actual stored mantissa bits.

[0065] By processing the integer or floating-point input data using the input data processing unit 110, the processed input data can be adapted to the operation logic of the multiplication and addition unit 120.

[0066] In some embodiments, the three input data to be processed for multiplication-addition operations form an input data group, which is described as a first input, a second input, and a third input, respectively. The first input, the second input, and the third input can be: a floating-point first input, a floating-point second input, and a floating-point third input; or they can be: an integer first input, an integer second input, and an integer third input.

[0067] In some application scenarios, the first, second, and third inputs can be initial values ​​or intermediate calculation results (including, but not limited to, calculation results corresponding to addition, subtraction, multiplication, and division) in various data processing scenarios. The values ​​of the first, second, and third inputs can be the same or different, depending on the actual operation scenario. For example, for the following operation scenario: m×n+m, the first input is m, the second input is n, and the third input is m. For the following operation scenario: a1×x1+a2×x2 (a2×x2 is the intermediate calculation result), the first input is a1, the second input is x1, and the third input is the result of a2×x2. For the following operation scenario: a1×x1+(a2+x2) ((a2+x2 is the intermediate calculation result), the first input is a1, the second input is x1, and the third input is the result of a2+x2. This disclosure describes the lowest-level operation structure used to implement basic multiplication and addition operations. Faced with various complex operation expressions, they can be decomposed into basic operation units by splitting and setting the calculation timing, and the three inputs corresponding to performing the most basic multiplication and addition operations can be obtained.

[0068] In this approach, both multiplier and adder units are time-division multiplexed, and for the same multiplier unit or the same adder unit, the processing of different types of inputs is distributed across different time periods.

[0069] The aforementioned time-sequential multiplexing includes at least the following: time-sequential processing within the same processing unit: for the same multiplier unit or the same adder unit, the processing of different types of inputs is distributed in different time periods during multiplexing; and includes at least one of the following situations: during pipelined processing, the processing time periods of different processing units within the operational structure for different types of inputs overlap, and the processing time periods of different processing units within the same type for different inputs overlap.

[0070] Specifically, in the aforementioned multiply-accumulate unit, based on the aforementioned time-division multiplexing, at least one of the following situations exists: During the same time period, the multiplier unit processes data of the first type, and the adder unit processes data of the second type; the first type and the second type are different, and are either integers or floating-point numbers; or, during the same time period, the multiplier unit processes data corresponding to the first input group, and the adder unit processes data corresponding to the second input group, where the data types corresponding to the first input group and the data corresponding to the second input group are the same but the input groups are different. These situations will be referred to in subsequent embodiments. Figure 7 A detailed introduction will be provided.

[0071] In some embodiments, refer to Figure 2 As shown, single and double arrows are used to illustrate the processing flow under different processing sequences.

[0072] existFigure 2 The diagram illustrates a set of integer input data, including three integer inputs: {A1, B1, C1}; it also illustrates a set of floating-point input data, including three floating-point inputs and their corresponding data types: {A2, B2, C2}.

[0073] Suppose that the input data processing unit 110 obtains data group 1: {A1, B1, C1} at time t1; and obtains data group 2: {A2, B2, C2} at time t2.

[0074] Reference Figure 2 The processing flow, indicated by the double arrows, is an example where A2 is used as the first floating-point input, B2 as the second floating-point input, and C2 as the third floating-point input. In the multiply-accumulate unit 120, for the floating-point input data, multiply-accumulate operations are performed by the multiplier unit 121, the adder unit 123, and the dedicated floating-point arithmetic unit, including: The multiplier unit 121 and the exponent alignment unit 122 are used to perform multiplication operations on the floating-point first input A2 and the floating-point second input B2 to obtain the floating-point multiplication result. The above-mentioned adder unit 123 performs an addition operation on the above-mentioned floating-point multiplication result and the above-mentioned floating-point third input C2 to obtain the floating-point addition result. The normalization and rounding unit 124 performs at least one of the mantissa normalization and rounding operations on the floating-point addition result to obtain the floating-point arithmetic result. The mantissa normalization operation includes normalizing the result of the adder unit (e.g., the floating-point addition result) during floating-point input processing, for example, ensuring the output conforms to the IEEE 754 standard. The rounding operation includes truncating or approximating the lower bits of the calculation result that exceed the mantissa representation range.

[0075] Specifically, the multiplier unit 121 is used to perform a multiplication operation on the mantissa portion of the first floating-point input A2 and the mantissa portion of the second floating-point input B2 to obtain a floating-point mantissa multiplication result, for example in... Figure 2 The diagram shows the last digit of A2 multiplied by the last digit of B2.

[0076] The aforementioned exponent alignment unit 122 is used to perform addition operations on the exponent portion of the first floating-point input A2 and the exponent portion of the second floating-point input B2 to obtain a floating-point exponent addition result, for example in... Figure 2The diagram shows A2 exponent + B2 exponent; and it is used to perform an alignment operation on the above floating-point exponent addition result and the exponent part of the above floating-point third input C2 to obtain the exponent alignment operation result; the above alignment operation is based on aligning the larger of the above floating-point exponent addition result and the exponent part of the third input.

[0077] The adder unit 123 is configured to perform mantissa shift adjustment on the mantissa portion corresponding to the smaller of the floating-point exponent addition result and the exponent portion of the floating-point third input C2, based on the exponent alignment operation result, and perform addition operation on the mantissa portion corresponding to the larger one to obtain a floating-point addition operation result; wherein the mantissa portion corresponding to the smaller one is the floating-point mantissa multiplication result or the mantissa portion of the third input.

[0078] In some embodiments, the input data to be processed includes: a first integer input, a second integer input, and a third integer input, as shown in the figure. Figure 2 The processing flow, indicated by the single arrow, is an example where A1 is the first integer input, B1 is the second integer input, and C1 is the third integer input. In the multiply-accumulate unit 120, for the integer input data, multiply-accumulate operations are performed by the multiplier unit 121 and the adder unit 123, including: Based on the multiplier unit 121, the integer first input A1 and the integer second input B1 are multiplied to obtain an integer multiplication result; based on the adder unit 123, the integer multiplication result and the integer third input C1 are added to obtain an integer operation result.

[0079] For example, the multiplier unit 121 described above is used to perform multiplication operations on the mantissa portion of the first floating-point input (e.g., A2 mantissa) and the mantissa portion of the second floating-point input (e.g., B2 mantissa) during the first processing period, to obtain a floating-point mantissa multiplication result; and to perform multiplication operations on the first integer input (e.g., A1) and the second integer input (e.g., B1) during the second processing period, to obtain an integer multiplication result. The first and second processing periods have a sequential order, but the specific order is not limited. In practical scenarios, the first processing period may occur before or after the second processing period.

[0080] Reference Figure 2 As indicated by the double arrows, in multiplier unit 121, the mantissa portions of the two floating-point inputs A2 and B2 from the aforementioned data group 2: {A2, B2, C2} are input to multiplier unit 121, and the mantissa portion multiplication operation is performed to obtain the corresponding floating-point mantissa multiplication result. For example, inFigure 2 The diagram shows the last digit of A2 multiplied by the last digit of B2.

[0081] Reference Figure 2 As indicated by the single arrow, in multiplier unit 121, the corresponding multiplication operation is performed on the two integer inputs A1 and B1 in the aforementioned data group 1: {A1, B1, C1}. Specifically, this can be a bitwise multiplication operation followed by accumulation to obtain the integer multiplication result corresponding to the two integer inputs A1 and B1. Figure 2 The diagram is shown as A1×B1.

[0082] The aforementioned exponent alignment unit 122 is used to perform addition operations on the exponent portions of the first and second floating-point inputs during the third processing period to obtain a floating-point exponent addition result; and to perform alignment operations on the above floating-point exponent addition result and the exponent portion of the third floating-point input during the fourth processing period to obtain an exponent alignment operation result; the above alignment operation is based on the larger of the floating-point exponent addition result and the exponent portion of the third input. In this embodiment, the exponent alignment unit 122 only involves operations on floating-point data. In this embodiment, the fourth processing period follows the third processing period. The processing operations corresponding to the third and first processing periods can be executed in parallel and are set in the same pipeline 1.

[0083] In other embodiments, since the processing of floating-point data requires processing by a multiplier unit and an exponent alignment unit respectively, and the processing of the adder unit depends on the processing results of the two units above: the multiplier unit and the exponent alignment unit, the third processing period, the fourth processing period and the first processing period executed in parallel can all be corresponding to another pipeline, pipeline2, and the processing time of pipeline2 is longer than that of pipeline1.

[0084] For example, refer to Figure 2 As indicated by the double arrows, in the exponent alignment unit 122, the exponent portions (simplified as A2 exponent and B2 exponent) of the two floating-point inputs A2 and B2 from the data group 2: {A2, B2, C2} are input to the exponent alignment unit 122. Addition of the exponent portions is performed to obtain the corresponding floating-point exponent addition result. For example, in... Figure 2The diagram illustrates A2 exponent + B2 exponent. In the exponent alignment unit 122, the exponent A2 + B2 exponent is aligned with the exponent part of another floating-point input C2 (simplified as C2 exponent) to obtain the exponent alignment result. For example, alignment is performed based on the larger of the exponent parts of A2 + B2 and C2, and the difference in the exponent parts is calculated. The resulting exponent alignment is as follows: the mantissa part corresponding to the smaller of the exponent parts of A2 + B2 and C2 is shifted to the right by x positions (the mantissa shifts to the right, which can be intuitively understood as the decimal point shifts to the left). Subsequent mantissa shift adjustments will then perform the right shift x positions operation. In this embodiment, by setting the larger one as the reference for exponent alignment, a certain level of calculation accuracy can be ensured. Because if aligning a large number to a small number, the mantissa part of the large number must be shifted to the left, which may result in the loss of the most significant bit of the large number; aligning a small number to a large number shifts the mantissa part of the small number to the right, and the loss of the small number's precision is irrelevant to the result, thus ensuring a certain level of calculation accuracy.

[0085] The adder unit 123 is configured to, based on the aforementioned time-division multiplexing, in the fifth processing period, perform mantissa shift adjustment on the mantissa corresponding to the smaller of the floating-point exponent addition result and the exponent part of the third input according to the aforementioned exponent alignment operation result, and perform addition operation processing on the mantissa corresponding to the smaller one with the mantissa corresponding to the larger one to obtain a floating-point addition operation result; in the sixth processing period, perform addition operation processing on the integer third input and the aforementioned integer multiplication operation result to obtain an integer operation result; wherein, the mantissa corresponding to the smaller one is the mantissa part of the aforementioned first operation result or the third input.

[0086] For example, refer to Figure 2 As shown by the double arrows, in adder unit 123, based on the exponent-aligned operation result: shifting x bits to the right, the mantissa part corresponding to the smaller exponent, for example, the mantissa of the second operation result A2 × B2, is adjusted by mantissa shift to obtain the exponent-aligned mantissa result. This mantissa result (already in an exponent-aligned state) is then added to the mantissa part (C2 mantissa) of another floating-point input C2 to obtain the floating-point addition result. Figure 2 The diagram is represented as A2×B2+C2.

[0087] Reference Figure 2 As shown by the single arrow, in adder unit 123, another integer input C1 is added to the integer multiplication result A1×B1 to obtain the integer operation result. Figure 3 The diagram is shown as A1×B1+C1.

[0088] Through the aforementioned time-series multiplexing, the multiply-add unit can reuse the multiplier and adder units within a reasonable and conflict-free time sequence to achieve compatible processing of multiply-add operations on integer and floating-point data.

[0089] In some embodiments, the above-described operational structure supports multiplication and addition operations on both signed and unsigned data.

[0090] Among them, the first input, the second input, and the third input are all unsigned data, and the first input, the second input, and the third input are all represented by binary original code.

[0091] Since the first input, the second input, and the third input are all signed data, they are all represented using two's complement.

[0092] For example, the first, second, and third inputs mentioned above are all represented using two's complement. Based on two's complement, for positive numbers, the two's complement is equal to the original code; for negative numbers, the two's complement is obtained by inverting the bits of the binary form of the absolute value of the original code and adding 1.

[0093] In this embodiment, the input is represented in a two's complement form, and the numerical values ​​are represented in a unified manner. The addition and multiplication operations are unified, and there is no need to calculate the sign bit or perform related representation conversions.

[0094] Alternatively, in other embodiments, the first input, the second input, and the third input are all signed data, and the first input, the second input, and the third input are all represented using binary original code. The multiplication and addition unit further includes a sign bit operation unit and a representation conversion unit.

[0095] The aforementioned sign bit operation unit is used to perform an XOR operation on the sign bits of the first and second inputs of floating-point or integer types to obtain the sign bit multiplication result. Specifically, in response to a floating-point input, the sign bit multiplication result is concatenated with the floating-point mantissa multiplication result to obtain a signed floating-point mantissa multiplication result; in response to an integer input, the sign bit multiplication result is concatenated with the integer multiplication result to obtain a signed integer multiplication result. This sign bit operation unit can interact with the multiplier unit. For example, the sign bit operation unit inputs the sign bit multiplication result to the multiplier unit, and the multiplier unit concatenates the sign bit multiplication result with the result obtained from multiplying the numerical parts (e.g., a floating-point mantissa multiplication result or an integer multiplication result) to obtain the signed bit multiplication result.

[0096] The aforementioned representation conversion unit is used to, in response to floating-point input, convert the signed floating-point mantissa multiplication result and the floating-point third input into two's complement form before inputting them to the adder unit for corresponding processing; and is also used to, in response to integer input, convert the signed integer multiplication result and the integer third input into two's complement form before inputting them to the adder unit for corresponding processing. The aforementioned representation conversion unit is located before the aforementioned adder unit.

[0097] Specifically, in some embodiments, the aforementioned sign bit operation unit is used to perform an XOR operation on the sign bits of the first floating-point input and the second floating-point input when the first floating-point input, the second floating-point input, and the third floating-point input are all signed data and are all represented using binary original code, to obtain a sign bit multiplication result; and to concatenate the sign bit multiplication result with the floating-point mantissa multiplication result to obtain a signed floating-point mantissa multiplication result.

[0098] The aforementioned representation conversion unit is used to convert the signed floating-point mantissa multiplication result and the floating-point third input into two's complement form and then input them to the adder unit for corresponding processing when the first floating-point input, the second floating-point input, and the third floating-point input are all signed data and are all represented using binary sign-magnitude representation.

[0099] In some embodiments, the above-mentioned sign bit operation unit is used to perform an XOR operation on the sign bits of the first integer input and the second integer input when the first integer input, the second integer input, and the third integer input are all signed data and are all represented using binary original code, to obtain a sign bit multiplication result; and to concatenate the sign bit multiplication result with the integer multiplication result to obtain a signed integer multiplication result. The aforementioned representation conversion unit is used to convert the signed integer multiplication result and the third integer input into two's complement form and then input them to the adder unit for corresponding processing when the first integer input, the second integer input, and the third integer input are all signed data and are all represented using binary sign-magnitude representation.

[0100] In this embodiment, the input can also be represented in binary original code form. The result of multiplying the two inputs is obtained by performing corresponding processing of the sign bit and the numerical part of the multiplication logic respectively and then concatenating them. Then, the original code form is converted into the two's complement form and the result of multiplying the two inputs is added to the other input to obtain the multiply-add result.

[0101] The three embodiments described above broaden the input format of the data to be processed, allowing the input format to be either binary sign-magnitude or two's complement, making the input format flexible and diverse; and enabling multiplication and addition operations for both non-signed and signed data.

[0102] Figure 3 A schematic diagram of the structure and a schematic diagram of the processing procedure of the arithmetic structure compatible with integer and floating-point processing according to another embodiment of the present disclosure are shown.

[0103] In some embodiments, refer to Figure 3 As shown, the multiply-add unit 120 further includes a bit selection unit 125. The bit selection unit 125 is used to adapt and select different input bit segments according to the difference of the control signal and input them to the subsequent unit. The subsequent unit includes some or all of the following: multiplier unit 121, adder unit 123 and exponent alignment unit 122. The control signal is generated based on the data type.

[0104] For example, the bit selection unit described above is used to select the corresponding input bit segment according to the first control signal and input it to the multiplier unit, the adder unit and the exponent alignment unit.

[0105] The step of selecting the corresponding input bit segment according to the first control signal and inputting it into the multiplier unit, the adder unit, and the exponent alignment unit includes: responding to the first control signal generated based on the floating-point data type, selecting the first input bit segment corresponding to the mantissa portion of the floating-point first input and the mantissa portion of the floating-point second input and inputting it into the multiplier unit; selecting the second input bit segment corresponding to the mantissa portion of the floating-point third input and inputting it into the adder unit; and selecting the third input bit segment corresponding to the exponent portion of each of the floating-point first input, the floating-point second input, and the floating-point third input and inputting it into the exponent alignment unit.

[0106] The bit selection unit described above is used to select the corresponding input bit segment according to the second control signal and input it to the multiplier unit and the adder unit; Selecting the corresponding input bit segment according to the second control signal and inputting it into the multiplier unit and the adder unit includes: in response to the second control signal generated based on the integer data type, selecting the fourth input bit segment corresponding to all data of the first integer input and the second integer input or all other data without the sign bit and inputting it into the multiplier unit, and selecting the fifth input bit segment corresponding to the third integer input and inputting it into the adder unit.

[0107] Specifically, refer to Figure 3 As shown by the double arrows, the process of adapting and selecting different input bit segments based on the differences in control signals and inputting them to subsequent units includes: In response to the above data type information indicating that the input type is floating point, the bit selection unit 125 is used to select the first input bit segment corresponding to the mantissa portion (mantissa of A2 and mantissa of B2) of the two floating point inputs (i.e., the first floating point input A2 and the second floating point input B2 in this embodiment) for multiplication and input it to the multiplier unit 121. The second operation result A2 mantissa × B2 mantissa output by the multiplier unit 121 is used as the input of the adder unit 123.

[0108] Continue to refer to Figure 3 As indicated by the double arrows, in response to the data type information indicating that the input type is floating-point, the bit selection unit 125 is also used to select the second input bit segment corresponding to the mantissa portion (C3 mantissa) of another floating-point input (corresponding to the third input) and input it into the adder unit 123, and to select the exponent portion (in the first input and the second input) of each of the two floating-point inputs (the first input and the second input) and the other floating-point input (the third input). Figure 3 The third input bit segment (represented as A2 index, B2 index, and C2 index) is input into the index alignment unit 122.

[0109] Reference Figure 4 As indicated by the single arrow, in response to the above data type information indicating that the input type is integer, the bit selection unit is used to select the fourth input bit segment corresponding to all data of the two integer inputs (e.g., the first input and the second input) or all other data without the sign bit and input it into the multiplier unit 121; it is also used to select the fifth input bit segment corresponding to another integer input (e.g., the third input) and input it into the adder unit 123.

[0110] In this embodiment, by setting the bit selection unit 125, different input bit segments can be adapted and selected based on the control signal generated according to the data type of the data to be processed, and input to at least part of the subsequent multiplier unit 121, exponent alignment unit 122, or adder unit 123, thereby achieving the effect of input filtering and directed input to the corresponding subsequent units (multiplier unit 121, exponent alignment unit 122, or adder unit 123). It is understood that in other modified embodiments, the bit selection unit can also be replaced by other functional units capable of input filtering and directed input.

[0111] Figure 4 A schematic diagram illustrating the structure and processing flow of an arithmetic structure compatible with integer and floating-point processing according to yet another embodiment of this disclosure is shown. Figure 4 The number selection unit 125, indicated by the dashed box, can be set or not.

[0112] Reference Figure 5As shown, based on the above embodiments, the above-described operational structure 100 further includes an input adjustment unit 140. The input adjustment unit 140 is used to perform at least one operation of negation and absolute value calculation on at least one of the input data to be processed (e.g., the first input, the second input, and the third input) to obtain an adjusted result, and input the adjusted result into the multiply-accumulate operation unit 120.

[0113] For example, in some embodiments, the above-mentioned input adjustment unit is used to perform at least one operation of negation and absolute value calculation on at least one of the floating-point first input, floating-point second input and floating-point third input to obtain an adjusted result, and input the adjusted result as input data to the above-mentioned multiply-accumulate operation unit.

[0114] In some embodiments, the above-described input adjustment unit is configured to perform at least one operation of negation and absolute value calculation on at least one of the integer first input, integer second input, and integer third input to obtain an adjusted result, and input the adjusted result as input data to the above-described multiply-accumulate operation unit.

[0115] In this embodiment, by setting an input adjustment unit 140 within the arithmetic structure 100, operations such as sign adjustment or absolute value calculation of input data can be supported within the arithmetic structure 100. This eliminates the need to set up separate hardware units outside the arithmetic unit for absolute value calculation or sign inversion (if such units were set up, logic for data interaction and reading would be required, resulting in the corresponding time consumption and affecting response speed). This also eliminates the logic for data interaction and reading with external hardware units in related technologies, enabling internal functional integration. At the same time, it saves the time required for data reading and interaction when setting up external processing units, improves response speed, and enhances the input adjustment flexibility of the arithmetic unit.

[0116] Figure 5 A schematic diagram illustrating the structure and processing flow of an arithmetic structure compatible with integer and floating-point processing according to another embodiment of the present disclosure is shown. Figure 5 The input adjustment unit 140, indicated by the dashed box, can be set or not.

[0117] Based on the above embodiments, referring to Figure 5As shown, the aforementioned operational structure 100 further includes a shared buffer unit 150. The shared buffer unit 150 supports the storage of integer and floating-point data, including: after data of the first type is read from a storage unit in the shared buffer unit, data of the second type can be written to the same storage unit; the first type and the second type are different types, and are either integer or floating-point. The index information of the shared buffer unit includes: the mapping relationship between the data's address, data type, and data identifier.

[0118] The input data processing unit 110 is further configured to read data from the shared cache unit 150 to obtain input data to be processed; when the input data processing unit 110 reads data from the shared cache unit 150, it uses a scheduling module that interacts with the computational structure 100 (in the following...) Figure 6 The diagram illustrates that this scheduling module can generally be set outside the computational structure, but in some cases it can also be set inside the computational structure, without any specific restrictions. The processing sequence indicated by the scheduling module (for example, the scheduling module instructs data group 1 of two sets of input data to be input and processed first, and data group 2 to be input and processed later, and this input order can be used as the processing sequence) determines the data identifier and corresponding target data type of the target data to be processed in the current processing cycle, determines the target address corresponding to the above data identifier and target data type based on the above index information, and reads the corresponding target data from the above shared cache unit 150 according to the above target address, and uses the above target data as the input data to be processed.

[0119] It should be noted that, since the aforementioned shared cache unit supports the storage of both integer and floating-point data, the same storage unit address may index different types of data at different times. For example, integer data might be stored in time period t1, while floating-point data might be stored in time period t2, which is different from time period t1. Therefore, by setting the mapping relationship between the data address, data type, and data identifier to form index information, it is helpful to accurately locate the required type of data to be processed.

[0120] Since the index information of the aforementioned shared cache unit contains a mapping relationship between the data address, data type, and data identifier, when the input data processing unit reads data from the aforementioned shared cache unit, it can accurately and quickly locate the target address corresponding to the data identifier and target data type based on the mapping relationship in the aforementioned index information, and obtain the corresponding target data based on the target address, thereby realizing fast data location in the shared cache unit.

[0121] In some embodiments, by setting up a shared cache unit that supports both integer and floating-point data storage, the same storage unit can store integer data (or floating-point data) and then continue storing floating-point data (as an example of different data types, in the case of floating-point data mentioned above, this is integer data) after the data is stored and read. The order of data types is also reversed. Therefore, in the shared cache unit: each storage unit can store either integer or floating-point data. For example, the shared cache unit supports storing both integer and floating-point data (e.g., to support the storage of 64-bit integer and 64-bit floating-point data, or to support the storage of multiple data types with lower bit widths). The two types are read indiscriminately; that is, the reading priority of different data types is not considered separately, but rather the reading order is based on the order of the operational data stream.

[0122] This configuration saves the area of ​​the shared cache unit and simplifies the logic of peripheral reading, avoiding the area cost required by the related technologies that require setting up two separate cache units to adapt to their respective processing units (INT64 floating-point arithmetic unit and FP64 floating-point arithmetic unit). Moreover, since the two types of data stored in the shared cache unit are read indiscriminately, compared with the scheme of setting up two independent caches adapted to different data types to store them separately, it can also simplify the logic of peripheral reading. If it is set up as two independent caches, it is necessary to set up corresponding input type determination logic and logic to locate a certain independent cache according to the different priorities of the input type and perform reading when reading from the outside. That is, in the embodiments of this disclosure, by setting up the above-mentioned operation structure and the above-mentioned shared cache unit, it also has the effect of simplifying the logic of peripheral reading.

[0123] If there are two independent caches, during data reading, the system considers which cache stores what data type and determines which cache to read first based on the read priority of different data types. This includes determining that lower-priority data reads must be read after higher-priority data (e.g., INT64 read priority is lower than FP64 read priority). However, in the embodiments of this disclosure, when the input data processing unit reads data from the shared cache unit, it only needs to obtain the data to be processed under the corresponding target data type as input according to the processing sequence indicated by the scheduling module. In other words, for the shared cache unit, different types of data (e.g., INT64, FP64) are treated equally.

[0124] Figure 7 The diagram illustrates the interaction between the arithmetic structure and the scheduling module that are compatible with integer and floating-point processing according to an embodiment of the present disclosure.

[0125] In the above operational structure, multiple input data groups are sequentially input into the operational structure for processing. Both the multiplier and adder units are time-division multiplexed, meaning that for the same multiplier unit or the same adder unit, the processing of different types of inputs is distributed across different time periods.

[0126] In some embodiments, the first input, the second input, and the third input constitute an input data group, and multiple input data groups are sequentially input into the operation structure 100 for processing.

[0127] In the embodiments of this disclosure, for multiple input data groups, namely multiple first inputs, second inputs, and third inputs input in different time sequences, based on the above-mentioned time-sequence multiplexing, the data processing timing of the different processing units (such as multiplier units, exponent alignment units, adder units, and result output units) set inside the above-mentioned arithmetic structure 100 for pipelined operations on multiple input data groups is further optimized, so as to satisfy at least one of the following: ensuring that the high-priority data group (e.g., data {A1, B1, and C1}) among the multiple input data groups (e.g., three data groups, {A2, B2, and C2}, {A3, B3, and C3}) is processed first; or, improving the processing time utilization of the multiplexed floating-point multiply-accumulate arithmetic unit, making the pipeline operation time more compact, thereby greatly reducing the impact of the multiplexing architecture on the overall task processing time.

[0128] For a large number of input groups to be processed, in the aforementioned multiplexed floating-point multiply-accumulate unit, based on the aforementioned time-division multiplexing, at least one of the following situations exists: During the same time period, the multiplier unit processes data of the first type, and the adder unit processes data of the second type; the first type and the second type are different, and are either integers or floating-point numbers; or, during the same time period, the multiplier unit processes data corresponding to the first input data group, and the adder unit processes data corresponding to the second input data group, where the data corresponding to the first input data group and the data corresponding to the second input data group have the same data type but different input data groups. These situations will be discussed later. Figure 6 A detailed explanation will not be provided here.

[0129] Reference Figures 2-6 As shown, in some embodiments, the above-mentioned operational structure 100 further includes a control unit, which is used to receive scheduling information from the scheduling module 200 and control the multiply-accumulate operation unit and the data output unit to execute the corresponding data processing timing based on the scheduling information.

[0130] The aforementioned data processing timing sequence includes: data group processing timing sequence and processing unit processing timing sequence. The aforementioned data group processing timing sequence and the aforementioned processing unit processing timing sequence respectively define the processing timing sequence of the data group and the internal processing unit from the perspectives of coarse-grainedness and fine-grainedness.

[0131] The above-mentioned data processing sequence is generally defined in terms of coarse and fine granularity, but does not restrict the actual processing order within each processing unit of the operation structure 100, nor does it care about the time order of the final output results.

[0132] The aforementioned scheduling information is used to indicate the processing sequence of each processing unit within the computational structure (i.e., the processing sequence of the aforementioned processing units). This includes: in the idle state, selecting one or more data from the waiting queue of each processing unit (used to buffer data input to the corresponding processing unit, which may be the output result of the previous unit with data correlation, or the input obtained from the input data processing unit, etc.) as input and processing; or in the occupied state, deciding whether to interrupt the current processing process and allow higher priority data in the waiting queue to be input and processed first before continuing the interrupted processing process, etc. This information is dynamically generated and adjusted continuously according to the execution status of the input data within the computational structure.

[0133] In some embodiments, the scheduling information is generated based on the acquisition timing of different input data groups, the current processing status of each unit in the above-mentioned operational structure, and the processing priority information. The processing priority information is used to indicate at least one of the following: the processing priority of a certain group in different input data groups for all units in the above-mentioned operational structure is set to the highest, and the preset priority order of the processing priorities of each group in different input data groups for at least some units in the operational structure. For example, within a certain processing cycle, there are three input data groups, described as data group a (with three inputs m1, n1, p1, all integers), data group b (with three inputs m2, n2, p2, all floating-point numbers), and data group c (with three inputs m3, n3, p3, all integers). In one exemplary scenario, the processing priority information is: data group b has the highest processing priority among all units in the above-mentioned operational structure relative to other data groups: data group a and data group c. Alternatively, in another exemplary scenario, the processing priority information is: in the multiplier unit, the priority of data group b is higher than the priorities of data group a and data group c, while the priorities of data group a and data group c are equal; in the adder unit, the priority of data group b is higher than the priority of data group a and higher than the priority of data group c. In other scenarios not illustrated, both of the above-mentioned processing priority information representations may exist simultaneously.

[0134] In some embodiments, combined withFigure 6 As shown, where the combination Figure 6 As indicated by the data stream in the sequence number ①, the above-mentioned operation structure 100 receives the data group processing sequence of different groups determined by the scheduling module 200. This data group processing sequence generally limits the order of input of different groups of data from a coarse and fine granular perspective. It does not restrict the actual order of processing in each processing unit within the operation structure 100 during the actual processing process, nor does it care about the time order of the final output results.

[0135] For example, if the scheduling module 200 instructs data group 1 to be input and processed first, and data group 2 to be input and processed later, then the processing sequence of the data groups is considered to be as follows on the side of the operation structure 100: data group 1 is input first, and data group 2 is input later.

[0136] As described in the above embodiments, when the input data processing unit 110 reads data from the shared cache unit 150, it determines the target data type to be processed in the current processing cycle according to the processing sequence indicated by the scheduling module (i.e., the data group processing sequence described in this embodiment), and reads the target data of the corresponding target data type from the shared cache unit 150, using the target data as the input data to be processed. That is, after the operation structure 100 receives the data group processing sequence, the input data processing unit 110 in the operation structure 100 reads the corresponding data group from the shared cache unit 150 according to the data group processing sequence.

[0137] Subsequently, within the arithmetic structure 100, the corresponding processing flow for integer or floating-point input is executed according to the previously described embodiment. Each processing unit within the arithmetic structure (such as the multiplier unit 121, exponent alignment unit 122, adder unit 123, normalization and rounding unit 124 in the multiply-add unit 120, or may further include at least one of the following units: bit selection unit 125, input adjustment unit 140, data output unit 130, etc.) records the timestamp of the input start execution, the start execution state corresponding to the execution start timestamp, the execution in progress state corresponding to the execution of the corresponding processing operation, the timestamp corresponding to the completion of the operation, the execution end state corresponding to the execution completion time, and the idle state from the end of the current operation execution until waiting for the next data input. This processing state record table can be stored in a pre-defined storage space, which is a storage space that the scheduling module 200 has permission to access.

[0138] Reference Figure 5 As shown in the data stream corresponding to sequence number ②, the operation structure 100 will also specify the timing of acquiring each group of inputs during actual execution (e.g., in...). Figure 6In the corresponding architecture, the timing of data acquisition corresponds to the timestamp of the input data processing unit 110 actually acquiring data from the shared cache unit 150, and the current processing status of each processing unit in the operation structure (such as the multiplier unit 121, exponent alignment unit 122, adder unit 123, normalization and rounding unit 124 in the multiply-accumulate unit 120, or may further include at least one of the following units: bit selection unit 125, input adjustment unit 140, data output unit 130, etc.) is synchronized to the scheduling module 200. For example, the above information synchronization can be performed through an internal communication line, or the scheduling module 200 can achieve information synchronization by accessing the agreed storage space.

[0139] The aforementioned scheduling module 200 is pre-configured with the aforementioned processing priority information. Based on the aforementioned scheduling module, it is possible to set the processing priorities of each unit within the computational structure in a more granular manner. When considering the aforementioned priority order, if satisfying the priority order results in an inability to obtain a better scheduling sequence (for example, it is impossible to obtain the input timing of the current unit for the related computation output result of the previous unit under the condition that the sum of the processing interval duration of each unit and the idle time within the unit is minimized), then according to the relative importance of priority and timing density, the condition with higher relative importance is satisfied first, while the other condition is slightly sacrificed. The other condition adopts a suboptimal solution rather than an optimal solution.

[0140] The scheduling module 200 can generate scheduling information based on the timing of the acquisition of different input data groups (the actual execution of the operation structure), the current processing status of each processing unit in the operation structure, and the processing priority information.

[0141] In some embodiments, the strategy for generating the scheduling information includes: determining the input timing of the first unit after the data acquisition unit in the above-mentioned operation structure corresponding to different input data groups based on the acquisition timing of different input data groups by the input data processing unit 110, wherein the first unit is one of the following: an input adjustment unit, a bit selection unit, or a multiplier unit; for each subsequent unit after the first unit (the order is perceived by the direction of the data flow), analyzing the processing completion time of the previous unit for one or more input data groups, whether the current unit is idle or occupied, and the processing priority information, and determining the input timing of the current unit for the relevant operation output result of the previous unit under the condition that the sum of the processing interval duration of each unit and the idle time within the unit is minimized or the processing priority information is satisfied.

[0142] Reference Figure 6As shown in the data stream corresponding to number ③, the scheduling module 200 sends the generated scheduling information to the arithmetic structure 100, for example, to the control unit in the arithmetic structure.

[0143] Then, refer to Figure 6 As shown in the data stream corresponding to sequence number ②-1, for the processing of a certain set of input data, as the data processing in the operation structure 100 is actually executed, the operation structure 100 continuously synchronizes the current processing status of each internal processing unit to the scheduling module 200 after the update.

[0144] The scheduling module 200 will generate updated scheduling information based on the timing of the acquisition of different input data groups (the actual execution status of the operation structure), the current processing status and processing priority information of each processing unit in the updated operation structure.

[0145] Reference Figure 6 As shown in the data stream corresponding to sequence number ③-1, the scheduling module 200 sends the updated scheduling information to the computation structure 100. Subsequently, the information will be continuously iterated and updated as the data processing execution progresses until the computation of all data groups is completed. Figure 7 The ellipsis is used to indicate the subsequent iterative update process.

[0146] Figure 7 This schematically illustrates the timing distribution of an arithmetic structure compatible with integer and floating-point processing according to an embodiment of the present disclosure, under the scheduling of a scheduling module, where three sets of inputs (a) data set 1, (b) data set 2, and (c) data set 3 are processed respectively. Figure 7 In the diagram, the dashed arrows indicate the direction of time progression. During the processing of data from the same input data set, internal processing units can process different inputs in parallel. The corresponding processing time periods are illustrated using a staggered approach. (Refer to...) Figures 5-7 The situations illustrated in (b) and (c) are as follows.

[0147] Combination Figure 7As shown in (a) to (c), as an example, the three sets of input data are data set 1: {A1, B1, C1; int64}, data set 2: {A2, B2, C2; float64}, and data set 3: {A3, B3, C3; float64}. The arithmetic structure 100, which is compatible with both integer and floating-point processing, includes: a shared cache unit 150, an input data processing unit 110, and a multiply-accumulate unit 120. The multiply-accumulate unit 120 includes: a multiplier unit 121, an exponent alignment unit 122, an adder unit 123, and a normalization and rounding unit 124 as an example. In this embodiment, integer input does not need to be processed by the exponent alignment unit 122, nor by the normalization and rounding unit 124. Therefore, in... Figure 7 The above situation is illustrated using a single-dot bounding box.

[0148] Assuming the above-mentioned operational structure 100 obtains three sets of input data from the scheduling module 200: the processing sequence of data sets 1 to 3 is as follows: first input data set 1, then input data set 2, and finally input data set 3; then, the input data processing unit 110 obtains the data corresponding to data set 1, data set 2, and data set 3 sequentially from the data sets already cached by the shared cache unit 150, and records the acquisition time of the input: for example, the time of acquiring data set 1 is t11, the time of acquiring data set 2 is t12, and the time of acquiring data set 3 is t13, where t11 < t12 < t13, and < means earlier than, that is, t11 occurs before t12, and t12 occurs before t13; assuming the time difference between t12 and t11 is 1ns, and the time difference between t13 and t12 is 1ns; assuming that the current processing state of each processing unit in the operational structure 100 is idle at time t11; then the scheduling module generates scheduling information based on the generation strategy described above.

[0149] Specifically, the input timing of the first unit in the operation structure corresponding to different input data groups is determined based on the acquisition timing of different input groups. In this embodiment, based on the acquisition time t11 < t12 < t13, it can be determined that the input timing of multiplier unit 121 is the order corresponding to data group 1, data group 2, and data group 3. Assuming that at time t11, A1 and B1 in data group 1 are input to multiplier unit 121 for processing, and assuming the processing time is Δt1 = 2ns (the specific value is only for example, and the specific value and the order of magnitude of the time scale can vary), then multiplier unit 121 performs the multiplication operation of A1 and B1 during the time period t11~t11+Δt1 (that is, t11~t11+2). The time when the occupation of multiplier unit 121 by A1 and B1 ends is simplified to t11+Δt1 (there may be some delay in reality, which is simplified here). Then, at time t11+Δt1, the mantissas A2 and B2 of data group 2 are input for processing, assuming the processing time is Δt2=2.5ns; then, during the time period t11+Δt1~t11+Δt1+Δt2 (i.e., t11+2~t11+4.5), multiplier unit 121 performs the multiplication operation of mantissas A2 and B2; similarly, at time t11+Δt1+Δt2, the mantissas A3 and B3 of data group 3 are input for processing, assuming the processing time is Δt3=1ns; then, during the time period t11+Δt1+Δt2~t11+Δt1+Δt2+Δt3 (i.e., t11+4.5~t11+5.5), multiplier unit 121 performs the multiplication operation of mantissas A3 and B3.

[0150] For each subsequent unit in the operation structure, the processing completion time of the previous unit for one or more sets of input data, the current processing status of the current unit (whether it is idle or occupied), and the processing priority information are analyzed to determine the input timing of the current unit for the relevant operation output results of the previous unit, under the condition that the processing interval of each unit and the total idle time within the unit are minimized.

[0151] Specifically, after time t11+Δt1, for example, at time t21 (t11+Δt1<t21), the operation result A1×B1 obtained by multiplier unit 121 (analysis example of the current unit) and another input C1 are both input to adder unit 123. The processing completion time of multiplier unit 121 for one or more sets of inputs is as follows: For example, if the time difference between t21 and t11+Δt1 is very small, which is 0.1ns, then at time t21 (t11+2.1), there is the multiplication processing result of data group 1. Data group 2 is input to multiplier unit 121 and has just started processing. At this time, the multiplier unit is in an occupied state, and data group 3 has not yet been input to multiplier unit 121 for processing. That is, in this case, only data group 1 corresponds to the processing completion time in multiplier unit 121, which is t11+Δt1. Assuming that in scenario 1, the processing priority information for adder unit 123 is: Data group 1 > (priority higher than) Data group 3 > Data group 2. Then, the operation result A1×B1 output by multiplier unit 121 and the other input C1 correspond to the next unit: the input timing of adder unit 123 is t21 (t11+2.1). Assuming that the summation processing of A1×B1 and C1 in adder unit 123 takes Δt4 = 2ns, then adder unit 123 performs the addition operation within the time period t21 (t11+2.1) ~ t21+Δt4 (that is, t11+2.1 ~ t11+4.1) to obtain A1×B1+C1. Afterwards, A1×B1+C1 is directly output through the data output unit 130. Assuming the output time is Δt5=0.1ns, the data output unit 130 will output the integer processing result during the time period t21+Δt4~t21+Δt4+Δt5 (that is, t11+4.1~t11+4.2).

[0152] For the exponent alignment unit 122, the processing priority information is: data group 2 > data group 3. Therefore, the corresponding exponents of data group 2 are input first, followed by the corresponding exponents of data group 3 for processing. Assume that the time when the A2 exponent, B2 exponent, and C2 exponent of data group 2 are input to the exponent alignment unit 122 is t12 (i.e., t11+1). Assume that the time required for the exponent alignment unit 122 to perform the summation of the A2 exponent and B2 exponent and the alignment with the C2 exponent is Δt6 = 1ns. Then, within the time period t12~t12+Δt6 (i.e., t11+1~t11+2), the summation of the A2 exponent and B2 exponent and the alignment with the C2 exponent are performed.

[0153] Assuming that at time t12+Δt6 (i.e. t11+2), the A3 exponent, B3 exponent, and C33 exponent of data group 3 are input into the exponent alignment unit 122, and the time required for the exponent alignment unit 122 to perform the summation of the A3 exponent and B3 exponent and the alignment with the C3 exponent is Δt7=1ns; then during the time period t12+Δt6~t12+Δt6+Δt7 (i.e. t11+2~t11+3), the summation of the A3 exponent and B3 exponent and the alignment with the C3 exponent are performed.

[0154] Reference Figure 7 As shown in (a) to (c), for adder unit 123, during the time period t21(t11+2.1) to t21+Δt4 (that is, t11+2.1 to t11+4.1), adder unit 123 performs addition operation processing of A1×B1 and C1, and this time period is occupied.

[0155] After t21+Δt4 (i.e., t11+4.1), adder unit 123 enters an idle state. Since in case 1, the processing priority information for adder unit 123 is: Data group 1 > (priority higher than) Data group 3 > Data group 2, from the perspective of the scheduling information generation strategy, if the condition of minimizing the sum of the processing interval duration of each unit and the idle time within the unit is prioritized, since the A2 exponent and B2 exponent addition processing is completed at time t12+Δt6 (i.e., t11+2),... And the process of aligning with the C2 exponent; at time t12+Δt6+Δt7 (i.e., t11+3), the summation of the A3 and B3 exponents and the alignment with the C3 exponent are completed; that is, while waiting for adder unit 123 to process data group 1 during the time period t21(t11+2.1)~t21+Δt4 (i.e., t11+2.1~t11+4.1), the exponent summation and exponent alignment operations of data group 2 and data group 3 have been completed, according to data group 2 The time periods for mantissa multiplication operations in data group 1 and data group 2 are: t11+Δt1~t11+Δt1+Δt2 (i.e., t11+2~t11+4.5) and t11+Δt1+Δt2~t11+Δt1+Δt2+Δt3 (i.e., t11+4.5~t11+5.5). That is, adder unit 123 completes the addition operation in data group 1 at time t21+Δt4 (i.e., t11+4.1). Since data group 2... During the mantissa multiplication process, no specific result has been obtained yet. Therefore, it is necessary to wait until the most recent mantissa product result is obtained to minimize the idle time within the unit. The input timing that minimizes the unit idle time is: first input the product result of data group 2, which is the first data group to output a result. That is, input the mantissa product result corresponding to data group 2 at time t11+Δt1+Δt2 (i.e., t11+4.5). This prioritizes satisfying the condition of minimizing the sum of the processing interval time of each unit and the idle time within the unit. This situation occurs in... Figure 7 The diagram in (b) is illustrated.

[0156] Assuming that the processing time of adder unit 123 for shifting the mantissa product result and adding it to the mantissa of another floating-point input is Δt8 = 2ns, then during the time period t11 + Δt1 + Δt2 ~ t11 + Δt1 + Δt2 + Δt8 (i.e., t11 + 4.5 ~ t11 + 6.5), adder unit 123 performs shifting and mantissa addition operations on data group 2.

[0157] Subsequently, similarly, assuming the processing time for data group 3 is Δt9 = 1ns, then within the time period t11 + Δt1 + Δt2 + Δt8 ~ t11 + Δt1 + Δt2 + Δt8 + Δt9 (i.e., t11 + 6.5 ~ t11 + 7.5), adder unit 123 performs shift processing and mantissa addition operation processing for data group 3.

[0158] For the adder unit, if prioritizing the processing priority information leads to the suboptimal solution with the smallest sum, then it is necessary to wait for the mantissa multiplication of data group 3 to finish, i.e., inputting the mantissa product result of data group 3 at time t11+Δt1+Δt2+Δt3 (i.e., t11+5.5); thus achieving the condition of prioritizing the processing priority information while weakening the requirement for the smallest sum. Subsequent analysis is similar and will not be elaborated further.

[0159] For normalization and rounding unit 124, assuming the processing priority information is: Data group 1 > (priority higher than) Data group 2 > Data group 3, refer to... Figure 7 As shown in (b), the following time period can be obtained: t11+Δt1+Δt2+Δt8~t11+Δt1+Δt2+Δt8+Δt10 (that is, t11+6.5~t11+7.5), where Δt10=1ns (the specific time consumption value is used as an example, and the following is similar), which means that the output processing time corresponding to data group 2 is used to perform normalization and rounding processing on the output result to obtain the floating-point processing result.

[0160] Similarly, refer to Figure 7 As shown in (c), the time interval is max{t11+Δt1+Δt2+Δt8+Δt9, t11+Δt1+Δt2+Δt8+Δt10}~max{t11+Δt1+Δt2+Δt8+Δt9, t11+Δt1+Δt2+Δt8+Δt10}+Δt11; where Δt11=1ns, representing the time taken for the output processing of data group 3 to perform normalization and rounding of the output result, resulting in a floating-point processing result. Since the value of max above is t11+7.5, the corresponding time interval is t11+7.5~t11+8.5.

[0161] Based on the scheduling process indicated by the above scheduling information, it can be seen that for the multiply-add unit 120, there are cases where different types of data processing flows appear in the same time period and correspond to different processing units. That is, for a large number of input data groups that need to be processed, in the multiplexed floating-point multiply-add unit, based on the above time-division multiplexing, there are cases where the multiplier unit processes the first type of data and the adder unit processes the second type of data in the same time period; the first type and the second type are different and are either integer or floating-point. For example, in the time period t11+2~t11+4.5 (corresponding to...)Figure 7 During the processing period corresponding to Δt2 in (b), data group 2 is being processed in multiplier unit 121, while data group 1 is in the time period t11+2.1~t11+4.1 in adder unit 123 (corresponding to...). Figure 7 Processing was performed during the processing period corresponding to Δt4 in (a); then, processing was performed again during the period t11+4.1~t11+4.2 (corresponding to...). Figure 7 The data is processed in the data output unit 130 during the processing period corresponding to Δt5 in (a).

[0162] As an example, another scenario is where, within the same time period, the multiplier unit processes data corresponding to the first input data group, and the adder unit processes data corresponding to the second input data group. The data corresponding to the first and second input data groups have the same data type but different input groups. This scenario exists in the following examples (not all are listed here, only examples are provided): [Refer to...] Figure 7 The multiplier unit shown in diagram (c) processes data group 3 (floating-point input data group, different input data groups) during the time period corresponding to Δt3. ​ The adder unit shown in (b) processes data group 2 (floating-point input data group, different input data groups) during the time period corresponding to Δt8.

[0163] It is understandable that the examples above are illustrative of execution time values ​​to highlight specific scheduling scenarios. In actual execution, the examples are not limited to these values ​​and dynamic scheduling can be performed based on actual execution times. Generally, based on experience, the execution times of multiplier and adder units can be fixed or variable. For example, the calculation times Δt1, Δt2, and Δt3 for multipliers can be equal or different; similarly, the calculation times Δt4, Δt8, and Δt9 for adders can be equal or different. The same applies to the output unit; Δt5, Δt10, and Δt11 can be equal or different.

[0164] This embodiment improves the strategy for generating scheduling information in the scheduling module. This not only ensures that the multiply-accumulate operation unit achieves space saving through reuse, but also further optimizes the operation, primarily by scheduling the data processing sequence within the multiply-accumulate operation unit 120 in the operation structure 100. This minimizes the processing interval (the difference between the first moment when the previous unit outputs the result and the second moment when the next unit finishes processing and transitions to an idle state, ready to input data for processing) and the idle time within a unit (a unit can process multiple sets of data sequentially). There may be gaps between data points, which may be idle periods due to waiting for the result of the previous unit to be calculated. The goal is to minimize the sum of these gaps. When multiple sets of inputs are processed within the multiply-accumulate unit, the different processing units (such as multiplier units, exponent alignment units, adder units, and normalization and rounding units) have the following effects on the pipelined data processing sequence for multiple sets of input data: they can ensure that high-priority input data sets are processed first, and / or improve the processing time utilization of the multiplexed floating-point multiply-accumulate unit, making the pipeline operation time more compact, thereby greatly reducing the impact of the multiplexed architecture on the overall task processing time.

[0165] A second exemplary embodiment of this disclosure provides a data processing method applied to the computational structure of the first embodiment.

[0166] The above data processing methods include: Based on the input data processing unit, the input data is formatted according to the data type of the input data to be processed, wherein the data type of the input data is integer or floating-point. Based on the multiply-accumulate unit, multiply-accumulate operations are performed on different types of input data; for floating-point input data, multiply-accumulate operations are performed through the multiplier unit, the adder unit, and the floating-point dedicated operation unit; for integer input data, multiply-accumulate operations are performed through the multiplier unit and the adder unit, and the floating-point dedicated operation module is disabled. Based on the data output unit, when the input data is an integer, the result of the multiplication and addition operation is output; when the input data is a floating-point number, the result of the multiplication and addition operation is adjusted to adapt to the floating-point data format before the operation result is output.

[0167] In this process, both the multiplier unit and the adder unit are time-division multiplexed, and the processing of different types of inputs is distributed across different time periods for the same multiplier unit or the same adder unit.

[0168] In some embodiments, the above data processing method further includes: Based on the control unit, scheduling information is received, and the multiply-accumulate operation unit and the data output unit are controlled to execute corresponding data processing timing based on the scheduling information. The scheduling information is generated according to the acquisition timing of different input data groups, the current processing status of each unit in the operation structure, and the processing priority information. The processing priority information is used to indicate at least one of the following: the processing priority of a certain group in different input data groups for all units in the operation structure is set to the highest, and the preset priority order of the processing priorities of each group in different input data groups for at least some units in the operation structure. The strategy for generating the aforementioned scheduling information includes: determining the input timing of the first unit following the input data processing unit in the aforementioned operational structure corresponding to different input data groups based on the timing of the input data processing unit's acquisition of different input data groups. The first unit can be one of the following: an input adjustment unit, a bit selection unit, or a multiplier unit. For each subsequent unit after the first unit, the timing of the input of the relevant operation output result of the previous unit is determined by analyzing the processing completion time of the previous unit for one or more input data groups, whether the current unit is idle or occupied, and the processing priority information, under the condition that the sum of the processing interval duration of each unit and the idle time within the unit is minimized or the processing priority information is satisfied.

[0169] In some embodiments, the scheduling module is located outside the computing structure but inside the electronic device containing the computing structure. In other embodiments, the scheduling module may also be a functional module within the computing structure.

[0170] Based on the aforementioned scheduling module, the processing priorities of each unit within the computational structure can be set at a more granular level. When considering the priority order, if satisfying the priority order results in an unoptimized scheduling sequence (e.g., failing to determine the input timing of the current unit's output result related to the previous unit while minimizing the sum of the processing interval duration and idle time within each unit), then, based on the relative importance of priority and timing density, the more important condition is satisfied first, while slightly sacrificing another condition. The other condition adopts a suboptimal solution rather than an optimal one. For example, prioritizing the condition of minimizing the sum of the processing interval duration and idle time within each unit allows disregarding the processing priority information corresponding to one or more processing units in the computational structure. Alternatively, priority can be given to satisfying the processing priority information corresponding to one or more processing units, and only the suboptimal solution corresponding to the smaller sum of the processing interval duration and idle time within each unit can be solved.

[0171] For more details of this embodiment and subsequent embodiments, please refer to the relevant description of the first embodiment, which will not be repeated here.

[0172] A third exemplary embodiment of this disclosure provides a processor. The processor includes the arithmetic structure for compatible integer and floating-point processing provided in the first embodiment, or is used to implement the data processing method provided in the second embodiment. For example, the processor is a digital signal processor, a vector processing unit, etc.

[0173] The fourth exemplary embodiment of this disclosure provides a chip. The processor described above includes the arithmetic structure for compatible integer and floating-point processing provided in the first embodiment, or is used to implement the data processing method provided in the second embodiment, or includes the processor provided in the third embodiment. The chip described above may include, but is not limited to, image processing chips, AI (artificial intelligence) related processing chips, arithmetic chips, data processing chips, etc.

[0174] A fifth exemplary embodiment of this disclosure provides an electronic device. The electronic device includes an arithmetic structure compatible with integer and floating-point processing provided in the first embodiment, or is used to implement the data processing method provided in the second embodiment, or includes a processor provided in the third embodiment, or includes a chip provided in the fourth embodiment. The electronic device may be a terminal device or a server. The terminal device includes, but is not limited to, smartphones, smart vehicles, desktop computers, laptops, smartwatches, smart bracelets, smart robots, wearable devices, etc.

[0175] At least one of the units mentioned in the embodiments of this disclosure can be implemented at least partially as a hardware circuit, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging the circuit, or as a suitable combination of any one of the three implementation methods of software, hardware, and firmware.

[0176] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0177] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. An operational structure, characterized in that, The operational structure includes: An input data processing unit is used to perform format processing on the input data according to the data type of the input data to be processed, wherein the data type of the input data is integer or floating-point. The multiply-accumulate unit is used to perform multiply-accumulate operations in response to different types of input data; wherein, for floating-point input data, multiply-accumulate operations are performed through a multiplier unit, an adder unit, and a dedicated floating-point arithmetic unit; for integer input data, multiply-accumulate operations are performed through the multiplier unit and the adder unit, and the dedicated floating-point arithmetic unit is disabled. The data output unit is used to output the result of the multiplication and addition operation when the input data is an integer, and to output the operation result after adjusting the multiplication and addition operation result to adapt to the floating-point data format when the input data is a floating-point type.

2. The operational structure according to claim 1, characterized in that, The input data processing unit is configured to perform sign bit extension on the integer input data when the data type of the input data is integer, and to perform splitting of the sign bit, exponent bit, and mantissa bit on the floating-point input data when the data type of the input data is floating-point.

3. The operational structure according to claim 1 or 2, characterized in that, The input data to be processed includes: a first floating-point input, a second floating-point input, and a third floating-point input; the dedicated floating-point arithmetic unit includes: an exponent alignment unit and a normalization and rounding unit. The multiplication and addition operation processing through the multiplier unit, adder unit, and floating-point dedicated arithmetic unit includes: The multiplier unit and the exponent alignment unit perform multiplication operations on the first floating-point input and the second floating-point input to obtain the floating-point multiplication result. The adder unit performs an addition operation on the floating-point multiplication result and the floating-point third input to obtain the floating-point addition result. The normalization and rounding unit performs at least one of the mantissa normalization and rounding operations on the floating-point addition result to obtain the floating-point operation result.

4. The operational structure according to claim 3, characterized in that, The multiplier unit is used to perform multiplication operations on the mantissa portion of the first floating-point input and the mantissa portion of the second floating-point input to obtain a floating-point mantissa multiplication result. The exponent alignment unit is used to perform addition operations on the exponent portions of the first floating-point input and the second floating-point input to obtain a floating-point exponent addition result; and to perform alignment operations on the floating-point exponent addition result and the exponent portion of the third floating-point input to obtain an exponent alignment operation result. The alignment operation is based on aligning the larger of the floating-point exponent addition result and the exponent part of the third input. The adder unit is configured to perform mantissa shift adjustment on the mantissa portion corresponding to the smaller of the floating-point exponent addition result and the exponent portion of the floating-point third input, based on the exponent alignment operation result, and perform addition operation on the mantissa portion corresponding to the larger one to obtain a floating-point addition operation result; wherein, the mantissa portion corresponding to the smaller one is the mantissa portion of the floating-point mantissa multiplication result or the mantissa portion of the third input.

5. The operational structure according to claim 4, characterized in that, The multiply-add operation unit further includes: a sign bit operation unit and a representation conversion unit; The sign bit operation unit is used to perform an XOR operation on the sign bits of the first floating-point input and the second floating-point input when the first floating-point input, the second floating-point input, and the third floating-point input are all signed data and are all represented using binary sign-magnitude representation, to obtain a sign bit multiplication result; and to concatenate the sign bit multiplication result with the floating-point mantissa multiplication result to obtain a signed floating-point mantissa multiplication result; The representation conversion unit is used to convert the signed floating-point mantissa multiplication result and the floating-point third input into two's complement form and then input them to the adder unit for corresponding processing when the first floating-point input, the second floating-point input, and the third floating-point input are all signed data and are all represented using binary sign-magnitude representation.

6. The operational structure according to claim 3, characterized in that, The multiply-add unit further includes a bit selection unit, which is used to select the corresponding input bit segment according to the first control signal and input it into the multiplier unit, the adder unit and the exponent alignment unit. Selecting corresponding input bit segments according to a first control signal and inputting them to a multiplier unit, an adder unit, and an exponent alignment unit includes: responding to a first control signal generated based on a floating-point data type, selecting a first input bit segment corresponding to the mantissa portion of a floating-point first input and the mantissa portion of a floating-point second input and inputting it to the multiplier unit; selecting a second input bit segment corresponding to the mantissa portion of a floating-point third input and inputting it to the adder unit; and selecting a third input bit segment corresponding to the exponent portion of each of the floating-point first input, the floating-point second input, and the floating-point third input and inputting it to the exponent alignment unit.

7. The operational structure according to claim 3, characterized in that, Also includes: The input adjustment unit is used to perform at least one operation of negation and absolute value calculation on at least one of the floating-point first input, floating-point second input and floating-point third input to obtain the adjusted result, and input the adjusted result as input data into the multiply-accumulate operation unit.

8. The operational structure according to claim 3, characterized in that, Also includes: Shared cache unit; The shared cache unit supports the storage of integer and floating-point data, including: after data of the first type is read from the storage unit in the shared cache unit, data of the second type is allowed to be written to the same storage unit; the first type and the second type are different types, and are either integer or floating-point; the index information of the shared cache unit includes: the mapping relationship between the address where the data is located, the data type, and the data identifier; The input data processing unit is also used to read data from the shared cache unit to obtain the input data to be processed; When the input data processing unit reads data from the shared cache unit, it determines the data identifier and corresponding target data type of the target data to be processed in the current processing cycle according to the processing sequence indicated by the scheduling module that interacts with the computing structure, determines the target address corresponding to the data identifier and the target data type according to the index information, and reads the corresponding target data from the shared cache unit according to the target address, and uses the target data as the input data to be processed.

9. The operational structure according to claim 1 or 2, characterized in that, The input data to be processed includes: a first integer input, a second integer input, and a third integer input. The multiplication-addition operation performed by the multiplier unit and the adder unit includes: Based on the multiplier unit, the integer first input and the integer second input are multiplied to obtain an integer multiplication result; based on the adder unit, the integer multiplication result and the integer third input are added to obtain an integer operation result.

10. The operational structure according to claim 9, characterized in that, The multiply-add operation unit further includes: a sign bit operation unit and a representation conversion unit; The sign bit operation unit is used to perform an XOR operation on the sign bits of the first integer input and the second integer input when the first integer input, the second integer input, and the third integer input are all signed data and are all represented using binary original code, to obtain a sign bit multiplication result; and to concatenate the sign bit multiplication result with the integer multiplication result to obtain a signed integer multiplication result. The representation conversion unit is used to convert the signed integer multiplication result and the third integer input into two's complement form and then input them to the adder unit for corresponding processing when the first integer input, the second integer input, and the third integer input are all signed data and are all represented using binary sign-magnitude representation.

11. The operational structure according to claim 9, characterized in that, The multiply-add unit further includes a bit selection unit, which is used to select the corresponding input bit segment according to the second control signal and input it to the multiplier unit and the adder unit. Selecting the corresponding input bit segment according to the second control signal and inputting it into the multiplier unit and the adder unit includes: in response to the second control signal generated based on the integer data type, selecting the fourth input bit segment corresponding to all data of the first integer input and the second integer input or all other data without the sign bit and inputting it into the multiplier unit, and selecting the fifth input bit segment corresponding to the third integer input and inputting it into the adder unit.

12. The operational structure according to claim 9, characterized in that, Also includes: The input adjustment unit is used to perform at least one operation of negating the sign and calculating the absolute value for at least one of the integer first input, integer second input and integer third input, to obtain the adjusted result, and input the adjusted result as input data into the multiply-accumulate operation unit.

13. The operational structure according to claim 9, characterized in that, Also includes: Shared cache unit; The shared cache unit supports the storage of integer and floating-point data, including: after data of the first type is read from the storage unit in the shared cache unit, data of the second type is allowed to be written to the same storage unit; the first type and the second type are different types, and are either integer or floating-point; the index information of the shared cache unit includes: the mapping relationship between the address where the data is located, the data type, and the data identifier; The input data processing unit is also used to read data from the shared cache unit to obtain the input data to be processed; When the input data processing unit reads data from the shared cache unit, it determines the data identifier and corresponding target data type of the target data to be processed in the current processing cycle according to the processing sequence indicated by the scheduling module that interacts with the computing structure, determines the target address corresponding to the data identifier and the target data type according to the index information, and reads the corresponding target data from the shared cache unit according to the target address, and uses the target data as the input data to be processed.

14. The operational structure according to claim 1 or 2, characterized in that, Both the multiplier unit and the adder unit are time-division multiplexed, and for the same multiplier unit or the same adder unit, the processing of different types of inputs is distributed in different time periods.

15. The operational structure according to claim 14, characterized in that, Multiple input data sets are sequentially input into the computational structure for processing; In the multiply-add unit, the time-division multiplexing occurs in at least one of the following situations: within the same time period, the multiplier unit processes data of a first type, and the adder unit processes data of a second type; the first type and the second type are different, and are either integer or floating-point; or, within the same time period, the multiplier unit processes data corresponding to a first input data group, and the adder unit processes data corresponding to a second input data group, wherein the data corresponding to the first input data group and the data corresponding to the second input data group have the same data type but different input data groups.

16. The operational structure according to claim 1 or 2, characterized in that, The computational structure further includes a control unit, which is used to receive scheduling information from the scheduling module and control the multiply-accumulate unit and the data output unit to execute corresponding data processing timing based on the scheduling information; The scheduling information is generated based on the acquisition timing of different input data groups, the current processing status of each unit in the operation structure, and the processing priority information. The processing priority information is used to indicate at least one of the following: the processing priority of a certain group in different input data groups for all units in the operation structure is set to the highest; the preset priority order of the processing priorities of each group in different input data groups for at least some units in the operation structure. The strategy for generating the scheduling information includes: determining the input timing of the first unit after the input data processing unit in the operation structure corresponding to different input data groups based on the timing of the input data processing unit acquiring different input data groups. The first unit can be one of the following: an input adjustment unit, a bit selection unit, or a multiplier unit. For each subsequent unit after the first unit, the timing of the input of the relevant operation output result of the previous unit is determined by analyzing the processing completion time of the previous unit for one or more input data groups, whether the current unit is idle or occupied, and the processing priority information, under the condition that the sum of the processing interval duration of each unit and the idle time within the unit is minimized or the processing priority information is satisfied.

17. A data processing method, characterized in that, The method, applied to the operational structure of any one of claims 1-16, comprises: Based on the input data processing unit, the input data is formatted according to the data type of the input data to be processed, wherein the data type of the input data is integer or floating-point. Based on the multiply-accumulate unit, multiply-accumulate operations are performed on different types of input data; specifically, for floating-point input data, multiply-accumulate operations are performed through the multiplier unit, the adder unit, and the dedicated floating-point arithmetic unit; for integer input data, multiply-accumulate operations are performed through the multiplier unit and the adder unit, and the dedicated floating-point arithmetic unit is disabled. Based on the data output unit, when the input data is an integer, the result of the multiplication and addition operation is output; when the input data is a floating-point number, the result of the multiplication and addition operation is adjusted to adapt to the floating-point data format before the operation result is output.

18. The data processing method according to claim 17, characterized in that, Also includes: Based on the control unit, scheduling information is received, and the multiply-accumulate unit and the data output unit are controlled to execute the corresponding data processing timing based on the scheduling information; The scheduling information is generated based on the acquisition timing of different input data groups, the current processing status of each unit in the operation structure, and the processing priority information. The processing priority information is used to indicate at least one of the following: the processing priority of a certain group in different input data groups for all units in the operation structure is set to the highest; the preset priority order of the processing priorities of each group in different input data groups for at least some units in the operation structure. The strategy for generating the scheduling information includes: determining the input timing of the first unit after the input data processing unit in the operation structure corresponding to different input data groups based on the timing of the input data processing unit acquiring different input data groups. The first unit can be one of the following: an input adjustment unit, a bit selection unit, or a multiplier unit. For each subsequent unit after the first unit, the timing of the input of the relevant operation output result of the previous unit is determined by analyzing the processing completion time of the previous unit for one or more input data groups, whether the current unit is idle or occupied, and the processing priority information, under the condition that the sum of the processing interval duration of each unit and the idle time within the unit is minimized or the processing priority information is satisfied.

19. A processor, characterized in that, It includes the operational structure described in any one of claims 1-16, or is used to perform the data processing method described in claim 17 or 18.

20. A chip, characterized in that, It includes the operational structure described in any one of claims 1-16, or is used to perform the data processing method described in claim 17 or 18, or includes the processor described in claim 19.

21. An electronic device, characterized in that, It includes the operational structure of any one of claims 1-16, or is used to perform the data processing method of claim 17 or 18, or includes the processor of claim 19, or includes the chip of claim 20.

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