Computing power server load distribution method and system based on structure perception

Abstract

The invention discloses a computing power server load distribution method and system based on structure perception, and relates to the technical field of multi-core processor scheduling processing. According to the method, task core structure information is collected in real time, task types are determined, three types of structure conflict indexes including a cache conflict index, a power consumption interference factor and an execution unit overlapping degree are calculated, a structure conflict matrix is constructed, a matrix spectrum balance method is adopted to realize load distribution, and hidden conflicts are converted into computable numerical values; local optimization deviation is avoided, the cache hit rate is improved, task delay and performance fluctuation are reduced, the core temperature peak value and power consumption waste are reduced, and collaborative optimization of performance, stability and energy consumption efficiency of the multi-core CPU computing power server is achieved.

Description

Technical Field

[0001] This invention relates to the field of multi-core processor scheduling technology, and in particular to a structure-aware computing server load distribution method and system. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and cloud computing, multi-core CPUs have become the core support for general-purpose computing servers, significantly improving overall computing performance by increasing the number of cores and parallel capabilities. Modern computing servers are widely used in data centers and scientific research computing, and task scheduling and load distribution have become key aspects to ensure the efficient utilization of computing power.

[0003] However, traditional load balancing methods primarily rely on core utilization and task quantity for scheduling, neglecting the fine-grained characteristics of multi-core architectures. This leads to three main problems: First, shared cache consistency domain conflicts. In multi-core CPU computing servers, caches are typically divided into three levels (L1, L2, L3). Frequent reads and writes between cores sharing the L3 cache cause a decrease in cache hit rate. Second, power domain frequency scaling conflicts. High-load tasks trigger voltage / frequency domain throttling, affecting the performance of low-load tasks in the same domain. Third, execution unit contention. In SMT or superscalar architectures, concurrent execution of floating-point or memory-intensive tasks can lead to contention for shared execution units, reducing instructions per cycle (IPC). Summary of the Invention

[0004] The purpose of this invention is to provide a structure-aware computing server load distribution method and system to improve the above-mentioned technical problems.

[0005] To achieve the above-mentioned objectives, the embodiments of the present invention provide the following technical solutions:

[0006] A structure-aware computing server load allocation method, comprising:

[0007] Real-time acquisition of core task structure information for each task in a multi-core CPU computing server, and determination of task type;

[0008] Based on the core structure information of the task and the types of each task, calculate the task structure conflict index of each task at the current moment; the task structure conflict index includes cache conflict index, power consumption interference factor and execution unit overlap.

[0009] Based on the structural conflict indicators of each task, a structural conflict matrix is ​​constructed, and the load is allocated to each task using the matrix spectrum balancing method to obtain the load allocation result; the load allocation result includes a task-core allocation matrix, a core state vector, and a task conflict indicator table.

[0010] In the above solution, this invention collects core task structure information in real time and determines the task type. It calculates three types of structural conflict indicators: cache conflict index, power consumption interference factor, and execution unit overlap. Then, it constructs a structural conflict matrix and uses the matrix spectrum balancing method to achieve load allocation. This effectively solves the technical problems of traditional load allocation, which relies solely on core utilization, cannot quantify cache sharing, power domain coupling, and execution unit contention, as well as the difficulties of Bayesian and other probabilistic methods in adapting to the deterministic structural competition of multi-core CPUs, easily leading to resource overruns, and large-scale scheduling efficiency and accuracy imbalances. The three types of indicators transform implicit conflicts into calculable values, avoiding local optimization deviations, improving cache hit rate, reducing task latency and performance fluctuations, reducing core temperature peaks and power consumption waste, and achieving coordinated optimization of multi-core CPU computing server performance, stability, and energy efficiency, adapting to the scheduling requirements of high-concurrency and complex tasks.

[0011] Furthermore, the calculation of the task structure conflict index for each task at the current moment includes:

[0012] Based on the task type, determine the instruction type of each task in each execution unit;

[0013] Based on the core structure information of the task, calculate the total calibration coefficient and execution frequency; based on the calibration coefficient, the total execution frequency, and the hardware capacity of the execution unit, calculate the execution unit overlap between two different tasks.

[0014] Collect the memory access address range of each task during runtime, and calculate the overlap ratio and cache conflict index between any two different tasks.

[0015] Based on the instantaneous power consumption, real-time temperature, and load rate of each task, the power interference factor between any two different tasks is calculated.

[0016] In the above scheme, this application calculates the calibration coefficient, the sum of execution frequencies, and the hardware capacity of the execution unit by combining the core structure information of the task to obtain the execution unit overlap. It collects the memory access address range to calculate the overlap ratio and cache conflict index. It uses instantaneous power consumption, real-time temperature, and load rate to obtain the power interference factor. The core advantage of these three types of indicators is that they transform the implicit structural conflicts such as execution unit contention, cache sharing conflict, and power domain coupling interference in multi-core CPUs into accurate and quantifiable values. This can effectively avoid the co-allocation of high-conflict tasks, reduce the performance loss caused by execution unit blocking, cache failure, and power consumption exceeding limits, and improve hardware resource utilization, task execution stability, and overall system energy efficiency.

[0017] Furthermore, the calculation of the execution unit overlap between every two different tasks includes:

[0018] All tasks on each execution unit are counted, and the weighted instruction load of each task on the execution unit is calculated and summed to obtain the total weighted instructions.

[0019] Based on the hardware parameters of each execution unit, calculate the corresponding maximum processing capacity; calculate the quotient of the maximum processing capacity and the total weighted instructions and normalize it to obtain the predicted utilization rate of the execution unit.

[0020] Calculate the calibration coefficient based on the predicted utilization rate of the implementing unit and the utilization rate of the implementing unit;

[0021] Calculate the sum of execution frequencies between any two different tasks, and combine this with the hardware capacity and calibration coefficient of the execution unit to calculate the overlap of execution units between any two different tasks.

[0022] In the above scheme, this invention calculates the total weighted instructions and then introduces the hardware occupancy weight of instruction types, avoiding treating the occupancy intensity of different instructions on the execution unit equally. This allows for the quantification of the comprehensive load pressure of multiple tasks on the execution unit. The maximum processing capacity is calculated by combining the execution unit hardware parameters, and then the predicted utilization rate is obtained through normalization. This ensures that the indicator calculation is anchored to the actual performance limit of the hardware, avoiding abstract estimations detached from hardware characteristics. A calibration coefficient is calculated based on the deviation between the predicted and actual utilization rates, effectively correcting the difference between the theoretical model and the dynamic operating state of the hardware. By combining the total execution frequency, hardware capacity, and calibration coefficient, the intensity of contention for execution units between task pairs is accurately characterized, rather than just reflecting the overall load. This provides a fine-grained and reliable decision-making basis for avoiding the co-allocation of highly conflicting tasks in load allocation, solving the pain point of traditional methods that cannot distinguish between "high load on a single task" and "high load due to multi-task contention."

[0023] Furthermore, the calculation of the overlap ratio and cache conflict index between every two different tasks includes:

[0024] Collect the memory access address range of each task during runtime, determine the address intersection between two different tasks, and calculate the corresponding overlap ratio;

[0025] Obtain historical cache conflict index and historical conflict factor; based on the historical cache conflict index, update the historical conflict factor smoothly through index smoothing;

[0026] Based on the updated historical conflict factor, calculate the cache conflict index between every two different tasks.

[0027] In the above scheme, this invention calculates the overlap ratio by directly collecting the memory access address range during task runtime. Based on objective address intersections, it quantifies the immediate conflict potential, avoiding abstract estimations detached from actual memory access behavior and ensuring accurate and reliable characterization of current cache contention. By introducing historical conflict factors and updating them exponentially, it retains the reference value of past conflict patterns for current evaluation and reduces the interference of occasional conflicts through a smoothing mechanism, enabling the indicator to reflect the long-term trend of cache conflicts between tasks. By combining the real-time overlap ratio with the updated historical conflict factors to calculate the exponent, it achieves a two-way fusion of immediate state and historical patterns. This captures both explicit conflicts caused by current address overlap and implicit conflicts formed in historical scheduling, providing fine-grained, multi-dimensional cache conflict decision-making basis for load allocation. This effectively avoids high-conflict tasks being allocated to the same cache domain, improving cache utilization and task execution stability.

[0028] Furthermore, the calculation of the power consumption interference factor between every two different tasks includes:

[0029] Collect the instantaneous power consumption of each task running in different power domains, and calculate the total instantaneous power consumption of each pair of different tasks in the same power domain;

[0030] Calculate the average temperature based on the real-time temperature of each power consumption domain; calculate the temperature-power consumption influence factor based on the average temperature and the preset temperature coupling coefficient.

[0031] Calculate the load rate of each task in different power domains; based on the load rate and the number of cores in each power domain, calculate the total load percentage of two different tasks in the same power domain;

[0032] The power interference factor is calculated based on the total instantaneous power consumption, the temperature-power consumption influence factor, and the total load ratio.

[0033] In the above scheme, this invention accurately captures the instantaneous power consumption pressure caused by task superposition by collecting the total instantaneous power consumption of each pair of tasks within the same power domain, avoiding misjudgments caused by isolated evaluation of the power consumption of a single task. It introduces a real-time temperature calculation temperature-power consumption impact factor, fully considering the dynamic amplification effect of temperature on power consumption, aligning with the hardware characteristics of temperature-power consumption coupling in multi-core CPU power domains, making the evaluation more consistent with actual operating scenarios. It combines load rate and the number of cores in the power domain to calculate the total load ratio, correcting the impact of differences in the number of cores in different power domains on load evaluation, and improving the consistency of cross-domain evaluation. Through the collaborative calculation of total instantaneous power consumption, temperature impact factor, and load ratio, multi-dimensional fusion is achieved, accurately characterizing the power interference intensity between each pair of tasks, providing a fine-grained basis for avoiding the co-allocation of high-interference tasks in load allocation, and effectively preventing the total power consumption of the power domain from exceeding limits, thermal throttling, or frequency reduction.

[0034] Furthermore, the load allocation for each task using the matrix spectral balancing method includes:

[0035] A structural conflict matrix is ​​constructed based on the structural conflict indicators of each task.

[0036] Set cache conflict constraints, power domain constraints, execution unit occupancy constraints, and core load balancing constraints, and construct a task-core constraint matrix based on the structural conflict matrix;

[0037] The task-core constraint matrix is ​​transformed into a graph form, with each task and core as a node and the value of the task-core constraint matrix as the weight. The matrix eigenvectors are calculated through spectral decomposition, and the tasks are then subjected to low-dimensional projection, spectral clustering, and allocation to obtain the load allocation results.

[0038] In the above scheme, this invention constructs a structural conflict matrix by integrating three types of structural conflict indicators, transforming implicit resource competition into a quantifiable global relationship network, thus avoiding the limitations of the local perspective of traditional methods. It introduces four types of constraints to construct a task-core constraint matrix, precisely matching the boundary characteristics of multi-core CPU hardware resources, thereby mitigating the risk of resource overruns from the source. Furthermore, it extracts global conflict patterns through graph transformation and spectral decomposition, combining low-dimensional projection and spectral clustering to achieve task-core matching. This not only overcomes the shortcomings of probabilistic methods in capturing deterministic structural competition but also significantly reduces the search space, balancing the efficiency and precision of large-scale scheduling. Ultimately, it achieves system structural balance and conflict minimization, significantly improving the efficiency of load allocation and hardware resource utilization.

[0039] Furthermore, the process of performing low-dimensional projection, spectral clustering, and allocation on the tasks to obtain the load allocation results includes:

[0040] The task-core constraint matrix is ​​transformed into a graph form, and a bipartite graph is constructed based on the task, core, and task-core constraint matrix.

[0041] The task similarity matrix is ​​generated by calculating the product of the task-core constraint matrix and its transpose using matrix multiplication.

[0042] The degree matrix is ​​calculated based on the task similarity matrix; the difference between the degree matrix and the task similarity matrix is ​​normalized to construct a normalized graph Laplacian matrix;

[0043] Spectral decomposition and low-dimensional embedding are performed on the normalized graph Laplacian matrix to generate a matrix composed of low-dimensional eigenvectors.

[0044] Spectral clustering is performed on the matrix composed of low-dimensional feature vectors to generate spectral clustering results, which are then used as task clusters.

[0045] Based on the real-time resource status of each core, a core cluster is constructed using a clustering algorithm; the core cluster and task cluster are matched and the task-core cluster mapping relationship is obtained using a minimum cost matching algorithm.

[0046] Based on the task-core cluster mapping relationship, a local greedy algorithm or genetic algorithm is used to refine the allocation of tasks within each task cluster and cores within the corresponding core cluster to obtain the load allocation result.

[0047] In the above scheme, this invention captures global correlations through graph-based modeling, narrows the optimization space through hierarchical clustering, and achieves structure-aware allocation through precise matching. The similarity matrix generated by the product of the task-core constraint matrix and its transpose can accurately capture the implicit structural correlations formed between tasks through shared core resources. Spectral decomposition preserves the core information of task conflicts and constraints, while low-dimensional embedding reduces data dimensionality and simplifies computational complexity. Spectral clustering and core cluster construction achieve structured grouping of tasks and adaptive grouping of core resources, and then minimum-cost matching locks the mapping relationship between clusters, significantly reducing the subsequent optimization search space. Refined allocation within clusters is performed through local greedy algorithms or genetic algorithms, avoiding the high complexity of global optimization while achieving precise matching based on fine-grained features of tasks and cores.

[0048] A structure-aware computing server load distribution system includes:

[0049] The acquisition module is used to collect the core structure information of each task in the multi-core CPU computing server in real time and determine the task type;

[0050] The indicator calculation module is used to calculate the task structure conflict index of each task at the current time based on the core structure information of the task and each task type; the task structure conflict index includes cache conflict index, power consumption interference factor and execution unit overlap.

[0051] The task allocation module is used to construct a structural conflict matrix based on the structural conflict index of each task, and to allocate the load of each task using the matrix spectrum balancing method to obtain the load allocation result.

[0052] Furthermore, the indicator calculation module includes:

[0053] The type determination unit is used to determine the instruction type of each task in each execution unit based on the task type;

[0054] The first computing unit is used to calculate the total calibration coefficient and execution frequency based on the core structure information of the task; and to calculate the execution unit overlap between two different tasks based on the calibration coefficient, the total execution frequency, and the hardware capacity of the execution unit.

[0055] The second computing unit is used to collect the memory access address range of each task during runtime and calculate the overlap ratio and cache conflict index between two different tasks.

[0056] The third computing unit is used to calculate the power interference factor between two different tasks based on the instantaneous power consumption, real-time temperature and load rate of each task.

[0057] This system features clear module division, precise structure awareness, deep hardware adaptation, and an optimized closed-loop logic, comprehensively addressing the pain points of traditional load balancing systems that neglect underlying structural conflicts and exhibit strong scheduling blindness. From data collection and metric quantification to task allocation, a complete closed loop is formed, with close collaboration between modules. It accurately adapts to the hardware structure characteristics of multi-core CPUs, significantly improving the scientific and rational nature of load balancing and the overall performance stability of the system. Attached Figure Description

[0058] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a flowchart of the method in an embodiment of the present invention;

[0060] Figure 2 This is a system structure diagram in an embodiment of the present invention. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0062] Please see Figure 1 This embodiment provides a structure-aware computing server load allocation method. Figure 1The execution entity of the method shown can be a software and / or hardware device. The execution entity of this application can include, but is not limited to, at least one of the following: user equipment, network equipment, etc. User equipment can include, but is not limited to, computers, smartphones, personal digital assistants (PDAs), and the aforementioned electronic devices. Network equipment can include, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing consisting of a large number of computers or network servers. Cloud computing is a type of distributed computing, consisting of a super virtual computer composed of a group of loosely coupled computers. This embodiment does not impose any limitations on this.

[0063] A structure-aware computing server load allocation method includes:

[0064] S1. Real-time acquisition of the core structure information of each task (to be assigned computing task) in the multi-core CPU computing server, and determination of the task type; the core structure information of the task includes task characteristic parameters and system structure parameters; the task characteristic parameters include task size, instruction type distribution, computing density, memory access frequency and estimated runtime; the system structure parameters include CPU utilization, access hit rate, power consumption domain information, cache status and execution unit utilization of each core.

[0065] S1 includes:

[0066] S1-1. For all tasks in a multi-core CPU computing server, the task's own task characteristic parameters are collected through static analysis and dynamic sampling to clarify the task's requirements for CPU hardware resources.

[0067] Specifically, for the first Task Static analysis of the binary file for this task is performed. For example, the number of instructions and code segment size are parsed using a quick viewing tool (such as objdump) to calculate the task size. The proportion of floating-point, integer, and branch instructions in the task is statistically analyzed using CPU performance counters to obtain the instruction type distribution. The number of instructions executed per byte of memory access (number of instructions / number of bytes accessed) is calculated to obtain the computational density. Dynamic analysis is performed using tools (such as perf_event) to count the number of memory accesses per thousand instructions (MPKI), combined with page table analysis of the address space distribution, to obtain the memory access frequency. The estimated runtime is calculated based on historical execution records.

[0068] S1-2. For the hardware architecture of multi-core CPUs (cache coherence domain, power domain, and execution unit layout), collect system state parameters strongly related to hardware architecture characteristics to clarify the current hardware resource load and conflict baseline. The cache coherence domain refers to the set of cores sharing the same last-level cache (e.g., shared L3 cache) and maintaining data consistency through cache coherence protocols (e.g., MESI, MOESI). The power domain refers to the set of cores sharing the same voltage regulator unit (VRM) and frequency controller, used for fine-grained power and thermal management. The execution unit layout refers to the physical distribution, functional division, and sharing mechanism of the arithmetic units (e.g., floating-point processing unit FPU, integer arithmetic unit ALU, SIMD vector unit, branch predictor, etc.) within the CPU physical core.

[0069] Specifically, for each physical / logical core, the percentage of busy time for each core is statistically analyzed using tools such as top / mpstat or kernel scheduler interfaces (e.g., / proc / stat), and the CPU utilization of each core is calculated to reflect the overall core load and provide a basis for load balancing.

[0070] For each cache coherence domain, the access hit rate is calculated using CPU performance counters. Since the access hit rate reflects the degree of shared conflicts within a cache coherence domain, a lower access hit rate indicates more severe conflicts. In this embodiment, the access hit rate is the access hit rate of the shared cache L3.

[0071] For each power consumption domain, the core temperature and current frequency within the domain are read through the CPUMSR register. Combined with the hardware topology diagram, the power consumption domain information is obtained. The power consumption domain information includes the core list within the domain, the current frequency (MHz), the average temperature (°C), and the maximum rated power consumption (W), which can reflect the voltage / frequency coupling characteristics of the power consumption domain (cores in the same domain have the same frequency).

[0072] For shared cache L3, the cache monitoring tool records the address tag, occupant (assigned task), and access frequency of cache lines, and outputs a cache line address-task mapping table and the proportion of frequently accessed cache lines, which are used to calculate the address overlap between tasks (related to MESI protocol conflicts).

[0073] The execution unit utilization rate for each physical core can be calculated and output by combining CPU performance counters (such as FP_COMP_OPS_EXE to count FPU operations and ALU_OPS to count ALU operations) with the execution unit hardware capacity (such as the number of FPU pipelines). The execution unit utilization rate includes ALU utilization and FPU utilization.

[0074] S1-3. Based on the characteristic parameters of each task, the tasks are classified into types using quantization threshold rules to clarify the hardware resource dependency attributes of the tasks and obtain the task type of each task. The task types are divided into floating-point intensive, integer intensive, and memory intensive.

[0075] Floating-point intensive tasks are defined as tasks with FP instructions accounting for ≥60% and a computation density of ≥50 instructions / byte. These tasks are computationally intensive and have high FPU requirements, relying on the physical core's FPU and the shared execution unit of SMT (Simultaneous Multithreading). Integer-intensive tasks are defined as tasks with INT instructions accounting for ≥70%, branch instructions accounting for ≤30%, and a computation density of ≥30 instructions / byte. These tasks have high ALU requirements, and their core relies on the physical core's ALU unit. Memory-intensive tasks refer to tasks with MPKI (memory accesses per thousand instructions) ≥30 times and a cache hit rate ≤50%. These tasks have high shared cache requirements, and their core relies on the cache coherence domain (shared cache L3) and memory interface.

[0076] Furthermore, if a task satisfies some conditions of multiple task types simultaneously, the maximum membership principle is used to determine the task type. This involves calculating the matching score of the task across the three task types, which is then used as the task type. In this embodiment, cosine similarity or fuzzy membership based on Gaussian membership functions can be used to calculate the matching score.

[0077] S2. Based on the core structure information of the task and the types of each task, calculate the task structure conflict index of each task at the current moment; the task structure conflict index includes cache conflict index, power consumption interference factor and execution unit overlap.

[0078] In multi-core CPU environments, traditional load balancing methods rely solely on core utilization or task size for scheduling, failing to reflect performance degradation caused by competition for underlying structural resources. Therefore, this invention introduces three types of structural conflict metrics: cache conflict index, power consumption interference factor, and execution unit overlap, corresponding to the degree of resource interference at the cache sharing layer, power consumption domain layer, and execution layer, respectively. These three metrics together constitute a quantitative description of inter-task structural conflicts, guiding load balancing optimization.

[0079] Therefore, S2 includes:

[0080] S2-1. Based on the task type, determine the instruction type of each task in each execution unit;

[0081] There is a mapping relationship between task type and instruction type, which allows us to use task type as a basis for determining instruction type, thus locating the instruction type based on the task type. For floating-point intensive tasks, the FPU primarily uses floating-point instructions (such as 32-bit / 64-bit floating-point operations and SIMD vector floating-point instructions), with a small number of integer auxiliary instructions. For integer intensive tasks, the ALU primarily uses integer arithmetic instructions (such as addition, subtraction, multiplication, division, and bitwise operations), with a low percentage of branch instructions. For memory intensive tasks, the memory interface-related units primarily use memory access instructions such as LOAD / STORE, supplemented by a small number of address calculation integer instructions.

[0082] S2-2. Based on the core structure information of the task, calculate the sum of the calibration coefficient and the execution frequency; based on the calibration coefficient, the sum of the execution frequency, and the hardware capacity of the execution unit, calculate the execution unit overlap between every two different tasks.

[0083] S2-2 includes:

[0084] S2-2-1. Count all tasks on each execution unit, calculate the weighted instruction load of each task on the execution unit, and sum them to obtain the total weighted instructions; for all tasks assigned to the execution unit... The core tasks are considered the first task set. Weighted instruction load refers to the execution units within the first task set. The product of the hardware occupancy weight of each supported instruction type and the execution frequency of the same instruction type for the corresponding task. Calculated in the execution unit. In this process, the sum of weighted instruction loads is calculated to obtain the total weighted instruction load, which is used to quantify the overall load pressure generated by all tasks sharing the execution unit.

[0085] S2-2-2. Based on the hardware parameters of each execution unit, calculate the corresponding maximum processing capacity; calculate the quotient of the maximum processing capacity and the total weighted instructions and normalize it to obtain the predicted utilization rate of the execution unit.

[0086] S2-2-3. Calculate the calibration coefficient based on the predicted utilization rate of the execution unit and the utilization rate of the execution unit;

[0087] S2-2-4. Calculate the sum of execution frequencies between any two different tasks, and combine the hardware capacity and calibration coefficient of the execution unit to calculate the overlap of execution units between any two different tasks.

[0088] Specifically, the formula for the calibration coefficient is:

[0089] ;

[0090] With the first The first task and the first Taking one task as an example, the formula for the overlap of execution units is:

[0091] ;

[0092] in, Indicates the first The first task and the first The overlap of execution units of each task. Indicates execution unit calibration coefficients, Represents a set of execution units. This represents the summation function. Indicates instruction type For execution unit The weight of the occupancy, , They represent the first The first task and the first Instruction types in each task Execution frequency, Indicates execution unit Hardware capacity, Indicates execution unit Supported instruction type set, Indicates calibration weights, , These represent the projected utilization rate of the implementing unit and the utilization rate of the implementing unit, respectively.

[0093] The execution unit (FPU) is the core hardware resource for the CPU to perform calculations. When multiple tasks share the same FPU, instruction contention can increase computational latency. For example, if two floating-point intensive tasks simultaneously occupy the FPU, they will block each other's pipelines. Execution unit overlap is used to transform this implicit competition for execution units into a quantifiable numerical metric, accurately characterizing the degree of conflict between any two tasks sharing an execution unit. The higher the value, the more intense the competition.

[0094] Traditional load balancing relies solely on core utilization to determine load balancing, but it cannot distinguish whether high utilization is caused by a single task or multiple tasks competing for execution units. Execution unit overlap, however, calculates a calibration coefficient based on the deviation between predicted and actual execution unit utilization, ensuring the metric aligns with dynamic hardware behavior. Furthermore, it directly calculates the overlap between every two different tasks, providing precise decision-making for task-core matching in load balancing. This avoids the co-allocation of highly conflicting task pairs, reduces invalid waiting time for execution units, and shortens task blocking time during the computation phase by reducing execution unit contention.

[0095] S2-3. Collect the memory access address range of each task during runtime, and calculate the overlap ratio and cache conflict index between each two different tasks.

[0096] S2-3 includes:

[0097] S2-3-1. Collect the memory access address range of each task during runtime, determine the address intersection between two different tasks, and calculate the corresponding overlap ratio.

[0098] S2-3-2, Obtain historical cache conflict index and historical conflict factor; Based on the historical cache conflict index, update the historical conflict factor smoothly through index;

[0099] S2-3-3: Based on the updated historical conflict factor, calculate the cache conflict index between every two different tasks.

[0100] Specifically, taking the first The first task and the first Taking one task as an example, the formula for the cache conflict index is:

[0101] ;

[0102] in, Indicates the first The first task and the first The cache conflict index for each task. , These represent the read operation weight and the write operation weight, respectively. Indicates the first The first task and the first The cumulative number of read accesses on the shared cache for each task Indicates the first The first task and the first The cumulative number of write accesses by a task on the shared cache Indicates the capacity of the shared L3 cache. Indicates the first The first task and the first The overlap ratio of the access address spaces of each task. Indicates the first The first task and the first Historical conflict factors in each task.

[0103] Since the core behavior of read operations is to retrieve data, they typically do not change the state of cache lines. However, the core behavior of write operations is to modify data, which forcibly changes the state of cache lines. Therefore, write operations are more likely to interfere with cache consistency than read operations. .

[0104] The cache conflict index quantifies the intensity of competition between tasks due to shared cache resources, transforming implicit conflicts such as cache address overlap causing contention and invalidation overhead from consistency protocols into quantifiable indicators. By collecting real-time memory access address ranges of tasks to calculate the overlap ratio and combining it with historical conflict factors that are updated smoothly by the index, it can comprehensively characterize the conflict risk between two tasks at the cache layer. It captures both immediate address overlap characteristics and incorporates conflict patterns from historical scheduling, avoiding the bias of single-dimensional judgment.

[0105] During load balancing, the cache conflict index provides a basis for fine-grained scheduling of cache resources. By allocating tasks with low cache conflict indices (such as task pairs with little address overlap or few historical conflicts) to the same cache domain, while avoiding co-allocation of high-conflict tasks, the frequency of cache line misses and consistency communication overhead can be reduced, improving cache hit rate. This directly reduces the memory access latency of tasks (especially effective for memory-intensive tasks), making cache resource utilization more efficient. Ultimately, this allows load balancing decisions to break through the limitation of "only considering core load" and better align with the hardware structure of multi-core CPU cache sharing.

[0106] S2-4. Based on the instantaneous power consumption, real-time temperature, and load rate of each task, calculate the power interference factor between any two different tasks.

[0107] S2-4 includes:

[0108] S2-4-1. Collect the instantaneous power consumption of each task running in different power domains, and calculate the total instantaneous power consumption of each pair of different tasks in the same power domain.

[0109] S2-4-2. Calculate the average temperature based on the real-time temperature of each power consumption domain; calculate the temperature-power consumption influence factor based on the average temperature and the preset temperature coupling coefficient.

[0110] S2-4-3. Calculate the load rate of each task in different power domains; based on the load rate and the number of cores in each power domain, calculate the total load ratio of two different tasks in the same power domain.

[0111] S2-4-4. Calculate the power interference factor based on total instantaneous power consumption, temperature-power consumption influence factor, and total load percentage.

[0112] Specifically, taking the first The first task and the first Taking one task as an example, the formula for the total load percentage is:

[0113] ;

[0114] The formula for the power consumption interference factor is:

[0115] ;

[0116] in, Indicates the first The first task and the first The power consumption interference factor of each task. , They represent the first The first task and the first Instantaneous power consumption of each task Represents the power consumption domain Maximum rated power consumption Represents the temperature coupling coefficient. Represents the power consumption domain average temperature Indicates the first The first task and the first The percentage of total load for each task This represents the temperature-power consumption impact factor. This represents the total instantaneous power consumption. Represents the power consumption domain The number of (physical cores / logical cores) cores. , They represent the first The first task and the first Instantaneous power consumption of each task.

[0117] The power consumption interference factor quantifies the power consumption and temperature coupling interference between tasks within the same power consumption domain, transforming implicit power consumption pressures such as the superposition of instantaneous power consumption, power consumption amplification due to temperature rise, and uneven core load distribution into quantifiable indicators. By calculating the total instantaneous power consumption of two tasks and combining it with the influence factor obtained from the real-time average temperature and temperature coupling coefficient, the dynamic amplification effect of temperature on power consumption can be reflected. Furthermore, the total load percentage is used to correct for the impact of differences in the number of cores within the power consumption domain. The power consumption interference factor captures the instantaneous power consumption superposition pressure while incorporating the synergistic effects of temperature and load, avoiding the one-sidedness of considering only a single power consumption value.

[0118] During load allocation, tasks with low power interference factors (such as low instantaneous power consumption and balanced load distribution) are prioritized to be allocated to the same power domain, while avoiding the co-allocation of high interference tasks. This prevents the total power consumption of the power domain from exceeding the limit (avoiding frequency reduction), and avoids frequency reduction triggered by power peaks or thermal throttling caused by excessive temperature. This helps maintain the stable operating frequency of tasks and reduces performance fluctuations caused by power consumption control (especially effective for high-power computing tasks). The load allocation decision takes into account both performance and power consumption, which is more in line with the power management characteristics of the power domain of multi-core CPUs.

[0119] S3. Based on the structural conflict index of each task, construct a structural conflict matrix, and perform load allocation on each task using the matrix spectrum balancing method to obtain the load allocation result; the load allocation result includes a task-core allocation matrix, a core state vector, and a task conflict index table.

[0120] Specifically, in traditional load balancing schemes, Bayesian feedback mechanisms can be used to achieve dynamic load balancing through probability distribution updates. However, the core assumption of Bayesian feedback mechanisms is that the system exhibits significant uncertainty, while the computing power scheduling process of multi-core CPUs is more of a deterministic structural competition and energy distribution problem, meaning that different tasks have measurable conflicts at the resource levels such as cache, power domain, and execution units. Therefore, if Bayesian feedback mechanisms are continued for load balancing, although they can demonstrate certain adaptive characteristics, they cannot directly capture the energy balance state of the system structure and are difficult to quantify global disturbance patterns.

[0121] Load balancing is not merely a matter of distributing tasks among cores, but rather a balance of energy (or resource conflict intensity) across the system structure. Matrix spectrum balancing is a mathematical approach to achieving global energy distribution equilibrium in complex systems. Therefore, a matrix spectrum balancing method is proposed for load balancing. The process of the matrix spectrum balancing method includes:

[0122] S3-1. Construct a structural conflict matrix based on the structural conflict indicators of each task;

[0123] It needs to be explained that the task structure conflict index for each task is normalized, and then an adaptive weight is used to synthesize the structure conflict matrix. The corresponding formula is:

[0124] ;

[0125] in, , , All represent structural conflict weights.

[0126] Considering the tasks currently assigned to each core in a multi-core CPU computing server, based on:

[0127] ;

[0128] Indicates the first One core The task on This represents the summation function. Indicates core The total conflict cost, i.e., the structural conflict matrix, Indicates the core Still running The conflict costs of a historical mission.

[0129] S3-2. Set cache conflict constraints, power domain constraints, execution unit occupancy constraints, and core load balancing constraints, and construct a task-core constraint matrix based on the structural conflict matrix.

[0130] It's important to note that in a multi-core CPU computing server, the cores typically share L3 or part of the L2 cache. If multiple tasks frequently access the same cache line, it can lead to cache conflicts, increasing the cache miss rate. Therefore, cache conflict constraints are implemented to reduce execution efficiency and limit the access pressure on the same cache line. The expression for a cache conflict constraint is:

[0131] ;

[0132] in, Indicates the first One core cache line, Indicates the first The task was assigned to the first Cache penalty per core, Indicates the first Each task caches lines Access frequency, Indicates the first Each task caches lines Access frequency, Indicates cache line The maximum allowed access frequency threshold.

[0133] To control the total power consumption within the same power domain and avoid overheating and excessive power consumption, a power range is set for the power domain. Once this range is exceeded, a power penalty is applied, reflecting the current stress on the power domain. The expression for the power domain constraint is:

[0134] ;

[0135] in, Indicates the first The task was assigned to the first Power penalty per core, Represents the maximum value function. , They represent the first The set of tasks running on each core and the set of tasks temporarily assigned to that core. Indicates the first The power domain of each core The maximum allowable power consumption.

[0136] Because the core has a limited number of execution units, uneven task allocation can lead to pipeline conflicts or execution unit bottlenecks, resulting in decreased throughput. To ensure that the core execution units are not overloaded during task allocation and that tasks can fully utilize hardware resources during execution, the execution unit occupancy constraint is set as follows:

[0137] ;

[0138] in, Indicates the first The task was assigned to the first Penalty for execution units at the core level Indicates the first A core set of execution units, , They represent the first The first task, the first Each task is executed by the unit. The proportion of occupancy, Indicates execution unit Maximum throughput capacity.

[0139] If some cores are overloaded while others are idle, performance bottlenecks and task waiting can easily occur, reducing the overall system throughput. To ensure even use of computing resources, core load balancing can improve the overall utilization of multi-core CPUs and task parallelization efficiency. Therefore, core load balancing constraints can be set as follows:

[0140] ;

[0141] in, Indicates the first The task was assigned to the first Core load penalty per core, Indicates the first The total load of each core (calculated as the sum of the runtime of tasks already running on that core and tasks to be assigned). This represents the average load across all cores. Indicates the allowable load deviation. It represents the absolute value.

[0142] By using a weighted fusion approach, cache conflict constraints, power domain constraints, execution unit occupancy constraints, and core load balancing constraints are incorporated into the structural conflict matrix to obtain the task-core constraint matrix. .

[0143] This invention introduces cache conflict constraints, power consumption constraints, execution unit occupancy constraints, and core load balancing constraints to construct a structural constraint-aware matrix based on the original task structure conflict matrix. This enables the load allocation process to consider not only structural conflicts between tasks but also the real-time boundary characteristics of system resources. This matrix dynamically reflects the combined state of cache contention, power consumption aggregation, execution unit occupancy, and core load distribution. Thus, the optimization objective is expanded from simply minimizing task conflicts to achieving structural balance and conflict minimization under resource constraints. It proactively avoids high cache contention and power hotspots, prevents the concentrated distribution of similar tasks on execution units, and achieves cross-core load balancing. This reduces resource interference between tasks, improves energy efficiency and operational stability, prevents power domain thermal imbalance or frequency throttling, and significantly enhances the overall performance sustainability and scheduling robustness of multi-core CPU computing servers.

[0144] S3-3. Transform the task-core constraint matrix into a graph form, take each task and each core as nodes, take the value of the task-core constraint matrix as weights, calculate the matrix eigenvectors through spectral decomposition, perform low-dimensional projection, spectral clustering and allocation on the tasks, and obtain the load allocation results.

[0145] S3-3 includes:

[0146] S3-3-1. Transform the task-core constraint matrix into a graph form, and construct a bipartite graph based on the task, core, and task-core constraint matrices.

[0147] Specifically, a bipartite graph has core nodes and task nodes. Tasks are treated as task nodes, and core nodes as core nodes. The elements of the task-core constraint matrix are used as the weights between the corresponding task nodes and core nodes, thus constructing the bipartite graph. The mathematical foundation and processing objects in S3-3 are indeed built on the bipartite graph model. The bipartite graph is both the structural carrier and the unified representation space for the entire load allocation optimization process.

[0148] S3-3-2. Calculate the product of the task-core constraint matrix and its transpose using matrix multiplication to generate the task similarity matrix. The first [part of the task similarity matrix]... Line number Column elements represent the first The first task and the first The structural similarity between tasks reflects the degree of association between two tasks indirectly generated by sharing core resources (cache, power domain, execution unit).

[0149] S3-3-3 Calculate the degree matrix based on the task similarity matrix; normalize the difference between the degree matrix and the task similarity matrix to construct a normalized graph Laplacian matrix.

[0150] Specifically, the normalized graph Laplacian matrix The expression is:

[0151] ;

[0152] ;

[0153] ;

[0154] in, Degree matrix, , These represent the task-core constraint matrix and its transpose, respectively. Represents the task similarity matrix. Indicates the first The first task and the first Similarity between tasks.

[0155] S3-3-4. Perform spectral decomposition and low-dimensional embedding on the normalized graph Laplacian matrix to generate a matrix composed of low-dimensional eigenvectors.

[0156] Specifically, eigenvalue decomposition is performed on the normalized graph Laplacian matrix to obtain eigenvectors. The first N eigenvectors are selected and formed into an eigenvector matrix. This eigenvector matrix is ​​then mapped to a low-dimensional space, allowing geometric distance to reflect the similarity or conflict between nodes, resulting in a low-dimensional eigenvector matrix.

[0157] S3-3-5. Perform spectral clustering on the matrix composed of low-dimensional feature vectors, generate spectral clustering results and use them as task clusters.

[0158] S3-3-6. Based on the real-time resource status of each core, a core cluster is constructed using a clustering algorithm; the core cluster and task cluster are matched and the task-core cluster mapping relationship is obtained using a minimum cost matching algorithm.

[0159] Specifically, the real-time resource status of each core (available computing power, power margin, available cache space, and execution unit utilization) is monitored and used as core features to calculate the Euclidean distance or cosine similarity between different cores. Then, based on the cosine similarity, a hierarchical clustering algorithm is used to cluster the cores, resulting in core clusters. Each core cluster represents a set of cores with similar resource status characteristics that can jointly undertake the same type of task.

[0160] For each pair of tasks in a task cluster and each core in a core cluster, the sum of the corresponding elements in the task-core constraint matrix is ​​calculated and averaged to construct a task cluster-core cluster matching matrix. The elements in the task cluster-core cluster matching matrix represent the overall conflict intensity value between a certain task cluster and a certain core cluster; the smaller the value, the weaker the resource conflict, and the more suitable it is for task allocation.

[0161] Based on the task cluster-core cluster matching matrix, a minimum cost matching algorithm is used to determine the mapping relationship between task clusters and core clusters, and then the task clusters are assigned to the corresponding core clusters. Once the mapping relationship is determined, it is only necessary to optimize the allocation of tasks within the corresponding task clusters on the cores within the core clusters, thereby reducing the search space.

[0162] S3-3-7. Based on the task-core cluster mapping relationship, a local greedy algorithm or genetic algorithm is used to perform local refinement allocation of tasks within each task cluster and cores within the corresponding core cluster to obtain the load allocation result. The load allocation result includes a task-core allocation matrix, a core state vector, and a task conflict index table.

[0163] After obtaining the mapping relationship between task clusters and core clusters, the local fine-tuning allocation stage begins. In this stage, each task cluster and its corresponding core cluster are treated as independent optimization units, and fine matching is performed on the tasks and cores within each cluster. First, the structural characteristic parameters of each task within the task cluster (including computational density, cache requirements, execution unit utilization, etc.) are obtained, as well as the real-time status information of each core within the core cluster (such as current load, cache hit rate, power margin, and execution unit utilization).

[0164] The matching order between tasks and cores is searched and iteratively optimized using either a local greedy algorithm or a genetic algorithm. The local greedy algorithm prioritizes assigning tasks with lower conflict indices and higher resource matching degrees to cores with lighter loads, thus completing intra-cluster task allocation. The genetic algorithm, through crossover and mutation operations, evolves among multiple candidate allocation schemes, gradually approaching the globally optimal intra-cluster allocation result, i.e., the load allocation result. The task-core allocation matrix represents the specific running core of each task, the core state vector describes the real-time resource usage status of each core, and the task conflict index table quantifies the structural conflict between tasks, thereby achieving structure-aware load optimization for multi-core CPU computing servers.

[0165] S3-4. Run the load allocation results and collect the corresponding running data (core power consumption, cache hit rate and execution unit utilization); adjust the constraint weights in the structural conflict matrix according to the running data for load allocation in the next time step.

[0166] This process constructs a structural conflict matrix that integrates cache conflict index, power consumption interference factor, and execution unit overlap (EOR). It then uses a matrix spectral balancing method to capture global energy distribution and incorporates four types of constraints—cache conflict, power domain, execution unit occupancy, and core load balancing—to build a task-core constraint matrix. A hierarchical strategy of "spectral clustering matching + local greedy / genetic algorithm optimization" is employed. Constraint weights are iteratively adjusted based on runtime data such as core power consumption and cache hit rate. This precisely addresses the core technical problems in traditional load balancing: the inability to quantify implicit structural conflicts, the inability of probabilistic methods like Bayesian methods to adapt to deterministic structural competition, easy resource overruns, and the imbalance between efficiency and precision in large-scale scheduling. By using the structural conflict matrix to transform implicit conflicts in cache, power domain, and execution units into computable values, the matrix spectral balancing method aligns with the deterministic structural competition inherent in multi-core CPUs to achieve global energy balance, the four types of constraints clearly define hardware resource boundaries to avoid overruns, and the hierarchical strategy significantly reduces the search space while balancing efficiency and accuracy, effectively improving cache hit rate and overall throughput.

[0167] like Figure 2 As shown, a structure-aware computing server load distribution system includes:

[0168] The acquisition module is used to collect the core structure information of each task in the multi-core CPU computing server in real time and determine the task type;

[0169] The indicator calculation module is used to calculate the task structure conflict index of each task at the current time based on the core structure information of the task and each task type; the task structure conflict index includes cache conflict index, power consumption interference factor and execution unit overlap.

[0170] The task allocation module is used to construct a structural conflict matrix based on the structural conflict index of each task, and to allocate the load of each task using the matrix spectrum balancing method to obtain the load allocation result.

[0171] The indicator calculation module includes:

[0172] The type determination unit is used to determine the instruction type of each task in each execution unit based on the task type;

[0173] The first computing unit is used to calculate the total calibration coefficient and execution frequency based on the core structure information of the task; and to calculate the execution unit overlap between two different tasks based on the calibration coefficient, the total execution frequency, and the hardware capacity of the execution unit.

[0174] The second computing unit is used to collect the memory access address range of each task during runtime and calculate the overlap ratio and cache conflict index between two different tasks.

[0175] The third computing unit is used to calculate the power interference factor between two different tasks based on the instantaneous power consumption, real-time temperature and load rate of each task.

[0176] It should be noted that the specific methods by which each module performs operations in the system described in the above embodiments have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0177] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0178] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A structure-aware computing server load allocation method, characterized in that, include: Real-time acquisition of core task structure information for each task in a multi-core CPU computing server, and determination of task type; Based on the core structure information of the task and the types of each task, calculate the task structure conflict index of each task at the current moment; the task structure conflict index includes cache conflict index, power consumption interference factor and execution unit overlap. Based on the structural conflict indicators of each task, a structural conflict matrix is ​​constructed, and the load is allocated to each task using the matrix spectrum balancing method to obtain the load allocation result; the load allocation result includes a task-core allocation matrix, a core state vector, and a task conflict indicator table.

2. The structure-aware computing server load allocation method according to claim 1, characterized in that, The calculation of the task structure conflict index for each task at the current moment includes: Based on the task type, determine the instruction type of each task in each execution unit; Based on the core structure information of the task, calculate the total calibration coefficient and execution frequency; based on the calibration coefficient, the total execution frequency, and the hardware capacity of the execution unit, calculate the execution unit overlap between two different tasks. Collect the memory access address range of each task during runtime, and calculate the overlap ratio and cache conflict index between any two different tasks. Based on the instantaneous power consumption, real-time temperature, and load rate of each task, the power interference factor between any two different tasks is calculated.

3. The structure-aware computing server load allocation method according to claim 2, characterized in that, The calculation of the execution unit overlap between every two different tasks includes: All tasks on each execution unit are counted, and the weighted instruction load of each task on the execution unit is calculated and summed to obtain the total weighted instructions. Based on the hardware parameters of each execution unit, calculate the corresponding maximum processing capacity; calculate the quotient of the maximum processing capacity and the total weighted instructions and normalize it to obtain the predicted utilization rate of the execution unit. Calculate the calibration coefficient based on the predicted utilization rate of the implementing unit and the utilization rate of the implementing unit; Calculate the sum of execution frequencies between any two different tasks, and combine this with the hardware capacity and calibration coefficient of the execution unit to calculate the overlap of execution units between any two different tasks.

4. The structure-aware computing server load allocation method according to claim 2, characterized in that, The calculation of the overlap ratio and cache conflict index between each pair of different tasks includes: Collect the memory access address range of each task during runtime, determine the address intersection between two different tasks, and calculate the corresponding overlap ratio; Obtain historical cache conflict index and historical conflict factor; based on the historical cache conflict index, update the historical conflict factor smoothly through index smoothing; Based on the updated historical conflict factor, calculate the cache conflict index between every two different tasks.

5. The method for load allocation of a computing server based on structure awareness according to claim 2, characterized in that, The calculation of the power consumption interference factor between every two different tasks includes: Collect the instantaneous power consumption of each task running in different power domains, and calculate the total instantaneous power consumption of each pair of different tasks in the same power domain; Calculate the average temperature based on the real-time temperature of each power consumption domain; calculate the temperature-power consumption influence factor based on the average temperature and the preset temperature coupling coefficient. Calculate the load rate of each task in different power domains; based on the load rate and the number of cores in each power domain, calculate the total load percentage of two different tasks in the same power domain; The power interference factor is calculated based on the total instantaneous power consumption, the temperature-power consumption influence factor, and the total load ratio.

6. The structure-aware computing server load allocation method according to claim 1, characterized in that, The load distribution for each task using the matrix spectral balancing method includes: A structural conflict matrix is ​​constructed based on the structural conflict indicators of each task. Set cache conflict constraints, power domain constraints, execution unit occupancy constraints, and core load balancing constraints, and construct a task-core constraint matrix based on the structural conflict matrix; The task-core constraint matrix is ​​transformed into a graph form, with each task and core as a node and the value of the task-core constraint matrix as the weight. The matrix eigenvectors are calculated through spectral decomposition, and the tasks are then subjected to low-dimensional projection, spectral clustering, and allocation to obtain the load allocation results.

7. The structure-aware computing server load allocation method according to claim 1, characterized in that, The process of performing low-dimensional projection, spectral clustering, and allocation on the tasks to obtain the load allocation results includes: The task-core constraint matrix is ​​transformed into a graph form, and a bipartite graph is constructed based on the task, core, and task-core constraint matrix. The task similarity matrix is ​​generated by calculating the product of the task-core constraint matrix and its transpose using matrix multiplication. The degree matrix is ​​calculated based on the task similarity matrix; the difference between the degree matrix and the task similarity matrix is ​​normalized to construct a normalized graph Laplacian matrix; Spectral decomposition and low-dimensional embedding are performed on the normalized graph Laplacian matrix to generate a matrix composed of low-dimensional eigenvectors. Spectral clustering is performed on the matrix composed of low-dimensional feature vectors to generate spectral clustering results, which are then used as task clusters. Based on the real-time resource status of each core, a core cluster is constructed using a clustering algorithm; the core cluster and task cluster are matched and the task-core cluster mapping relationship is obtained using a minimum cost matching algorithm. Based on the task-core cluster mapping relationship, a local greedy algorithm or genetic algorithm is used to refine the allocation of tasks within each task cluster and cores within the corresponding core cluster to obtain the load allocation result.

8. A structure-aware computing server load allocation system, used to implement the structure-aware computing server load allocation method according to any one of claims 1 to 7, characterized in that, include: The acquisition module is used to collect the core structure information of each task in the multi-core CPU computing server in real time and determine the task type; The indicator calculation module is used to calculate the task structure conflict index of each task at the current moment based on the core structure information of the task and each task type; the task structure conflict index includes cache conflict index, power consumption interference factor and execution unit overlap. The task allocation module is used to construct a structural conflict matrix based on the structural conflict index of each task, and to allocate the load of each task using the matrix spectrum balancing method to obtain the load allocation result.

9. A structure-aware computing server load distribution system according to claim 8, characterized in that, The indicator calculation module includes: The type determination unit is used to determine the instruction type of each task in each execution unit based on the task type; The first computing unit is used to calculate the sum of calibration coefficients and execution frequencies based on the core structure information of the task; and to calculate the execution unit overlap between two different tasks based on the calibration coefficients, the sum of execution frequencies, and the hardware capacity of the execution unit. The second computing unit is used to collect the memory access address range of each task during runtime and calculate the overlap ratio and cache conflict index between two different tasks. The third computing unit is used to calculate the power interference factor between two different tasks based on the instantaneous power consumption, real-time temperature and load rate of each task.

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