Flash memory data recovery method and device, equipment and medium

Abstract

The invention discloses a flash memory data recovery method and device, equipment and a medium. The flash memory data recovery method comprises the following steps: reading flash memory data, entering a read cycle operation, and carrying out a hard decoding operation on the flash memory data; when the hard decoding operation is successful, the flash memory data is recovered successfully, and the read cycle operation is quitted; when the hard decoding operation fails, entering a first rereading list, sequentially selecting the rereading voltage of the flash memory data for reading, and performing the hard decoding operation; starting a read calibration function, determining an execution strategy of the hard decoding operation according to the steps of the hard decoding operation until the hard decoding operation is successful, or traversing the first re-read list, and quitting the read cycle operation of the flash memory data; and starting a read compensation function, entering a second reread list, sequentially selecting the reread voltage of the flash memory data for reading, performing soft decoding operation on the reread voltage to obtain a soft decoding operation result, and closing the read compensation function.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of flash memory data recovery, and particularly relates to a flash memory data recovery method, device, equipment and medium. BACKGROUND

[0002] NAND Flash memory has become the core device in the field of mass storage due to its high storage density and low cost advantage. Multiple-bit data is represented by adjusting the charge level in the storage unit. However, due to the limitation of physical mechanism, the charge stored in the storage unit is easily affected by factors such as data retention, read interference, temperature drift, etc., and decays or disturbs, causing the charge distribution to deviate, and then causing bit errors. When the number of error bits exceeds the tolerance of the error correction code, data reading will fail.

[0003] To solve this problem, the prior art generally uses two ways of hard decoding and soft decoding. Hard decoding is based on the determined bit value for error correction, and the decoding speed is fast, but the error correction capability is limited. Soft decoding uses the probability confidence information of the bit, and significantly improves the error correction success rate through multiple sampling and iterative calculation, but the decoding delay is significantly higher than that of hard decoding. SUMMARY

[0004] Therefore, the present application aims to provide a flash memory data recovery method, device, equipment and medium, which uses the advantages of each function and decoding mode to automatically read and calibrate the function, uses different read-write methods with hard decoding, uses automatic read compensation function with soft decoding, and flexibly selects the hard decoding or soft decoding process, improves the success rate of soft decoding in extreme scenarios, corrects the data with a high probability, ends the read process as soon as possible, and reduces the read delay.

[0005] To achieve the above purpose, the technical scheme of the present application is as follows: In a first aspect, the embodiment of the present application provides a flash memory data recovery method, comprising: S1: reading flash memory data with a default read voltage, so that the flash memory data enters a read cycle operation, and performing a hard decoding operation on the read flash memory data; S2: when the hard decoding operation of the flash memory data is successful, the flash memory data recovery is successful, and the flash memory data exits the read cycle operation; S3: when the hard decoding operation of the flash memory data fails, a preset first re-reading list is entered, and a re-reading voltage of the flash memory data is sequentially selected for reading, and a hard decoding operation is performed on the re-reading voltage; S4: enabling a read calibration function, determining a step of the hard decoding operation, determining an execution strategy of the hard decoding operation according to the step of the hard decoding operation, and calibrating a re-reading voltage of the flash memory data until the hard decoding operation is successful; if the hard decoding operation is still not successful, after the first re-reading list is traversed, the read cycle operation is exited; S5: enabling a read compensation function, entering a second re-reading list, sequentially selecting the re-reading voltage of the flash memory data for reading, and performing a soft decoding operation on the re-reading voltage to obtain a soft decoding operation result; S6: closing the read compensation function according to the soft decoding operation result.

[0006] In some embodiments of the present application, the step of determining the execution strategy of the hard decoding operation according to the step of the hard decoding operation comprises: S41: sequentially selecting a re-reading voltage of the first re-reading list for reading to obtain a first current re-reading voltage of the flash memory data; S42: performing a hard decoding operation on the first current re-reading voltage, when the hard decoding operation is successful, the flash memory data is successfully recovered; when the hard decoding operation fails, an automatic read calibration function is started to obtain a first re-reading parameter of the first current re-reading voltage of the current reading; S43: performing the hard decoding operation on the first re-reading parameter; S44: when the hard decoding operation on the first re-reading parameter is successful, the automatic read calibration function is closed, and the flash memory data is successfully recovered; S45: when the hard decoding operation on the first re-reading parameter fails, the automatic read calibration function is closed, and a bit value of the current reading parameter is confirmed; S46: according to the reading state of the bit value, a read compensation function is performed on the current reading parameter, and after the automatic read calibration, an offset voltage of the current reading parameter is written into the second re-reading list.

[0007] In some embodiments of the present application, the read compensation function performed on the flash memory data according to the reading state comprises: S451: obtaining a set interval of the current reading parameter; S452: when the bit value is in the set interval, the offset voltage of the current reading parameter after the automatic read calibration is read out, and the offset voltage is written into the second re-reading list; S453: when the bit value is not in the set interval, the steps S41 to S46 are traversed until the re-reading voltage of the last re-reading list is read.

[0008] In some embodiments of the present application, the starting of the automatic read calibration function to obtain the first re-read parameter of the first current re-read voltage of the current read includes: S421: obtaining a base read voltage of the flash memory data; S422: in response to an automatic calibration signal and a timing signal generated by the flash memory controller, obtaining the first re-read parameter of the first current re-read voltage based on the base read voltage, the automatic calibration signal and the timing signal.

[0009] In some embodiments of the present application, the read compensation function according to the read state to the current read parameter includes: S461: obtaining an automatic read compensation signal and a second timing signal generated by the flash memory controller; S462: performing read compensation on the current read parameter according to the automatic read compensation signal and the timing signal, wherein the read compensation function is only started when the soft decoding operation.

[0010] In some embodiments of the present application, the soft decoding operation on the re-read voltage to obtain a soft decoding operation result includes: S51: sequentially selecting the re-read voltage of the second re-read list for reading to obtain a second current re-read voltage of the flash memory data; S52: performing the soft decoding operation on the second current re-read voltage, when the soft decoding operation is successful, closing the read compensation function, and the flash memory data is recovered successfully; S53: when the soft decoding operation fails, traversing the re-read voltage of the second re-read list until all the re-read voltage of the second re-read list is completed, and closing the read compensation function.

[0011] In some embodiments of the present application, the base re-read voltage parameter of the flash memory data is written in the first re-read list, and the re-read voltage parameter after the automatic read calibration of the base re-read voltage parameter is written in the second re-read list.

[0012] Secondly, the embodiments of the present application provide a flash memory data recovery device, which comprises at least one control processor and a memory connected with the at least one control processor for communication; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the flash memory data recovery method as described in the first aspect above.

[0013] In a third aspect, an electronic device is provided, and the electronic device comprises the flash memory data recovery apparatus according to the second aspect.

[0014] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores computer executable instructions for causing a computer to execute the flash memory data recovery method according to the first aspect.

[0015] The flash memory data recovery method according to the embodiments of the present application has at least the following beneficial effects: First, the automatic read calibration function is combined with the hard decoding operation to ensure that most flash memory data can be recovered at a low calculation cost, and then the flash memory data that does not pass the hard decoding operation is combined with the soft decoding operation and the read compensation function to further process and recover the flash memory data, and the read voltage of the flash memory data is covered by multiple levels and multiple strategies through the soft decoding operation and the hard decoding operation, so that the flash memory data of different degrees can be effectively recovered during the flash memory data recovery process, and the reading process can be ended as soon as possible to reduce the flash memory data reading time. By flexibly using the hard decoding operation and the automatic read calibration function, and combining the automatic read compensation function with the soft decoding operation, different decoding processes are flexibly selected, the number of read groups of the read voltage is reduced, blind polling of different read voltages is avoided, and the success rate of the soft decoding operation in different scenarios is improved, and the read voltage of the flash memory data is corrected. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which form a part of the present application, are included to provide a further understanding of the application and are incorporated herein for reference. The detailed description of the application and its illustrations provide a clear and concise comprehensive description of the embodiments disclosed herein and are explanatory thereof and not limiting thereof. In the drawings: Figure 1 is a flowchart of the flash memory data recovery method provided by the embodiments of the present application; Figure 2 is a flowchart of determining the execution strategy of the hard decoding operation according to the steps of the hard decoding operation provided by an embodiment of the present application; Figure 3 is a flowchart of performing the read compensation function on the flash memory data according to the read state provided by an embodiment of the present application; Figure 4 is a flowchart of obtaining the first read parameter of the first current read voltage of the current read provided by an embodiment of the present application; Figure 5 is a flowchart of performing the read compensation function on the current read parameter according to the read state provided by an embodiment of the present application; Figure 6is a flow chart of soft decoding operation on the heavy read voltage to obtain a soft decoding operation result provided by one embodiment of the present application; Figure 7 is a structure diagram of a flash memory data recovery device provided by one embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and do not constitute a limitation on the present application. Similar elements in different embodiments use similar element labels. In the following embodiments, many details are described in order to make the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different cases, or can be replaced by other elements, materials or methods. In some cases, some operations related to the present application are not shown or described in the specification in order to avoid the core part of the present application being overwhelmed by too much description, and it is not necessary to describe these related operations in detail for those skilled in the art according to the description in the specification and general technical knowledge in the art.

[0018] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other to form various embodiments without conflict. Meanwhile, each step or action in the method description can also be sequentially adjusted or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for clear description of a certain embodiment, and do not mean a necessary sequence, unless otherwise stated that a certain sequence must be followed.

[0019] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" and the like can be explicitly or implicitly included one or more. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0020] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood through specific circumstances.

[0021] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0022] Referring to Figure 1 , Figure 1 The overall flowchart of the flash memory data recovery method of the present application comprises the following steps: S1: reading the flash memory data with a default read voltage, so that the flash memory data enters the read cycle operation, and performing a hard decoding operation on the read flash memory data; It should be noted that the flash memory unit represents data by storing the amount of charge; the read voltage is the threshold voltage for judging the state of the flash memory unit; the default read voltage is the reference voltage for the flash memory controller to perform the read operation, and the flash memory controller compares the threshold voltage of the flash memory unit with one or more preset voltages to determine the data state of the current flash memory unit.

[0023] S2: when the hard decoding operation of the flash memory data is successful, the flash memory data recovery is successful, and the flash memory data exits the read cycle operation; S3: When the hard decoding operation of the flash data fails, the flash data enters the read cycle, enters a preset first re-reading list, sequentially selects a re-reading voltage of the flash data for reading, and performs a hard decoding operation on the re-reading voltage; It should be noted that in the recovery of the flash data, the voltage threshold of the flash data changes due to various factors, such as read interference, which causes the voltage threshold of the flash data source to shift as a whole, so that the initial read voltage of the flash data is not accurate, the overlap region between two voltage thresholds in the adjacent state increases among the plurality of voltage thresholds, thereby causing the hard decoding of the flash data to fail. In this embodiment, by entering the preset first re-reading list, the re-reading voltage in the first re-reading list is sequentially selected for reading, so that a re-reading voltage more matching the flash data is continuously found, and the flash data is correctly read, thereby improving the success rate of flash data recovery to avoid blind polling of different re-reading voltages.

[0024] S4: The read calibration function is started, the step of the hard decoding operation is determined, the execution strategy of the hard decoding operation is determined according to the step of the hard decoding operation, the re-reading voltage of the flash data is calibrated until the hard decoding operation is successful; if the hard decoding operation of the flash data is still not successful, the read cycle operation is exited after traversing the first re-reading list; It should be noted that the execution strategy of the hard decoding operation is determined according to the step of the hard decoding operation until the hard decoding operation is successful, which can reduce unnecessary occupation of hardware resources. The sequential attempt of traversing the first re-reading list can quickly locate the best voltage reading condition suitable for the current flash data through accurate coverage of the voltage gradient, and avoid time waste caused by random retry.

[0025] Further, due to the synergistic effect of the read calibration function and the hard decoding step, even if there is a partial deviation in the initial reading of the flash data, the read calibration function can correct the timing error when the flash data is read. If the hard decoding fails for the first time, the hard decoding of the flash data is performed according to the execution strategy until the voltage of the first re-reading list is traversed.

[0026] Through the above operation, the data recovery can be completed without enabling the soft decoding operation with high calculation cost in the flash data recovery process. Only when the hard decoding operation is still not successful after traversing the first re-reading list, the step S5 is entered.

[0027] S5: The read compensation function is started, the second re-reading list is entered, the re-reading voltage of the flash data is sequentially selected for reading, and the soft decoding operation is performed on the re-reading voltage to obtain a soft decoding operation result; It should be noted that the hard decoding and the first re-reading list consume less resources and are fast, and preferentially cover simple errors. Only when the conventional means fail, the read compensation function and the soft decoding operation with higher resource consumption are enabled. By setting the second re-reading list, the re-reading voltage of the flash memory data is sequentially selected for reading, and the soft decoding operation is performed on the re-reading voltage, thereby reducing the amount of redundant data processed by the soft decoding operation, controlling the overall time consumption while ensuring the recovery depth, and further balancing the recovery effect and efficiency of the flash memory data.

[0028] S6: According to the soft decoding operation result, the read compensation function is closed.

[0029] It should be noted that the present embodiment flexibly uses the hard decoding operation and the automatic read calibration function, and the automatic read compensation function cooperates with the soft decoding operation, flexibly selects different decoding processes, reduces the reading group number of the re-reading voltage, avoids blind polling of different re-reading voltages, thereby improving the success rate of the soft decoding operation in the limit scenario, and with a large probability, the data of the re-reading voltage of the flash memory data is corrected, so as to end the reading process as soon as possible, thereby reducing the re-reading delay.

[0030] In addition, in an embodiment, referring to Figure 2 , in Figure 1 In step S4 of the embodiment shown, the execution strategy of the hard decoding operation is determined according to the steps of the hard decoding operation, and further includes the following steps: S41: sequentially selecting the re-reading voltage of the first re-reading list for reading to obtain the first current re-reading voltage of the flash memory data; S42: performing the hard decoding operation on the first current re-reading voltage, when the hard decoding operation is successful, the flash memory data recovery is successful; when the hard decoding operation fails, the automatic read calibration function is started to obtain the first re-reading parameter of the first current re-reading voltage of the current reading; S43: performing the hard decoding operation on the first re-reading parameter; S44: when the hard decoding operation on the first re-reading parameter is successful, the automatic read calibration function is closed, and the flash memory data recovery is successful; S45: when the hard decoding operation on the first re-reading parameter fails, the automatic read calibration function is closed, and the bit value of the current reading parameter is confirmed; S46: according to the reading state of the re-reading voltage, the read compensation function is performed on the current reading parameter according to the reading state, and after the automatic read calibration, the offset voltage of the current reading parameter is written into the second re-reading list.

[0031] It should be noted that the first re-reading list is read by sequentially selecting the re-reading voltage, so as to cover the conventional voltage offset scene of flash memory data; the automatic read calibration function is started after the hard decoding operation fails, the systematic deviation of the hardware level is corrected by dynamically adjusting the read parameter, and more accurate input is provided for the hard decoding; if it still fails, the voltage reading state is determined through bit value analysis, the read compensation function is enabled in a targeted manner, and finally the effective offset voltage is written into the second list.

[0032] It should be noted that the automatic read calibration function is not blind adjustment of parameters, but generates the first re-reading parameter based on the first current re-reading voltage, so that the calibration is more targeted; the read compensation is started after the reading state is confirmed by the bit value, which further avoids the waste of resources caused by indiscriminate compensation. Invalid retries are reduced, and recovery efficiency is improved. The offset voltage after automatic read calibration is written into the second re-reading list, and the second re-reading list will gradually accumulate the effective voltage value of the flash memory; in subsequent recovery, the verified offset voltage can be directly called, the overhead of repeated calibration and compensation is reduced, and the recovery speed and stability of the flash memory data are significantly improved.

[0033] Further, the hard decoding operation and the fixed voltage are used to read the flash memory data in priority, and the automatic read calibration function is enabled only when necessary; finally, the read compensation operation handles the soft decoding operation scene, and reduces the processing cost in the form of recording parameters, which guarantees the recovery of the flash memory data while avoiding excessive consumption of hardware resources.

[0034] In addition, in an embodiment, referring to Figure 3 In Figure 2 In step S45 of the embodiment, the read compensation function is performed on the flash memory data according to the reading state, and further includes the following steps: S451: Obtain the setting interval of the current read parameter; S452: When the bit value is in the setting interval, the offset voltage of the current read parameter after the automatic read calibration is read out, and the offset voltage is written into the second re-reading list; S453: When the bit value is not in the setting interval, steps S41 to S46 are traversed until the last re-reading voltage of the first re-reading list is read.

[0035] It should be noted that by setting the judgment interval of the bit value, only the offset voltage with the bit value in the set interval is written to the second read list, avoiding the accumulation of invalid or abnormal parameters. In subsequent calls, the verified offset voltage can be directly used, thereby reducing the redundant attempts during flash data recovery and improving the efficiency of flash data recovery. When the bit value is not in the set interval, it indicates that the current offset voltage may not have reference value due to severe damage to the flash memory cell, strong interference, etc. At this time, the remaining voltage in the first read list is selected instead of blindly recording invalid parameters, which can avoid excessive processing of abnormal data and reduce the consumption of computing resources and time cost of the controller.

[0036] Further, by filtering the bit value through the set interval of the current read parameter, the quality of the parameters in the second read list is ensured, and the coverage of the offset voltage is increased through the traversal mechanism. This enables the rapid accumulation of available offset voltages in the conventional deviation scenario, further improving the efficiency of flash data recovery.

[0037] In addition, in an embodiment, referring to Figure 4 , in Figure 2 the step S42 of the embodiment shown, the automatic read calibration function is started to obtain the first read parameter of the first current read voltage, further comprising the following steps: S421: obtaining the basic read parameter of the flash memory data; S422: in response to the automatic calibration signal and the first timing signal generated by the flash controller, obtaining the first read parameter of the first current read voltage based on the basic read parameter, the automatic calibration signal and the first timing signal.

[0038] It should be noted that automatic read calibration is an enhanced function of NAND Flash. After starting this function, a small range of calibration can be performed on the first current read voltage based on the provided basic read voltage, and the optimal read voltage, i.e., the first current read voltage, can be found near the basic read voltage.

[0039] Specifically, the flash controller starts the function by sending the automatic calibration signal and the timing signal to the NAND Flash, and gives the basic read parameter. The NAND Flash automatically completes the calibration of the first current read voltage. The calibrated current read voltage is stored in the NAND Flash. By sending the command to obtain the calibrated read voltage and the timing to the NAND Flash, the calibrated first read parameter can be obtained.

[0040] In addition, in an embodiment, referring to Figure 5 , in Figure 2 the step S46 of the embodiment shown, the read compensation function is performed on the current read parameter according to the read state, further comprising the following steps: S461: obtaining the automatic read compensation signal and the second timing signal generated by the flash memory controller; S462: performing read compensation on the current read parameter according to the automatic read compensation signal and the second timing signal, wherein the read compensation function is only started when the soft decoding operation is performed.

[0041] It should be noted that after the read compensation function is started, the interference between the flash memory storage units of the flash memory controller can be reduced when reading the flash memory data, and the number of error bits can be reduced. The flash memory controller sends the automatic read compensation signal and the second timing signal to the NAND Flash to start or stop the automatic read compensation function. Since the automatic read compensation function increases the time in the flash memory data recovery process, and the benefit is not great when the bit value error is low, the automatic read compensation function needs to be enabled at an appropriate time. In this embodiment, the automatic read compensation function can only be started when the soft decoding operation is performed on the read voltage.

[0042] In addition, in an embodiment, referring to Figure 6 In Figure 3 In step S5 of the embodiment shown, according to the soft decoding operation on the read voltage, the soft decoding operation result is obtained, and the following steps are further included: S51: sequentially selecting the read voltage of the second read list to perform reading to obtain the second current read voltage of the flash memory data; S52: performing soft decoding operation on the second current read voltage, and when the soft decoding operation is successful, the read compensation function is stopped, and the flash memory data recovery is successful; S53: when the soft decoding operation fails, the read voltage of the second read list is traversed until all read voltages of the second read list are read, and the read compensation function is stopped.

[0043] It should be noted that although the soft decoding operation has strong error correction capability, it has high computational complexity and high power consumption. In this embodiment, the second current read voltage of the flash memory data is obtained by sequentially traversing the second read list, and the soft decoding operation is performed on the second current read voltage. Only when the current voltage of the flash memory data fails after the soft decoding operation, the next group of voltages is tried, and the traversal is completed. While ensuring the recovery of the flash memory data, the computational complexity is reduced, and the recovery effect and system resource occupation are balanced. The read compensation function only takes effect in the second read list operation stage, and is immediately stopped after the soft decoding operation is successful, thereby avoiding the waste of hardware resources caused by long-term opening.

[0044] In an embodiment, the basic read voltage parameter of the flash memory data is written in the first read list, and the read voltage parameter of the basic read voltage parameter after the automatic read calibration is written in the second read list.

[0045] It should be noted that the first re-reading list of the base voltage parameter is for the slight voltage offset common to the flash memory, and under the read calibration function cooperating with the hard decoding operation, the first round of reading attempt of the flash memory data can be quickly completed without additional calculation; the re-reading voltage of the second re-reading list is read, and under the read compensation function cooperating with the soft decoding operation, the complex scene is directly coped with, the resource waste of repeated calibration is avoided, and the calculation and time cost of repeated calibration are reduced; at the same time, with the continuous supplement of new calibration parameters in the use process, the second re-reading list can dynamically adapt to the flash memory data characteristics, so that the recovery strategy evolves with the hardware state, and the efficiency is maintained for a long time.

[0046] As shown in Figure 7 , Figure 7 is a structural diagram of a flash memory data recovery device provided by an embodiment of the application. The application further provides a flash memory data recovery device, which comprises: The processor 701 can be implemented in a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute related programs to implement the flash memory data recovery method provided by the above-mentioned embodiments of the application. The memory 702 can be implemented in a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 702 can store an operating system and other application programs. When the flash memory data recovery method provided by the above-mentioned embodiments of the application is implemented by software or firmware, the related program codes are stored in the memory 702 and called and executed by the processor 701 to implement the flash memory data recovery method of the embodiments of the application. The input / output interface 703 is used to realize information input and output. The communication interface 704 is used to realize the communication interaction between the device and other devices, and can realize communication through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.). The bus 705 transmits information between various components (such as the processor 701, the memory 702, the input / output interface 703, and the communication interface 704) of the device. The processor 701, the memory 702, the input / output interface 703, and the communication interface 704 are connected to each other through the bus 705 for communication within the device.

[0047] The memory 702, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory 702 can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory 702 can optionally include a memory 702 that is remotely arranged relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The above-described device embodiments are only illustrative, and units described as separate components can or can not be physically separated to be located in one place, or can also be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment.

[0048] The embodiment of the present application also provides an electronic device, which comprises the flash data recovery device as described above.

[0049] The embodiment of the present application also provides a storage medium, which is a computer-readable storage medium, and the storage medium stores a computer program. The computer program is executed by a processor to implement the flash data recovery method.

[0050] Those skilled in the art can understand that all or some steps of the method disclosed above can be implemented as software, firmware, hardware and appropriate combinations thereof. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes but is not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, as known to those skilled in the art, communication media generally includes computer readable instructions, data structures, program modules or other data in a modulated data signal carrier or other transmission mechanism, and can include any information delivery medium.

[0051] The systems, apparatuses, modules, or units illustrated by one or more embodiments described above can be implemented by a computer chip or entity, or by a product with some functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0052] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements in the list, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0053] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments.

[0054] In summary, the above only describes the preferred embodiments of the present specification, and is not intended to limit the protection scope of the present specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the protection scope of the present specification.

Claims

1. A method for recovering data from a flash memory, the method comprising: The method comprises the following steps: S1: reading the flash memory data with a default read voltage to make the flash memory data enter a read cycle operation and performing a hard decoding operation on the read flash memory data; S2: when the hard decoding operation on the flash memory data is successful, the flash memory data is recovered successfully, and the flash memory data exits the read cycle operation; S3: when the hard decoding operation on the flash memory data fails, a preset first re-reading list is entered, the re-reading voltage of the flash memory data is sequentially selected for reading, and a hard decoding operation is performed on the re-reading voltage; S4: a read calibration function is started, the step of the hard decoding operation is determined, the execution strategy of the hard decoding operation is determined according to the step of the hard decoding operation, the re-reading voltage of the flash memory data is calibrated until the hard decoding operation is successful, and if the hard decoding operation on the flash memory data is still unsuccessful, the read cycle operation is exited after the first re-reading list is traversed; S5: a read compensation function is started, a second re-reading list is entered, the re-reading voltage of the flash memory data is sequentially selected for reading, and a soft decoding operation is performed on the re-reading voltage to obtain a soft decoding operation result; S6: the read compensation function is closed according to the soft decoding operation result.

2. The flash memory data recovery method of claim 1, wherein, The execution strategy of the hard decoding operation is determined according to the step of the hard decoding operation, comprising: S41: the re-reading voltage of the first re-reading list is sequentially selected for reading to obtain a first current re-reading voltage of the flash memory data; S42: a hard decoding operation is performed on the first current re-reading voltage, when the hard decoding operation is successful, the flash memory data is recovered successfully, when the hard decoding operation fails, an automatic read calibration function is started to obtain a first re-reading parameter of the first current re-reading voltage currently read; S43: the first re-reading parameter is subjected to the hard decoding operation; S44: when the first re-reading parameter is subjected to the hard decoding operation successfully, the automatic read calibration function is closed, and the flash memory data is recovered successfully; S45: when the first re-reading parameter is subjected to the hard decoding operation unsuccessfully, the automatic read calibration function is closed, and a bit value of the current reading parameter is confirmed; S46: the reading state of the re-reading voltage is confirmed according to the bit value, the read compensation function is performed on the current reading parameter according to the reading state, and the offset voltage of the current reading parameter after the automatic read calibration is written into the second re-reading list.

3. The flash memory data recovery method of claim 2, wherein, The read compensation function is performed on the flash memory data according to the reading state, comprising: S451: a set interval of the current reading parameter is obtained; S452: when the bit value is in the set interval, the offset voltage of the current reading parameter after the automatic read calibration is read out, and the offset voltage is written into the second re-reading list; S453: when the bit value is not in the set interval, the steps S41 to S46 are traversed until the re-reading voltage of the last re-reading list is read.

4. The flash memory data recovery method of claim 2, wherein, The automatic read calibration function is started to obtain the first re-reading parameter of the first current re-reading voltage currently read, comprising: S421: obtaining a base read voltage of the flash memory data; S422: in response to an automatic calibration signal and a first timing signal generated by a flash memory controller, obtaining the first re-read parameter of the first current re-read voltage based on the base read voltage, the automatic calibration signal and the first timing signal.

5. The flash memory data recovery method of claim 2, wherein, The read compensation function on the current read parameter according to the read state comprises: S461: obtaining an automatic read compensation signal and a second timing signal generated by a flash memory controller; S462: performing read compensation on the current read parameter according to the automatic read compensation signal and the timing signal, wherein the read compensation function is only started when the soft decoding operation is performed.

6. The flash memory data recovery method of claim 1, wherein, The soft decoding operation on the re-read voltage comprises: S51: sequentially selecting a re-read voltage of the second re-read list to perform read operation, to obtain a second current re-read voltage of the flash memory data; S52: performing the soft decoding operation on the second current re-read voltage, and when the soft decoding operation is successful, the read compensation function is closed, and the flash memory data is recovered successfully; S53: when the soft decoding operation fails, the re-read voltage of the second re-read list is traversed until all the re-read voltages of the second re-read list are read, and the read compensation function is closed.

7. The flash memory data recovery method of claim 1, wherein, The first re-read list writes the base re-read voltage parameter of the flash memory data, and the second re-read list writes the re-read voltage parameter after the automatic read calibration of the base re-read voltage parameter.

8. A flash memory data recovery apparatus, characterized by comprising: The flash memory data recovery device comprises at least one control processor and a memory connected in communication with the at least one control processor; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to perform the flash memory data recovery method according to any one of claims 1 to 7.

9. An electronic device, comprising: The flash memory data recovery device according to claim 8.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions for enabling a computer to perform the flash memory data recovery method according to any one of claims 1 to 7. The computer readable storage medium stores computer executable instructions for enabling a computer to perform the flash memory data recovery method according to any one of claims 1 to 7.

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