Wavefront distributor, chip and computer device

Abstract

The application relates to a wave front distributor, a chip and a computer device. The wave front distributor comprises N columns of computing nodes, each column of computing nodes comprising N rows of computing nodes; an initial computing node in each column acquires a row token and a column token, outputs a signal indicating whether approval is obtained, and outputs the row token and the column token to a next computing node in the initial computing node in each column; the next computing node in each column acquires the row token and the column token, outputs the signal indicating whether approval is obtained, and outputs the row token and the column token to a subsequent computing node in each column until a last computing node in each column acquires the row token and the column token and outputs the signal indicating whether approval is obtained; the signal indicating whether approval is obtained output by each computing node in the wave front distributor is used to judge a request in a request queue; and the initial computing nodes in different columns are located in different rows. The application can avoid ring flow of the signal and improve the order of the control logic.

Description

Technical Field

[0001] This application relates to the field of on-chip communication technology, and in particular to a wavefront distributor, chip, and computer device. Background Technology

[0002] In on-chip communication, there may be multiple requests competing for the same resource. However, each resource can only be used by one request at a time. Therefore, it is necessary to determine which request can use the resource in this situation.

[0003] Typically, when multiple requests compete for the same resource, an allocator or arbitrator is used to adjudicate which request the resource should be allocated to. For example, a wavefront allocator is used to assign multiple requests to multiple resources.

[0004] However, wavefront distributors in related technologies have combinational logic loops, which cause signals to flow continuously in the combinational logic loops, making it impossible to guarantee that the requested decision result will be obtained within the specified time, resulting in control logic chaos. Summary of the Invention

[0005] Therefore, it is necessary to provide a wavefront distributor, chip, and computer device to address the aforementioned technical problems, which can avoid the circumferential flow of signals, facilitate obtaining the requested decision result within a specified time, and improve the orderliness of the control logic.

[0006] In one aspect, this application provides a wavefront distributor, which includes N columns of computing nodes, and each column of computing nodes includes N rows of computing nodes.

[0007] The initial compute node in each column acquires row and column tokens, outputs a signal indicating whether approval is granted, and outputs row and column tokens to the next compute node in the same column. The next compute node in each column acquires row and column tokens, outputs a signal indicating whether approval is granted, and outputs row and column tokens to the next compute node in the same column, until the last compute node in each column acquires row and column tokens and outputs a signal indicating whether approval is granted. The approval signals output by each compute node in the wavefront allocator are used to adjudicate requests in the request queue.

[0008] The initial calculation nodes of different columns are located in different rows.

[0009] In one embodiment, the input terminal of the computing node in the i-th row and i-th column is connected to the i-th output port of the random sorting logic circuit, and the output terminal is connected to the i-th input port of the recovery sorting logic circuit; i is an integer less than or equal to N;

[0010] The input signals of requests in the request queue are randomly sorted by the random sorting logic circuit and then enter the corresponding computing node for adjudication of valid requests. They then enter the recovery sorting logic circuit to restore the sorting of the adjudication results.

[0011] In one embodiment, each computing node in the wavefront allocator is configured to output a signal indicating whether approval has been granted based on the acquired row tokens, column tokens, and a signal indicating whether a valid request exists.

[0012] In one embodiment, for each non-last compute node in each column, each compute node is also configured to output a row token to the next compute node in the row it is in, and to output a column token to the next compute node in the column it is in.

[0013] The next computation node in a given row is determined by the polling order, and the next computation node in a given column is determined by the polling order.

[0014] In one embodiment, for each non-last computing node in each column, each computing node is further configured to output a second value for both the row token and column token when both the obtained row token and column token are first values ​​and an approval signal is output, or when both the obtained row token and column token are second values; and to output a first value for both the row token and column token when both the obtained row token and column token are first values ​​and an approval signal is output.

[0015] In one embodiment, each computing node in the wavefront distributor includes an AND gate circuit for outputting a signal indicating whether approval has been granted based on the row token, column token, and a signal indicating whether a valid request exists obtained by each computing node.

[0016] In one embodiment, for each non-last computing node in each column, each computing node further includes a first logic gate circuit and a second logic gate circuit.

[0017] The first logic gate circuit of each computing node is used to perform a NOT operation on the signal indicating whether approval has been obtained, and then perform a AND operation with the row token obtained by each computing node to obtain the output row token.

[0018] The second logic gate circuit of each computing node is used to perform a NOT operation on the signal indicating whether approval has been obtained, and then perform a AND operation with the column token obtained by each computing node to obtain the output column token.

[0019] In one embodiment, in each column of computing nodes, if there is a target computing node that outputs an approved signal, all computing nodes after the target computing node output an unapproved signal, and the target computing node is not the last computing node.

[0020] In one embodiment, the wavefront distributor further includes random sorting logic circuitry and reordering logic circuitry;

[0021] The random sorting logic circuit is also used to obtain the input signal of the request in each of the N queues, randomly sort the N queues to obtain the input signal of the request in each of the N queues after sorting, and output a signal that there is a valid request to the corresponding computing node according to the queue number of the request and the resource number requested by the request in each of the N queues after sorting.

[0022] The restoration sorting logic circuit is also used to obtain the adjudication results output by the corresponding computing nodes, restore the sorting of each adjudication result, and obtain the adjudication result of the request in each of the N queues.

[0023] In one embodiment, the random sorting logic circuit is further configured to determine the computing node whose number of columns is the same as the resource sequence number among the N computing nodes connected to the output port with the same sorting number, based on the queue sorting number of the request in each of the N queues after sorting and the resource sequence number requested by the request.

[0024] In one embodiment, the first compute node in each column obtains both the row token and the column token as first values.

[0025] Secondly, this application provides a chip that includes any of the wavefront distributors described above.

[0026] Thirdly, this application provides a computer device that includes the aforementioned chip.

[0027] In the technical solution provided in the embodiments of this application, in the N columns of computing nodes of the wavefront distributor, each column of computing nodes always starts the calculation from the initial computing node and passes the row token and column token to the next computing node in each column so that the next computing node in each column can start the calculation and pass the row token and column token to the next computing node in each column, and so on, until the last computing node in each column finishes the calculation. The last computing node in each column will no longer output row tokens and column tokens to other computing nodes. Therefore, the wavefront distributor does not have combinational logic loops, which can avoid the circular flow of signals, which is conducive to obtaining the requested decision result within a specified time and improves the orderliness of the control logic. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A schematic diagram of the structure of an M×K distributor provided for some embodiments;

[0030] Figure 2 A schematic diagram of a wavefront distributor with 3x3 computing nodes provided for related technologies;

[0031] Figure 3 This is a schematic diagram of the circuit structure of a computing node in related technologies;

[0032] Figure 4 A schematic diagram of the structure of a wavefront distributor with N×N computing nodes is provided for some embodiments;

[0033] Figure 5 A schematic diagram of a wavefront distributor with N×N computing nodes is provided for some other embodiments;

[0034] Figure 6 A schematic diagram of a wavefront distributor with 3×3 computing nodes is provided for some embodiments;

[0035] Figure 7 A schematic diagram of a wavefront distributor with 4×4 computing nodes is provided for some embodiments;

[0036] Figure 8 A schematic diagram of a wavefront distributor with 4×4 computing nodes is provided for some other embodiments;

[0037] Figure 9 A schematic diagram of a wavefront distributor with 4×4 computing nodes is provided for some embodiments;

[0038] Figure 10 A schematic diagram of the circuit structure of each computing node in the first N-1 computing nodes of each column is provided for some embodiments;

[0039] Figure 11 A schematic diagram of a chip structure is provided for some embodiments;

[0040] Figure 12 A schematic diagram of the structure of a computer device provided for some embodiments. Detailed Implementation

[0041] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0043] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined. In the description of the embodiments of this application, "each" means each of the multiple options, unless otherwise explicitly defined.

[0044] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0045] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0046] In the description of the embodiments of this application, the technical terms "row", "column", "up", "down", "left", "right", "front", "back", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0047] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0048] In on-chip communication, multiple requests may compete for the same resource within a switching node. For example, multiple requests for input virtual channels might need to enter from the same input port of a crossbar switch. However, without optimization, each resource can only be used by one request at a time. Therefore, a referee is needed to decide which request can use the resource. This refereeing is performed by an allocator / arbitrator. The allocator can match M requests to K resources, while the arbitrator matches M requests to 1 resource. Allocators and arbitrators are widely used in Graphics Processing Units (GPUs), Central Processing Units (CPUs), Neural-network Processing Units (NPUs), or other chips with data processing capabilities.

[0049] To reduce the complexity of the allocator and make it pipelineable, in some embodiments, the allocator can be constructed as a combination of multiple arbitrators. An arbitrator selects one from multiple requests for a single resource. For example, an M:K allocator (meaning matching requests from M request queues to K resources) can be replaced with a two-stage arbitrator system (M being the total number of request queues and N being the total number of resources). The first stage consists of K M:1 arbitrators, obtaining K requests from M initial requests; the second stage consists of M K:1 arbitrators, producing the final approval. For example, there are four request queues. Each of the K M:1 arbitrators in the first level handles a request from one queue. Taking the first arbitrator as an example, the first arbitration can obtain the resource identifier of at least one request in the first queue. Different requests correspond to different resource identifiers. A request is decided from at least one request. And so on, the K M:1 arbitrators will decide one request from each of the K request queues. A request from each of the K request queues may have resource conflicts. In this case, the M K:1 arbitrators in the second level need to make a decision. In this way, each K:1 arbitrator decides one request. The request decided by the i-th K:1 arbitrator can be approved to use the i-th resource.

[0050] The challenge faced by separable allocators is often the inefficiency of matching requests with resources, because the first phase is unaware of the outcome of the second phase, and requests that win in the first phase still face arbitration contention in the second phase. Therefore, the two-stage arbitration can be combined into a single stage to improve the matching rate. Wavefront allocators perform the entire allocation as a single step, making them more efficient and feasible to implement in hardware.

[0051] Figure 1 A schematic diagram of the structure of an M×K distributor provided in some embodiments, such as Figure 1 As shown, the M×K allocator can match requests from M request queues to K resources.

[0052] The wavefront distributor is an M×M or K×K computing node distributor (taking the maximum value of M and K).

[0053] Figure 2 A schematic diagram of a wavefront distributor with 3x3 computing nodes provided for related technologies. Figure 3 This is a schematic diagram of the circuit structure of a computing node in related technologies.

[0054] like Figure 3 As shown, each computing node can obtain the priority signal (pri), the row token signal (xin), and the column token signal (yin). The pri and xin signals are ORed to output the xpri signal, and the pri and yin signals are ORed to output the ypri signal. A signal indicating whether a valid request exists (req) is also provided. ij The signals xpri, ypri, and xpri are approved (also known as authorized) by an AND gate output. ij The signal is passed through the first logic gate circuit to grant ij The NOT signal is ANDed with the xpri signal to obtain the output row token xout signal, which is then passed through the second logic gate circuit to grant. ij The NOT signal is ANDed with the ypri signal to obtain the output row token youout signal. The pri signal can be 0 or 1, where 0 represents a low level and 1 represents a high level. When the pri signal is 1, the calculation node that receives the pri signal equal to 1 begins the calculation. Any one of the xin, yin, xout, and youout signals can have a value of 0 or 1. ij The signal value can be 0 or 1, where 0 indicates a valid request and 1 indicates no valid request. ij The signal can take the value of 0 or 1. 0 indicates that the computing node ij has not been approved, and 1 indicates that the computing node ij has been approved.

[0055] In any embodiment of this application, i represents the row identifier of the computing node, j represents the column identifier of the computing node, i+1 represents the row number of the computing node, and j+1 represents the column number of the computing node.

[0056] Figure 2 As shown, each of the signals p0, p1, and p2 is a pri signal. Only one of the pri signals input to the wavefront distributor has a value of 1, while the others have values ​​of 0. The wavefront distributor's execution begins by setting one of the three priority lines (one of the p0, p1, or p2 signals to a high level). This provides row and column tokens (also called tokens) to the diagonal group of cells connected to the selected priority line. If one of the cells is requesting a resource, it consumes the row and column tokens, and its resource request is granted. Cells that cannot use their tokens pass the row token to the right and the column token down. To improve fairness, the initial priority group changes every cycle.

[0057] from Figure 2 As can be seen, the wavefront distributor contains multiple combinational logic loops. A combinational logic loop is a logic loop that starts at a combinational logic unit, passes through a series of combinational logic steps, and returns to the starting combinational logic unit. The characteristic of a loop is that the output signal is directly fed back to the input node, forming a closed-loop structure. For example, the signal output from compute node 00 is input to compute node 01, the signal output from compute node 01 is input to compute node 02, and the signal output from compute node 02 is input back to compute node 00.

[0058] Combinational logic loops cause signals to flow continuously within the loop, making it impossible to guarantee obtaining the requested decision result within the specified time, leading to control logic chaos. Furthermore, the presence of combinational logic loops prevents digital circuit synthesis, requiring manual breaking of the loops and introducing risks to subsequent stages such as static timing analysis.

[0059] Based on this, the present application provides a novel wavefront distributor that can avoid the circumferential flow of signals, which is beneficial for obtaining the requested decision result within a specified time and improves the orderliness of the control logic.

[0060] Figure 4 This is a schematic diagram of a wavefront distributor with N×N computing nodes provided in the first embodiment. Figure 5 A schematic diagram of a wavefront distributor with N×N computing nodes is provided for some other embodiments, such as Figure 4 and Figure 5 As shown, the wavefront distributor includes N columns of computation nodes, and each column of computation nodes includes N rows of computation nodes;

[0061] The initial compute node in each column acquires row and column tokens, outputs a signal indicating whether approval is granted, and outputs row and column tokens to the next compute node in the same column. The next compute node in each column acquires row and column tokens, outputs a signal indicating whether approval is granted, and outputs row and column tokens to the next compute node in the same column (i.e., the next compute node after the next compute node), until the last compute node in each column acquires row and column tokens and outputs a signal indicating whether approval is granted. The approval signals output by each compute node in the wavefront allocator are used to adjudicate requests in the request queue.

[0062] The initial calculation nodes of different columns are located in different rows.

[0063] In some embodiments, N is the maximum of the number of request queues and the number of resources to be allocated.

[0064] The wavefront distributor consists of N×N computational nodes, with each column containing N computational nodes.

[0065] For example, the N columns of computing nodes are shifted up one computing node position in each column, so that the first row has one computing node, and one computing node is added to each row from the first row until the Nth row, and one computing node is removed from each row from the Nth row until the 2N-1th row.

[0066] For example, the wavefront distributor occupies 2N-1 rows. The mth row from the 1st to the N-1th row has m computing nodes and occupies the last m columns; the Nth row has N computing nodes and occupies N columns; and the nth row from the N+1th to the 2N-1th row has 2N-n computing nodes and occupies the first 2N-n columns.

[0067] In this embodiment, the initial compute node in each column is the compute node of the first row in each column.

[0068] For example, the wavefront assigner occupies N rows. The initial computation node in the first column is the computation node in the first row of the first column. The initial computation node in the m-th column from the 2nd to the Nth column is the computation node in the (N+2-m)-th row of the m-th column. Taking N as 4 as an example, the initial computation node in the first column is the computation node in the first row of the first column, the initial computation node in the second column is the computation node in the 4th row of the second column, the initial computation node in the third column is the computation node in the 3rd row of the third column, and the initial computation node in the fourth column is the computation node in the 2nd row of the fourth column.

[0069] Row tokens can be the xin signal mentioned above, and column tokens can be the yin signal. For any compute node, the row tokens and column tokens obtained are the same.

[0070] Each compute node outputs an approval signal to indicate whether its request has been approved. Compute node approval means that the request corresponding to the compute node has been approved. Specifically, a compute node can only output an approval signal if it receives a signal indicating that a valid request exists; it cannot output an approval signal if it receives a signal indicating that no valid request exists.

[0071] In some embodiments, computing nodes in different columns can be computed in parallel. For example, the initial computing nodes in different columns can be computed in parallel, the next computing node in different columns can be computed in parallel, the next computing node in different columns can be computed in parallel, and the last computing node in different columns can be computed in parallel.

[0072] In this case, once the computation of the last computation node in each column of the wavefront allocator has ended, row and column tokens will no longer be passed between these computation nodes, which differs from [the previous point]. Figure 2 and Figure 3 In the illustrated embodiment, the presence of combinational logic loops causes row tokens and column tokens to be passed endlessly through the loops.

[0073] It should be noted that the value of N is not unique. For example, the value of N can be any integer greater than or equal to 2. Exemplarily, the range of N can be from 2 to 200. For example, the value of N can be 2, 3, 4, 8, 16, 100, or 200, etc., and this application embodiment does not impose any limitation on this. As an example, Figure 6 A schematic diagram of a wavefront distributor with 3×3 computing nodes is provided for some embodiments. Figure 7 This is a schematic diagram of a wavefront distributor with 4×4 computing nodes provided for some embodiments. Figure 6 The token passing structure of the demonstrated 3×3 wavefront distributor uses three highest-priority compute nodes: Node 00, Node 21, and Node 12. After processing at their respective nodes, row and column tokens are passed to the next highest-priority compute nodes (Node 10, Node 01, and Node 22) in the direction indicated by the arrows. After processing at their respective nodes, the same row and column tokens are passed to the next highest-priority compute nodes (Node 20, Node 11, and Node 02), and the token passing process ends. For larger-scale wavefront distributors, this rule is extended, for example, to obtain... Figure 7 The diagram shows the structure of a wavefront distributor with 4×4 computational nodes.

[0074] For example, when N equals 2, the calculation process of the wavefront allocator is as follows: the initial computing node in each column obtains the row token and column token, outputs a signal indicating whether it has been approved, and outputs the row token and column token to the next computing node of the initial computing node in each column; the next computing node of the initial computing node in each column obtains the row token and column token, outputs a signal indicating whether it has been approved, and thus the calculation of each computing node in the wavefront allocator ends.

[0075] For example, when N equals 3, the calculation process of the wavefront allocator is as follows: the initial computing node in each column obtains the row token and column token, outputs a signal indicating whether it has been approved, and outputs the row token and column token to the next computing node in each column; the next computing node in each column obtains the row token and column token, outputs a signal indicating whether it has been approved, and outputs the row token and column token to the next computing node in each column; the next computing node in each column obtains the row token and column token, outputs a signal indicating whether it has been approved, and so on. Thus, the calculation of each computing node in the wavefront allocator ends.

[0076] For example, when N equals 4, the calculation process of the wavefront allocator is as follows: the initial computing node in each column obtains the row token and column token, outputs a signal indicating whether approval is granted, and outputs the row token and column token to the next computing node in each column; the next computing node in each column obtains the row token and column token, outputs a signal indicating whether approval is granted, and outputs the row token and column token to the next computing node in each column; the next computing node in each column obtains the row token and column token, outputs a signal indicating whether approval is granted, and outputs the row token and column token to the last computing node in each column; the last computing node in each column obtains the row token and column token, outputs a signal indicating whether approval is granted, and thus, the calculation of each computing node in the wavefront allocator ends.

[0077] In the technical solution provided in the embodiments of this application, in the N columns of computing nodes of the wavefront distributor, each column of computing nodes always starts the calculation from the initial computing node and passes the row token and column token to the next computing node in each column so that the next computing node in each column can start the calculation and pass the row token and column token to the next computing node in each column, and so on, until the last computing node in each column finishes the calculation. The last computing node in each column will no longer output row tokens and column tokens to other computing nodes. Therefore, the wavefront distributor does not have combinational logic loops, which can avoid the circular flow of signals, which is conducive to obtaining the requested decision result within a specified time and improves the orderliness of the control logic.

[0078] Figure 8A schematic diagram of a wavefront distributor with 4×4 computing nodes is provided for some other embodiments. Figure 9 A schematic diagram of a wavefront distributor with 4×4 computing nodes is provided for some embodiments.

[0079] exist Figure 8 and Figure 9 In the above, the input terminal of the computing node in the i-th row and i-th column is connected to the i-th output port of the random sorting logic circuit, and the output terminal is connected to the i-th input port of the recovery sorting logic circuit; i is an integer less than or equal to N; the input signals of requests in the request queue are randomly sorted by the random sorting logic circuit and then enter the corresponding computing node for adjudication of valid requests, and then enter the recovery sorting logic circuit to restore the sorting of the adjudication results.

[0080] exist Figure 8 and Figure 9 In the embodiment shown, the compute node ij represents the compute node in the (i+1)th row and (j+1)th column.

[0081] In some embodiments, the random sorting logic circuit can obtain the input signal of a request from the request queue from a register. In some embodiments, the reordering logic circuit can output the reordered decision result to a register. Thus, the register can determine whether to output a request based on the decision result of each request.

[0082] The input signal of the request can indicate the queue sequence number of the request queue in which the request belongs and the sequence number of the requested resource. The input signal acquired at the p-th input port of the random sorting logic circuit indicates the queue sequence number p of the request queue in which each request belongs and the sequence number q of the resource requested by each request. Exemplarily, p can be an integer greater than or equal to 0, and q can be an integer greater than or equal to 0. In some embodiments, the 0th input actually refers to the first input, and so on; for example, the 0th to 3rd inputs are essentially the 1st to 4th inputs.

[0083] In some embodiments, the random sorting logic circuit is used to process input signals of requests in the request queue. Exemplarily, the random sorting logic circuit is used to process input signals of requests in the request queue according to the queue sequence number of the request queue.

[0084] In some embodiments, the random sorting logic circuit is further configured to output a signal indicating the existence of a valid request to the corresponding computing node based on the input signals of the requests in the sorted request queue.

[0085] In some embodiments, the corresponding compute node adjudicates a valid request based on a signal indicating that a valid request exists. Exemplarily, the corresponding compute node adjudicates a valid request based on the signal indicating that a valid request exists, and based on the acquired row token and column token. For example, for a compute node, if the signal indicating that a valid request exists, and if both the acquired row token and column token are first values, the result of adjudicating the valid request is to output a signal indicating approval. As another example, for a compute node, if the signal indicating that a valid request exists, and if both the acquired row token and column token are second values, the result of adjudicating the valid request is to output a signal indicating disapproval.

[0086] It should be noted that in any embodiment of this application, the first value can be 0 and the second value can be 1. Exemplarily, 0 represents a low level and 1 represents a high level. In other embodiments outside of this application, the first value can be 1 and the second value can be 0, or the first and second values ​​can be other values; this application does not impose any restrictions on this.

[0087] In some embodiments, the recovery sorting logic circuit is used to restore the sorting of the adjudication results. For example, the recovery sorting logic circuit can restore the sorting of the adjudication results according to the above-described random sorting mapping relationship, thus obtaining the adjudication results requested in each request queue.

[0088] In some embodiments, the random sorting logic circuit and the reordering logic circuit may be included in the wavefront distributor. In other embodiments, the random sorting logic circuit and the reordering logic circuit may not be included in the wavefront distributor.

[0089] In the solution of this application embodiment, the priority line is eliminated, and random sorting and reordering functions are introduced before and after the computing node, so that the tokens of the row and column are only passed in one direction, thus solving the problem of combinational logic loops.

[0090] In some embodiments, each computing node in the wavefront allocator is configured to output a signal indicating whether an approval has been granted based on the acquired row token, column token, and a signal indicating whether a valid request exists. In some embodiments, the register can output a signal indicating a valid request to the corresponding computing node and a signal indicating no valid request to other computing nodes based on the initial queue number of the request in the request queue and the resource number of the requested resource. In other embodiments, the random sorting logic circuit can output a signal indicating a valid request to the corresponding computing node and a signal indicating no valid request to other computing nodes based on the sorted queue number of the request in the sorted request queue and the resource number of the requested resource. For example, if the initial queue number of a queue is 0, after sorting the queue, the queue number of the sequence can be 2.

[0091] In some embodiments, for non-last compute nodes in each column, each compute node is also configured to output a row token to the next compute node in the row it is in, and a column token to the next compute node in the column it is in.

[0092] The next computation node in a given row is determined by the polling order, and the next computation node in a given column is determined by the polling order.

[0093] For example, if the current compute node is the t-th compute node (t is less than N) in the s-th row, then the next compute node in the row where the current compute node is located is the (t+1)-th compute node in the s-th row.

[0094] For example, if the current compute node is the t-th compute node in the r-th column (t is less than N), then the next compute node in the column where the current compute node is located is the (t+1)-th compute node in the r-th row.

[0095] For example, if the current compute node is the Nth compute node in the s-th row, then the next compute node in the row where the current compute node is located is the first compute node in the s-th row.

[0096] For example, if the current compute node is the Nth compute node in the rth column, then the next compute node in the column where the current compute node is located is the first compute node in the rth column.

[0097] In some embodiments, for non-last computing nodes in each column, each computing node is further configured to output a second value for both the row token and column token when both the acquired row token and column token are first values ​​and an approval signal is output, or when both the acquired row token and column token are second values; and to output a first value for both the row token and column token when both the acquired row token and column token are first values ​​and an approval signal is output.

[0098] The following example uses requests from four request queues, combined with... Figure 8 and Figure 9 The implementation process of the embodiments of this application is explained as follows:

[0099] The four input ports of the random sorting logic circuit obtain the resource sequence number indicated by the requests in the four request queues respectively. There are two requests in the first request queue (queue number 0), indicating resource sequence number 0 and 1 respectively. There is one request in the second request queue (queue number 1), indicating resource sequence number 1. There is one request in the third request queue (queue number 2), indicating resource sequence number 0. There is one request in the fourth request queue (queue number 4), indicating resource sequence number 2.

[0100] The random sorting logic circuit sorts the four request queues by their sorting numbers 0, 1, 2, and 3. For example, the random sorting result is 2, 1, 0, and 3. The four output ports of the random sorting logic circuit correspond to the sorting numbers of the queues. Thus, the first output port of the random sorting logic circuit corresponds to the resource number 0 indicated by the request in the third request queue, and outputs a signal indicating a valid request to compute node 00. The second output port corresponds to the resource number 1 indicated by the request in the second request queue, and outputs a signal indicating a valid request to compute node 11. The third output port corresponds to the resource numbers 0 and 1 indicated by the requests in the first request queue, and outputs a signal indicating a valid request to compute nodes 20 and 21. The fourth output port corresponds to the resource number 2 indicated by the request in the fourth request queue, and outputs a signal indicating a valid request to compute node 32.

[0101] Therefore, the random sorting logic circuit outputs a signal indicating that a valid request exists to computing nodes 00, 11, 20, 21, and 32, and outputs a signal indicating that no valid request exists to other computing nodes.

[0102] The first computing node in each column starts the calculation. Computing node 00 outputs an approved signal and outputs a second value for both the row token and column token, based on the fact that both the row token and column token are the first value and the signal that a valid request exists. Each computing node in computing nodes 31, 22, and 13 outputs an unapproved signal and outputs a first value for both the row token and column token, based on the fact that both the row token and column token are the first value and the signal that no valid request exists.

[0103] Next, the second computing node in each column begins calculation. Computing node 10, based on the fact that both the obtained row token and column token are second values ​​and the signal that no valid request exists, outputs a signal that approval has not been granted and outputs a signal that both the row token and column token are second values. Computing node 32, based on the fact that both the obtained row token and column token are first values ​​and the signal that a valid request exists, outputs a signal that approval has been granted and outputs a signal that both the row token and column token are second values. Each computing node in computing nodes 01 and 23, based on the fact that both the obtained row token and column token are first values ​​and the signal that no valid request exists, outputs a signal that approval has not been granted and outputs a signal that both the row token and column token are first values.

[0104] Then, the third computing node in each column begins the calculation. Computing node 20, based on the fact that both the obtained row token and column token are the second value and the signal that there is a valid request, outputs a signal that approval has not been granted and outputs a signal that both the row token and column token are the second value. Computing node 11, based on the fact that both the obtained row token and column token are the first value and the signal that there is a valid request, outputs a signal that approval has been granted and outputs a signal that both the row token and column token are the second value. Computing node 02, based on the fact that both the obtained row token and column token are the second value and the signal that there is no valid request, outputs a signal that approval has not been granted and outputs a signal that both the row token and column token are the second value. Computing node 33, based on the fact that both the obtained row token and column token are the first value and the signal that there is no valid request, outputs a signal that approval has not been granted and outputs a signal that both the row token and column token are the first value.

[0105] Finally, the third computing node in each column begins calculation. Computing node 30, based on the second value of both the row and column tokens and the signal that no valid request exists, outputs a signal indicating approval was denied, completing the calculation for the first column. Computing node 21, based on the second value of both the row and column tokens and the signal that a valid request exists, outputs a signal indicating approval was denied, completing the calculation for the second column. Computing node 12, based on the second value of both the row and column tokens and the signal that no valid request exists, outputs a signal indicating approval was denied, completing the calculation for the third column. Computing node 03, based on the first value of both the row and column tokens and the signal that no valid request exists, outputs a signal indicating approval was denied, completing the calculation for the fourth column. Computing nodes 30, 21, 12, and 03 do not have output terminals for row and column tokens. Computing nodes 30, 21, 12, and 03 do not output row and column tokens to other computing nodes.

[0106] Through the calculations of the computing nodes described above, it can be seen that computing nodes 00, 11, and 32 output approved signals. Therefore, computing nodes 00, 11, and 32 output approved signals to the fourth, first, and third input ports of the recovery sorting logic circuit, respectively. Other computing nodes output unapproved signals to their connected input ports.

[0107] However, the random sorting logic circuit shuffles the queue's sequence numbers, so the approval signal input to the reordering logic circuit is the approval signal corresponding to the shuffled sequence number. Therefore, the reordering logic circuit needs to reorder the queue. For example, if the random sorting logic circuit replaces queue sequence numbers 0 and 2, the reordering logic circuit will modify 00, 11, 32 to 20, 11, 32. Thus, the approval signal output from the first output port of the reordering logic circuit indicates that the request with initial sequence number 0 in the request queue was not approved; the approval signal output from the second output port indicates that the request for resource 1 in initial sequence number 1 of the request queue was approved; the approval signal output from the third output port indicates that the request for resource 0 in initial sequence number 2 of the request queue was approved; and the approval signal output from the fourth output port indicates that the request for resource 2 in initial sequence number 3 of the request queue was approved. For example, in the next clock cycle, the three approved requests in the request queue will be allowed to be released, and the unapproved requests will not be allowed to be released.

[0108] For example, taking a wavefront distributor with 4x4 computing nodes as an example, the original 4 input signals first pass through a random sorting module to generate 4 new input signals in. ij . will in 00 The req port sent to compute node 00 will send in 01 The req port sent to compute node 01 will send in 02 The req port sent to compute node 02 will send in 03 Sending the in to the req port of compute node 03 10 Send it to the req port of compute node 10, and so on.

[0109] Computation nodes 00, 31, 22, and 13, as the highest priority computation nodes, obtain row and column tokens by inputting 1 through xin and yin. After processing, the tokens are passed to the next priority computation nodes (computation nodes 10, 01, 32, and 23), then to the next priority computation nodes (computation nodes 20, 11, 02, and 33), and finally to the next priority computation nodes (computation nodes 30, 21, 12, and 03), and the token passing process ends.

[0110] According to the token passing, each computing node completes the processing and outputs its own grant signal (i.e., the signal indicating whether it has been approved), a total of 4 groups, which are sent to the recovery sorting module to restore the original input sorting and output the final approval signal.

[0111] Figure 10 A schematic diagram of the circuit structure of each computing node in the first N-1 computing nodes of each column is provided for some embodiments, such as... Figure 10 As shown, each computing node in the wavefront distributor includes an AND gate circuit, used to determine the row token xin, column token yin, and the signal req indicating whether a valid request exists based on the data obtained by each computing node. ij Output a signal indicating whether the grant has been approved. ij .

[0112] In some embodiments, for computing nodes other than the last one in each column, each computing node further includes a first logic gate and a second logic gate; the first logic gate of each computing node is used to transfer a grant signal indicating whether approval has been granted. ij After performing the NOT operation, a AND operation is then performed with the row tokens obtained from each compute node to obtain the output row token xout; the second logic gate circuit of each compute node is used to input the grant signal indicating whether approval has been granted. ij After performing the NOT operation, a AND operation is then performed with the column tokens obtained from each computing node to obtain the output column token yout.

[0113] In this design, the circuit structure of the last computing node in each column does not include the first logic gate circuit and the second logic gate circuit. As a result, row tokens and column tokens will not be output. Thus, the circuit structure of the last computing node in each column only includes AND gate circuits.

[0114] In the technical solution provided in this application embodiment, since the pri signal input is not required, one level of combinational logic is reduced (i.e., Figure 3 (Logic of OR gates in the code). If the inputs xin and yin of the compute node are both 1 (indicating that there are both row tokens and column tokens), and req ij If the value is 1 (indicating that the compute node has a valid request), then grant ij A value of 1 indicates that the compute node has been approved. Simultaneously, xout and yout output 0, indicating that the row and column tokens have been consumed and will not be passed down to the next level. If the compute node's inputs xin and yin are not both 1, or although both are 1, req... ij If the value is 0, the compute node will not be approved and will pass the input token to the next level.

[0115] The AND gate's OR operation logic is that the output is high if and only if all inputs are high (logic 1); the output is low if any input is low (logic 0).

[0116] The NOT operation logic is such that when the input is high (logic 1), the output is low (logic 0); when the input is low (logic 0), the output is high (logic 1), thus achieving the function of logical inversion.

[0117] In some embodiments, in each column of computing nodes, if there is a target computing node that outputs an approved signal, all computing nodes after the target computing node output an unapproved signal, and the target computing node is not the last computing node.

[0118] In some embodiments, the wavefront distributor further includes a random sorting logic circuit and a recovery sorting logic circuit;

[0119] The random sorting logic circuit is also used to obtain the input signal of the request in each of the N queues, randomly sort the N queues to obtain the input signal of the request in each of the N queues after sorting, and output a signal that there is a valid request to the corresponding computing node according to the queue number of the request and the resource number requested by the request in each of the N queues after sorting.

[0120] The restoration sorting logic circuit is also used to obtain the adjudication results output by the corresponding computing nodes, restore the sorting of each adjudication result, and obtain the adjudication result of the request in each of the N queues.

[0121] In some embodiments, the random sorting logic circuit is further configured to determine the computing node whose number of columns is the same as the resource sequence number among the N computing nodes connected to the output port with the same sorting number, based on the queue sorting number of the request in each of the N queues after sorting and the resource sequence number requested by the request.

[0122] In some embodiments, the row token and column token obtained by the first compute node in each column compute node are both first values.

[0123] Figure 11 This is a schematic diagram of the structure of a chip provided for some embodiments. For example, the chip may include an on-chip communication chip, such as... Figure 11 As shown, the chip may include the wavefront distributor in any of the above embodiments.

[0124] In some embodiments, the chip may further include registers connected to the wavefront distributor in any of the above embodiments. The registers store multiple request queues. Exemplarily, the chip may be a processor.

[0125] For example, a chip may include an integration of one or more of the following: a general-purpose processor, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field-programmable gate array (FPGA), a CPU, a GPU, an NPU, a controller, a microcontroller, a microprocessor, a programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The general-purpose processor may be a microprocessor or any conventional processor.

[0126] In some embodiments, a computer device may also be provided, which includes the chip in any of the above embodiments. For example, the computer device may include the chip in any of the above embodiments and a memory connected to the chip.

[0127] In one exemplary embodiment, a computer device is provided. Figure 12This is a schematic diagram of the structure of a computer device provided for some embodiments. The computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used for exchanging information between the processor and external devices. The communication interface of the computer device is used for wired or wireless communication with external terminals. Wireless communication can be implemented through Wireless Fidelity (WIFI), mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements an instruction processing method. The display unit of the computer device is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0128] The computer device in any embodiment of this application includes the integration of one or more of the following: server, mobile phone, tablet computer, computer with wireless transceiver function, handheld computer, desktop computer, personal digital assistant, portable media player, smart speaker, navigation device, smartwatch, smart glasses, smart necklace and other wearable devices, pedometer, digital TV, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, vehicle in vehicle networking system, in-vehicle equipment, in-vehicle module, etc.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0130] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A wavefront distributor, characterized in that, The wavefront distributor includes N columns of computing nodes, and each column of computing nodes includes N rows of computing nodes; The initial computing node in each column acquires row tokens and column tokens, outputs a signal indicating whether approval has been granted, and outputs row tokens and column tokens to the next computing node in each column. The next compute node in each column acquires the row token and column token, outputs a signal indicating whether approval has been granted, and outputs the row token and column token to the next compute node, until the last compute node in each column acquires the row token and column token and outputs a signal indicating whether approval has been granted; the signal indicating whether approval has been granted output by each compute node in the wavefront allocator is used to adjudicate requests in the request queue; The initial computing nodes in different columns are in different row numbers; for non-last computing nodes in each column, each computing node is also used to output a row token to the next computing node in its row and a column token to the next computing node in its column. The next computation node in a given row is determined by a polling order, and the next computation node in a given column is determined by a polling order.

2. The wavefront distributor according to claim 1, characterized in that, The input terminal of the computation node in the i-th row and i-th column is connected to the i-th output port of the random sorting logic circuit, and the output terminal is connected to the i-th input port of the recovery sorting logic circuit; i is an integer less than or equal to N; The input signals of requests in the request queue are randomly sorted by the random sorting logic circuit and then enter the corresponding computing node for adjudication of valid requests. They then enter the recovery sorting logic circuit to restore the sorting of the adjudication results.

3. The wavefront distributor according to claim 1, characterized in that, Each computing node in the wavefront allocator is used to output a signal indicating whether approval has been granted based on the acquired row tokens, column tokens, and a signal indicating whether a valid request exists.

4. The wavefront distributor according to claim 1, characterized in that, For each non-last computing node in each column, each computing node is further configured to output a signal of approval when both the obtained row token and column token are first values, or when both the obtained row token and column token are second values. If both the obtained row token and column token are first values, and the output signal indicates that approval has not been obtained, the output row token and column token will both be first values.

5. The wavefront distributor according to any one of claims 1-4, characterized in that, Each computing node in the wavefront distributor includes an AND gate circuit, used to output a signal indicating whether approval has been granted based on the row token, column token, and a signal indicating whether a valid request exists obtained by each computing node.

6. The wavefront distributor according to claim 5, characterized in that, For each non-last computing node in each column, each computing node further includes a first logic gate circuit and a second logic gate circuit; The first logic gate circuit of each computing node is used to perform a NOT operation on the signal indicating whether approval has been obtained, and then perform a AND operation with the row token obtained by each computing node to obtain the output row token. The second logic gate circuit of each computing node is used to perform a NOT operation on the signal indicating whether approval has been obtained, and then perform a AND operation with the column token obtained by each computing node to obtain the output column token.

7. The wavefront distributor according to any one of claims 1-4, characterized in that, In each column of computing nodes, if there is a target computing node that outputs an approved signal, all computing nodes after the target computing node output an unapproved signal, where the target computing node is not the last computing node.

8. The wavefront distributor according to any one of claims 1-4, characterized in that, The wavefront distributor also includes a random sorting logic circuit and a recovery sorting logic circuit; The random sorting logic circuit is also used to obtain the input signal of the request in each of the N queues, randomly sort the N queues to obtain the input signal of the request in each of the sorted N queues, and output a signal that there is a valid request to the corresponding computing node according to the queue sort number of the request in each of the N queues and the resource sequence number requested by the request. The recovery sorting logic circuit is also used to obtain the adjudication results output by the corresponding computing nodes, restore the sorting of each adjudication result, and obtain the adjudication result of the request in each of the N queues.

9. The wavefront distributor according to claim 8, characterized in that, The random sorting logic circuit is further configured to determine the corresponding computing node from among the N computing nodes connected to the same output port as the sorting number, based on the queue sorting number of the request in each of the N queues and the resource sequence number requested by the request.

10. The wavefront distributor according to any one of claims 1-4, characterized in that, The first compute node in each column obtains both the row token and column token with the first value.

11. A chip, characterized in that, The chip includes the wavefront distributor according to any one of claims 1 to 10.

12. A computer device, characterized in that, The computer device includes the chip of claim 11.

Images