Code-free power management controller design system and method

Abstract

The invention relates to a system and a method for designing a power management controller in a code-free manner. The system comprises a memory for storing at least one instruction; and at least one processor to execute the at least one instruction stored in the memory. The at least one instruction includes instructions to generate a root power manager instance based on a root power manager component, a domain power manager instance based on a domain power manager component; instructions to set a connection between an output port of the root power manager instance and an input port of the at least one domain power manager instance; instructions to respectively allocate memory storage space to power manager instances constituting the power management controller; and instructions for generating hardware codes of power elements included in the power management controller, register codes corresponding to the respective power elements, hardware codes corresponding to the plurality of ports and connections, and binary codes corresponding to a working sequence of the power management controller.

Description

TECHNICAL FIELD

[0001] The present invention relates to a power management controller design for controlling power of a system-on-chip device, and more particularly, to a system and method of designing a power management controller for performing power control of a plurality of power domains constituting a system-on-chip device in a codeless manner. BACKGROUND

[0002] A system-on-chip (SOC) refers to a technology of integrating a plurality of function blocks such as a central processing unit (CPU), a memory, an interface, a digital signal processing circuit, and an analog signal processing circuit in one semiconductor integrated circuit or an integrated circuit (IC) integrated according to the technology for implementing a computer system or other electronic system. The system-on-chip is developing into a more complex system including a processor, a multimedia, a graphic, an interface, and a security.

[0003] Generally, in the system-on-chip, power and clock design is very important. The system-on-chip needs a power management unit for properly managing power, and needs to design a power management controller for controlling power of a plurality of power domains when designing the system-on-chip.

[0004] Generally, a power and clock design process of the system-on-chip includes a power / clock diagram drawing step, a verilog coding and scripting step, a first documentation step, a unified power format / standard design constraint (UPF / SDC) file generation step, an implementation layout design step, a second documentation step, a design for testability (DFT) controller insertion step, a hardware system parsing step, and a software optimization step.

[0005] The power / clock diagram drawing step visually represents the power and clock structure and creates a block diagram to represent the power domain and clock tree. In the power / clock diagram drawing step, only the clock elements and their linkages are represented in a graphic manner. The Verilog coding and script writing step creates the Verilog code and scripts used to define and implement the functions of the system-on-chip to perform the register transfer level (RTL) design of the hardware. That is, based on the power / clock diagram drawing product, the developer manually generates the register transfer level (RTL) code.

[0006] The first texturization step is a step of texturizing the design intent and structure at the early stage of the project to create various requirement specifications, architecture designs, power / clock diagrams, and the like, which are required by various stakeholders such as the verification team and the software development team.

[0007] The unified power format / standard design constraint file generation step is a step of generating unified power format (UPF) and standard design constraint (SDC) files for controlling power management and timing constraints, which are required as input for hardware synthesis.

[0008] The implementation layout design step is a step of designing and configuring the layout of the actual system-on-chip at the gate level. The second texturization step is a step of updating and refining various files by reflecting the changes in the design and implementation. The testability design controller insertion step is a step of designing and integrating a testability design controller and logic circuit for testing and debugging in the system-on-chip. The hardware system resolution step is a step of confirming and resolving the operation of the software through simulation and verification to confirm the accuracy and effectiveness of the design, and the software optimization step is a step of analyzing and optimizing the software code executed on the system-on-chip to optimize the performance of the software.

[0009] The respective steps of the design process of such a system-on-chip are independently performed by each stakeholder for the corresponding step, and the information required in each step can be different. That is, the information required for the first half of the work and the information required for the second half of the work can be different. Therefore, problems in the design work product of the first half of the project by the workers can be found through the simulation and verification of the second half, and it is necessary to repeatedly perform from the beginning of the first half of the work in order to solve such problems. Also, when the requirements or design objects change during the progress of the project, it is necessary to repeatedly perform from the beginning of the initial design work.

[0010] As described above, in a component in which a plurality of steps are repeatedly performed, a plurality of stakeholders need to reflect changes in other steps and repeatedly perform similar jobs, and thus, a system-on-chip design will consume much time and manpower. SUMMARY

[0011] The present application is to solve the above-described problems, and an object of the present application is to provide a codeless power management controller design system and method that automatically derives register transfer level (RTL) codes corresponding to a power management controller by considering power and processor requirements of a system-on-chip.

[0012] The present application can be implemented in a variety of ways including a device (system), a method, a computer program stored in a computer readable medium, or a computer readable medium storing a computer program.

[0013] The codeless power management controller design system according to an embodiment of the present application includes a memory for storing at least one instruction, a power manager component repository storing a root power manager component and at least one type of domain power manager component, and at least one processor for executing the at least one instruction stored in the memory.

[0014] The at least one instruction includes an instruction for generating a root power manager instance constituting a power management controller based on the root power manager component, an instruction for generating at least one domain power manager instance constituting the power management controller based on the at least one type of domain power manager component, an instruction for setting a connection between an output port of the root power manager instance and an input port of the at least one domain power manager instance, an instruction for respectively allocating memory storage spaces to the root power manager instance and the at least one domain power manager instance constituting the power management controller, and an instruction for generating hardware codes of power elements included in the power management controller, register codes corresponding to the power elements, hardware codes corresponding to a plurality of ports and connections, and binary codes corresponding to a work sequence of the power management controller.

[0015] Preferably, the at least one instruction includes an instruction for copying register field values and work sequences of the root power manager component to register field values and work sequences of the root power manager instance, and respectively copying register field values and work sequences of the at least one domain power manager component to register field values and work sequences of the corresponding domain power manager instances.

[0016] Preferably, the at least one instruction includes an instruction for setting a number of domain groups and a number of power domains connected to each domain group for the root power manager instance.

[0017] More preferably, the memory storage space allocated to the domain power manager instance is determined based on the number of domain groups and the number of power domains included in the domain group having the domain power manager instance.

[0018] Preferably, the at least one instruction includes an instruction for generating a power management interface instance connected to the domain power manager instance through the P-link, respectively corresponding to the at least one domain power manager instance.

[0019] Preferably, the at least one instruction includes an instruction for generating at least one power instance constituting at least one power manager component of the root power manager component and the at least one type of domain power manager component based on the at least one power component; generating a first instruction instance based on the at least one instruction component; determining a target power instance of the first instruction instance and setting a value in the at least one power instance; and generating a code containing an instruction, a register address, and data based on the first instruction instance and the target power instance and the value.

[0020] More preferably, the at least one instruction includes an instruction for generating a second instruction instance based on the at least one instruction component; setting a target power instance and a value of the second instruction instance in the at least one power instance; and setting an execution order of the first instruction instance and the second instruction instance.

[0021] More preferably, the at least one power component is at least one of a reset component, an isolation component, a switch control component, a hold component, an automatic power manager (APM) component, a reference clock gating component, a memory component, a handshake component, a clock link component, a P-channel handshake component, a user-defined output component, and a user-defined input component.

[0022] More preferably, the at least one power component is at least one of a notification register generation component, a TIMEOUT register generation component, an upper layer information transfer register generation component, an internal register storage component, an internal register control interrupt generation component, an external input control interrupt generation component, a timer generation component, and a domain power manager connection component.

[0023] More preferably, the at least one instruction component is at least one of a WRITE component for writing a specific value in a specific register field, a READ WAIT component for waiting for a specific value to be input to a specific register field, a WAIT component for waiting for a specified time, an IF component for branching according to a condition, a GOTO component for moving to a specific location, and a CALL component capable of moving to a specific location and restoring.

[0024] The codeless power management controller design method of one embodiment of the present application is executed by at least one processor in a computer system including a power manager component repository storing a root power manager component and at least one type of domain power manager component. The codeless power management controller design method includes the steps of generating a root power manager instance constituting a power management controller based on the root power manager component, generating at least one domain power manager instance constituting the power management controller based on the at least one type of domain power manager component, setting a connection between an output port of the root power manager instance and an input port of the at least one domain power manager instance, respectively allocating memory storage spaces to the root power manager instance and the at least one domain power manager instance constituting the power management controller, and generating hardware codes of power elements included in the power management controller, register codes corresponding to the power elements, hardware codes corresponding to the plurality of ports and the connection, and binary codes corresponding to a work sequence of the power management controller.

[0025] Preferably, the codeless power management controller design method includes the steps of copying register field values and a work sequence of the root power manager component to register field values and a work sequence of the root power manager instance, and copying register field values and a work sequence of the at least one domain power manager component to register field values and a work sequence of the corresponding domain power manager instance, respectively.

[0026] Preferably, the codeless power management controller design method includes the steps of setting a number of domain groups and a number of power domains connected to each domain group for the root power manager instance.

[0027] More preferably, in the codeless power management controller design method, the memory storage space allocated to the domain power manager instance is determined based on the number of domain groups and the number of power domains included in the domain group having the domain power manager instance.

[0028] Preferably, the codeless power management controller design method includes the steps of respectively generating power management interface instances connected to the domain power manager instances through P-links corresponding to the at least one domain power manager instance.

[0029] Preferably, the codeless power management controller design method includes the steps of generating at least one power instance constituting at least one power manager component of the root power manager component and the at least one type of domain power manager component based on at least one power component, generating a first instruction instance based on at least one instruction component, determining a target power instance of the first instruction instance and setting a value in the at least one power instance, and generating a code including an instruction, a register address, and data based on the first instruction instance and the target power instance and the value.

[0030] More preferably, the codeless power management controller design method comprises the steps of generating a second instruction instance based on at least one instruction component; setting a target power instance and a value of the second instruction instance in at least one power instance; and setting an execution order of the first instruction instance and the second instruction instance.

[0031] More preferably, the at least one power component is at least one of a reset component, an isolation component, a switch control component, a hold component, an automatic power management component, a reference clock gating component, a memory component, a handshake component, a clock link component, a P-channel handshake component, a user-defined output component, and a user-defined input component.

[0032] More preferably, the at least one power component is at least one of a notification register generation component, a timeout register generation component, an upper layer information transfer register generation component, an internal register storage component, an internal register control interrupt generation component, an external input control interrupt generation component, a timer generation component, and a domain power manager connection component.

[0033] More preferably, the at least one instruction component is at least one of a write component for writing a specific value in a specific register field, an input wait component for waiting for a specific value to be input to a specific register field, a wait component for waiting for a specified time, a condition component for branching according to a condition, a move component for moving to a specific location, and a call component capable of moving to a specific location and restoring.

[0034] A computer program stored in a computer readable medium is provided for executing the method of an embodiment of the present application in a computer.

[0035] In the embodiments of the present application, a hardware code corresponding to a power management controller, i.e., a register transfer level (RTL) code, can be automatically derived to effectively improve the efficiency of design work.

[0036] In the embodiments of the present application, a hardware code corresponding to a power management controller, i.e., a register transfer level (RTL) code, can be automatically derived to effectively improve the efficiency of design work.

[0037] In the embodiments of the present application, a hardware code corresponding to a power management controller, i.e., a register transfer level (RTL) code, can be automatically derived to effectively improve the efficiency of design work.

[0038] In the embodiments of the present application, a hardware code corresponding to a power management controller, i.e., a register transfer level (RTL) code, can be automatically derived to effectively improve the efficiency of design work.

[0039] Effects of the present application are not limited to the above-mentioned effects, and other effects not mentioned above will become apparent to those skilled in the art to which the present application pertains (hereinafter referred to as "the ordinary skilled person") from the description of the claims. BRIEF DESCRIPTION OF DRAWINGS

[0040] Embodiments of the present application will be described with reference to the accompanying drawings, in which like reference numerals denote like elements, but the present application is not limited thereto.

[0041] Figure 1 A block diagram of a system-on-chip including a general power management controller.

[0042] Figure 2 A block diagram of a domain power manager. Figure 1

[0043] Figure 3 A diagram showing a codeless power management controller design system of the present application.

[0044] Figure 4 An example diagram showing a display screen of a codeless power management controller design system of the present application.

[0045] Figure 5 An example diagram showing a power management controller (PMC) displayed in a design window.

[0046] Figure 6 An example diagram showing a root power manager component displayed in a design window.

[0047] Figure 7 An example diagram showing a domain power manager component displayed in a design window.

[0048] Figure 8 An example diagram showing a power manager component work sequence displayed in a design window.

[0049] Figure 9 An example diagram showing a target power instance setting screen of an arbitrary one instruction instance.

[0050] Figure 10 A workflow diagram showing a codeless power management controller design method of the present application.

[0051] Figure 11 An exemplary computing device for performing the described methods and / or embodiments, etc.

[0052] Explanation of reference numerals

[0053] 310: screen window processing section 311: command window processing section​

[0054] 312: content window processing section 313: design window processing section

[0055] 314: setting window processing section 320: design processing section

[0056] 321: power instance management section 322: instruction instance management section

[0057] 323: power manager instance management section 324: memory allocation section

[0058] 325: register setting section 330: data repository

[0059] 331: power component repository 332: instruction component repository

[0060] 333: power manager component repository 334: power management controller repository

[0061] 335: code logic repository 340: hardware code processing section

[0062] 341: power element code generation section 342: register code generation section

[0063] 343: port and connection code generation section 344: sequence generation section

[0064] 410: command window 420: component window

[0065] 430: content window 440: design window

[0066] 450: setting window DETAILED DESCRIPTION

[0067] Hereinafter, specific contents for implementing the present application will be explained in detail with reference to the accompanying drawings. Only in the following explanation, when there is a concern that the gist of the present application is unnecessarily confused, specific explanation about known functions or structures will be omitted.

[0068] In the drawings, the same or corresponding structural elements are given the same reference numerals. Also, in explaining the following embodiments, repeated explanation about the same or corresponding structural elements can be omitted. However, even if the explanation about the structural elements is omitted, it does not mean that such structural elements are not included in any of the embodiments.

[0069] Advantages, features and methods of realizing these of the embodiments described in the present specification will be explained with reference to the accompanying drawings, and the embodiments will be explained in more detail. Figure 1The present application will become more apparent by describing in detail embodiments thereof with reference to the attached drawings. The present application is not limited to the following disclosed embodiments, but can be embodied in various different forms, and the present embodiments are provided in order to completely inform those skilled in the art of the scope of the present application.

[0070] The terms used in the present specification are simply explained, and the disclosed embodiments are specifically described. The terms used in the present specification are considered in terms of functions in the present application and are selected, as far as possible, from general terms which are widely used at present, and can be changed in accordance with the intention of those skilled in the art, customs, or appearance of new technologies, etc. Also, in certain cases, there is an intention of arbitrarily selecting a term by the applicant, in which case the meaning is to be detailed in the corresponding description part of the disclosure. Therefore, the terms used in the present application are not by the simple names of the terms, but are defined based on the meanings of the terms and the overall contents of the present application.

[0071] The singular expression in the present specification includes the plural expression, unless clearly specified as the singular in the context. Also, the plural expression includes the singular expression, unless clearly specified as the negative in the context. Throughout the specification, when a part includes a structural element, unless there is a specific description against it, it means that other structural elements are also included, not that other structural elements are excluded.

[0072] In the present application, the terms such as "include", "comprise" or the like can mean the presence of characteristics, steps, actions, elements and / or structural elements, and such terms do not exclude the addition of more than one other features, steps, actions, elements, structural elements and / or combinations thereof.

[0073] In the present application, when a specific structural element is referred to as "combined", "comprised", "connected", "associated" or "reacted" with other structural elements, the specific structural element can be directly combined, comprised, connected and / or associated or reacted with the other structural elements, but is not limited thereto. For example, there can be at least one intermediate structural element between the specific structural element and the other structural element. Also, in the present application, "and / or" can include a combination of each of the listed items or at least a part of at least one item.

[0074] In the present application, the terms such as "first", "second", etc. are used to distinguish a specific structural element from other structural elements, and the structural elements are not limited to such terms. For example, the "first" structural element can be used to mean an element of the same or similar form as the "second" structural element.

[0075] In various embodiments, a "power component" can be a tool for designing a power manager component, i.e., a domain power manager component and a root power manager component. A power component that can be used to design a domain power manager component can include a reset component, an isolation component, a switch control component, a hold component, an Automatic Power Manager (APM) component, a Reference Clock Gating component, a memory component, a handshake component, a clock link component, a P-channel handshake component, a user-defined output component, a user-defined input component, etc. A power component that can be used to design a root power manager component can include a notification register generation component, a TIMEOUT register generation component, an upper layer information transfer register generation component, an internal register storage component, an internal register control interrupt generation component, an external input control interrupt generation component, a timer generation component, a domain power manager connection component, etc.

[0076] In various embodiments, a "power instance" as a power component included in a power manager component, can be a power component added in a design window by a user's operation. The characteristics of a corresponding power manager component can be determined by a plurality of power instances included in the power manager component. If a user drags and drops (Drag & Drop) any power component icon of a power component window to a design window area, a power instance corresponding to the corresponding power component can be generated. If a power instance is generated, a register of the corresponding power instance can be automatically generated. The field values of the register constituting each power instance generated can be pre-set, or can be changed by a user's input. A domain power manager and a root power manager can include a plurality of power instances of each power component. A power instance generated based on a reset component is referred to as a reset instance, a power instance generated based on an isolation component is referred to as an isolation instance, a power instance generated based on a switch control component is referred to as a switch control instance, and a power instance generated based on a hold component is referred to as a hold instance. In addition, individual power instances can be generated based on each power component. If a power instance is generated, the register field values assigned to the corresponding power instance can be automatically assigned. Also, a hardware code can be generated based on the register field values of the power instance.

[0077] In various embodiments, an "instruction component" is a tool that can be used for a work sequence of a domain power manager and a root power manager. The instruction component can include a write (WRITE) component for writing a specific value to a specific register field, a read wait (READ WAIT) component for waiting for a specific value to be input to a specific register field, a wait (WAIT) component for waiting for a specified time, a conditional (IF) component for branching according to a condition, a go to (GOTO) component for moving to a specific location, a call (CALL) component capable of moving to a specific location and restoring, a label component, a start component, and an end component.

[0078] In various embodiments, an "instruction instance" can be an instruction component added to a design window by a user's operation. Each instruction instance can be set with a power instance and a value. An instruction code is determined according to the instruction instance, a register field address is determined according to the power instance, and data is determined according to the value. A sequence formed by the instruction and the register field address and data thus determined can be stored in a memory such as a read only memory (ROM) and a random access memory (RAM).

[0079] In the present invention, a "power manager component" can be a tool that can be used in a design of a power management controller. The power manager component can include at least one domain power manager component and at least one root power manager component. Each of the domain power manager component and the root power manager component independently includes at least one power instance and can be designed for a work sequence of the at least one power instance. A user can design the domain power manager component and the root power manager component using the power component and the instruction component, and design the power management controller using the designed domain power manager component and the root power manager component.

[0080] In various embodiments, a "power manager instance" can be a power manager component added to a design window by a user's operation. The user can generate a power manager instance icon in the design window, and can match a corresponding power manager instance to one of the pre-designed power manager components. As described above, if the power manager instance is matched to one of the power manager components, the register field value and the read only memory / random access memory work sequence of the corresponding power manager component can be copied to the power manager instance.

[0081] The power component and the instruction component are materials for designing individual power manager components, and the power management controller can be designed by combining the designed power manager components.

[0082] Figure 1 A block diagram of a system on chip including a general power management controller is shown. The system on chip device 100 is a product and a system that is completely driven on one integrated circuit, and can be implemented as a chip or a module or a system, etc.

[0083] The system on chip device 100 includes a power management controller (PMC), a central processing unit 120 (CPU) controlling the power management controller 110 by software, at least one power domain 130, 140, 150 (PD). The central processing unit 120 can control the power management controller 110 which is one power domain constituting the system on chip device.

[0084] The power management controller 110 can provide power up / down sequences corresponding to the at least one power domain 130, 140, 150, respectively. Each power domain 130, 140, 150 can process the power up / down sequences to be in a power up state or a power down state. The system on chip device includes at least one power management controller 110.

[0085] The power domains 130, 140, 150 can include a core domain having the central processing unit 120, a memory domain including a memory subsystem such as a main memory or a cache memory, a graphic and video domain including a multimedia device such as a graphic processing device or a video encoder / decoder device, and an input / output domain including an input / output interface device for communication with the outside, etc. Each power domain can include a lower sub power domain.

[0086] The power management controller 110 includes at least one domain power manager 112, 113, 114 (PMD) corresponding to each power domain 130, 140, 150, controlling the corresponding power domain 130, 140, 150, a root power manager 111 (PMR) for managing the at least one power manager 112, 113, 114, a memory 115 storing programs for operating the root power manager 111 and the at least one domain power manager 112, 113, 114, and at least one power management interface 117, 118, 119 (PMIF) provided between the at least one domain power manager 112, 113, 114 and the power domain 130, 140, 150.

[0087] The root power manager 111, the domain power managers 112, 113, 114, and the memory 115 are disposed in an always-on (AON) region, and the domain power managers 112, 113, 114 corresponding to each other are connected to the power management interfaces 117, 118, 119 through P-links. The power management interfaces 117, 118, 119 are disposed on the sides of the power domains 130, 140, 150.

[0088] The at least one domain power manager 112, 113, 114, the root power manager 111, and the memory 115 are connected to each other through an internal bus 116. Programs stored in the memory 115 include instructions (Instruction) and data.

[0089] The root power manager 111 can receive a system power-up / power-down command from the central processor 120. The root power manager 111, upon startup, can operate the at least one domain power manager 112, 113, 114 to perform a startup of the system-on-chip device 100 based on a read-only memory sequence (instructions and data for performing a startup). Also, if a system power-up / power-down command is received from the central processor 120, the at least one domain power manager 112, 113, 114 can operate to turn on / turn off the system-on-chip device 100 or a subsystem formed of a plurality of power domains based on a random access memory sequence (instructions and data for performing a command).

[0090] If a domain power-up / power-down command for controlling power of a power domain is received from the central processor 120, the at least one domain power manager 112, 113, 114 can perform a power-up / power-down sequence control in the corresponding power domain based on a random access memory sequence (instructions and data for performing a command).

[0091] The first domain power manager 112 outputs a power control signal to the first power domain 130 and performs a power-up / power-down sequence, the second domain power manager 113 outputs a power control signal to the second power domain 140 and performs a power-up / power-down sequence, and the third domain power manager 114 outputs a power control signal to the third power domain 150 and performs a power-up / power-down sequence. That is, each power domain 130, 140, 150 is matched with a separate domain power manager 112, 113, 114 to perform power control of each power domain 130, 140, 150 in parallel, and thus efficient and rapid processing can be achieved.

[0092] The memory 115 stores instructions and data for the root power manager 111 to execute system power-up / power-down commands in binary code, and stores instructions and data for each domain power manager 112, 113, 114 to execute domain power-up / power-down commands in binary code. The memory 115 can include read-only memory and random access memory.

[0093] Figure 1 An on-chip system device composed of 3 power domains and 3 domain power managers is exemplified, but the number of power domains can be designed in different numbers according to the complexity of the on-chip system device, and the number of domain power managers can be changed according to the number of power domains.

[0094] Figure 2 For Figure 1 a configuration diagram of the domain power manager 210.

[0095] The domain power manager 210 transmits power control signals to the power domains through the power management interface 220 and performs power-up / power-down sequences of the power domains. Accordingly, the power domains can be changed from a power-up state to a power-down state or from a power-down state to a power-up state. The power control signals for performing the power-up / power-down sequences can include a reset signal (RESET), an isolation signal (ISOLATION), a switch control signal (SWITCH CONTROL), a retention signal (RETENTION), etc. Such power control signals can be added / removed / changed according to the form of the power domains.

[0096] Figure 2 The domain power manager 210 of Figure 1 one of the first domain power manager 112, the second domain power manager 113, and the third domain power manager 114 of Figure 2 The power management interface 220 of Figure 1 one of the power management interfaces 117, 118, 119 of When designing the domain power manager, binary code storage of a program including instructions and data that the domain power manager 210 needs to execute can be in the memory 115.

[0097] The central processor 120 outputs domain power-up / power-down commands for controlling power of the power domains to the domain power manager 210. If receiving the domain power-up / power-down commands, the domain power manager 210 transmits power control signals to the corresponding power domains through the power management interface 220 and performs power-up / power-down sequences. Thereby, the corresponding power domains are changed to a power-up state or a power-down state.

[0098] The domain power manager 210 includes a processing unit 211 receiving a domain power up / down command related to power control of a power domain from the central processing unit 120, accessing a memory 115 storing an instruction for executing a corresponding command to execute the instruction stored in the memory 115, and a register bank 212 transmitting a power control signal to the power domain by changing at least one field value through the processing unit 211. The processing unit 211 includes a plurality of power elements each of which can correspond to one of the power control signals.

[0099] The processing unit 211 can include at least one of a power element for transmitting a reset signal to the power domain, a power element for transmitting an isolation signal to the power domain, a power element for transmitting a switch control signal to the power domain, a power element for transmitting a hold signal to the power domain, a power element automatically executing power up / down by a trigger signal of hardware, a power element for controlling a reference clock supplied to the power domain, a power element for generating a power control signal in a memory of the power domain, a power element for generating a handshake control signal with the power domain, a power element for generating a link control signal with a clock management unit, a power element for generating a P-channel handshake control signal with the power domain, a power element for generating a user-defined output signal in the power domain, and a power element for generating a user-defined input signal in the power domain. The power elements constituting such a processing unit 211 can generate a power instance in the design system of the present application and be constituted based on the hardware code generated based on the power instance.

[0100] The register bank 212 includes a plurality of register fields corresponding to the plurality of power elements constituting the processing unit 211. The power elements responsible for the transmission and reception of the power domain and the power control signal can change the value of the corresponding register field, and the plurality of values recorded in the corresponding register field will be transmitted to the power domain as the corresponding power control signal. For example, the power element for transmitting a reset signal can change the value of the register field corresponding to the reset signal of the register bank 212 to 0 or 1, in which case 0 or 1 is transmitted to the reset port of the power domain 220. Also, the power element for transmitting an isolation signal can change the value of the register field corresponding to the isolation signal of the register bank 212 to 0 or 1, in which case 0 or 1 is transmitted to the isolation port of the power domain. Similarly, the power elements corresponding to the switch control signal or the hold signal can change the value of the register field corresponding to the switch control signal or the hold signal of the register bank 212 to 0 or 1, respectively, in which case 0 or 1 is transmitted to the switch control port or the hold port of the power domain, respectively. For the operation of such a processing unit, the memory 115 can further store instructions and data and register field addresses as execution targets of the corresponding instructions, which can be referred to as a read-only memory / random access memory sequence.

[0101] The instructions stored in the memory 115 include a write instruction to write a specific register field value of the register bank 212 to 0 and a write instruction to write a specific field value of the register bank 212 to 1. The processing unit 211 executes the corresponding instructions to change the specific register field value of the register bank 212 to 0 or 1. Accordingly, the value of the corresponding power control signal is changed to 0 or 1 and is transmitted to the power domain.

[0102] The power management interface 220 can receive a signal from the power domain and transmit it to at least one of the processing unit 211 and the register bank 212. There are a plurality of signals formed by a handshake in the power control signal. For example, after transmitting a power switch enable signal, it is necessary to wait until a corresponding feedback signal is received. In this case, the feedback signal output from the power domain will be recorded as a specific register field value of the register bank 212 through the power management interface 220, and the processing unit 211 waits until the corresponding register field value is recorded as a corresponding specific value. For this, the instructions stored in the memory 115 can include an instruction to wait until a specific register field value of the register bank 212 becomes 0, and an instruction to wait until a specific register field value of the register bank 212 becomes 1.

[0103] Also, in the power control signal, after transmitting one signal, the next operation can also be performed after waiting for more than a specified time. For example, when the power domain is reset released, the power domain is reset and waits until normal operation is performed. For this, the instructions stored in the memory 115 can include an instruction to wait for a specific period of time, and the waiting time information can also be stored in a specific register field of the register bank 212, and a constant value input by a user can also be stored in an internal register of the processing unit.

[0104] Also, the instructions stored in the memory 115 can include an instruction to record an internal register value of the processing unit 211 as a specific register field of the register bank 212, an instruction to record a specific register field value of the register bank 212 in an internal register of the processing unit 211, and an instruction to record a constant value input by a user in an internal register of the processing unit 211. Also, the instructions stored in the memory 115 can include an instruction to determine the execution order of a plurality of instructions stored in the memory 115, and such an instruction can include an instruction to jump to a specific address, an instruction to return to a previous address, and an instruction to move to a specific address according to an instruction execution result, etc.

[0105] Similar to the domain power manager, the memory 115 can store a program including instructions and data that the root power manager 111 needs to execute. The central processor 120 can change and store the program including the instructions and data stored in the memory 115. The central processor 120 can output a system power up / down command to the root power manager 111.

[0106] The memory 115 stores instructions that the root power manager 111 executes according to the system power up / down command, and if the system power up / down command is received from the central processor 120, the root power manager 111 executes the instructions stored in the memory 115 and transmits a power control signal to at least one domain power manager 112, 113, 114 to control power.

[0107] As described above, each domain power manager 112, 113, 114 controls power of the power domain 130, 140, 150 through the power management interface 117, 118, 119, and the root power manager 111 controls the plurality of domain power managers 112, 113, 114, and thus, a power management controller 110 for controlling power of a plurality of power domains constituting a system on chip needs to be designed.

[0108] Figure 3 To show a diagram of a codeless power management controller design system of the present application, Figure 4 To show a diagram of a display screen of a codeless power management controller design system of the present application. The codeless power management controller design system of the present application can be implemented as a computer system.

[0109] The power management controller design system of the present application can be a system for designing Figure 1 a power management controller 110.

[0110] As Figure 3As shown, the power management controller design system of the present invention may include: a screen window processing unit 310, which detects user input and outputs the processing result of the user output on a display screen; a design processing unit 320, which generates at least one power manager instance constituting the power management controller based on power manager component information, sets the connection between the at least one power manager instance, allocates memory according to the number of at least one power manager instance, and sets registers for defining the functions of the at least one power manager instance; a data storage unit 330, which stores hardware code logic for generating hardware code of the designed power management controller and software code logic for generating the working sequence of the designed power management controller; and a hardware code processing unit 340, which generates hardware code and register code of the power manager instance based on the designed power manager instance information, generates port and connection code for the connection between power manager instances, and stores the working sequence of the power manager instance in memory.

[0111] like Figure 4 As shown, the display screen of the power management controller design system of the present invention may include: a command window 410 for inputting user commands; a component window 420 for displaying power manager component icons; a content window 430 for providing an environment for adding, deleting, and changing the list of power management controllers under design; displaying the power manager component list and the list of power manager instances included in the power management controller under design; a design window 440 for displaying a diagram of the power management controller under design and providing an environment for adding, deleting, and changing power manager instances; and a setting window 450 for providing an environment for changing the setting values ​​of the power manager instance selected from the design window 440.

[0112] In this invention, a power manager component can be designed before designing the power management controller. For this purpose, the design processing unit 320 can use the power component to generate power instances included in the power manager component, and can use the instruction component to design the working sequence of the power instances. Furthermore, the component window can display power component icons and instruction component icons, and the design window 440 can provide an environment for adding, deleting, and changing at least one power instance constituting the power manager component under design, and an environment for adding, deleting, and changing instruction instances for designing the working sequence of the power instances in the power manager component.

[0113] The power manager components may include the root power manager component and the domain power manager component.

[0114] The command window 410 can include a CHECK button to receive an instruction to check for errors of the power management controller and power manager component and power instance being designed, an UNCHECK button to receive an instruction to inactivate a check result, a SAVE button to receive an instruction to store the power management controller being designed, the power manager component being designed, and the power instance being designed, which are displayed in the design window 440, and a GENRTL button to receive an instruction to generate hardware code of the power manager instance displayed in the design window 440.

[0115] The component window 420 can display a list of power component icons that can be used in the design of the power manager component or a list of instruction component icons or a list of power manager components that can be used in the design of the power management controller.

[0116] When the power manager component to be designed is a domain power manager, the power component can include a reset component to transmit a reset signal to a power domain, an isolation component to transmit an isolation signal to the power domain, a switch control component to transmit a switch control signal to the power domain, a hold component to transmit a hold signal to the power domain, an automatic power manager component to automatically perform power up / down by a trigger signal of hardware, a reference clock gating component to control a reference clock supplied to the power domain, a memory component to generate a power control signal in a memory of the power domain, a handshake component to generate a handshake control signal with the power domain, a clock link component to generate a link control signal with a clock management unit, a P-channel handshake component to generate a P-channel handshake control signal with the power domain, a user defined output component to generate a user defined output signal in the power domain, and a user defined input component to generate a user defined input signal in the power domain, etc.

[0117] When the power manager component to be designed is a root power manager, the power component can include a component to generate a register used for an INFORM purpose in software, a component to generate a register used for a TIMEOUT purpose in software, a component to generate a register used for information transfer between upper layer software and the root power manager, a component to store a specific signal value input to the root power manager in an internal register of the root power manager, a component to generate an interrupt by control of the internal register of the root power manager, a component to generate an interrupt by an external input input to an input port of the root power manager, a component to generate an internal timer, and a component to generate a slot of a domain power manager connected to a lower layer of the root power manager, etc.

[0118] When a power management controller is designed, the power manager components can include a root power manager component and a domain power manager component, or a plurality of types of root power manager components and a plurality of types of domain power manager components. The meaning of the types of any two power manager components being different can be that the power instances or the working sequences of the power instances that constitute the power manager components are different.

[0119] The instruction components can include a WRITE component for writing a specific value in a specific register field, a READ WAIT component for waiting for a specific value to be input to a specific register field, a WAIT component for waiting for a specified time, an IF component for branching according to a condition, a GOTO component for moving to a specific location, and a CALL component capable of moving to a specific location and restoring, etc. Meanwhile, the auxiliary instruction components can include a label component, a start component, and an end component. The instruction components and the auxiliary instruction components can have inherent border shapes. For example, the WRITE component and the READ WAIT component can have rectangular borders, the IF component can have a prismatic border, and the label component can have an arrow-shaped border. The label component can be used in connection with the instruction components, and any two or more instruction components that are spaced apart from each other can be virtually connected. The design window can use at least two label components, each of which can be provided with a name and a color for identification.

[0120] The design window 440 displays a diagram of the power management controller being designed and provides addition, deletion, and change of the power manager instances.

[0121] Figure 5 An example diagram of a power management controller (PMC) displayed in the design window is shown. The power management controller can be composed of one root power manager instance (PMR) and eleven domain power manager instances (MFC, ISP, ISP_CORE0 to ISP_CORE3, XPU_CORE0 to XPU_CORE4), but is not limited thereto.

[0122] The user can set the number of domain groups and the number of power domains per domain group for the root power manager instance displayed in the design window. If the number of domain groups and the number of power domains per group are set, output ports corresponding to the total number of power domains can be generated. Figure 5 The power management controller of FIG. 4B shows an example in which the eleven domain power manager instances are divided into three domain groups. The first domain group can be formed of two power domains, the second domain group can be formed of four power domains, and the third domain group can be formed of five power domains. The root power manager instance can generate eleven output ports.

[0123] The GRP0_PMD0~GRP0_PMD1 ports of the root power manager instance can be connected to the domain power manager instances (MFC, ISP) of the first group. The GRP2_PMD0~GRP2_PMD4 ports of the root power manager instance can be connected to the domain power manager instances (XPU_CORE0~XPU_CORE4) of the third group. In the figure, MFC, ISP, ISP_CORE0~ISP_CORE3, XPU_CORE0~XPU_CORE4 can be the names of the domain power manager instances, and MFC, ISP, CORE can be other types of domain power manager components. For example, after designing a MFC type domain power manager component, an ISP type domain power manager component, and a CORE type domain power manager component, respectively, a MFC type domain power manager instance, an ISP type domain power manager instance, and nine CORE type domain power manager instances can be combined to design a power management controller, but are not limited thereto.

[0124] Also, the design window 440 displays the power instances of the power manager component being designed, and provides an environment for adding, deleting, and changing the power instances constituting the power manager component being designed.

[0125] Figure 6 An example diagram showing the graph of the root power manager component displayed in the design window is shown. The root power manager component is composed of eight power instances, such as one notification instance (INFORM_0), one notification instance (INFORM_1), one notification instance (INFORM_2), one notification instance (INFORM_3), one timeout instance (TIMEOUT_VDD), one timer instance (TIMER_GRP0), one slot generation (PMDDGPR) instance (PMDGRP_GRP0), and one isolation (ISOEN) instance (ISOEN_PMR), but is not limited thereto.

[0126] Figure 7 An example diagram showing the graph of the domain power manager component displayed in the design window is shown. The domain power manager component is composed of seven power instances, such as one switch control (PSW) instance (PSW_AA), one reset instance (RESET_AA), one isolation (ISOEN) instance (ISOEN_AA), a memory (MEM) instance (MEM_AA), a handshake (OTP) instance (OTP_AA), a clock link (CLINK) instance (CLINK_AA), and a clock reset (RESET_CMU) instance (RESET_CMU_AA), but is not limited thereto.

[0127] After adding power instances of the power manager component, design window 440 can display a working sequence diagram so that the connection relationships between instruction instances can be set.

[0128] Figure 8 This is an example diagram illustrating the working sequence of the power manager component displayed in the design window. Figure 8 In the workflow, two power instances (RESET, NMI) can be set through the same process. Two start instances (START_RESET, START_NMI) can be connected to the call instance via a tag instance (RESETSEQ). The tag instance, connected to the backend of the call instance, is then linked to other separated instruction instances. Figure 8 The example diagram uses call instances, write instances, wait instances, and move instances, but is not limited to these.

[0129] Each instruction instance can be configured with a power instance and value that serves as the target for instruction execution. Figure 9 This is an example of a screen showing the target power instance settings for any given command instance. If a command instance is added, all power instances included in the corresponding power manager component are displayed, allowing selection of one power instance from among them. Figure 9 In this context, PSW_AA to CLINK_AA are the names of the power instances that constitute the power manager component. Users can set one of the multiple power instances in each instruction instance.

[0130] The connections between instruction instances can be displayed using arrows connecting them, and these connections determine the execution order of multiple instruction instances. This invention can represent and design the working sequence of the power manager component in the form of a flowchart.

[0131] If the user moves any power component of the component window 420 to the design window 440 through a drag-and-drop operation, a power instance corresponding to the corresponding power manager component can be added, and if the power instance is generated, a new power instance list and register information of the new power instance can be added by layer in the content window 430. Also, if the user moves any power manager component of the component window 420 to the design window 440 through a drag-and-drop operation or matches the power manager instance icon with any one of the power manager components after generating the power manager instance icon in the design window 440, a power manager instance corresponding to the corresponding power manager component can be generated, in which case the register field value and the read-only memory / random access memory operation sequence of the power manager component can be copied to the register field value and the read-only memory / random access memory operation sequence of the corresponding power manager instance, respectively.

[0132] The setting window 450 displays a setting value change environment of the power instance selected from the design window 440, and provides a selection and change environment of the power instance related to the instruction instance selected from the design window 440, a value input environment.

[0133] The screen window processing part 310 can include a command window processing part 311 that displays buttons for receiving user instructions in the command window 410, detects input of each button of the command window 410 to perform an operation corresponding to the input button, a content window processing part 312 that displays a list of power management controllers being designed, a list of power manager instances included in each power management controller being designed, a list of power manager components, and a list of power instances and register information included in each power manager component by layer in the content window 430, detects user input in the content window 430 to perform an operation corresponding to the user input, a design window processing part 313 that displays a graph of the power management controller being designed and a graph of the power manager component being designed selected by the user in the design window 440, detects user input in the design window 440 to perform an operation corresponding to the user input, and a setting window processing part 314 that displays setting information of the power instance and the power manager instance selected by the user or setting information of the instruction instance selected by the user in the setting window 450, detects user input in the setting window 450 to perform an operation corresponding to the user input.

[0134] If the check button is selected, the command window processing section 311 checks and displays the error of the drawing of the power management controller being designed, the power manager instance constituting the power management controller being designed, and the kind of the plurality of power instances included in the power manager instance and the set value thereof, and the like. If the no check button is selected, the error portion of the drawing of the power management controller being designed is restored to the original state and displayed. If the save button is selected, the power management controller being designed and the lower structure elements thereof displayed in the design window 440 are stored in the data storage 330. If the GENRTL button is selected, the hardware code of the power management controller being designed displayed in the design window 440 and the binary code of the work sequence are generated.

[0135] The content window processing section 312 displays the list of the power management controller being designed, the list of the power manager instance included in each power management controller being designed, and the list of the power instance included in each power manager instance in the content window 430, and provides the addition, deletion, and change environment. The content window processing section 312 displays the list of the power manager instance included in the corresponding power management controller under each power management controller being designed, and displays the list of the power instance included in the corresponding power manager instance and the register information of each power instance by layer under each power manager instance. Also, the content window processing section 312 can display the power manager component list information in the content window 430. The power management controller can include at least one root power manager instance and at least one domain power manager instance connected to the root power manager instance.

[0136] The user can add, delete, change the name, and the like of the power management controller in the content window 430, and the addition, deletion, name change of the power management controller list can be performed in the power management controller storage 334 in correspondence with the user input. If the user changes the name of the power management controller, the content window processing section 312 can change the name of the corresponding power management controller, the name of the power manager instance of the lower layer of the corresponding power management controller, the name of the power instance of the lower layer of the corresponding power manager instance, and the register name of the corresponding power instance.

[0137] The design window processing section 313 displays the drawing of the power management controller being designed in the design window 440, and provides the addition, deletion, change environment of the power manager instance constituting the power management controller being designed. Also, the drawing of each power management component being designed is displayed, and the addition, deletion, change environment of the power instance constituting the power management component being designed is provided.

[0138] When the power manager component is designed, if the user performs an operation of adding any power component of the component window 420 to the design window 440, the design window processing part 313 detects it and performs a power instance addition job. Meanwhile, if the user performs an operation of adding any instruction component of the component window 420 to the design window 440, the design window processing part 313 detects it and performs an instruction instance addition job. When the power management controller is designed, if the user performs an operation of adding a power manager component to the design window 440, the design window processing part 313 detects it and performs a power manager instance addition job.

[0139] The setting window processing part 314 displays the setting information of the power instance selected by the user in the setting window 450, and detects the user input in the setting window 450 to perform an operation corresponding to the user input. Also, the setting information of the instruction instance selected by the user is displayed, and the user input in the setting window 450 is detected to perform an operation corresponding to the user input.

[0140] The data repository 330 can include a power component repository 331 storing power component information, an instruction component repository 332 storing instruction component information, a power manager component repository 333 storing power manager component information, a power management controller repository 334 storing a list of power management controllers being designed, a list of power manager instances of each power management controller being designed, a list of power instances of each power manager instance, and register information corresponding to each power instance and an operation sequence of each power manager instance, and a code logic storage 335 storing hardware code logic for generating hardware code based on the power manager instances and register information constituting the designed power management controller.

[0141] The power component information stored in the component repository 331 can include an address range allocated to each power component, a memory offset size of each power component. The power component information specifies a register address and a field value of the power instance generated based on the corresponding power component. The maximum number information of the power instance of each power component can be calculated using the address range allocated to each power component and the register offset size of the individual power component. The address range allocated to each power component, the register offset size of the individual power component, and the setting field information of each power component can each be differently set.

[0142] The power components can include at least one of a reset component, an isolation component, a switch control component, a hold component, an Automatic Power Manager component, a Reference Clock Gating component, a memory component, a handshake component, a clock link component, a P-channel handshake component, a user defined output component, and a user defined input component.

[0143] Also, the power components can include at least one of a component for generating a register used in software to inform a usage, a component for generating a register used in software to time out a usage, a component for generating a register used between upper software and a root power manager to transfer information, a component for storing a specific signal value input to the root power manager in an internal register of the root power manager, a component for generating an interrupt by control of the internal register of the root power manager, a component for generating an interrupt by an external input input to an input port of the root power manager, a component for generating an internal timer, and a component for generating a slot of a lower connected domain power manager of the root power manager.

[0144] The instruction components stored in the instruction component repository 332 can include a write component for writing a specific value in a specific register field, an input wait component for waiting for a specific value to be input to a specific register field, a wait component for waiting for a prescribed time, a condition component for branching according to a condition, a move component for moving to a specific location, and a call component capable of moving to a specific location and restoring, etc. Meanwhile, the auxiliary instruction components can include a label component, a start component, and an end component. The instruction components and the auxiliary instruction components can have an inherent border shape. For example, the write component and the input wait component can have a rectangular border, the condition can have a prismatic border, and the label component can have an arrow-shaped border. The label component can be used in connection with the instruction components, and any two or more instruction components spaced apart from each other can be virtually connected. The label component can be provided with a name and a color for identification.

[0145] The power manager component repository 333 can store power manager components for designing a power management controller. The power manager components can include root power manager components and domain power manager components. Each power manager component can include at least one power instance, and can include a work sequence of the power instance. The work sequence of the power instance can be designed based on an instruction component, and can include a power instance and a value as a target of each instruction instance. That is, when the instruction component is a write component, it is necessary to set which power instance (e.g., a reset instance or an isolation instance, etc.) writes which value (data), which power instance is a target power instance, and which value is a value. In the present invention, each power instance can determine a register field, and thus, if a target power instance of an instruction instance is determined, a field address of a corresponding power instance can be determined.

[0146] The instruction instance can be at least one of a write instance based on a write component, an input wait instance based on an input wait component, a wait instance based on a wait component, a condition instance based on a condition component, a move instance based on a move component, and a call instance based on a call component. The target power instance can be one of at least one power instance constituting the power manager component. The value can be decimal or hexadecimal.

[0147] The power management controller repository 334 can store, by layer, a list of power manager instances included in the power management controller being designed, a list of power instances included in each power manager instance, register information of each power instance, and a work sequence of each power manager instance, etc.

[0148] The code logic repository 335 stores hardware code logic for generating hardware code based on the power manager instances constituting the designed power management controller and the plurality of power instances and register information of the lower layer thereof, and stores software code logic for generating binary code of instructions and register addresses and data for driving power elements generated through the power manager instances based on the designed instruction instances.

[0149] The design processing part 320 can include a power instance management part 321 generating and storing at least one power instance constituting a power manager component in a power manager component storage 333, an instruction instance management part 322 storing at least one instruction instance and an execution order of any two instruction instances and setting a target power instance and a value of each instruction instance and storing in the power manager component storage 333, a power manager instance management part 323 generating at least one power manager instance constituting a power management controller based on the power manager component generated through the power instance management part 321 and the instruction instance management part 322, setting a connection between the at least one power manager instance and storing in a power management controller storage 334, a memory allocation part 324 dividing a memory based on the number of power manager instances included in the power management controller and allocating a memory area to each power manager instance, and a register setting part 325 setting a field value of a register defining a power instance function for each power manager instance.

[0150] If the user adds any power component of the component window 420 in the design window 440 in the process of designing the power manager component, the power instance management part 321 can be executed and a new power instance can be generated. The name of the new power instance can include the name of the power manager component having the new power instance and power component type information of the new power instance. Also, the address of the new power instance can be set based on the existing generated power instance information of the power component type and the power component information. That is, the start address of the register of the new power instance can be determined by adding the start address of the register of the existing generated power instance and the register offset size, and the initial set value of the register field can be determined based on the register field information of the power component information. The user can add a new power instance to design the power manager component.

[0151] The instruction instance management part 323 can set a connection relationship between at least one instruction instance and the instruction instance according to the work sequence of the power manager component. Each instruction instance can include a target power instance and a value. The instruction instance management part 323 can add a tag instance between any two instruction instances. A pair of tag instances can be identified as the same position, and thus can be set to substantially connect two instruction instances spaced apart from each other using a pair of tag instances. Also, a start instance and an end instance can be added at the start and end positions of the work sequence to set the start and end. The user can set the work sequence of the power manager component through the instruction instance management part 323.

[0152] The user can design at least one type of root power manager component and at least one type of domain power manager component using the power instance management unit 321 and the instruction instance management unit 322, and the designed root power manager component and domain power manager component can be stored in the power manager component storage 333. The root power manager component can set the domain group corresponding to the root power manager control and the number of power domains of each domain group. If the domain group and the number of power domains of each domain group are set, the output port of the root power manager component can be generated, and the port name can be determined based on the name of each domain group.

[0153] If at least one of at least one type of root power manager component and at least one type of domain power manager component is added in the design window 440, the power manager instance management unit 323 is executed and a power manager instance is generated. If the root power manager component is added, a root power manager instance is additionally generated, and if the domain power manager component is added, a domain power manager instance is generated, and at the same time, a power management interface instance connected to the corresponding domain power manager instance through a P-link can be automatically generated. If the power manager instance is generated, the register field value and the work sequence of the corresponding power manager component are copied to the corresponding power manager instance.

[0154] The power manager instance management unit 323 can change the number of domain groups of the root power manager instance and the number of power domains of each domain group, and thus the output port of the root power manager instance can be changed. The name of each output port can be generated based on the domain group name and the number of power domains connected to the corresponding domain group. The input port of the domain power manager instance is generated, and the output port of the root power manager instance and the input port of the domain power manager instance can be connected by user operation. Such a connection can be used to generate hardware code.

[0155] The memory allocation unit 324 can allocate a memory interval to each power manager instance based on the type and number of power manager instances constituting the power management controller. The memory can allocate an upper address storage space to the root power manager instance and a lower address storage space to the domain power manager instance. The memory allocation unit 324 can have a read-only memory allocation rule and a random access memory allocation rule based on the number of domain groups and the number of domain power managers of each domain group, and can allocate a read-only memory and a random access memory storage space to each domain power manager instance.

[0156] The register setting unit 325 can display the field name, bit position, etc. of the register field of each power instance included in each power manager instance in the design window 440 or the setting window 450, and can be changed according to user input.

[0157] The hardware code processing section 340 includes a power element code generation section 341 that generates power element codes based on the designed power manager instances and the designed power instance information, a register code generation section 342 that generates register codes corresponding to the power elements, a port and connection code generation section 343 that generates hardware codes corresponding to the ports and connections of the connections between the power manager instances, and a sequence generation section 344 that generates binary codes of the operation sequences of the power management controller.

[0158] If the GENRTL button of the command window 410 is selected, the hardware code processing section 340 can be executed. The user can select the GENRTL button to execute it in the state in which the design window 440 displays the graph of the power management controller being designed, and can execute the check button to verify in advance whether there is an error in the graph before executing the GENRTL button.

[0159] The power element code generation section 341 generates hardware codes of all the power elements constituting the power management controller according to the hardware code logic adaptation stored in the code logic storage 335 from the power instance information constituting the designed power management controller. The port type of the power element and the layer structure of the hardware module are determined according to the settings of the designed power instance.

[0160] The register code generation section 342 can generate register codes of the register bank according to the hardware code logic based on the register field values of the designed power instance, and generate ports of the register bank corresponding to the ports of the power elements.

[0161] The port and connection code generation section 343 generates hardware codes corresponding to each of the ports and connections of the power manager instances constituting the designed power management controller, connects the ports of the power elements and the ports of the register bank according to the hardware code logic, and generates corresponding hardware codes in the corresponding ports and connections.

[0162] The sequence generation section 344 generates binary codes of the operation sequences corresponding to the power manager instances constituting the power management controller based on the software code logic stored in the code logic storage 335. The operation sequence can include instructions, register addresses, and data. The instructions can be derived based on the instruction instances, the register addresses can be derived based on the target power instances, and the data can be derived based on the values.

[0163] The binary codes of the operation sequences thus derived are stored in the storage spaces of the memories allocated to each of the power manager instances by the memory allocation section 324, and the processing unit 211 can read the corresponding binary codes and execute the corresponding instructions targeting the addresses of the register bank, so that the power control signals can be transmitted to the power domain.

[0164] Figure 10To show the workflow of the codeless power management controller design method of the present application. The power management controller design method of the present application can be executed by a processor of a computer system.

[0165] The computer system includes a power manager component repository storing power manager component information and a code logic repository storing hardware code logic for generating hardware code based on a plurality of power manager instances constituting the designed power management controller and a plurality of power instances and register information thereunder.

[0166] The processor designs at least one root power manager component and at least one domain power manager component (step S1010). The root power manager component can include at least one power instance and set a work sequence. The domain power manager component can include at least one power instance and set a work sequence. The at least one domain power manager component is designed to be of different types, respectively. The root power manager component can set a number of domain groups and a number of power domains connected by domain groups.

[0167] Next, the processor generates a root power manager instance based on the root power manager component and domain power manager instances based on the at least one domain power manager component (step S1020). The root power manager instance has a copy of the register field information and the work sequence of the root power manager component, and the domain power manager instances have a copy of the register field information and the work sequence of the domain power manager components based thereon, respectively.

[0168] Next, the processor generates a power management interface instance connected through a P-link corresponding to each of the domain power manager instances (step S1030). The power management interface instance can be automatically generated by the processor even without a user operation.

[0169] Next, the processor forms a connection between an output port of the root power manager instance and an input port of the at least one domain power manager instance (step S1040).

[0170] Next, the processor allocates a memory storage space to the root power manager instance and the at least one domain power manager instance, respectively (step S1050). The memory storage space allocated to the domain power manager instances can be determined based on the number of domain groups and the number of power domains connected to each of the domain groups.

[0171] Next, the processor generates hardware code of power elements constituting the power management controller, register code, and binary code of a work sequence of the power management controller (step S1060).

[0172] Figure 11An exemplary computing device 1100 for performing the method and / or embodiments, etc. is shown. According to an embodiment, the computing device 1100 can be implemented using hardware and / or software for interacting with a user. Among other things, the computing device 1100 can include a laptop, a desktop, a workstation, a personal digital assistant, a server, a blade server, a main frame, etc., but is not limited thereto. The structural elements of the computing device 1100, the connection relationship of these, and the functions of these are exemplary, and the examples of the present application described in the specification and / or claimed in the scope of the invention are not limited thereto.

[0173] The computing device 1100 includes a processor 1110, a memory 1120, a storage device 1130, a communication device 1140, a high-speed port 1150 connected to the memory 1120 and a high-speed expansion port, and a low-speed port 1160 connected to a low-speed bus and the storage device. The structural elements 1110, 1120, 1130, 1140, 1150, and 1160 can be connected to each other using various buses, can be installed on the same main board or by other appropriate means, and can be connected and implemented. The processor 1110 can execute basic arithmetic, logic, and input / output operations, and thus can process computer program instructions. For example, the processor 1110 can process instructions stored in the memory 1120, the storage device 1130, etc. and / or instructions executed within the computing device 1100, and thus can display graphic information on an external input / output device 1170 such as a display device combined with the high-speed port 1150.

[0174] The communication device 1140 can provide a structure or function that enables the input / output device 1170 and the computing device 1100 to communicate with each other over a network, and can provide a structure or function that enables the input / output device 1170 and / or the computing device 1100 to communicate with other external devices, etc. For example, a processor of an external device can be transmitted to the computing device 1100 over a network under the control of the communication device 1140 according to a request or data generated by arbitrary program code. Conversely, a control signal or an instruction provided under the control of the processor 1110 of the computing device 1100 can be transmitted to other external devices through the communication device 1140 and the network.

[0175] Figure 11 The computing device 1100 includes one processor 1110, one memory 1120, etc. as shown in the middle, but is not limited thereto, and the computing device 1100 can be implemented using multiple memories, multiple processors, and / or multiple buses, etc. Also,Figure 11 The diagram shows the presence of a computing device 1100, but is not limited to this; multiple computing devices can interact and perform the necessary work to execute the method.

[0176] The memory 1120 can store information within the computing device 1100. According to one embodiment, the memory 1120 can be composed of volatile memory cells or multiple memory cells. Alternatively or additionally, the memory 1120 can be composed of non-volatile memory cells or multiple memory cells. Furthermore, the memory 1120 can be composed of other forms of computer-readable media such as a magnetic disk or optical disk. The memory 1120 can also store an operating system and at least one program code and / or instructions.

[0177] Storage device 1130 may be at least one high-capacity storage device for storing data for computing device 1100. For example, storage device 1130 may be a computer-readable medium including, or may include, semiconductor storage devices such as hard disks, magnetic discs, optical discs, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory devices, CD-ROMs, and DVD-ROMs. Furthermore, computer programs may be tangibly implemented on such computer-readable media.

[0178] The high-speed interface 1150 and the low-speed interface 1160 can be units for interacting with the input / output device 1170. For example, the input device may include a camera, keyboard, microphone, mouse, etc., with an audio sensor and / or image sensor, and the output device may include a display, speaker, haptic feedback device, etc. In other examples, the high-speed interface 1150 and the low-speed interface 1160 can be units for interfacing with a device that integrates input and output structures or functions, such as a touchscreen.

[0179] According to an embodiment, the high-speed interface 1150 can manage bandwidth-intensive operations, while the low-speed interface 1160 can manage lower bandwidth-intensive operations. Such allocation of functions is for purposes of example only. According to an embodiment, the high-speed interface 1150 can be comprised of a bus system, a message system, a full-duplex, a half-duplex, a crossbar switch, a network, a point-to-point system, a serial system, a parallel system, a multi-drop system, and the like. According to an embodiment, the high-speed interface 1150 can be comprised of a bus system, a message system, a full-duplex, a half-duplex, a crossbar switch, a network, a point-to-point system, a serial system, a parallel system, a multi-drop system, and the like. According to an embodiment, the high-speed interface 1150 can be coupled to the memory 1120, the input / output device 1170, and a high-speed expansion port, which can include various expansion cards (not shown) for example. Also, the low-speed interface 1160 can be coupled to the storage device 1130 and a low-speed expansion port. Additionally, a low-speed expansion card, which includes an interface for various communication ports (e.g., USB, Bluetooth, Internet of Things, Wireless Internet of Things), can be coupled to at least one of the input / output device 1170, such as a keyboard, a pointing device, a scanner, and the like, or a network device, such as a router, a switch, and the like, through a network adapter, and the like.

[0180] The computing device 1100 can be implemented as a variety of different forms. For example, the computing device 1100 can be implemented as a standard server, or multiple such servers, as a rack server system, or as a personal computer such as a notebook computer. In this case, the computing device 1100 can be coupled to other computing devices, such as a networked server, a networked personal computer, and the like. The computing device 1100 can include at least one other computing device, or be a part of at least one other computing device.

[0181] Figure 11 The input / output device 1170 is not included in the computing device 1100, but is not limited thereto, and can be configured as one device with the computing device 1100. Also, Figure 11 The high-speed interface 1150 and / or the low-speed interface 1160 and the processor 1110 are shown as separate elements, but are not limited thereto, and the high-speed interface 1150 and / or the low-speed interface 1160 can be included in the processor 1110.

[0182] The methods and / or embodiments can be implemented by one or more computer programs executed by one or more programmable processing apparatuses, e.g., at least one processor and / or at least one computer device. The computer programs can be implemented in a high level procedural or object oriented programming and / or scripting languages, and / or in assembly or machine language. The computer programs can be stored in any

[0183] The methods and / or embodiments can operate on input data and / or generate output data, and can be implemented using one or more computer programs executed by one or more programmable processing apparatuses. For example, the methods and / or embodiments of the present application can be implemented using a special purpose logic circuit, such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC). The apparatus and / or system that implements the methods and / or embodiments of the present application can be made into a special purpose logic circuit, such as an FPGA or an ASIC, when the apparatus and / or system is manufactured.

[0184] The one or more processors that execute the computer programs can include one or more microprocessors and / or one or more digital signal processors. The processors can receive instructions and / or data from a read only memory and / or a random access memory. In the present application, the structural elements of the computing device that execute the methods and / or embodiments can include one or more processors that execute instructions and one or more memories that store the instructions and / or data.

[0185] According to an embodiment, the computing device can transceive data with at least one mass storage device for storing data. For example, the computing device can receive data from and can transmit data to a magnetic disc or an optical disc. A computer readable medium suitable for storing instructions and / or data related to a computer program can include any form of non-volatile memory having a semiconductor memory device, such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory device, etc., but is not limited thereto. For example, the computer readable medium can include a magnetic disc, such as an internal hard disk or a removable magnetic disc, a photomagnetic disc, a CD-ROM, and a DVD-ROM optical disc.

[0186] To provide an interaction with a user, the computing device can include a display device (e.g., a cathode ray tube (CRT), a liquid crystal display (LCD), etc.) for providing or displaying information to the user, and a pointing device (e.g., a keyboard, a mouse, a trackball, etc.) for providing an input and / or an instruction, etc. to the computing device by the user, but is not limited thereto. That is, the computing device can further include any other kind of device for providing an interaction with the user. For example, the computing device can provide any form of sensory feedback, including visual feedback, audible feedback, and / or tactile feedback, etc. to the user for the interaction with the user. In this regard, the user can provide an input to the computing device through various kinds of gestures, such as a visual, a voice, a motion, etc.

[0187] In the present application, various embodiments can be implemented in a computer apparatus including a back-end structure element (e.g., a data server), a middleware structure element (e.g., an application server), and / or a front-end structure element. In this case, the structure elements can be connected to each other through any form or medium of digital data communication such as a communication network. According to an embodiment, the communication network can be composed of a wired network such as Ethernet, Power Line Communication, a telephone line communication device, and RS-serial communication, a mobile communication network, a wireless local area network (WLAN), Wi-Fi, Bluetooth, and cellular communication, or a combination thereof. For example, the communication network can include a local area network (LAN), a wide area network (WAN), or the like.

[0188] The computing apparatus based on the exemplary embodiments described in the present specification can be implemented using hardware and / or software that includes a user device, a user interface (UI) device, a user terminal, or a client device to interact with a user. For example, the computing apparatus can include a portable computing device such as a laptop computer. Additionally or alternatively, the computing apparatus can include a personal data assistant (PDA), a tablet, a game console, a wearable device, an internet of things (IoT), a virtual reality (VR) device, an augmented reality (AR) device, or the like, but is not limited thereto. The computing apparatus can also include other types of devices that interact with a user. Also, the computing apparatus can include a portable communication device (e.g., a mobile phone, a smart phone, a wireless cellular phone, or the like) that is suitable for wireless communication through a network such as a mobile communication network. The computing apparatus can use wireless communication technologies and protocols such as radio frequency (RF), microwave frequency (MWF), and / or infrared ray frequency (IRF) to wirelessly communicate with a network server.

[0189] In the present application, various embodiments including specific structural and functional details are illustrated as example embodiments. Therefore, the present application is not limited to the described content, but can be embodied in various different forms. Also, the terms used in the present application are used to explain a part of the embodiments, and not to limit the embodiments. For example, unless clearly indicated in the context, singular words include plural types.

[0190] In the present application, unless defined otherwise, all terms used in the specification including technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. Also, the meaning of the terms defined in a dictionary and the like generally used are the same as the meaning in the same technical context.

[0191] In the present application, the present application is described in relation to a part of the embodiments, and it can be understood that one of ordinary skill in the art can make various modifications and changes within the scope of the present application without departing from the scope of the present application. Also, such modifications and changes should belong to the scope of the present application claimed in the attached specification.

Claims

1. A no-code power management controller design system, used for designing power management controllers in a no-code manner, characterized in that, include: Memory for storing at least one instruction; A power manager component repository stores the root power manager component and at least one type of domain power manager component; and At least one processor for executing the at least one instruction stored in the memory. The at least one instruction includes: Instructions for generating a root power manager instance constituting a power management controller based on the root power manager component, and for generating at least one domain power manager instance constituting the power management controller based on at least one type of domain power manager component; Instructions for setting the connection between the output port of the root power manager instance and the input port of at least one domain power manager instance; Instructions for allocating memory storage space for the root power manager instance and the at least one domain power manager instance constituting the power management controller, respectively; and Instructions for generating hardware code for the power components included in the power management controller, register code corresponding to each power component, hardware code corresponding to the multiple ports and connections, and binary code corresponding to the working sequence of the power management controller.

2. The no-code power management controller design system according to claim 1, characterized in that, The at least one instruction includes: an instruction for copying the register field value and working sequence of the root power manager component to the register field value and working sequence of the root power manager instance, and an instruction for copying the register field value and working sequence of at least one domain power manager component to the register field value and working sequence of the corresponding domain power manager instance.

3. The no-code power management controller design system according to claim 1, characterized in that, The at least one instruction includes: an instruction for setting the number of domain groups and the number of power domains connected to each domain group for the root power manager instance.

4. The no-code power management controller design system according to claim 3, characterized in that, The memory storage space allocated to the domain power manager instance is determined based on the number of domain groups and the number of power domains included in the domain groups containing the domain power manager instance.

5. The no-code power management controller design system according to claim 1, characterized in that, The at least one instruction includes: an instruction for generating a power management interface instance that is connected to the domain power manager instance via a P-link, corresponding to the at least one domain power manager instance respectively.

6. The no-code power management controller design system according to claim 1, characterized in that, It also includes a power component repository for storing at least one power component and an instruction component repository for storing at least one instruction component. The at least one instruction includes: Instructions for generating at least one power instance of at least one power manager component constituting the root power manager component and the at least one type of domain power manager component based on the at least one power component; Instructions for generating a first instruction instance based on the at least one instruction component; An instruction for determining the target power instance of the first instruction instance and setting a value in the at least one power instance; and Instructions are used to generate code containing instructions, register addresses, and data based on the first instruction instance and the target power instance and value.

7. The no-code power management controller design system according to claim 6, characterized in that, The at least one instruction includes: Instructions for generating a second instruction instance based on the at least one instruction component; An instruction for setting the target power instance and value of the second instruction instance in the at least one power instance; and Instructions used to set the execution order of the first instruction instance and the second instruction instance.

8. The no-code power management controller design system according to claim 6, characterized in that, The at least one power component is at least one of the following: a reset component, an isolation component, a switch control component, a holding component, an automatic power management component, a reference clock gating component, a memory component, a handshake component, a clock link component, a P-channel handshake component, a user-defined output component, and a user-defined input component.

9. The no-code power management controller design system according to claim 6, characterized in that, The at least one power component is at least one of the following: a notification register generation component, a timeout register generation component, an upper-layer information transmission register generation component, an internal register storage component, an internal register control interrupt generation component, an external input control interrupt generation component, a timer generation component, and a domain power manager connection component.

10. The no-code power management controller design system according to claim 6, characterized in that, The at least one instruction component is at least one of the following: a write component for writing a specific value to a specific register field, an input wait component for waiting for a specific value to be input to a specific register field, a wait component for waiting for a specified time, a condition component for branching based on conditions, a move component for moving to a specific position, and a call component capable of moving to a specific position and restoring.

11. A no-code power management controller design method, executed by at least one processor in a computer system including a power manager component repository, the power manager component repository storing a root power manager component and at least one type of domain power manager component, characterized in that the no-code power management controller design method includes the following steps: A root power manager instance constituting the power management controller is generated based on the root power manager component, and at least one domain power manager instance constituting the power management controller is generated based on at least one type of domain power manager component. Configure the connection between the output port of the root power manager instance and the input port of at least one domain power manager instance; Memory storage space is allocated to the root power manager instance and the at least one domain power manager instance that constitute the power management controller, respectively. as well as The hardware code of the power components included in the power management controller, the register code corresponding to each power component, the hardware code corresponding to the multiple ports and connections, and the binary code corresponding to the working sequence of the power management controller are generated.

12. The no-code power management controller design method according to claim 11, characterized in that, It also includes the following steps: copying the register field values ​​and working sequences of the root power manager component to the register field values ​​and working sequences of the root power manager instance, and copying the register field values ​​and working sequences of at least one of the domain power manager components to the register field values ​​and working sequences of the corresponding domain power manager instances.

13. The no-code power management controller design method according to claim 11, characterized in that, It also includes the following steps: setting the number of domain groups and the number of power domains connected to each domain group for the root power manager instance.

14. The no-code power management controller design method according to claim 13, characterized in that, The memory storage space allocated to the domain power manager instance is determined based on the number of domain groups and the number of power domains included in the domain groups containing the domain power manager instance.

15. The no-code power management controller design method according to claim 11, characterized in that, It also includes the following steps: generating power management interface instances that are connected to the domain power manager instances via P links, corresponding to the at least one domain power manager instance.

16. The no-code power management controller design method according to claim 11, characterized in that, It also includes the following steps: At least one power instance is generated based on the at least one power component, constituting at least one power manager component among the root power manager component and the at least one type of domain power manager component; A first instruction instance is generated based on the at least one instruction component; In the at least one power instance, determine the target power instance of the first instruction instance and set a value; as well as Code containing instructions, register addresses, and data is generated based on the first instruction instance and the target power instance and value.

17. The no-code power management controller design method according to claim 16, characterized in that, It also includes the following steps: A second instruction instance is generated based on the at least one instruction component; In the at least one power instance, the target power instance and value of the second instruction instance are set; and Set the execution order of the first instruction instance and the second instruction instance.

18. The no-code power management controller design method according to claim 16, characterized in that, The at least one power component is at least one of the following: a reset component, an isolation component, a switch control component, a holding component, an automatic power management component, a reference clock gating component, a memory component, a handshake component, a clock link component, a P-channel handshake component, a user-defined output component, and a user-defined input component.

19. The no-code power management controller design method according to claim 16, characterized in that, The at least one power component is at least one of the following: a notification register generation component, a timeout register generation component, an upper-layer information transmission register generation component, an internal register storage component, an internal register control interrupt generation component, an external input control interrupt generation component, a timer generation component, and a domain power manager connection component.

20. The no-code power management controller design method according to claim 16, characterized in that, The at least one instruction component is at least one of the following: a write component for writing a specific value to a specific register field, an input wait component for waiting for a specific value to be input to a specific register field, a wait component for waiting for a specified time, a condition component for branching based on conditions, a move component for moving to a specific position, and a call component capable of moving to a specific position and restoring.

21. A computer program, characterized in that, Stored on a computer-readable medium for the purpose of performing the method according to any one of claims 11 to 20 in a computer.

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