A method, apparatus and electronic device for automatically generating filter layouts

Abstract

This invention discloses a method, apparatus, and electronic device for automatically generating filter layouts. The method includes: acquiring circuit parameters and process parameters of the filter to be patterned; updating the resonator model in the filter to be patterned based on the circuit parameters; acquiring process constraint rules based on the process parameters, establishing a rule mapping relationship corresponding to the process constraint rules, and updating the parameterized units according to the rule mapping relationship and the resonator model; generating an optimization objective function based on the rule mapping relationship, and iteratively optimizing the resonator layout structure based on the optimization objective function to obtain a first layout structure; adjusting the shape of the resonator layout structure and the resonator model in the first layout structure based on a preset compression deformation algorithm to obtain a second layout structure; and generating a filter layout file based on the second layout structure. This invention enables fully automated design from filter parameter input to layout output without manual intervention, thus improving design efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer-aided design technology for integrated circuits, and in particular to a method, apparatus, and electronic device for automatically generating filter layouts. Background Technology

[0002] Bulk Acoustic Wave (BAW) filters are electronic devices that utilize the bulk acoustic wave resonant characteristics of piezoelectric materials to achieve filtering functions. Operating at radio frequency, they are an indispensable key component in modern wireless communication systems. The core of BAW filter layout design lies in the geometry and arrangement of the resonators (such as FBAR or SMR resonators). On the layout, each resonator represents a specific multilayer structure region, and the layout structure of the resonators significantly impacts the filter's electrical performance (such as center frequency, bandwidth, insertion loss, and out-of-band rejection).

[0003] The existing Automatic Placement and Routing (APR) is a design method that automatically allocates the physical locations of circuit cells and interconnects them on an integrated circuit layout. It is usually used for electrical network design that includes logical connections of circuits. However, it cannot adjust the shape and layout of resonant devices to take into account their unique electromagnetic-acoustic coupling characteristics. Therefore, the existing filter layout design mainly relies on manual work, which has the following problems: manual design is inefficient and has a long cycle time. In scenarios with high power handling capacity and limited chip area constraints, manual design is more difficult. In addition, the update speed of high-performance filter layout is slow during the design iteration process, and the design cost is high. Summary of the Invention

[0004] This invention provides a method, apparatus, and electronic device for automatically generating filter layouts, which solves the problems of existing filter layout design relying on manual intervention, resulting in low design efficiency, long cycle time, and high difficulty. It can automatically complete filter layout design and improve design efficiency.

[0005] To address the aforementioned technical problems, according to one aspect of the present invention, an automatic filter layout generation method is provided, comprising: acquiring circuit parameters and process parameters of a filter to be patterned; updating a resonator model in the filter to be patterned based on the circuit parameters; acquiring process constraint rules based on the process parameters, establishing a rule mapping relationship corresponding to the process constraint rules, and updating a parameterized unit based on the rule mapping relationship and the resonator model; wherein the rule mapping relationship is at least used to determine the layer information of each layer of the resonator device; generating an optimization objective function based on the rule mapping relationship, and iteratively optimizing the resonator layout structure based on the optimization objective function to obtain a first layout structure; adjusting the shape of the resonator layout structure and the resonator model in the first layout structure based on a preset compression deformation algorithm to obtain a second layout structure; and generating a filter layout file based on the second layout structure.

[0006] Optionally, the step of generating an optimization objective function based on the rule mapping relationship and iteratively optimizing the resonator layout structure based on the optimization objective function to obtain a first layout structure includes: establishing an interlayer constraint cost term based on the degree of conformity between the actual spacing and the minimum spacing between different film layers; establishing a same-layer constraint cost term based on the degree of satisfaction of electrical performance layout requirements based on the horizontal spatial relationship between patterns within the same film layer; establishing a connection relationship constraint cost term based on the degree of realization of circuit connection relationships based on the layout routing; and performing a weighted summation of the interlayer constraint cost term, the same-layer constraint cost term, and the connection relationship constraint cost term to establish the optimization objective function.

[0007] Optionally, the step of generating an optimization objective function based on the rule mapping relationship and iteratively optimizing the resonator layout structure based on the optimization objective function to obtain a first layout structure further includes: taking the position coordinates of each resonator device as optimization variables and iteratively updating the optimization variables with the goal of minimizing the optimization objective function; the first layout structure also satisfies at least one of the following optimization indicators: area utilization, distribution uniformity, input-output coupling isolation, and device spacing.

[0008] Optionally, the preset compression deformation algorithm is based on polygon shape adjustment, elastic mesh transformation, or elastic mechanical model establishment; the adjustment of the shape of the resonator layout structure and the resonator model in the first layout structure based on the preset compression deformation algorithm to obtain the second layout structure includes: modeling all resonator devices in the first layout structure as elastic variable objects, and modeling the input, output, and grounding devices in the first layout structure as inelastic objects, and establishing an elastic mechanical model; applying dynamic compressive force to the elastic mechanical model in multiple preset compression directions based on preset constraints, so that the elastic variable objects produce elastic deformation, rotation, and movement to fill the empty area in the first layout structure; wherein, the preset constraints include at least one of the following: electrical performance constraints, connectivity constraints, and parasitic effect constraints.

[0009] Optionally, the process parameters include at least the film layer structure and minimum spacing of the resonator; the step of obtaining process constraint rules based on the process parameters, establishing the rule mapping relationship corresponding to the process constraint rules, and updating the parameterized unit according to the rule mapping relationship and the resonator model includes: establishing a film layer set based on the film layer structure; obtaining spacing type constraint rules between the same layer and different layers within the film layer set based on the minimum spacing; and establishing the rule mapping relationship based on the mathematical expression of the spacing type constraint rules.

[0010] Optionally, the circuit parameters include at least: resonator area and filter topology; updating the resonator model in the filter to be plotted based on the circuit parameters includes: obtaining an initial model of all resonator devices in the filter to be plotted; wherein the shape contour of the initial model is any one of the following: rectangular, pentagonal, or convex polygonal; scaling the initial model according to the resonator area to establish the updated resonator model.

[0011] Optionally, generating the filter layout file according to the second layout structure includes: automatically generating metal interconnect lines based on the connectivity constraints in the second layout structure, and adding signal lines connecting the metal layers; converting the layout data containing the metal interconnect lines and the signal lines into a format, and outputting a layout file in a preset format; wherein the preset format is any one of the following: GDSII or OASIS format.

[0012] Optionally, after generating a filter layout file including connecting films based on the second layout structure, the method further includes: evaluating the filter layout file based on at least one of area utilization, wiring completion rate, and design rule compliance.

[0013] According to another aspect of the present invention, an automatic filter layout generation apparatus is provided for implementing the above-described automatic filter layout generation method. The apparatus includes: a parameter acquisition module for acquiring circuit parameters and process parameters of a filter to be patterned; a model adjustment module for updating the resonator model in the filter to be patterned according to the circuit parameters; a constraint rule acquisition model for acquiring process constraint rules based on the process parameters, establishing a rule mapping relationship corresponding to the process constraint rules, and updating the parameterization unit according to the rule mapping relationship and the resonator model; wherein the rule mapping relationship is at least used to determine the layer information of each layer of the resonator device; a first layout adjustment module for generating an optimization objective function according to the rule mapping relationship, and iteratively optimizing the resonator layout structure based on the optimization objective function to obtain a first layout structure; a second layout adjustment module for adjusting the shape of the resonator layout structure and the resonator model in the first layout structure based on a preset compression deformation algorithm to obtain a second layout structure; and a layout output module for generating a filter layout file according to the second layout structure.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the above-described automatic filter layout generation method.

[0015] Based on the above technical solution, the present invention has the following technical effects: It updates the resonator model in the filter to be patterned by updating the circuit parameters of the filter; it obtains process constraint rules and forms a rule mapping relationship by obtaining the process parameters of the filter, and updates the parameterized units of the resonator devices; it establishes an optimization objective function based on the rule mapping relationship, and iteratively optimizes the layout through an automated placement and routing algorithm to seek the minimum value of the optimization objective function, thereby automatically generating a high-quality layout that meets all constraints; by introducing a preset compression deformation algorithm to optimize and adjust the placement position, angle, and shape of each resonator in the first layout structure, it can obtain a compact layout result with higher area utilization, better parasitic characteristics, and compliance with design rules; finally, it generates a filter layout file based on the compressed and deformed second layout structure, which can improve chip area utilization and solve the problems of existing filter layout design relying on manual intervention, low design efficiency, long cycle, and high difficulty. It can realize fully automated design from filter parameter input to layout output, significantly improving design efficiency and design accuracy. The layout design process does not require manual intervention, which can save design costs.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating an automatic filter layout generation method provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the core structure of a parameterized unit provided in an embodiment of the present invention;

[0020] Figure 3 A flowchart of another automatic filter layout generation method provided in an embodiment of the present invention;

[0021] Figure 4 A schematic diagram of a resonator topology provided in an embodiment of the present invention;

[0022] Figure 5 A schematic diagram of the layout structure before and after compression deformation provided in an embodiment of the present invention;

[0023] Figure 6 A schematic diagram illustrating the layout structure of a manual layout layout and an automatic layout layout provided in an embodiment of the present invention;

[0024] Figure 7 A schematic diagram of the frequency response curves of a filter with manual and automatic layout provided in an embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of the structure of an automatic filter layout generation device provided in an embodiment of the present invention;

[0026] Figure 9 A schematic diagram of an electronic device for implementing the automatic filter layout generation method of this invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] Figure 1 This is a flowchart of an automatic filter layout generation method provided by an embodiment of the present invention. This embodiment can be applied to layout design scenarios of high-power chips, limited area constraints, or high-performance chips. The method can be executed by an automatic filter layout generation device, which can be implemented in hardware and / or software. The automatic filter layout generation device can be configured in an electronic device with automatic routing function.

[0030] like Figure 1 As shown, the automatic filter layout generation method of the present invention includes the following steps:

[0031] S1: Obtain the circuit parameters and process parameters of the filter to be patterned.

[0032] In this embodiment, the filter to be mapped can be a bulk acoustic wave filter.

[0033] Circuit parameters can be understood as data characterizing the electrical performance of a filter. Optionally, circuit parameters may include at least: resonator area, the relationship between resonator area and center frequency, and the filter topology. Typically, the filter topology includes, but is not limited to: trapezoidal topology or other complex topologies, and the connection relationships between the various resonators.

[0034] Process parameters can be understood as data characterizing the specific technical specifications, material properties, physical limitations, and manufacturing rules involved in the manufacturing process of a filter. Optionally, process parameters may include at least the resonator's film layer structure and spacing type. The film layer structure refers to a multilayer thin-film system composed of thin-film materials with different functions stacked in a specific order and thickness. Typically, the resonator's film layer structure includes, but is not limited to: the materials, thicknesses, and stacking order of the bottom electrode, piezoelectric layer, top electrode, and passivation layer. Spacing types include, but are not limited to: the minimum spacing between different film layers and the minimum spacing between the resonator device and other devices.

[0035] S2: Update the resonator model in the filter to be plotted based on the circuit parameters.

[0036] The resonator model can be understood as a model with a specific shape and contour, built based on circuit parameters and a resonator graphics library.

[0037] In some optional embodiments, step S2 specifically includes: obtaining initial models of all resonator devices in the filter to be patterned; scaling the initial models according to the resonator areas to establish updated resonator models. The shape of the initial model is any one of the following: rectangular, pentagonal, or convex polygonal. For example, Figure 2 This is a schematic diagram of the core structure of a parameterized unit provided in an embodiment of the present invention. See also... Figure 2 As shown, the initial model can be a regular pentagon.

[0038] Specifically, if the area of ​​the reference layer pattern (e.g., the top electrode pattern) of the initial model is defined as A0, and the area of ​​the resonator in the circuit parameters is defined as A1, then during the resonator model update process, the reference layer pattern of the initial model is scaled from area A0 to A1, thereby obtaining the initial model of the resonator that meets the circuit performance requirements.

[0039] S3: Obtain process constraint rules based on process parameters, establish rule mapping relationships corresponding to process constraint rules, and update resonator parameterized units according to rule mapping relationships and resonator models.

[0040] In this context, a parameterized unit can be understood as a reusable resonator unit containing a specific shape and size. See also... Figure 2 As shown, after the resonator model is updated, it is also necessary to update the remaining layers (such as the bottom electrode, piezoelectric layer, and passivation layer) based on the rule mapping relationship (such as the stacked structure type) and update the parameterized units corresponding to the model.

[0041] Process constraint rules can be understood as drawing constraints established based on process parameters. In this embodiment, process constraint rules include, but are not limited to, spacing type and stack-up structure type. The spacing type rule specifically states that the minimum spacing between layer A and layer B is X (A and B can be the same layer). The stack-up structure type rule specifically states the relative contour relationship between layer A and layer B (A and B are different layers).

[0042] A rule-based mapping relationship can be understood as a functional expression of constraint rules established based on one or more process constraint rules. At a minimum, rule-based mapping relationships are used to determine the layer information of a resonator device, such as the film layer stack structure and the minimum spacing between different film layers, based on the shape and device parameters in the resonator model, and to generate parameterized units based on this.

[0043] In some optional embodiments, step S3 specifically includes: establishing a membrane set based on the membrane structure; obtaining spacing type constraint rules between the same layer and different layers within the membrane set based on the minimum spacing; and establishing a rule mapping relationship based on the mathematical expression of the spacing type constraint rules.

[0044] Specifically, the process of generating the rule mapping relationship can be transformed into reading each spacing type constraint rule in the process parameters and converting it into a mathematical expression. Taking layers A and B with a minimum spacing of X as an example, the rule mapping relationship can be expressed as X = Rule(A, B), where layers A and B can be the same layer or different layers. Taking a membrane structure including M1, M2, and M3 as an example, defining the membrane layer set S={M1, M2, M3}, then for any A, B ∈ S, the rule mapping relationship Rule(A,B) represents the minimum spacing between layers A and B. Assuming the process parameters impose the following constraints on the spacing type of these three layers: a minimum spacing of 0.25 μm between M1 layers, a minimum spacing of 0.28 μm between M2 layers, and a minimum spacing of 0.30 μm between M3 layers, then the corresponding rule mapping values ​​are: Rule(M1, M1) = 0.25, Rule(M2, M2) = 0.28, Rule(M3, M3) = 0.30. For spacing constraints between different layers, such as a minimum spacing of 0.35 μm between M1 and M2 layers, the rule mapping relationship is further extended to: Rule(M1, M2) = Rule(M2, M1) = 0.35. It should be noted that the enclosure type constraint rules are satisfied through the parameterized cell structure design during device generation and do not need to be checked again during the layout stage.

[0045] S4: Generate an optimization objective function based on the rule mapping relationship, and iteratively optimize the resonator layout structure based on the optimization objective function to obtain the first layout structure.

[0046] The optimization objective function can be understood as a cost function used to evaluate the quality of the layout.

[0047] The first layout structure can be understood as an initial layout that can satisfy all process constraints.

[0048] Specifically, by introducing a rule mapping relationship to establish an optimization objective function, and by iteratively optimizing the layout through an automated placement and routing algorithm, the minimum value of the optimization objective function is sought, thereby automatically generating a high-quality layout that meets all process constraints.

[0049] S5: Adjust the shape of the resonator layout structure and the resonator model in the first layout structure based on the preset compression deformation algorithm to obtain the second layout structure.

[0050] The second layout structure can be understood as a compact layout result formed by optimizing and adjusting the position, angle, and shape of each resonator in the first layout structure. The chip area utilization rate of the second layout structure is higher than that of the first layout structure.

[0051] Optionally, the preset compression deformation algorithm is based on polygon shape adjustment, elastic mesh transformation, or elasticity model.

[0052] Specifically, by introducing a preset compression deformation algorithm to optimize and adjust the layout position, angle and shape of each resonator in the first layout structure, a compact layout result with higher area utilization, better parasitic characteristics and in accordance with design rules can be obtained.

[0053] S6: Generate the filter layout file based on the second layout structure.

[0054] In this embodiment, the final output layout file contains geometric information of each film layer, the correspondence between layers, and necessary annotation layers (device identifiers).

[0055] In some optional embodiments, step S6 specifically includes: automatically generating metal interconnect lines based on the connectivity constraints in the second layout structure, and adding signal lines connecting to the metal layer; converting the layout data containing the metal interconnect lines and signal lines into a format, and outputting a layout file in a preset format; wherein the preset format is any one of the following: GDSII or OASIS format. The metal interconnect lines are the conductive paths in the chip that actually carry current and connect various components (transistors, resistors, capacitors, etc.). Specifically, after obtaining the second layout structure, the second layout structure is first imported into an autorouter. The autorouter first generates the metal interconnect lines, and during the routing process, the line width and spacing parameters are detected in real time to ensure that the metal interconnect lines conform to the process design rules. Subsequently, signal lines connecting to the metal layer are automatically added. Finally, the complete layout data is converted into a standard layout file in GDSII or OASIS format.

[0056] In some alternative embodiments, after generating a filter layout file including connecting films based on the second layout structure, the automatic filter layout generation method of the present invention further includes: evaluating the filter layout file based on at least one of area utilization, routing completion rate, and design rule compliance. Specifically, after obtaining the filter layout file, a layout verification report is generated by detecting the area utilization, routing completion rate, and design rule compliance of the layout. After the area utilization, routing completion rate, and design rule compliance verifications are passed, a standard layout file in GDSII or OASIS format is output.

[0057] Therefore, the technical solution of this invention updates the resonator model in the filter to be patterned by updating the circuit parameters of the filter; obtains process constraint rules by obtaining the process parameters of the filter and forms a rule mapping relationship, and updates the parameterized unit of the resonator device; establishes an optimization objective function according to the rule mapping relationship, and iteratively optimizes the layout by an automated placement and routing algorithm to seek the minimum value of the optimization objective function, thereby automatically generating a high-quality layout that meets all constraints; by introducing a preset compression deformation algorithm to optimize and adjust the placement position, angle and shape of each resonator in the first layout structure, a compact layout result with higher area utilization, better parasitic characteristics and conforming to design rules can be obtained; finally, a filter layout file is generated based on the compressed and deformed second layout structure, which can improve chip area utilization, realize fully automated design from filter parameter input to layout output, significantly improve design efficiency and design accuracy, solve the problems of existing filter layout design relying on manual intervention, low design efficiency, long cycle and high difficulty, and the layout design process does not require manual intervention, which can save design costs.

[0058] In some optional embodiments, step S4 above specifically includes: establishing an interlayer constraint cost term based on the degree of conformity between the actual spacing and the minimum spacing between different film layers; establishing a same-layer constraint cost term based on the degree of satisfaction of the electrical performance layout requirements by the horizontal spatial relationship between patterns within the same film layer; establishing a connection constraint cost term based on the degree of realization of circuit connection relationships by the layout routing; and performing a weighted summation of the interlayer constraint cost term, the same-layer constraint cost term, and the connection constraint cost term to establish an optimization objective function.

[0059] Specifically, the rule mapping relationship is transformed into an optimization objective function for evaluating the layout quality. The mathematical expression of the optimization objective function is: Cost = a * x + b * y + c * z. Here, a, b, and c are weighting coefficients used to balance the importance of different types of constraints; x is the cost term for constraints between different layers, calculated based on the rule mapping relationship Rule(A, B) to determine the degree to which the actual spacing meets the minimum spacing requirement; y is the cost term for constraints within the same layer, characterizing the degree to which the horizontal spatial relationship between graphics within the same material layer meets the electrical performance layout requirements; z is the cost term for establishing connection constraints based on the degree to which the circuit connection relationship is realized in the layout routing. The function value of the optimization objective function is negatively correlated with the layout quality; that is, the lower the function value Cost, the better the layout. Therefore, by iteratively optimizing the layout through an automated placement and routing algorithm, the minimum value of the optimization objective function Cost is sought, thereby automatically generating a high-quality layout that satisfies all constraints.

[0060] In some optional embodiments, step S4 above further includes: taking the position coordinates of each resonator device as an optimization variable, and iteratively updating the optimization variable with the goal of minimizing the optimization objective function; the first layout structure also satisfies at least one of the following optimization indices: area utilization, distribution uniformity, input-output coupling isolation, and device spacing.

[0061] Among them, the area utilization rate is evaluated by calculating the ratio of the total area of ​​the devices to the area of ​​the layout area; the distribution uniformity is calculated by calculating the filling ratio of the sub-region graphics after the overall layout is divided (the number of sub-regions can be 4, 9, or 16 depending on the actual accuracy requirements, and the division of sub-regions can be uniform or non-uniform, and includes but is not limited to the above division methods); the input-output coupling isolation can be guaranteed by the distance and relative position constraints between the input, output, and ground devices; the device spacing must meet the minimum distance between real-time detection devices and meet the spacing requirements defined by the rule mapping relationship Rule(A, B).

[0062] Specifically, during the optimization process, the position coordinates of each resonator device are used as optimization variables. The algorithm for iteratively updating the optimization variables can be one or more of the following: differential evolution algorithm, particle swarm optimization algorithm, simulated annealing algorithm, or genetic algorithm. The optimization objective function value is minimized by iteratively updating the optimization variables.

[0063] In some alternative embodiments, during the iterative optimization process, the weight coefficients of the inter-layer constraint cost term, the same-layer constraint cost term, and the connectivity constraint cost term in the objective function can be dynamically adjusted to balance the relative importance of each optimization index. During the iterative optimization process, collision detection and design rule checking mechanisms can also be introduced to ensure that there is no overlap between devices, thereby obtaining a layout result that satisfies the design rules and has optimized performance.

[0064] In some optional embodiments, step S5 above specifically includes: modeling all resonator devices in the first layout structure as elastic variable objects, and modeling the input, output and grounding devices in the first layout structure as inelastic objects, and establishing an elastic mechanical model; applying dynamic compressive force to the elastic mechanical model in multiple preset compression directions based on preset constraints, so that the elastic variable objects produce elastic deformation, rotation and movement to fill the empty areas in the first layout structure; wherein, the preset constraints include at least one of the following: electrical performance constraints, connectivity constraints and parasitic effect constraints.

[0065] Typically, electrical performance constraints include, but are not limited to: the total area of ​​all resonator devices remains constant, and the aspect ratio variation is within a preset range (e.g., ±30%). During compression deformation optimization, these electrical performance constraints ensure the stability of the device's resonant frequency and Q-value parameters.

[0066] Connectivity constraints include, but are not limited to, maintaining the circuit connections between resonator devices and preserving interconnect routing channels. In the compression deformation optimization process, introducing connectivity constraints (such as reserving necessary channel space for interconnect routing) creates favorable conditions for subsequent automatic routing steps, improving the success rate and quality of the final routing.

[0067] Parasitic effect constraints include, but are not limited to, the deformation structure not exhibiting pre-defined undesirable geometry. Typical pre-defined undesirable geometry includes, but is not limited to, the formation of parallel or near-parallel relationships between long-side boundaries, and the presence of excessively small acute angle structures. In this embodiment, the case where the included angle between two non-adjacent sides is less than 5° is considered approximately parallel; in this embodiment, the case where the included angle between adjacent sides is less than 60° is considered an excessively small acute angle. During compression deformation optimization, by introducing parasitic effect constraints, the formation of parallel or near-parallel relationships between long-side boundaries is avoided, and excessively small acute angle structures are prevented, thereby reducing parasitic coupling effects and improving the stability of the layout's electrical performance.

[0068] Specifically, taking the compression deformation algorithm based on an elastic mechanics model as an example, all resonator devices in the first layout structure are modeled as elastically variable objects, while the input, output, and grounding devices in the first layout structure are modeled as inelastic objects. These inelastic objects only undergo rotation and movement. By applying dynamic compressive forces in multiple preset directions, each device undergoes elastic deformation, rotation, and movement to fill the empty areas in the layout region. The compressive force is dynamically adjusted during the iteration process, thereby improving chip area utilization. In this embodiment, the compression direction settings include, but are not limited to, 4 directions, 8 directions, or multiple direction vectors customized according to layout characteristics. During the iterative compression deformation process, the structure after compression deformation is monitored in real time to ensure that it meets the aforementioned electrical performance constraints, connectivity constraints, and parasitic effect constraints. Thus, by introducing electrical performance constraints, connectivity constraints, and parasitic effect constraints, and through multiple iterative optimizations, the empty areas between devices are gradually reduced, resulting in a compact layout with higher area utilization, better parasitic characteristics, and compliance with design rules.

[0069] Based on the above embodiments, Figure 3 A flowchart of another automatic filter layout generation method provided in an embodiment of the present invention is shown. Figure 1 Based on the illustrated embodiment, an exemplary implementation of the process from filter parameter input to layout output is shown.

[0070] See Figure 3 As shown, the automatic filter layout generation method of the present invention specifically includes the following steps:

[0071] S101: Obtain the circuit parameters and process parameters of the filter to be patterned.

[0072] S102: Obtain process constraint rules based on process parameters and establish the rule mapping relationship corresponding to the process constraint rules.

[0073] S103: Update the resonator mode according to the circuit parameters, and update the resonator parameterization unit according to the rule mapping relationship and the resonator model.

[0074] S104: Generate an optimization objective function based on the rule mapping relationship, and iteratively optimize the resonator layout structure based on the optimization objective function.

[0075] S105: Determine whether the iterative optimization is complete.

[0076] If the iterative optimization is complete, proceed to step S106; if the iterative optimization is complete, return to continue executing step S104.

[0077] S106: Output the first layout structure.

[0078] S107: Initialization of multi-directional compression iteration parameters.

[0079] S108: Update the multi-directional compression iteration step size and number of iterations.

[0080] S109: Unidirectional resonator pattern compression deformation.

[0081] S110: Determine whether the geometric structure of the resonator pattern satisfies the electrical performance constraints, connectivity constraints, and parasitic effect constraints.

[0082] If the geometric structure of the resonator pattern does not satisfy any of the electrical performance constraints, connectivity constraints, and parasitic effect constraints, then proceed to step S111; if the geometric structure of the resonator pattern satisfies the electrical performance constraints, connectivity constraints, and parasitic effect constraints, then proceed to step S112.

[0083] S111: Decrease the iteration step size and return to step S109.

[0084] S112: Update the compressed map layout.

[0085] S113: Determine whether the preset number of iterations and minimum step size are met.

[0086] If the preset number of iterations and minimum step size are met, proceed to step S114; otherwise, return to step S108.

[0087] S114: Output the second layout structure.

[0088] S115: Automatically routes the filter based on the second layout result and outputs a filter layout file in GDSII or OASIS format.

[0089] For example, Figure 4 A schematic diagram of a resonator topology provided in an embodiment of the present invention; Figure 5 A schematic diagram of the layout structure before and after compression deformation provided in an embodiment of the present invention; Figure 6 A schematic diagram illustrating the layout structure of a manual layout layout and an automatic layout layout provided in an embodiment of the present invention; Figure 7 This is a schematic diagram illustrating the frequency response curves of a filter with manual and automatic placement layouts, provided as embodiments of the present invention. Figure 4 S1, S2, S3, S4, and S5 are resonators connected in series; P1, P2, P3, P4, and P5 are resonators connected in parallel. For example, the resonator area of ​​resonator S1 is 8007 μm. 2 The resonator area of ​​resonator S2 is 8001 μm. 2The resonator area of ​​resonator S3 is 8000μm. 2 The resonator area of ​​resonator S4 is 8000μm. 2 The resonator area of ​​resonator S5 is 8099 μm. 2 The resonator area of ​​resonator P1 is 7800 μm. 2 The resonator area of ​​resonator P2 is 5673 μm. 2 The resonator area of ​​resonator P3 is 6149 μm. 2 The resonator area of ​​resonator P4 is 7620 μm. 2 The resonator area of ​​resonator P5 is 4481 μm. 2 . Figure 5 Different graphics in the diagram correspond to different devices.

[0090] See Figures 4 to 7 As shown, to verify the effectiveness of the present invention, an FBAR filter with a bandwidth of 4.1GHz-4.2GHz is used as an example to automatically generate an FBAR filter layout using the filter layout automatic generation method provided by the present invention.

[0091] Specifically, such as Figure 4 As shown, the circuit topology and resonator area of ​​the input FBAR filter are shown. Considering the power factor of the filter, the resonator is multiplied. The process parameters are simplified and determined to be the minimum spacing of the top electrode patterns of each resonator, which is set to 40μm. Figure 5 A schematic diagram of a first layout structure obtained by an automatic routing iterative optimization algorithm and a second layout structure obtained by a compression deformation algorithm is shown. To reasonably evaluate the layout effect, the top electrode pattern of the resonator in the layout is expanded outward by 20 μm. Based on the updated layout distribution, the fill ratio and layout outline are then calculated. Figure 5 As shown, the area before compression deformation is 1110*1001, with a fill ratio of 42.0%; the area after compression deformation is 789*726, with a fill ratio of 81.0%; the area utilization rate of the final layout is improved by about 39%. Figure 6 The comparison between the automatic layout results of this invention and the manual layout results of experienced engineers is shown. Both are correct in terms of stacking structure and connection relationships. The area occupied by the automatic layout is 94% of that occupied by the manual layout, achieving a 6% area saving. Performance Comparison: Figure 7 The presentation compares the frequency response curves obtained from circuit simulations based on manually laid-out layouts and automatically generated layouts after extracting parasitic parameters. (See also...) Figure 7As shown, the filter layout generated by the automatic layout generation method provided by this invention has an in-band insertion loss that is on par with manual design. The out-of-band rejection performance is better at high frequencies, with an optimal improvement of -25dB. Furthermore, the in-band return loss is generally better with automatic layout than manual layout, with an optimal improvement of -7dB. This fully demonstrates the performance advantages of this invention. Efficiency comparison: The entire automatic layout generation process took 25 minutes, while traditional manual design for a layout of equivalent complexity takes 1 hour or more, resulting in a design efficiency improvement of more than 2 times. In summary, this invention effectively solves the industry problems of reliance on manual labor, low efficiency, and difficulty in optimization in bulk acoustic wave filter layout design, providing core support for achieving full-process automation of filter design.

[0092] Based on the same inventive concept as the above embodiments, the present invention provides an automatic filter layout generation device, which can execute the automatic filter layout generation method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method.

[0093] Figure 8 This is a schematic diagram of an automatic filter layout generation device provided in an embodiment of the present invention. Figure 8 As shown, the device includes: a parameter acquisition module 101, a model adjustment module 102, a constraint rule acquisition model 103, a first layout adjustment module 104, a second layout adjustment module 105, and a layout output module 106.

[0094] The system includes the following modules: a parameter acquisition module 101, used to acquire the circuit parameters and process parameters of the filter to be patterned; a model adjustment module 102, used to update the resonator model in the filter to be patterned based on the circuit parameters; a constraint rule acquisition model 103, used to acquire process constraint rules based on the process parameters, establish the rule mapping relationship corresponding to the process constraint rules, and update the resonator parameterization unit based on the rule mapping relationship and the resonator model; wherein the rule mapping relationship is used to determine the information of each layer of the resonator device; a first layout adjustment module 104, used to generate an optimization objective function based on the rule mapping relationship, and iteratively optimize the resonator layout structure based on the optimization objective function to obtain a first layout structure; a second layout adjustment module 105, used to adjust the shape of the resonator layout structure and the resonator model in the first layout structure based on a preset compression deformation algorithm to obtain a second layout structure; and a layout output module 106, used to generate a filter layout file based on the second layout structure.

[0095] Optionally, the first layout adjustment module 104 is configured to: establish an interlayer constraint cost item based on the degree of conformity between the actual spacing and the minimum spacing between different film layers; establish a same-layer constraint cost item based on the degree of satisfaction of the electrical performance layout requirements by the horizontal spatial relationship between the patterns within the same film layer; establish a connection relationship constraint cost item based on the degree of realization of the circuit connection relationship by the layout routing; and perform a weighted summation of the interlayer constraint cost item, the same-layer constraint cost item, and the connection relationship constraint cost item to establish an optimization objective function.

[0096] Optionally, the first layout adjustment module 104 is further configured to: use the position coordinates of each resonator device as optimization variables, and iteratively update the optimization variables with the goal of minimizing the optimization objective function; the first layout structure also satisfies at least one of the following optimization indicators: area utilization, distribution uniformity, input-output coupling isolation, and device spacing.

[0097] Optionally, the preset compression deformation algorithm is based on polygon shape adjustment, elastic mesh transformation, or elasticity model.

[0098] Optionally, the second layout adjustment module 105 is configured to: model all resonator devices in the first layout structure as elastic variable objects, and model the input, output and grounding devices in the first layout structure as inelastic objects, and establish an elastic mechanical model; apply dynamic compressive force to the elastic mechanical model in multiple preset compression directions based on preset constraints, so that the elastic variable objects produce elastic deformation, rotation and movement to fill the empty areas in the first layout structure; wherein, the preset constraints include at least one of the following: electrical performance constraints, connectivity constraints and parasitic effect constraints.

[0099] Optionally, the process parameters may include at least the resonator's film structure and minimum spacing.

[0100] Optionally, the constraint rule acquisition model 103 is configured to: establish a membrane set based on the membrane structure; acquire spacing type constraint rules between the same layer and different layers within the membrane set based on the minimum spacing; and establish a rule mapping relationship based on the mathematical expression of the spacing type constraint rules.

[0101] Optionally, the circuit parameters may include at least: the resonator area and the filter topology.

[0102] Optionally, the model adjustment module 102 is configured to: obtain the initial model of all resonator devices in the filter to be plotted; wherein the shape contour of the initial model is any one of the following: rectangular, pentagonal or convex polygonal; and perform area scaling processing on the initial model according to the resonator area to establish an updated resonator model.

[0103] Optionally, the layout output module 106 is configured to: automatically generate metal interconnect lines based on the connectivity constraints in the second layout structure, and add signal lines connecting the metal layers; convert the layout data containing metal interconnect lines and signal lines into a format, and output a layout file in a preset format; wherein the preset format is any one of the following: GDSII or OASIS format.

[0104] Optionally, the layout output module 106 is also configured to evaluate the filter layout file based on at least one of area utilization, routing completion rate, and design rule compliance.

[0105] Based on any of the above embodiments, the present invention also provides an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to execute the filter layout automatic generation method provided in any of the above embodiments.

[0106] Figure 9 This is a schematic diagram of an electronic device for implementing the automatic filter layout generation method of this invention. The electronic device is intended to represent various forms of digital computers, such as laptops, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0107] like Figure 9 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0108] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0109] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the automatic filter layout generation method described above.

[0110] In some embodiments, the above-described automatic filter layout generation method can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the above-described automatic filter layout generation method can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the above-described automatic filter layout generation method by any other suitable means (e.g., by means of firmware).

[0111] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0112] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0113] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0114] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0115] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0116] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system, addressing the shortcomings of traditional physical hosts and VPS servers, such as high management difficulty and weak business scalability.

[0117] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0118] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for automatically generating filter layouts, characterized in that, include: Obtain the circuit parameters and process parameters of the filter to be patterned; The resonator model in the filter to be plotted is updated based on the circuit parameters. Based on the process parameters, process constraint rules are obtained, a rule mapping relationship corresponding to the process constraint rules is established, and the parameterization unit is updated according to the rule mapping relationship and the resonator model; wherein, the rule mapping relationship is used at least to determine the information of each layer of the resonator device; An optimization objective function is generated based on the rule mapping relationship, and the resonator layout structure is iteratively optimized based on the optimization objective function to obtain a first layout structure; The shape of the resonator layout structure and the resonator model in the first layout structure is adjusted based on a preset compression deformation algorithm to obtain the second layout structure. Generate a filter layout file based on the second layout structure; The preset compression deformation algorithm is established based on polygon shape adjustment, elastic mesh transformation, or elastic mechanics model; The step of adjusting the shape of the resonator layout structure and the resonator model in the first layout structure based on a preset compression deformation algorithm to obtain the second layout structure includes: All resonator devices in the first layout structure are modeled as elastic and variable objects, and the input, output and grounding devices in the first layout structure are modeled as inelastic objects, thus establishing an elastic mechanical model. Based on preset constraints, dynamic compressive forces are applied to the elastic mechanical model in multiple preset compression directions, causing the elastic variable object to undergo elastic deformation, rotation, and movement to fill the empty areas in the first layout structure. The preset constraints include at least one of the following: electrical performance constraints, connectivity constraints, and parasitic effect constraints.

2. The automatic filter layout generation method according to claim 1, characterized in that, The step of generating an optimization objective function based on the rule mapping relationship, and iteratively optimizing the resonator layout structure based on the optimization objective function to obtain a first layout structure, includes: An interlayer constraint cost item is established based on the degree of conformity between the actual spacing and the minimum spacing between different film layers; The same-layer constraint cost item is established based on the degree to which the electrical performance layout requirements are met by the horizontal spatial relationship between the patterns within the same film layer. The cost item is constrained by establishing connection relationships based on the degree to which circuit connections are realized in the layout routing. The optimization objective function is established by weighted summation of the inter-layer constraint cost item, the same-layer constraint cost item, and the connection relationship constraint cost item.

3. The automatic filter layout generation method according to claim 2, characterized in that, The step of generating an optimization objective function based on the rule mapping relationship, and iteratively optimizing the resonator layout structure based on the optimization objective function to obtain a first layout structure, further includes: The position coordinates of each resonator device are used as optimization variables, and the optimization variables are iteratively updated with the goal of minimizing the optimization objective function. The first layout structure also satisfies at least one of the following optimization indicators: area utilization, distribution uniformity, input-output coupling isolation, and device spacing.

4. The automatic filter layout generation method according to claim 1, characterized in that, The process parameters include at least the resonator's film structure and minimum spacing; The step of obtaining process constraint rules based on the process parameters, establishing rule mapping relationships corresponding to the process constraint rules, and updating the parameterization unit according to the rule mapping relationships and the resonator model includes: A membrane layer assembly is established based on the aforementioned membrane structure; Based on the minimum spacing, obtain the spacing type constraint rules between the same layer and different layers within the membrane layer set; The rule mapping relationship is established based on the mathematical expression of the spacing type constraint rule.

5. The automatic filter layout generation method according to claim 1, characterized in that, The circuit parameters include at least: the resonator area and the filter topology; The step of updating the resonator model in the filter to be plotted based on the circuit parameters includes: Obtain an initial model of all resonator devices in the filter to be plotted; wherein the shape profile of the initial model is any one of the following: rectangular, pentagonal, or convex polygonal; The initial model is scaled based on the resonator area to create an updated resonator model.

6. The automatic filter layout generation method according to claim 1, characterized in that, The step of generating a filter layout file based on the second layout structure includes: Based on the connectivity constraints in the second layout structure, metal interconnect lines are automatically generated, and signal lines connecting the metal layers are added. The layout data containing the metal interconnect lines and the signal lines is converted into a format, and a layout file in a preset format is output. The preset format is either GDSII or OASIS format.

7. The automatic filter layout generation method according to any one of claims 1-6, characterized in that, After generating the filter layout file including the connecting film layer according to the second layout structure, the method further includes: The filter layout file is evaluated based on at least one of the following: area utilization, wiring completion rate, and design rule compliance.

8. An automatic filter layout generation device, characterized in that, The apparatus for implementing the automatic filter layout generation method according to any one of claims 1-7 comprises: The parameter acquisition module is used to acquire the circuit parameters and process parameters of the filter to be patterned; The model adjustment module is used to update the resonator model in the filter to be plotted according to the circuit parameters; A constraint rule acquisition model is used to acquire process constraint rules based on the process parameters, establish a rule mapping relationship corresponding to the process constraint rules, and update the parameterization unit according to the rule mapping relationship and the resonator model; wherein, the rule mapping relationship is used at least to determine the information of each layer of the resonator device; The first layout adjustment module is used to generate an optimization objective function according to the rule mapping relationship, and to iteratively optimize the resonator layout structure based on the optimization objective function to obtain a first layout structure. The second layout adjustment module is used to adjust the shape of the resonator layout structure and the resonator model in the first layout structure based on a preset compression deformation algorithm to obtain the second layout structure. The layout output module is used to generate a filter layout file based on the second layout structure; The preset compression deformation algorithm is established based on polygon shape adjustment, elastic mesh transformation, or elastic mechanics model; The step of adjusting the shape of the resonator layout structure and the resonator model in the first layout structure based on a preset compression deformation algorithm to obtain the second layout structure includes: All resonator devices in the first layout structure are modeled as elastic and variable objects, and the input, output and grounding devices in the first layout structure are modeled as inelastic objects, thus establishing an elastic mechanical model. Based on preset constraints, dynamic compressive forces are applied to the elastic mechanical model in multiple preset compression directions, causing the elastic variable object to undergo elastic deformation, rotation, and movement to fill the empty areas in the first layout structure. The preset constraints include at least one of the following: electrical performance constraints, connectivity constraints, and parasitic effect constraints.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the filter layout automatic generation method according to any one of claims 1-7.

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