Deinterlacing device based on shared register array
By implementing image deinterlacing through a hardware architecture with a shared register array, the problems of excessive chip area and increased system power consumption in existing technologies are solved, thereby improving processing efficiency and reducing circuit complexity.
Patent Information
- Application Number
- CN202411102707.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-12
- Publication Date
- 2026-02-13
AI Technical Summary
In existing technologies, image deinterlacing is achieved through software algorithms, resulting in excessively large chip areas and increased system power consumption.
A hardware architecture based on a shared register array is adopted to achieve image deinterlacing through multiple cascaded processing modules and a shared register group, thereby reducing circuit complexity and chip area.
It improves the efficiency of deinterlacing, reduces circuit complexity and chip area, and reduces the workload of design and verification.
Smart Images
Figure CN121528131A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the field of image processing, and in particular, to a de-interlacing device based on a shared register array. BACKGROUND
[0002] Interlaced and progressive are both methods of displaying moving pictures on a display device. In the interlaced method, each frame is divided into two fields and displayed alternately. In the progressive method, all pictures in each frame are displayed simultaneously. The scanning method of a common liquid crystal television is from left to right and from top to bottom, and a fixed number of frames are scanned per second.
[0003] In the progressive method, the entire scanning frame is displayed each time. If the frame rate of the progressive method is the same as the field rate of the interlaced method, the human eye will see a smoother image than the interlaced method, and the flicker is smaller compared to the interlaced method.
[0004] In the interlaced method, each frame is divided into two fields, and each field contains all the odd-numbered scanning lines or even-numbered scanning lines in a frame. Usually, the odd-numbered scanning lines are scanned first to obtain the first field, and then the even-numbered scanning lines are scanned to obtain the second field. In this way, the amount of data of the overall video source is halved, thereby reducing the overall data storage and transmission amount. Due to the visual persistence effect, the human eye will see smooth motion instead of flickering half-frame half-frame images. However, there will be almost unnoticed flicker, which makes the human eye prone to fatigue. When the content of the screen is a horizontal stripe, this flicker is particularly easy to notice. In addition, when performing post-processing on an image (such as keying), directly processing interlaced material will produce edge jaggy phenomenon, resulting in a decrease in picture quality. In the process of converting digital interlaced format to film and constructing relatively perfect progressive video, each frame needs to be a non-interlaced high-quality picture. Therefore, it is necessary to convert the interlaced image to a progressive image, i.e., to perform de-interlacing processing.
[0005] In the prior art, image de-interlacing processing is usually implemented through software algorithms, such as algorithms based on motion detection, motion estimation, motion compensation, motion adaptive, etc. However, the above algorithms will bring a large amount of cache, resulting in excessive chip area and increased system consumption. SUMMARY
[0006] The embodiments of this disclosure provide a deinterlacing device based on a shared register array. The deinterlacing processing of images is realized through the hardware architecture of the shared register array, which reduces the complexity of the circuit, reduces the workload of chip design and verification, and saves a lot of resources and chip area.
[0007] This disclosure provides a deinterlacing device based on a shared register array. The device includes: a deinterlacing processing module comprising multiple cascaded processing modules, configured to sequentially perform multiple processes on interlaced image field data to generate deinterlaced image frame data; a shared register array comprising multiple cascaded register groups, configured to store block information associated with the multiple processes in the register groups corresponding to the multiple processing modules; and a control module configured to control the multiple processing modules to perform the multiple processes based on the block information stored in the corresponding register groups in the multiple register groups, and to control the preceding register group in the multiple register groups to update the stored block information to the next-level register group.
[0008] In one embodiment of this disclosure, the control module is configured to generate a start signal for executing the current block processing, such that the subsequent processing module among the plurality of processing modules performs processing corresponding to the current block processing based on the processing result received from the previous processing module and the block information retrieved from the corresponding register group, according to the start signal.
[0009] In one embodiment of this disclosure, the control module is configured to generate an update signal after each of the plurality of processing modules has completed its corresponding processing, such that the previous level register group in the plurality of register groups stores the stored block information to the next level register group according to the update signal.
[0010] In one embodiment of this disclosure, the deinterlacing processing module includes a motion detection module, a motion estimation module, a motion compensation module, an enhanced edge-based interpolation module, a motion adaptation module, and an output detection module.
[0011] The motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module are configured to share block information associated with the plurality of processes to achieve deinterlacing of the image field data.
[0012] In one embodiment of this disclosure, the plurality of register groups are configured to store block information associated with a plurality of consecutive image field data.
[0013] In an embodiment of the present disclosure, the control module is configured to control the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module to process the image blocks simultaneously.
[0014] In an embodiment of the present disclosure, the control module is configured to update the shared register array once after completing the de-interlacing process for an image block, so that the block information of the previous register group is updated to the following register group, and the block information associated with the newly read image field data is updated to the first register group.
[0015] In an embodiment of the present disclosure, the shared register array only stores the block information required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the output detection module for the image block.
[0016] In an embodiment of the present disclosure, the de-interlacing device based on the shared register array further comprises a storage module configured to store a plurality of block information associated with a plurality of image field data, and provide the plurality of block information associated with the plurality of image field data to the shared register array based on the DMA controller.
[0017] In an embodiment of the present disclosure, the de-interlacing device based on the shared register array further comprises a first data buffer and a second data buffer configured to provide the plurality of block information associated with the plurality of image field data provided by the DMA controller to the shared register array through a ping-pong mechanism.
[0018] In an embodiment of the present disclosure, the de-interlacing device based on the shared register array further comprises a cache module configured to obtain the plurality of block information associated with the plurality of image field data in the storage module based on the DMA controller, and provide the plurality of block information associated with the plurality of image field data to the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module respectively based on the DMA controller.
[0019] In an embodiment of the present disclosure, when the DMA controller provides the plurality of block information associated with the plurality of image field data to the shared register array, the plurality of block information associated with the image field data is first read based on a row, and then the plurality of block information associated with the image field data is read based on an image block, wherein the image block is read in a left-to-right and top-to-bottom order.
[0020] In an embodiment of the present disclosure, the de-interlacing device based on the shared register array further comprises a parameter detection module configured to perform frame field detection, field sequence detection, pull-down detection and caption detection on the current image field data to generate detection parameters, so as to adjust the de-interlacing processing of the next image field data based on the detection parameters.
[0021] According to the embodiments of the present disclosure, the de-interlacing processing of the image is implemented through the hardware architecture of the shared register array, which effectively improves the efficiency of the de-interlacing processing and greatly reduces the chip area. At the same time, the circuit complexity is greatly reduced, and the workload of circuit design and verification is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 A schematic diagram showing a motion detection algorithm in an embodiment;
[0023] Figure 2 A schematic diagram showing a motion detection algorithm in an embodiment;
[0024] Figure 3 A search schematic diagram showing a motion estimation algorithm in an embodiment;
[0025] Figure 4 A search schematic diagram showing a motion estimation algorithm in an embodiment in the time domain;
[0026] Figure 5 A schematic diagram showing a motion compensation algorithm in an embodiment;
[0027] Figure 6 A schematic diagram showing an enhanced edge-based interpolation in an embodiment;
[0028] Figure 7 A schematic diagram showing a motion adaptive algorithm in an embodiment;
[0029] Figure 8A A block diagram showing a de-interlacing device based on a shared register array of the present disclosure in an embodiment;
[0030] Figure 8B A structural schematic diagram showing a de-interlacing device based on a shared register array of the present disclosure in an embodiment;
[0031] Figure 9 A data flow schematic diagram showing a de-interlacing device in an embodiment;
[0032] Figure 10 A schematic diagram showing a shared register array update in an embodiment of the present disclosure;
[0033] Figure 11The diagram shows a storage schematic of a shared register array in one embodiment of the present disclosure;
[0034] Figure 12 This diagram illustrates a data reading method for a shared register array in one embodiment of the present disclosure.
[0035] Figure 13 This diagram illustrates the data read sequence of a shared register array in one embodiment of the present disclosure. Detailed Implementation
[0036] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure.
[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Therefore, the drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0038] During deinterlacing, it is necessary to fill in the unscanned half-field pixels; these pixels that need to be filled are simply called padding points. The initial points obtained in order to acquire padding points are called candidate padding points. Typically, these candidate padding points come from multiple sources.
[0039] The main purpose of motion detection is to determine whether each point in an image is dynamic or static, so as to perform deinterlacing processing on dynamic and static points. For dynamic points, if a matching block can be found, candidate padding points are obtained from the positions after the movement in the temporal domain before and after the frame; if no matching block is found, the missing data is obtained by interpolation in the spatial domain (current frame). Figure 1 This is a schematic diagram illustrating a motion detection algorithm in an embodiment of the prior art. For example... Figure 1 As shown, a 16×4 block in the current frame is searched on the reference frame, with a range of ±20 in the vertical direction and ±XX in the horizontal direction. Normally, each block should store the image data from its left and right sides for use in the search.
[0040] Figure 2 This is a schematic diagram illustrating a motion estimation algorithm in an embodiment of the prior art. For example... Figure 2As shown, four fields of data are combined to form two frames (Frame0 and Frame1). Then, by performing an MxN matrix operation on the same location, it is determined whether each point (such as the center point in the box) is dynamic or static.
[0041] Motion estimation is used to determine whether a matching block can be found. Figure 3 This diagram illustrates a search scenario in one embodiment of a prior art motion estimation algorithm. Figure 3 As shown, T2 and B3 are the current input fields, and matching blocks will be searched on T4 and B5 or T0 and B1. This search is performed on a block-by-block basis, with each block searched a certain number of times. For example, if the block size is set to 16×4, it will actually be searched using 16×6 or similar methods. The search method can be based on algorithms such as 3-dimensional recursive search (3DRS). Figure 4 The display shows a temporal search diagram of the block in the current field relative to the previous and next fields. Finally, motion estimation generates a motion vector for each block.
[0042] Motion compensation involves finding candidate fill points by moving them from the front and back fields in the time domain after a matching block has been found. Figure 5 This is a schematic diagram illustrating a motion compensation calculation method in the prior art in one embodiment. For example... Figure 5 As shown, motion compensation is performed based on the motion vector (mv) and the foreground and background fields.
[0043] Enhanced Edge-based Interpolation (EEDI) refers to the process of backtracking to use interpolation points to fill in missing data when a pixel is in motion but no matching block can be found. Figure 6 The diagram shown illustrates an embodiment of enhanced edge-based interpolation in the prior art. (See diagram for example.) Figure 6 As shown, candidate fill points are obtained in the other half of the field in the current field space by interpolation.
[0044] Motion adaptation refers to the fusion processing of static candidate fill points at the same position in the temporal direction, candidate fill points obtained by motion compensation, and candidate fill points obtained by enhanced edge-based interpolation. Figure 7 This is a schematic diagram illustrating a motion adaptive algorithm in one embodiment of the prior art. For example... Figure 7 As shown, some parameters are added during the fusion process, such as motion-static decision parameters obtained from motion detection, and other weight information.
[0045] After motion adaptive processing, there can be a judgment error to cause a final image to have a pull-out. Therefore, output image detection (CHECK) is needed. When image detection is performed and it is detected that there is a pull-out, some rollback operation is needed, and finally image data after de-interlacing is output.
[0046] The shared register array based de-interlacing device according to embodiments of the present disclosure is described below with specific examples.
[0047] Figure 8A A block diagram of a shared register array based de-interlacing device according to embodiments of the present disclosure is shown. As Figure 8A shown, the shared register array based de-interlacing device 800 includes a de-interlacing processing module 802, a shared register array 804, and a control module 806.
[0048] The de-interlacing processing module 802 includes a plurality of processing modules in cascade, and is configured to successively perform a plurality of processes on interlaced image field data by the plurality of processing modules to generate de-interlaced image frame data. In some embodiments, the de-interlacing processing module 802 can include any known module for performing de-interlacing image processing.
[0049] The shared register array 804 includes a plurality of register groups in cascade, and is configured to store respective block information associated with the plurality of processes in the plurality of register groups corresponding to the plurality of processing modules.
[0050] The control module 806 is configured to control the plurality of processing modules to perform the plurality of processes based on block information stored in a corresponding register group of the plurality of register groups, respectively, and control a previous stage register group of the plurality of register groups to update and store the stored block information to a next stage register group.
[0051] Figure 8B A structural schematic diagram of a shared register array based de-interlacing device according to embodiments of the present disclosure is shown. As Figure 8B shown, in some embodiments, the de-interlacing processing module can include a motion detection module (MD), a motion estimation module (ME), a motion compensation module (MC), an enhanced edge-based interpolation module (EEDI), a motion adaptive module (MA), and an output detection module (CHECK), etc. The motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module, and the output detection module are configured to share respective block information associated with the plurality of processes to achieve de-interlacing processing of the image field data.
[0052] In addition, asFigure 8B As shown, the shared register array includes multiple register groups TILE0, TILE1, TILE2, TILE3, and TILE4. These register groups are configured to store block information associated with multiple consecutive image field data.
[0053] Figure 9 This is a schematic diagram illustrating the data flow according to an embodiment of this disclosure. For example... Figure 9 As shown, in some embodiments, when the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module each set their own buffer BUF, the required buffer BUF capacity is very large. Therefore, this disclosure uses the shared register array to simultaneously provide each processing module with shared block information associated with multiple consecutive image field data, thereby effectively reducing data buffer capacity, reducing chip area, and improving data processing efficiency.
[0054] In some embodiments, the shared register array includes multiple registers (e.g., TILE0, TILE1, TILE2, TILE3, TILE4) configured to store multiple consecutive block information associated with image field data. In some embodiments, the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module each require all or part of the multiple consecutive block information associated with the image field data. For example, the motion estimation module may actually use information stored in TILE0, TILE1, TILE2, TILE3, TILE4.
[0055] The shared register array is composed of registers, characterized by its stable output until new data is written. Each bit has an input and an output, and the output can be directly sent to various modules, enabling high-bandwidth data output. For example, if the motion estimation module needs 16 × 6 × 8 bits = 768 bits of data per frame during calculation, it can obtain this directly from the shared register array, whereas the bandwidth obtained through MEM storage is very limited. For instance, a large SPRF1920×128 MEM with only one read / write port can read 128 bits of data per frame at its peak, and averages 64 bits of data per frame when read / write operations are fully utilized.
[0056] In some embodiments, the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the output detection module simultaneously process in units of image tiles, and the image tiles are obtained by scanning from top to bottom and from left to right. It should be noted that, according to different application requirements, the size of the image tile can be 16x6, 16x4, 16x2, etc. When the image tile is selected, the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the output detection module select the data required by themselves from the shared register array through a data selector MUX. The above-mentioned processing modules can select different data selectors MUX. For example, some modules select data through a counter COUNT, and some modules select data through a candidate motion vector mv (for example, the motion estimation module uses the algorithm of 3DRS, and in the operation process, 16x6 data is selected from the shared register array according to the candidate motion vector mv for operation multiple times).
[0057] In some embodiments, the control module is configured to generate a start signal for performing current block processing, so that a next stage processing module in the plurality of processing modules performs processing corresponding to the current block processing based on the processing result received from a previous stage processing module and the block information retrieved from the corresponding register group according to the start signal. For example, the control module uniformly generates a start signal for starting operation of each module for the current image tile, which is named as ctrl_xxx_start_p, where xxx is the alias of each module. The signal is a pulse signal, which indicates that the image tile data required by the module is ready, and the operation task is started. At the same time, the control module has a special counter for obtaining the coordinates of each image tile in a frame of image. After receiving the pulse signal, each processing module starts a state machine, reads the corresponding block information from the shared register array, and completes the operation task in a specified time slice according to the respective operation logic.
[0058] Each processing module stores its own operation result for the current image block tile and outputs to the next level processing module for use. The next level processing module stores the operation result provided by the previous level module when receiving the ctrl_xxx_start_p signal. Taking the motion detection module and the motion estimation module as examples, the motion detection module will obtain 16x4 motion and static judgment results for each image block tile, and has 16x4 register storage units inside to save these operation results. When the motion estimation module receives the ctrl_me_start_p pulse signal, it will store these results in its own internal unit in one frame of time. For another example, the motion estimation module provides the motion vector mv of the current image block tile to the motion compensation module. The enhanced edge-based interpolation module provides two 16x2 image interpolation results obtained by interpolation to the motion adaptive module. The motion compensation module provides two 16x2 motion compensation results to the motion adaptive module. In some embodiments, the control module is configured to generate an update signal after each of the plurality of processing modules completes the corresponding processing, so that the previous level register group in the plurality of register groups stores the stored block information to the next level register group according to the update signal.
[0059] In some embodiments, the de-interlacing device based on the shared register array of the present disclosure can further comprise a storage module. The storage module is configured to store a plurality of block information associated with a plurality of image field data, and provide the plurality of block information associated with the plurality of image field data to the shared register array based on a DMA (Direct Memory Access) controller. In some embodiments, the storage module employs a DDR. The DDR stores image field data obtained by de-interlacing, and the image field data is provided to the shared register array and the input FIFO of the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module by the DMA controller, so as to facilitate the respective processing modules to perform their own data processing. It should be noted that the data required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module comes from the shared register array, the input FIFO and the output data of the previous stage module. The required data for different modules can be different, which will not be described here. The data in the input FIFO is directly used by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module, and is not sent to the shared register array. The input FIFO is used to buffer data, because a long latency is required from the data fetch command to the obtained data, and the performance loss caused by the latency is compensated by buffering data. In addition, the de-interlaced image frame data obtained by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module is stored in the storage module based on the DMA controller.
[0060] In some embodiments, the de-interlacing device based on the shared register array of the present disclosure can further comprise a cache module ORGLINEBUF. The cache module is configured to obtain a plurality of block information associated with a plurality of image field data in the storage module based on a DMA controller, and provide the plurality of block information associated with the plurality of image field data to the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module based on the DMA controller. By providing the required data to the register array quickly through the cache module ORGLINEBUF, the speed of de-interlacing processing can be accelerated, and additional data fetching can be avoided, thereby reducing the data fetching bandwidth.
[0061] In some embodiments, the control module is configured to update the shared register array once after one de-interlacing process for an image block is completed, so that the block information of the previous stage register group is updated to the following register group, and the block information associated with the newly read image field data is updated in the first register group.
[0062] Figure 10 A schematic diagram of the shared register array update according to embodiments of the present disclosure is shown. As shown, the block information of TILE3 is updated to TILE4, the block information of TILE2 is updated to TILE3, the block information of TILE1 is updated to TILE2, the block information of TILE0 is updated to TILE1, and the new block information of TILE0 is read from the shared register array, the input FIFO, and the cache module ORG LINE BUF. Figure 10
[0063] In some embodiments, each of the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module, and the detection module sends a ready signal after completing the operation of the current image block tile. After all modules complete the operation of their current image block tile, a unified update of the shared register array is performed to start the operation of the next image block tile of each module. It should be noted that, in order to avoid a large power peak caused by updating too many memories at one time, the shared memory array update is divided into two strokes, and TILE2, TILE3, and TILE4 are updated first, and the other TILES are updated one stroke later, so that the power peak can be reduced by half.
[0064] In some embodiments, the shared register array only stores the block information required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module, and the output detection module for the image block.
[0065] Figure 11 A storage schematic diagram of the shared register array according to embodiments of the present disclosure is shown. As shown, Figure 11 As shown, each small circle in the figure represents a pixel point. The line of registers where the current frame Cur is located indicates that the register array is used to store the block information of the current frame Cur, and the Nxt frame is the same. Taking the motion estimation module as an example, the current image block tile is TILE2. In order to realize image block matching, it will search for a matching image block in the shared register array centered on TILE2 and expand 28 left and right. Other modules are the same. Therefore, the shared register array in the present disclosure only stores the block information required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module. The image frame data range used by each processing module to complete the operation of the current image block is different. In order to save area, only the union of the data required by each processing module is stored, and all data does not need to be stored. For example Figure 11 As shown, when TILE1 provides data to TIEL2, some useless data will be discarded. For each TILE, the more data discarded to the right.
[0066] Figure 12 The figure shows the data reading mode of the shared register array according to an embodiment of the present disclosure. As shown Figure 12 As shown, in some embodiments, the de-interlacing device based on the shared register array of the present disclosure can further include a first data buffer DATA_IN_BUF0 and a second data buffer DATA_IN_BUF1. The first data buffer DATA_IN_BUF0 and the second data buffer DATA_IN_BUF1 are configured to provide a plurality of block information associated with the plurality of image field data provided by the DMA controller to the shared register array through a ping-pong mechanism. From the command to obtain data, there is a long latency. In order to make up for the performance loss caused by the latency, the present disclosure adopts the ping-pong data acquisition scheme. For example, in the T0 time period, DATA_IN_BUF0 is configured to receive the block information provided by the DDR, and DATA_IN_BUF1 is configured to update the data of the shared register array. When DATA_IN_BUF0 has been filled with data, DATA_IN_BUF1 has been emptied. Enter the T1 time period, DATA_IN_BUF1 is configured to receive the block information provided by the DDR, and DATA_IN_BUF0 is configured to update the data of the shared register array.
[0067] In some embodiments, when the DMA controller provides the plurality of block information associated with the plurality of image field data to the shared register array, the plurality of block information associated with the image field data is first read based on a row, and then the plurality of block information associated with the image field data is read based on an image block, wherein the image block is read in a left-to-right and top-to-bottom order.
[0068] Figure 13 A diagram showing the data read order of the shared register array according to an embodiment of the present disclosure. As shown, for each block information, row fetching is first performed, and then block fetching is performed. It should be noted that, in order to maintain the friendliness of the storage module DDR, the fetching block is larger than the size of the image block tile, for example, the fetching block can be 256x4, and the image block tile is 16x4. When row fetching is performed, the number of rows is related to the vertical extension of the related module, for example, when motion estimation is performed, up and down extension is required. Figure 13
[0069] In some embodiments, the de-interlacing device based on the shared register array of the present disclosure can further comprise a parameter detection module. The parameter detection module is configured to perform frame field detection, field sequence detection, pull-down detection and subtitle detection on the current image field data to generate detection parameters, so as to adjust the de-interlacing processing of the next image field data based on the detection parameters. It should be noted that the detection parameters are provided to the CPU, and the CPU provides the detection parameters to the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptive module and the detection module, so that each module adjusts the processing parameters of the next image frame data in real time.
[0070] The above embodiments are only illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the present disclosure should be covered by the claims of the present disclosure.
Claims
1. A deinterlacing device based on a shared register array, characterized in that, include: The deinterlacing processing module includes multiple cascaded processing modules and is configured to perform multiple processing steps on the interlaced image field data to generate deinterlaced image frame data. A shared register array, comprising multiple cascaded register groups, is configured to store block information associated with the multiple processes in the multiple register groups corresponding to the multiple processing modules. as well as The control module is configured to control the plurality of processing modules to perform the plurality of processes based on the block information stored in the corresponding register groups of the plurality of register groups, and to control the previous level register group of the plurality of register groups to update the stored block information to the next level register group.
2. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The control module is configured to generate a start signal for executing the current block processing, such that the subsequent processing module among the plurality of processing modules performs processing corresponding to the current block processing based on the processing result received from the previous processing module and the block information retrieved from the corresponding register group, according to the start signal.
3. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The control module is configured to generate an update signal after each of the multiple processing modules has completed its corresponding processing, so that the previous level register group in the multiple register groups stores the stored block information to the next level register group according to the update signal.
4. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The deinterlacing module includes a motion detection module, a motion estimation module, a motion compensation module, an enhanced edge-based interpolation module, a motion adaptation module, and an output detection module. The motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module are configured to share block information associated with the plurality of processes to achieve deinterlacing of the image field data.
5. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The multiple register groups are configured to store block information associated with multiple consecutive image field data.
6. The deinterlacing device based on a shared register array according to claim 4, characterized in that, The control module is configured to control the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module to simultaneously perform their respective processing on an image patch basis.
7. The deinterlacing device based on a shared register array according to claim 6, characterized in that, The control module is configured to update the shared register array once after a deinterlacing process is completed for an image block, such that the block information of the previous register group is updated in the subsequent register group, and the block information associated with the newly read image field data is updated in the first register group.
8. The deinterlacing device based on a shared register array according to claim 6, characterized in that, The shared register array stores only the block information required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module for the image patch.
9. The deinterlacing device based on a shared register array according to claim 1, characterized in that, It also includes a storage module configured to store multiple block information associated with multiple image field data, and to provide the multiple block information associated with the multiple image field data to the shared register array based on the DMA controller.
10. The deinterlacing device based on a shared register array according to claim 9, characterized in that, It also includes a first data cache and a second data cache, which are configured to provide multiple block information associated with the multiple image field data provided by the DMA controller to the shared register array via a ping-pong mechanism.
11. The deinterlacing device based on a shared register array according to claim 9, characterized in that, It also includes a caching module, which is configured to acquire multiple block information associated with the multiple image field data in the storage module based on the DMA controller, and provide the multiple block information associated with the multiple image field data to the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module and the detection module respectively based on the DMA controller.
12. The deinterlacing device based on a shared register array according to claim 9, characterized in that, When the DMA controller provides multiple block information associated with the multiple image field data to the shared register array, it first reads the multiple block information associated with the image field data based on rows, and then reads the multiple block information associated with the image field data based on image blocks. When reading the image blocks, the order is from left to right and from top to bottom.
13. The deinterlacing device based on a shared register array according to claim 1, characterized in that, It also includes a parameter detection module, which is configured to perform frame field detection, field order detection, drop-down detection, and subtitle detection on the current image field data to generate detection parameters, and to adjust the deinterlacing processing of the next image field data based on the detection parameters.