Display device and electronic device

Abstract

According to the aspect of the disclosure, the invention provides a display device and an electronic device. The display device includes a first transistor connected between a driving voltage line and a second node, a sixth transistor connected between the second node and a common voltage line, a light emitting element connected between the sixth transistor and the common voltage line, and a fourth transistor connected between the second node and an initialization voltage line.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0107275, filed on August 12, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device that can improve its image quality and power consumption. Background Technology

[0003] Organic light-emitting display devices include display elements whose brightness is changed by an electric current, such as organic light-emitting diodes (OLEDs). Summary of the Invention

[0004] This disclosure provides a display device that can improve its image quality and power consumption.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0006] According to an aspect of this disclosure, a display device is provided, the display device comprising: a first transistor connected between a driving voltage line and a second node; a sixth transistor connected between the second node and a common voltage line; a light-emitting element connected between the sixth transistor and the common voltage line; and a fourth transistor connected between the second node and an initialization voltage line.

[0007] The initial voltage of the initialization voltage line can be less than the driving voltage of the driving voltage line.

[0008] The display device may further include: a second transistor connected between the data line and the first node; a third transistor connected between the third node and the second node; a fifth transistor connected between the drive voltage line and the first node; and a seventh transistor connected between the bias voltage line and the first node, wherein the first transistor is connected between the first node and the second node, and wherein the gate electrode of the first transistor is connected to the third node.

[0009] The display device may further include: a write gate line connected to the gate electrode of a second transistor; a compensation gate line connected to the gate electrode of a third transistor; an initialization gate line connected to the gate electrode of a fourth transistor; a first emitter line connected to the gate electrode of a fifth transistor; a second emitter line connected to the gate electrode of a sixth transistor; a bias gate line connected to the gate electrode of a seventh transistor; and a capacitor connected between the drive voltage line and the third node.

[0010] The write gate line can be configured to transmit a write gate signal, the compensation gate line can be configured to transmit a compensation gate signal, the initialization gate line can be configured to transmit an initialization gate signal, the first emitter line can be configured to transmit a first emitter signal, the second emitter line can be configured to transmit a second emitter signal, the bias gate line can be configured to transmit a bias gate signal, the drive voltage line can be configured to transmit a drive voltage, the common voltage line can be configured to transmit a common voltage, the initialization voltage line can be configured to transmit an initialization voltage, and the bias voltage line can be configured to transmit a bias voltage.

[0011] During the first time period, the second transmit signal and the initialization gate signal may have valid levels, while the first transmit signal, the compensation gate signal, the write gate signal, and the bias gate signal may have invalid levels.

[0012] In the second period following the first period, the compensation gate signal and the bias gate signal may have valid levels, and the first transmit signal, the second transmit signal, the initialization gate signal, and the write gate signal may have invalid levels.

[0013] In the third period following the second period, the initial gate signal and the compensation gate signal may have valid levels, and the first transmit signal, the second transmit signal, the write gate signal, and the bias gate signal may have invalid levels.

[0014] In the fourth period following the third period, the compensation gate signal and the write gate signal may have active levels, the first transmit signal, the second transmit signal, the initialization gate signal, and the bias gate signal may have inactive levels, and the data voltage is provided to the data line.

[0015] In the fifth period following the fourth period, the compensation gate signal may have an active level, and the first transmit signal, the second transmit signal, the initialization gate signal, the write gate signal, and the bias gate signal may have inactive levels.

[0016] In the sixth period following the fifth period, the bias gate signal may have an active level, and the first transmit signal, the second transmit signal, the initialization gate signal, the compensation gate signal, and the write gate signal may have inactive levels.

[0017] In the seventh period following the sixth period, the initialization gate signal may have an active level, and the first transmit signal, the second transmit signal, the compensation gate signal, the write gate signal, and the bias gate signal may have inactive levels.

[0018] In the eighth period following the seventh period, the first and second transmit signals may have valid levels, while the initial gate signal, the compensation gate signal, the write gate signal, and the bias gate signal may have invalid levels.

[0019] The fourth transistor may include a transistor of a different type than the first, second, fifth, sixth, and seventh transistors.

[0020] The fourth transistor may include an n-type transistor, and the first, second, fifth, sixth, and seventh transistors may include p-type transistors.

[0021] The third transistor may include transistors of the same type as the fourth transistor.

[0022] The third and fourth transistors may include n-type transistors.

[0023] The driving voltage line may include a lower driving voltage line and an upper driving voltage line above the lower driving voltage line and connected to the lower driving voltage line through contact holes in the insulating layer.

[0024] The lower drive voltage line may include extended electrodes.

[0025] The extended electrode can be stacked with the first emitter line, the second emitter line, and the bias voltage line.

[0026] According to an aspect of this disclosure, an electronic device including a display device is provided, the display device including a first transistor connected between a driving voltage line and a second node, a sixth transistor connected between the second node and a common voltage line, a light-emitting element connected between the sixth transistor and the common voltage line, and a fourth transistor connected between the second node and an initialization voltage line. Attached Figure Description

[0027] These and / or other aspects will become apparent and more readily understood from the following description of embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view of a display device according to one or more embodiments; Figure 2 This is a cross-sectional view of a display device according to one or more embodiments; Figure 3 It is a plan view of the display of a display device according to one or more embodiments; Figure 4 It is a block diagram of a display panel and a display driver according to one or more embodiments; Figure 5 It is a circuit diagram of the pixels of a display device according to one or more embodiments; Figure 6 yes Figure 5 Timing diagram of the first transmit signal, the second transmit signal, the initial gate signal, the compensation gate signal, the write gate signal, and the bias gate signal; Figure 7 It is used for explanation Figure 5 pixels in Figure 6 A diagram of the operations during the first time period; Figure 8 It is used for explanation Figure 5 pixels in Figure 6 A diagram of the operations during the second time period; Figure 9 It is used for explanation Figure 5 pixels in Figure 6 A diagram of the operations during the third time period; Figure 10 It is used for explanation Figure 5 pixels in Figure 6 A diagram of the operations in the fourth time period; Figure 11 It is used for explanation Figure 5 pixels in Figure 6 A diagram of the operations during the fifth time period; Figure 12 It is used for explanation Figure 5 pixels in Figure 6 A diagram of the operations during the sixth time period; Figure 13 It is used for explanation Figure 5 pixels in Figure 6 A diagram of the operations during the seventh time period; Figure 14 It is used for explanation Figure 5 pixels in Figure 6 A diagram of the operations during the eighth time period; Figure 15 The simulated waveforms of the first transmit signal, the second transmit signal, the bias gate signal, the compensation gate signal, the initialization gate signal, the write gate signal, the voltage of the source electrode of the first transistor, the voltage of the gate electrode of the first transistor, the voltage of the drain electrode of the first transistor, the voltage of the anode of the light-emitting element, and the current of the light-emitting element are shown. Figure 16 The diagram shows analog waveforms used to explain aspects of a display device according to one or more embodiments; Figure 17 It is a plan view of the pixel array of a display device according to one or more embodiments; Figure 18 yes Figure 17 A planar view of only the first pattern layer; Figure 19 yes Figure 17 A plan view of only the second pattern layer; Figure 20 yes Figure 17 A plan view of only the third pattern layer; Figure 21 yes Figure 17 A plan view of only the fourth pattern layer; Figure 22 yes Figure 17 A plan view of only the fifth pattern layer; Figure 23 yes Figure 17 A plan view of only the sixth pattern layer; Figure 24 yes Figure 17 A plan view of only the seventh pattern layer; Figure 25 yes Figure 17 A plan view of only the eighth pattern layer; Figure 26 yes Figure 17 A plan view of only the second and third pattern layers; Figure 27 yes Figure 17 The plan view of only the fifth and sixth pattern layers; Figure 28 This is a plan view of the seventh pattern layer of a display device according to one or more embodiments; Figure 29 yes Figure 23 The sixth pattern layer and Figure 28 A plan view of the seventh pattern layer; Figure 30 This is a block diagram of an electronic device according to one embodiment; and Figure 31 , Figure 32 and Figure 33 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0028] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments or are not essential for a full understanding of aspects of this disclosure by those skilled in the art may be omitted. Unless otherwise stated, the same reference numerals, symbols, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated description may be omitted.

[0029] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of “may,” “may,” or “may not” corresponds to one or more embodiments of this disclosure.

[0030] In view of the full contents of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable way.

[0031] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, the disclosure is not limited thereto because the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for ease of description. Additionally, crosshairs and / or shading are typically used in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, scale, commonalities among the elements shown, and / or any other characteristics, properties, etc.

[0032] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations of examples and / or intervening structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances will be expected. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shape due to, for example, manufacturing processes.

[0033] For ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “lower side,” “below,” “above,” “upper,” “above,” “higher,” “upper side,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and another element or feature. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to also encompass different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can encompass both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged on the upper or lower side of the second part, and is not limited to the upper side of the second part based on the direction of gravity.

[0034] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic sectional view" means when viewing a schematic section taken by vertically cutting the portion of the object from the side. The terms "overlapping with" or "overlapping" mean that the first object may be above, below, or to the side of the second object, or vice versa. Additionally, the term "overlapping with" can include stacking, facing or oriented, extending over, covering or partially covering, or any other suitable terms as will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping with" can include meanings such as "separated from," "offset from," or "deviation from," and any other suitable equivalents as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can mean that the first object may be directly or indirectly opposite the second object. In cases where a third object is placed between the first and second objects, although the first and second objects still face each other, they can be understood as being indirectly opposite each other.

[0035] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed on," "on," "connected to," or "(operationally, functionally, or communicatively) incorporated into" another component, layer, region, or assembly, it can be directly formed on, directly on, directly connected to, or directly incorporated into the other component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or indirectly incorporated into the other component, layer, region, or assembly, such that one or more intermediary components, layers, regions, or assemblies may be present. Furthermore, this can collectively mean direct or indirect incorporation or connection, as well as integral or non-integral incorporation or connection. For example, when a layer, region, or component is referred to as "electrically connected" or "electrically bonded" to another layer, region, or component, it can be directly electrically connected or directly bonded to said other layer, region, and / or component, or one or more intermediary layers, regions, or components may be present. One or more intermediary components may include switches, transistors, resistors, inductors, capacitors, and / or diodes, etc. Therefore, the connection is not limited to the connections shown in the accompanying drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "directly connected / directly bonded" or "directly on" means that a component is directly connected or directly bonded to another component or directly on another component without an intermediary component.

[0036] Furthermore, in this specification, when a portion of a layer, film, region, plate, etc., is formed on another portion, the formation direction is not limited to the upward direction, but includes forming the portion on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, plate, etc., is formed "below" another portion, this includes not only the case where the portion is "directly below" the other portion, but also the case where there is another portion between the portion and the other portion. Similarly, other expressions describing the relationship between components, such as "between," "immediately adjacent to," or "adjacent to" and "directly adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0037] For the purposes of this disclosure, expressions such as “at least one of…” or “any one of…” or “one or more of…” modify the entire list of elements when following a list of elements, without modifying any individual element in that list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when expressions such as “at least one of…”, “multiple (species / beings)…”, “one of…”, and other prepositional phrases follow (before) a list of elements, they modify the entire list of elements, not individual elements within that list. When “C to D” is stated, unless otherwise specified, it means C or greater and D or less.

[0038] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, part, or component from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, first assembly, first region, first layer, or first part described below may be designated as a second element, second assembly, second region, second layer, or second part. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0039] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0040] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms, and the plural forms are intended to include the singular forms. It will also be understood that when the terms “comprising,” “having,” “including,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0041] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. For example, “substantially” can include a range of + / - 5% of the corresponding value. As used herein, “about” or “approximately” includes the stated value and means: within an acceptable deviation range of the specific value as determined by one of ordinary skill in the art, taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, the use of “may” when describing embodiments of this disclosure refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range that is tolerable by one of ordinary skill in the art. Other expressions may also be those from which “substantially” has been omitted.

[0042] In some embodiments, well-known structures and arrangements may be described in conjunction with one or more functional blocks (e.g., block diagrams), units, and / or modules in the accompanying drawings to avoid unnecessarily obscuring various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware performing some functions and processors performing functions different from those of the dedicated hardware (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, in some embodiments, blocks, units, and / or modules may be physically separated into two or more interacting individual blocks, units, and / or modules without departing from the scope of this disclosure. In addition, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of this disclosure.

[0043] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or in the context of this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0044] According to one or more embodiments of the display device, flicker can be reduced or minimized even when the display device is driven at a low frequency. Furthermore, according to one or more embodiments of the display device, leakage current and voltage drop can be reduced. Additionally, according to one or more embodiments of the display device, the image corresponding to the black grayscale level can be accurately represented even when the image rapidly changes from a white grayscale level to a black grayscale level. Furthermore, according to one or more embodiments of the display device, the swing width of the data voltage can be reduced. Therefore, according to one or more embodiments of the display device, image quality and power consumption can be improved.

[0045] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the claims.

[0046] Figure 1 This is a perspective view of a display device 10 according to one or more embodiments.

[0047] Reference Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display for televisions, laptops, monitors, billboards, or Internet of Things (IoT) devices. As another example, the display device 10 can be applied to wearable devices such as smartwatches, watch phones, glasses displays, and head-mounted displays.

[0048] The display device 10 may have a planar shape similar to a quadrilateral. For example, the display device 10 may have a planar shape similar to a quadrilateral having a short side in the first direction DR1 and a long side in the second direction DR2. Each corner where the short side extending in the first direction DR1 intersects the long side extending in the second direction DR2 may be rounded to have a corresponding curvature or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0049] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, a touch driver 400, and a power supply 500.

[0050] The display panel 100 may include a main area MA and a sub-area SBA.

[0051] The main region MA may include a display region DA containing pixels for displaying an image and (e.g., in a plan view) a non-display region NDA located around the display region DA. The display region DA may emit light from multiple emission regions or multiple aperture regions. For example, the display panel 100 may include pixel circuitry containing switching elements, a pixel defining layer defining the emission region or aperture region, and self-emissive elements.

[0052] For example, each of the self-emissive elements may include, but is not limited to, at least one of an organic light-emitting diode including an organic light-emitting layer, a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, and a micro light-emitting diode.

[0053] The non-display area NDA can be a region outside the display area DA. The non-display area NDA can be defined as the edge region of the main area MA of the display panel 100. In one or more embodiments, the non-display area NDA may include a gate driver that supplies gate signals to the gate lines and a fan-out line that connects the display driver 200 and the display area DA.

[0054] A sub-region SBA can extend from one side of the main region MA. The sub-region SBA can include a flexible material that can be bent, folded, rolled, etc. For example, when the sub-region SBA is bent, it can be stacked on top of the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA can include a display driver 200 and pads (or "solder pads") (e.g., pad units) connected to the circuit board 300. Optionally, the sub-region SBA can be omitted, and the display driver 200 and pads can be located in a non-display area NDA.

[0055] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltage to data lines. The display driver 200 can supply power voltage to power lines and can supply gate control signals to gate drivers. The display driver 200 can be formed as an integrated circuit and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be located in a sub-region SBA and can be stacked with the main region MA in the thickness direction (third direction DR3) by bending the sub-region SBA. In another example, the display driver 200 can be mounted on a circuit board 300.

[0056] The circuit board 300 can be attached to the pad of the display panel 100 using an anisotropic conductive film. The leads of the circuit board 300 can be electrically connected to the pad of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0057] The touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be electrically connected to the touch sensor (e.g., touch sensing unit) of the display panel 100. The touch driver 400 can supply touch drive signals to multiple touch electrodes of the touch sensor and sense changes in capacitance between the touch electrodes. For example, the touch drive signal can be a pulse signal with a frequency (e.g., a predetermined frequency). The touch driver 400 can determine whether an input has been made based on the changes in capacitance between the touch electrodes and calculate the coordinates of the input. The touch driver 400 can be formed as an integrated circuit.

[0058] Power supply 500 may be located on circuit board 300 and may supply power voltage to display driver 200 and display panel 100 (as used herein, "located on" may mean "above"). Power supply 500 may generate drive voltage and supply drive voltage to drive voltage line VDL (see...). Figure 3 This can generate an initialization voltage and supply it to the initialization voltage line, generate a bias voltage and supply it to the bias voltage line, and generate a common voltage and supply it to the common voltage line. Here, the common voltage of the common voltage line can be supplied to multiple pixels PX (see...). Figure 3 ) light-emitting element ED (see Figure 5 A common cathode. The driving voltage can be a high potential voltage used to drive the light-emitting element (ED), and the common voltage can be a low potential voltage used to drive the light-emitting element (ED).

[0059] Figure 2This is a cross-sectional view of a display device 10 according to one or more embodiments.

[0060] Reference Figure 2 The display panel 100 may include a display DU, a touch sensor TSU, and a color filter layer CFL. The display DU may include a substrate SUB, a thin film transistor layer TFTL, a light-emitting element layer EMTL, and an encapsulation layer ENC.

[0061] The substrate SUB can be a matrix substrate or a matrix component. The substrate SUB can be a flexible substrate that can be bent, folded, rolled, etc. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but this disclosure is not limited thereto. As another example, the substrate SUB can include a glass material or a metal material.

[0062] The thin-film transistor layer (TFTL) can be located on the substrate SUB. The TFTL can include multiple thin-film transistors constituting pixel circuitry. The TFTL can also include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 and the data lines, and leads connecting the display driver 200 and the pad. Each of the thin-film transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, it can include a thin-film transistor.

[0063] The thin-film transistor layer (TFTL) can be located in the display area (DA), the non-display area (NDA), and the sub-area (SBA). The thin-film transistors, gate lines, data lines, and power lines of the pixels of the TFTL can be located in the display area (DA). The gate control lines and fan-out lines of the TFTL can be located in the non-display area (NDA). The leads of the TFTL can be located in the sub-area (SBA).

[0064] The light-emitting element layer (EMTL) can be located on the thin-film transistor layer (TFTL). The EMTL may include multiple light-emitting elements (EDs) sequentially stacked to emit light, a first electrode (hereinafter referred to as the anode), a light-emitting layer, and a second electrode (hereinafter referred to as the cathode), and a pixel defining layer defining pixels. The light-emitting elements (EDs) of the EMTL may be located in the display area (DA).

[0065] For example, the light-emitting layer can be an organic light-emitting layer comprising organic materials. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the anode receives a voltage (e.g., a predetermined voltage) through the thin-film transistor of the thin-film transistor layer (TFTL) and the cathode receives a cathode voltage, holes and electrons can move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively. The holes and electrons can then recombine with each other in the organic light-emitting layer to emit light.

[0066] In another example, each of the light-emitting elements (EDs) may include a quantum dot light-emitting diode containing a quantum dot light-emitting layer, an inorganic light-emitting diode containing an inorganic semiconductor, or a micro light-emitting diode.

[0067] The encapsulation layer ENC can cover the top and side surfaces of the light-emitting element layer EMTL and protect the EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer to encapsulate the light-emitting element layer EMTL.

[0068] The touch sensor TSU can be located on the encapsulation layer ENC. The touch sensor TSU may include multiple touch electrodes for capacitively sensing the user's touch and touch lines connecting the touch electrodes and the touch driver 400. For example, the touch sensor TSU can sense the user's touch using mutual capacitance or self-capacitance.

[0069] In another example, the touch sensor TSU can be located on a separate substrate positioned on the display DU. In this case, the substrate supporting the touch sensor TSU can be a substrate component that encapsulates the display DU.

[0070] The touch electrodes of the touch sensor TSU can be located in the touch sensor area superimposed on the display area DA. The touch lines of the touch sensor TSU can be located in the touch periphery area superimposed on the non-display area NDA.

[0071] A color filter layer (CFL) may be located on the touch sensor (TSU). The CFL may include multiple color filters, each corresponding to a plurality of emission areas. Each color filter selectively transmits light of a corresponding wavelength and may block or absorb light of other wavelengths. The CFL may absorb a portion of the light from outside the display device 10, thereby reducing reflected light caused by external light. Therefore, the CFL can reduce or prevent color distortion caused by reflection of external light.

[0072] Because the color filter layer CFL is located directly on the touch sensor TSU, the display device 10 does not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively reduced.

[0073] The sub-region SBA of the display panel 100 can extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, rolled, etc. For example, when the sub-region SBA is bent, it can be stacked with the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a display driver 200 and a pad electrically connected to the circuit board 300.

[0074] Figure 3 This is a plan view of the display DU of the display device 10 according to one or more embodiments. Figure 4 This is a block diagram of a display panel 100 and a display driver 200 according to one or more embodiments.

[0075] Reference Figure 3 and Figure 4 The display panel 100 may include a display area DA and a non-display area NDA.

[0076] The display area DA may include multiple pixels PX, multiple drive voltage lines VDL connected to the pixels PX, and multiple common voltage lines VSL (see...). Figure 5 It has multiple gate lines (GL), multiple emitter lines (EML), and multiple data lines (DL).

[0077] Each pixel PX can be connected to a gate line GL, a data line DL, an emitter line EML, a drive voltage line VDL, and a common voltage line VSL. Each pixel PX may include at least one transistor, a light-emitting element ED, and / or a capacitor.

[0078] Gate lines GL can extend along a first direction DR1 and can be separated from each other along a second direction DR2 that intersects the first direction DR1. Gate lines GL can be arranged along the second direction DR2. Gate lines GL can sequentially supply gate signals to pixels PX.

[0079] The transmit lines EML can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The transmit lines EML can be arranged along the second direction DR2. The transmit lines EML can sequentially supply the transmit signals to the pixels PX.

[0080] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can be arranged along the first direction DR1. Data lines DL can supply data voltage to pixels PX. The data voltage determines the brightness of each pixel PX.

[0081] The driving voltage lines VDL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The driving voltage lines VDL can be arranged along the first direction DR1. The driving voltage lines VDL can supply driving voltage to the pixel PX. The driving voltage can be a high potential voltage used to drive the light-emitting element ED of the pixel PX.

[0082] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, an emitter control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0083] The fan-out line FL can extend from the display driver 200 to the display area DA. The fan-out line FL can supply the data voltage received from the display driver 200 to the data line DL.

[0084] The first gate control line GSL1 can extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 can supply the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0085] The second gate control line GSL2 can extend from the display driver 200 to the transmit control driver 620. The second gate control line GSL2 can supply the transmit control signal ECS received from the display driver 200 to the transmit control driver 620.

[0086] The sub-region SBA can extend from one side of the non-display region NDA. The sub-region SBA may include a display driver 200 and a pad DP. The pad DP may be closer to the edge of the sub-region SBA than the display driver 200. The pad DP can be electrically connected to the circuit board 300 through an anisotropic conductive film.

[0087] Display driver 200 may include timing controller 210 and data driver 220.

[0088] The timing controller 210 can receive digital video data DATA and timing signals from the circuit board 300. Based on the timing signals, the timing controller 210 can control the operation timing of the data driver 220 by generating a data control signal DCS, control the operation timing of the gate driver 610 by generating a gate control signal GCS, and control the operation timing of the transmit control driver 620 by generating a transmit control signal ECS. The timing controller 210 can supply the gate control signal GCS to the gate driver 610 via a first gate control line GSL1. The timing controller 210 can supply the transmit control signal ECS to the transmit control driver 620 via a second gate control line GSL2. The timing controller 210 can supply digital video data DATA and the data control signal DCS to the data driver 220.

[0089] Data driver 220 converts digital video data DATA into analog data voltage and supplies the analog data voltage to data line DL via fan-out line FL. Gate driver 610's gate signal selects the pixel PX to which data voltage is to be supplied, and the selected pixel PX receives the data voltage via data line DL.

[0090] Power supply 500 may be located on circuit board 300 to supply power voltage to display driver 200 and display panel 100. Power supply 500 can generate drive voltage and supply drive voltage to drive voltage line VDL, and can generate initialization voltage and supply initialization voltage to initialization voltage line VIL (see [link to initialization voltage line]). Figure 5 It can generate a common voltage and can supply the common voltage to the cathode shared by the light-emitting elements (EDs) of the pixel PX.

[0091] The gate driver 610 may be located outside one side of the display area DA or on one side of the non-display area NDA, and the emitter control driver 620 may be located outside the other side of the display area DA or on the other side of the non-display area NDA. However, this disclosure is not limited thereto. For another example, the gate driver 610 and the emitter control driver 620 may be located on one side or the other side of the non-display area NDA.

[0092] Gate driver 610 may include multiple transistors that generate a gate signal based on gate control signal GCS. Emitter control driver 620 may include multiple transistors that generate an emitt signal based on emitt control signal ECS. For example, the transistors of gate driver 610 and emitt control driver 620 may be formed on the same layer as the transistors of pixel PX. Gate driver 610 may supply a gate signal to gate line GL, and emitt control driver 620 may supply an emitt signal to emitt line EML.

[0093] Figure 5 This is a circuit diagram of a pixel PX of a display device 10 according to one or more embodiments.

[0094] like Figure 5 As shown, pixel PX can be connected to write gate line GWL, compensation gate line GCL, initialization gate line GIL, bias gate line GBL, first emitter line EML1, second emitter line EML2, data line DL, drive voltage line VDL, common voltage line VSL, initialization voltage line VIL, and bias voltage line VBL.

[0095] A pixel PX may include a pixel circuit PC and a light-emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor Cst.

[0096] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 can control the source-drain current (hereinafter referred to as the drive current) based on the data voltage applied to the gate electrode. The drive current flowing through the channel region of the first transistor T1 (e.g., Isd) can be proportional to the square of the difference between the voltage (Vsg) between the source and gate electrodes of the first transistor T1 and the threshold voltage (Vth) (Isd = k × (Vsg - Vth)). 2 ), where k is a scaling factor determined by the structure and physical characteristics of the first transistor T1, Vsg is the source-gate voltage of the first transistor T1, and Vth is the threshold voltage of the first transistor T1.

[0097] An LED can receive a driving current Isd and can emit light. The amount of light emitted from the LED, or the brightness of the LED, can be proportional to the magnitude of the driving current Isd.

[0098] An ED (Emitting Diode) can be an organic light-emitting diode (OLED) comprising an anode, a cathode, and an organic light-emitting layer located between these electrodes (e.g., anode and cathode). As another example, an ED can be an inorganic ED comprising an anode, a cathode, and an inorganic semiconductor located between these electrodes (e.g., anode and cathode). As yet another example, an ED can be a quantum dot ED comprising an anode, a cathode, and a quantum dot light-emitting layer located between these electrodes (e.g., anode and cathode). As yet another example, an ED can be a micro ED.

[0099] The anode of the light-emitting element (ED) can be electrically connected to the second node N2. The anode of the ED can also be connected to the second node N2 via a sixth transistor T6. The cathode of the ED can be connected to the common voltage line VSL. The cathode of the ED can receive a common voltage ELVSS (e.g., a low potential voltage) from the common voltage line VSL.

[0100] The second transistor T2 can be turned on by the write gate signal GW from the write gate line GWL to electrically connect the data line DL and the first node N1, which serves as the source electrode of the first transistor T1. The second transistor T2, turned on by the write gate signal GW, can supply a data voltage to the first node N1. The second transistor T2 may have a gate electrode electrically connected to the write gate line GWL, a source electrode electrically connected to the data line DL, and a drain electrode electrically connected to the first node N1.

[0101] The third transistor T3 can be turned on by the compensation gate signal GC from the compensation gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor T1, and the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 can be connected between the third node N3 and the second node N2. For example, the third transistor T3 can have a gate electrode electrically connected to the compensation gate line GCL, a source electrode electrically connected to the third node N3, and a drain electrode electrically connected to the second node N2. The third transistor T3, turned on by the compensation gate signal GC from the compensation gate line GCL, can electrically connect the second node N2, which is the drain electrode of the first transistor T1, and the third node N3, which is the gate electrode of the first transistor T1. The third transistor T3 can be a dual-gate transistor with two gate electrodes (e.g., a gate electrode and a counter gate electrode). The gate electrode and the counter gate electrode can be located on different layers facing each other.

[0102] The fourth transistor T4 can be turned on by the initialization gate signal GI from the initialization gate line GIL to electrically connect the second node N2 and the initialization voltage line VIL. The fourth transistor T4 can be connected between the second node N2 and the first initialization voltage line VIL. For example, the fourth transistor T4 can have a gate electrode electrically connected to the initialization gate line GIL, a drain electrode electrically connected to the second node N2, and a source electrode electrically connected to the initialization voltage line VIL. The fourth transistor T4 can be a dual-gate transistor. The initialization voltage line VIL can transmit the initialization voltage VINT.

[0103] The fifth transistor T5 can be turned on by a first emitter control signal EM1 from the first emitter line EML1 to electrically connect the drive voltage line VDL and the first node N1, which serves as the source electrode of the first transistor T1. The fifth transistor T5 may have a gate electrode electrically connected to the first emitter line EML1, a source electrode electrically connected to the drive voltage line VDL, and a drain electrode electrically connected to the first node N1.

[0104] The sixth transistor T6 can be turned on by the second emitter control signal EM2 from the second emitter line EML2 to electrically connect the second node N2, which serves as the drain electrode of the first transistor T1, and the anode of the light-emitting element ED. The sixth transistor T6 may have a gate electrode electrically connected to the second emitter line EML2, a drain electrode electrically connected to the second node N2, and a source electrode electrically connected to the anode of the light-emitting element ED. When the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all turned on, a drive current Isd can be supplied to the light-emitting element ED.

[0105] The seventh transistor T7 can be turned on by a bias gate signal GB from the bias gate line GBL to electrically connect the bias voltage line VBL to the first node N1, which is the source electrode of the first transistor T1. The seventh transistor T7, turned on by the bias gate signal GB, can supply a bias voltage VB to the first node N1. The seventh transistor T7 can improve the hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1. The seventh transistor T7 may have a gate electrode electrically connected to the bias gate line GBL, a source electrode electrically connected to the bias voltage line VBL, and a drain electrode electrically connected to the first node N1.

[0106] Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a silicon-based active layer. For example, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a p-type transistor including an active layer made of low-temperature polycrystalline silicon (LTPS). The active layer made of LTPS can have high electron mobility and excellent conduction characteristics. Therefore, the display device 10 including transistors with excellent conduction characteristics can drive the pixel PX stably and efficiently. Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can output the current flowing into the source electrode to the drain electrode based on a low gate voltage applied to the gate electrode.

[0107] Each of the third transistor T3 and the fourth transistor T4 can be an n-type transistor including an oxide-based active layer. The transistor including the oxide-based active layer can have a coplanar structure in which the gate electrode is located at the top. The transistor including the oxide-based active layer can output current flowing into the drain electrode to the source electrode based on a high gate voltage applied to the gate electrode.

[0108] The capacitor Cst can be electrically connected between the third node N3, which serves as the gate electrode of the first transistor T1, and the drive voltage line VDL. For example, the first electrode of the capacitor Cst can be electrically connected to the third node N3, and the second electrode of the capacitor Cst can be electrically connected to the drive voltage line VDL, thereby maintaining the potential difference between the drive voltage line VDL and the gate electrode of the first transistor T1.

[0109] The bias voltage VB can be greater than the drive voltage ELVDD, the drive voltage ELVDD can be greater than the common voltage ELVSS, and the common voltage ELVSS can be greater than the initialization voltage VINT. However, this disclosure is not limited thereto. For example, the common voltage ELVSS can be equal to or less than the initialization voltage VINT. The bias voltage VB can be a voltage relatively close to the black grayscale level (e.g., about 5V).

[0110] The above Figure 3 Each of the pixels in PX can have Figure 5 The circuit structure shown is illustrated.

[0111] Figure 6 yes Figure 5 Timing diagram of the first transmit signal EM1, the second transmit signal EM2, the initial gate signal GI, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB.

[0112] Reference Figure 6 The display device 10 can operate based on the first time period P1, the second time period P2, the third time period P3, the fourth time period P4, the fifth time period P5, the sixth time period P6, the seventh time period P7 and the eighth time period P8.

[0113] The first transmit signal EM1, the second transmit signal EM2, the initial gate signal GI, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can each have an active or inactive level in each of the time periods P1 to P8. Here, the active level of each of the above signals EM1, EM2, GI, GC, GW, and GB can refer to the voltage level that enables the corresponding transistor to conduct. In other words, a signal at an active level can have a value greater than the threshold voltage of the corresponding transistor. For example, when the corresponding transistor is an n-type transistor, the active level of the signal transmitted to the gate electrode of the corresponding transistor can refer to a high level (e.g., a positive level or a high voltage level).

[0114] The inactive level of each of the signals EM1, EM2, GI, GC, GW, and GB can refer to the voltage level that turns off the corresponding transistor. In other words, a signal at an inactive level can have a value smaller than the threshold voltage of the corresponding transistor. For example, when the corresponding transistor is an n-type transistor, the inactive level of the signal transmitted to the gate electrode of the corresponding transistor can refer to a low level (e.g., a negative level or a low voltage level).

[0115] Conversely, when the corresponding transistor is a p-type transistor, the effective level of the signal transmitted to the gate electrode of the corresponding transistor can be a low level (e.g., a negative level or a low voltage level), and the ineffective level of the signal transmitted to the gate electrode of the corresponding transistor can be a high level (e.g., a positive level or a high voltage level).

[0116] During the first time period P1, the second transmit signal EM2 and the initialization gate signal GI can both have active levels. During the first time period P1, the first transmit signal EM1, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can all have inactive levels. The first time period P1 can be, for example, a time period used to initialize the voltage of the anode of the light-emitting element ED.

[0117] In the second time period P2, both the compensation gate signal GC and the bias gate signal GB can have active levels. In the second time period P2, the first transmit signal EM1, the second transmit signal EM2, the initialization gate signal GI, and the write gate signal GW can all have inactive levels. The second time period P2 can be, for example, a period used to improve the hysteresis of the first transistor T1.

[0118] In the third time period P3, the initialization gate signal GI and the compensation gate signal GC can both have active levels. In the third time period P3, the first transmit signal EM1, the second transmit signal EM2, the write gate signal GW, and the bias gate signal GB can all have inactive levels. The third time period P3 can be, for example, a time period used to initialize the voltage of the gate electrode of the first transistor T1.

[0119] In the fourth time period P4, both the compensation gate signal GC and the write gate signal GW can have active levels. In the fourth time period P4, the first transmit signal EM1, the second transmit signal EM2, the initialization gate signal GI, and the bias gate signal GB can all have inactive levels. Additionally, in the fourth time period P4, a data voltage can be provided to the data line DL. The fourth time period P4 can be, for example, a period used to supply the data voltage to the pixel circuit PC and to detect and compensate the threshold voltage of the first transistor T1.

[0120] In the fifth time period P5, the compensation gate signal GC may have an active level. In the fifth time period P5, the first transmit signal EM1, the second transmit signal EM2, the initialization gate signal GI, the write gate signal GW, and the bias gate signal GB may all have inactive levels. The fifth time period P5 may be, for example, a time period used to additionally compensate the threshold voltage of the first transistor T1.

[0121] In the sixth time period P6, the bias gate signal GB may have an active level. In the sixth time period P6, the first transmit signal EM1, the second transmit signal EM2, the initialization gate signal GI, the compensation gate signal GC, and the write gate signal GW may all have inactive levels. The sixth time period P6 may, for example, be a time period used to additionally improve the hysteresis of the first transistor T1.

[0122] In the seventh time period P7, the initialization gate signal GI may have an active level. In the seventh time period P7, the first transmit signal EM1, the second transmit signal EM2, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB may all have inactive levels. The seventh time period P7 may be, for example, a time period used to improve the expression of black grayscale levels by discharging the voltage of the drain electrode of the first transistor T1.

[0123] In the eighth time period P8, both the first transmission signal EM1 and the second transmission signal EM2 can have active levels. In the eighth time period P8, the initialization gate signal GI, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can all have inactive levels. The eighth time period P8 can be, for example, a time period used for emitting light from the light-emitting element ED.

[0124] The following will refer to Figures 7 to 14 The operation of the display device 10 according to one or more embodiments is described. Figures 7 to 14 In the diagram, the transistor surrounded by the dashed circle can be a conducting transistor, and the transistors other than those surrounded by the dashed circle can be cut-off transistors.

[0125] First, the following will refer to Figure 6 and Figure 7 Describe the operation of pixel PX in the first time period P1.

[0126] Figure 7 It is used for explanation Figure 5 The pixel PX in Figure 6 The diagram shows the operations in the first time period P1.

[0127] like Figure 6As shown, during the first time period P1, the second transmit signal EM2 and the initialization gate signal GI can both have valid levels. During the first time period P1, the first transmit signal EM1, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can all have invalid levels.

[0128] The first transistor T1 can be kept on by the data voltage from the previous frame period. For example, the voltage at the gate electrode of the first transistor T1 (e.g., the third node N3) can include the data voltage provided in the previous frame period. Therefore, the first transistor T1 can be turned on by the data voltage from the previous frame period.

[0129] The initialization gate signal GI, which is at an active level, can be transmitted to the gate electrode of the fourth transistor T4 through the initialization gate line GIL. Therefore, the fourth transistor T4 can be turned on.

[0130] The second transmit signal EM2, which is at an effective level, can be transmitted to the gate electrode of the sixth transistor T6 through the second transmit line EML2. Therefore, the sixth transistor T6 can be turned on.

[0131] The write gate signal GW, which is at an inactive level, can be transmitted to the gate electrode of the second transistor T2 through the write gate line GWL. Therefore, the second transistor T2 can be turned off.

[0132] The compensation gate signal GC, which is at an inactive level, can be transmitted to the gate electrode of the third transistor T3 through the compensation gate line GCL. Therefore, the third transistor T3 can be turned off.

[0133] The first transmit signal EM1, which is at an inactive level, can be transmitted to the gate electrode of the fifth transistor T5 through the first transmit line EML1. Therefore, the fifth transistor T5 can be turned off.

[0134] The bias gate signal GB, which is at an inactive level, can be transmitted to the gate electrode of the seventh transistor T7 through the bias gate line GBL. Therefore, the seventh transistor T7 can be turned off.

[0135] When the fourth transistor T4 and the sixth transistor T6 are turned on as described above, the initialization voltage VINT from the initialization voltage line VIL can be applied to each of the second node N2 and the anode of the light-emitting element ED through the turned-on fourth transistor T4 and sixth transistor T6. Therefore, during the first time period P1, the voltage at the anode of the light-emitting element ED and the voltage at the drain electrode of the first transistor T1 connected to the second node N2 can both be initialized to the initialization voltage VINT.

[0136] Next, the following will refer to Figure 6 and Figure 8 Describe the operation of pixel PX in the second time period P2.

[0137] Figure 8 It is used for explanation Figure 5 The pixel PX in Figure 6 The diagram shows the operations in the second time period P2.

[0138] like Figure 6 As shown, in the second time period P2, both the compensation gate signal GC and the bias gate signal GB can have active levels. In the second time period P2, the first transmit signal EM1, the second transmit signal EM2, the initialization gate signal GI, and the write gate signal GW can all have inactive levels.

[0139] The compensated gate signal GC, which is at an effective level, can be transmitted to the gate electrode of the third transistor T3 through the compensated gate line GCL. Therefore, the third transistor T3 can be turned on.

[0140] The bias gate signal GB, which is at an active level, can be transmitted to the gate electrode of the seventh transistor T7 through the bias gate line GBL. Therefore, the seventh transistor T7 can be turned on.

[0141] The write gate signal GW, which is at an inactive level, can be transmitted to the gate electrode of the second transistor T2 through the write gate line GWL. Therefore, the second transistor T2 can be turned off.

[0142] The initialization gate signal GI, which is at an inactive level, can be transmitted to the gate electrode of the fourth transistor T4 through the initialization gate line GIL. Therefore, the fourth transistor T4 can be turned off.

[0143] The first transmit signal EM1, which is at an inactive level, can be transmitted to the gate electrode of the fifth transistor T5 through the first transmit line EML1. Therefore, the fifth transistor T5 can be turned off.

[0144] The second transmit signal EM2, which is at a non-active level, can be transmitted to the gate electrode of the sixth transistor T6 through the second transmit line EML2. Therefore, the sixth transistor T6 can be turned off.

[0145] When the seventh transistor T7 is turned on as described above, the bias voltage VB from the bias voltage line VBL can be applied to the source electrode of the first transistor T1 (e.g., the first node N1) through the turned-on seventh transistor T7. Then, the voltage difference between the gate electrode and the source electrode of the first transistor T1 (hereinafter referred to as the gate-source voltage) can become greater than the threshold voltage of the first transistor T1. Therefore, the first transistor T1 can be turned on.

[0146] When the third transistor T3 is turned on as described above, the gate electrode (e.g., third node N3) and drain electrode (e.g., second node N2) of the first transistor T1 can be electrically connected to each other. In other words, the first transistor T1 can be connected to the pixel circuit PC in the form of a diode. Therefore, current can be generated to flow through the turned-on first transistor T1 in a direction from the bias voltage line VBL toward the drain electrode (e.g., second node N2) and gate electrode (e.g., third node N3) of the first transistor T1. Therefore, the voltage at the gate electrode (e.g., third node N3) of the first transistor T1 can be increased, and the first transistor T1 can be turned off when the gate-source voltage of the first transistor T1 becomes equal to the threshold voltage of the first transistor T1.

[0147] When the first transistor T1, the third transistor T3, and the seventh transistor T7 are turned on as described above, the bias voltage VB from the bias voltage line VBL can be applied to each of the first node N1, the second node N2, and the third node N3 through the turned-on first transistor T1, third transistor T3, and seventh transistor T7. Therefore, in the second time period P2, the hysteresis of the first transistor T1 can be improved. Furthermore, in the second time period P2, the voltage at the source electrode of the first transistor T1 can be initialized to the bias voltage VB.

[0148] Next, refer to the following: Figure 6 and Figure 9 Describe the operation of pixel PX in the third time period P3.

[0149] Figure 9 It is used for explanation Figure 5 The pixel PX in Figure 6 The diagram shows the operations in the third time period P3.

[0150] like Figure 6 As shown, in the third time period P3, the initialization gate signal GI and the compensation gate signal GC can both have valid levels. In the third time period P3, the first transmit signal EM1, the second transmit signal EM2, the write gate signal GW, and the bias gate signal GB can all have invalid levels.

[0151] The compensated gate signal GC, which is at an effective level, can be transmitted to the gate electrode of the third transistor T3 through the compensated gate line GCL. Therefore, the third transistor T3 can be turned on.

[0152] The initialization gate signal GI, which is at an active level, can be transmitted to the gate electrode of the fourth transistor T4 through the initialization gate line GIL. Therefore, the fourth transistor T4 can be turned on.

[0153] The first transmit signal EM1, which is at an inactive level, can be transmitted to the gate electrode of the fifth transistor T5 through the first transmit line EML1. Therefore, the fifth transistor T5 can be turned off.

[0154] The second transmit signal EM2, which is at a non-active level, can be transmitted to the gate electrode of the sixth transistor T6 through the second transmit line EML2. Therefore, the sixth transistor T6 can be turned off.

[0155] The bias gate signal GB, which is at an inactive level, can be transmitted to the gate electrode of the seventh transistor T7 through the bias gate line GBL. Therefore, the seventh transistor T7 can be turned off.

[0156] When the third transistor T3 is turned on as described above, the gate electrode (e.g., third node N3) and drain electrode (e.g., second node N2) of the first transistor T1 can be electrically connected to each other. At the same time, the first transistor T1 can be kept off by the previous time period (e.g., the second time period P2).

[0157] When the third transistor T3 and the fourth transistor T4 are turned on as described above, the initialization voltage VINT from the initialization voltage line VIL can be applied to each of the second node N2 and the third node N3 through the turned-on third transistor T3 and fourth transistor T4. Therefore, in the third time period P3, the voltage of the gate electrode of the first transistor T1 and the voltage of the drain electrode of the first transistor T1 can both be initialized to the initialization voltage VINT.

[0158] Next, the following will refer to Figure 6 and Figure 10 Describe the operation of pixel PX in the fourth time period P4.

[0159] Figure 10 It is used for explanation Figure 5 The pixel PX in Figure 6 The diagram shows the operations in the fourth time period, P4.

[0160] like Figure 6 As shown, in the fourth time period P4, both the compensation gate signal GC and the write gate signal GW can have active levels. In the fourth time period P4, the first transmit signal EM1, the second transmit signal EM2, the initialization gate signal GI, and the bias gate signal GB can all have inactive levels. Additionally, in the fourth time period P4, the data voltage can be provided to the data line DL.

[0161] The write gate signal GW, which is at an active level, can be transmitted to the gate electrode of the second transistor T2 through the write gate line GWL. Therefore, the second transistor T2 can be turned on.

[0162] The compensated gate signal GC, which is at an effective level, can be transmitted to the gate electrode of the third transistor T3 through the compensated gate line GCL. Therefore, the third transistor T3 can be turned on.

[0163] The initialization gate signal GI, which is at an inactive level, can be transmitted to the gate electrode of the fourth transistor T4 through the initialization gate line GIL. Therefore, the fourth transistor T4 can be turned off.

[0164] The first transmit signal EM1, which is at an inactive level, can be transmitted to the gate electrode of the fifth transistor T5 through the first transmit line EML1. Therefore, the fifth transistor T5 can be turned off.

[0165] The second transmit signal EM2, which is at a non-active level, can be transmitted to the gate electrode of the sixth transistor T6 through the second transmit line EML2. Therefore, the sixth transistor T6 can be turned off.

[0166] The bias gate signal GB, which is at an inactive level, can be transmitted to the gate electrode of the seventh transistor T7 through the bias gate line GBL. Therefore, the seventh transistor T7 can be turned off.

[0167] When the third transistor T3 is turned on as described above, the gate electrode (e.g., third node N3) and drain electrode (e.g., second node N2) of the first transistor T1 can be electrically connected to each other. In other words, the first transistor T1 can be connected to the pixel circuit PC in the form of a diode.

[0168] When the second transistor T2 is turned on as described above, the data voltage from the data line DL can be applied to the source electrode of the first transistor T1 (e.g., the first node N1) through the turned-on second transistor T2. The voltage at the source electrode of the first transistor T1 can be maintained as the data voltage in this way, but the voltage at the gate electrode of the first transistor T1 (e.g., the third node N3) can be gradually increased. In other words, as the current generated by the data voltage applied to the first node N1 is supplied to the second node N2 and the third node N3 through the turned-on first transistor T1, the voltage at the gate electrode of the first transistor T1 can be gradually increased. As the voltage at the gate electrode of the first transistor T1 gradually increases, the gate-source voltage of the first transistor T1 can gradually decrease. When the gate-source voltage of the first transistor T1 decreases to the threshold voltage of the first transistor T1, the first transistor T1 can be turned off. Therefore, the threshold voltage of the first transistor T1 can be detected when the first transistor T1 is turned off, and the detected threshold voltage can be reflected in the third node N3. For example, the voltage at the third node N3 when the first transistor T1 is off can be obtained by subtracting the threshold voltage of the first transistor T1 from the data voltage. The voltage at the third node N3 (e.g., data voltage - threshold voltage of the first transistor T1) can be stored by a capacitor Cst and maintained for a specific time period. Therefore, in the fourth time period P4, the threshold voltage of the first transistor T1 can be detected and maintained while the data voltage is applied. Thus, in the fourth time period P4, the voltage at the third node N3 can include the threshold voltage of the first transistor T1.

[0169] Next, the following will refer to Figure 6 and Figure 11 Describe the operation of pixel PX in the fifth time period P5.

[0170] Figure 11 It is used for explanation Figure 5 The pixel PX in Figure 6 The diagram shows the operations in the fifth time slot, P5.

[0171] like Figure 6 As shown, in the fifth time period P5, the compensation gate signal GC can have an active level. In the fifth time period P5, the first transmit signal EM1, the second transmit signal EM2, the initialization gate signal GI, the write gate signal GW, and the bias gate signal GB can all have inactive levels.

[0172] The compensated gate signal GC, which is at an effective level, can be transmitted to the gate electrode of the third transistor T3 through the compensated gate line GCL. Therefore, the third transistor T3 can be turned on.

[0173] The write gate signal GW, which is at an inactive level, can be transmitted to the gate electrode of the second transistor T2 through the write gate line GWL. Therefore, the second transistor T2 can be turned off.

[0174] The initialization gate signal GI, which is at an inactive level, can be transmitted to the gate electrode of the fourth transistor T4 through the initialization gate line GIL. Therefore, the fourth transistor T4 can be turned off.

[0175] The first transmit signal EM1, which is at an inactive level, can be transmitted to the gate electrode of the fifth transistor T5 through the first transmit line EML1. Therefore, the fifth transistor T5 can be turned off.

[0176] The second transmit signal EM2, which is at a non-active level, can be transmitted to the gate electrode of the sixth transistor T6 through the second transmit line EML2. Therefore, the sixth transistor T6 can be turned off.

[0177] The bias gate signal GB, which is at an inactive level, can be transmitted to the gate electrode of the seventh transistor T7 through the bias gate line GBL. Therefore, the seventh transistor T7 can be turned off.

[0178] When the third transistor T3 is turned on as described above, the gate electrode (e.g., third node N3) and drain electrode (e.g., second node N2) of the first transistor T1 can be electrically connected to each other. In other words, the first transistor T1 can be connected to the pixel circuit PC in the form of a diode.

[0179] The fifth time period P5 can be a time period for additionally detecting the threshold voltage of the first transistor T1. For example, if the effective time period of the write gate signal GW (e.g., the time period during which the write gate signal GW remains at an effective level) is not long enough to detect the threshold voltage of the first transistor T1 in the fourth time period P4, the first transistor T1 may not be turned off, but may remain on in the fourth time period P4. In this case, the threshold voltage of the first transistor T1 may not be detected in the fourth time period P4. Therefore, the third transistor T3 may be turned on again in the fifth time period P5, such that the first transistor T1 is connected to the pixel circuit PC in the form of a diode. Then, the voltage of the third node N3 can be sufficiently increased by the on-state first transistor T1. Therefore, the first transistor T1 may be turned off in the fifth time period P5, and thus the threshold voltage of the first transistor T1 can be detected.

[0180] Next, the following will refer to Figure 6 and Figure 12 Describe the operation of pixel PX in the sixth time period P6.

[0181] Figure 12 It is used for explanation Figure 5 The pixel PX in Figure 6The diagram shows the operations in the sixth time period, P6.

[0182] like Figure 6 As shown, in the sixth time period P6, the bias gate signal GB can have an active level. In the sixth time period P6, the first transmit signal EM1, the second transmit signal EM2, the initialization gate signal GI, the compensation gate signal GC, and the write gate signal GW can all have inactive levels.

[0183] The bias gate signal GB, which is at an active level, can be transmitted to the gate electrode of the seventh transistor T7 through the bias gate line GBL. Therefore, the seventh transistor T7 can be turned on.

[0184] The write gate signal GW, which is at an inactive level, can be transmitted to the gate electrode of the second transistor T2 through the write gate line GWL. Therefore, the second transistor T2 can be turned off.

[0185] The compensation gate signal GC, which is at an inactive level, can be transmitted to the gate electrode of the third transistor T3 through the compensation gate line GCL. Therefore, the third transistor T3 can be turned off.

[0186] The initialization gate signal GI, which is at an inactive level, can be transmitted to the gate electrode of the fourth transistor T4 through the initialization gate line GIL. Therefore, the fourth transistor T4 can be turned off.

[0187] The first transmit signal EM1, which is at an inactive level, can be transmitted to the gate electrode of the fifth transistor T5 through the first transmit line EML1. Therefore, the fifth transistor T5 can be turned off.

[0188] The second transmit signal EM2, which is at a non-active level, can be transmitted to the gate electrode of the sixth transistor T6 through the second transmit line EML2. Therefore, the sixth transistor T6 can be turned off.

[0189] When the seventh transistor T7 is turned on as described above, the bias voltage VB from the bias voltage line VBL can be applied to the source electrode of the first transistor T1 (e.g., the first node N1) through the turned-on seventh transistor T7. Therefore, the voltage at the source electrode of the first transistor T1 can gradually increase, and thus the gate-source voltage of the first transistor T1 can become greater than the threshold voltage of the first transistor T1. Therefore, the first transistor T1 can be turned on. The bias voltage VB from the bias voltage line VBL can be applied to the first node N1 and the second node N2 through the turned-on first transistor T1. Here, the voltage at the second node N2 can be the difference voltage obtained by subtracting the threshold voltage of the first transistor T1 from the bias voltage VB. Therefore, the hysteresis of the first transistor T1 can be improved in the sixth time period P6. Therefore, even when the scan rate of the display device 10 changes rapidly, the deviation of the drive current Isd flowing through the first transistor T1 can be reduced or minimized, thereby improving the image quality of the display device 10.

[0190] Next, the following will refer to Figure 6 and Figure 13 Describe the operation of pixel PX in the seventh time period P7.

[0191] Figure 13 It is used for explanation Figure 5 The pixel PX in Figure 6 The diagram shows the operations in the seventh time period, P7.

[0192] like Figure 6 As shown, in the seventh time period P7, the initialization gate signal GI can have an active level. In the seventh time period P7, the first transmit signal EM1, the second transmit signal EM2, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can all have inactive levels.

[0193] The initialization gate signal GI, which is at an active level, can be transmitted to the gate electrode of the fourth transistor T4 through the initialization gate line GIL. Therefore, the fourth transistor T4 can be turned on.

[0194] The write gate signal GW, which is at an inactive level, can be transmitted to the gate electrode of the second transistor T2 through the write gate line GWL. Therefore, the second transistor T2 can be turned off.

[0195] The compensation gate signal GC, which is at an inactive level, can be transmitted to the gate electrode of the third transistor T3 through the compensation gate line GCL. Therefore, the third transistor T3 can be turned off.

[0196] The first transmit signal EM1, which is at an inactive level, can be transmitted to the gate electrode of the fifth transistor T5 through the first transmit line EML1. Therefore, the fifth transistor T5 can be turned off.

[0197] The second transmit signal EM2, which is at a non-active level, can be transmitted to the gate electrode of the sixth transistor T6 through the second transmit line EML2. Therefore, the sixth transistor T6 can be turned off.

[0198] The bias gate signal GB, which is at an inactive level, can be transmitted to the gate electrode of the seventh transistor T7 through the bias gate line GBL. Therefore, the seventh transistor T7 can be turned off.

[0199] When the fourth transistor T4 is turned on as described above, the initialization voltage VINT from the initialization voltage line VIL can be applied to the drain electrode of the first transistor T1 (e.g., the second node N2) through the turned-on fourth transistor T4. Therefore, the voltage at the drain electrode of the first transistor T1 can discharge to the initialization voltage VINT. Consequently, the voltage at the second node N2 can be maintained at a low voltage during the seventh time period P7. Because the voltage at the second node N2 is maintained at the same low voltage as the initialization voltage VINT during the seventh time period P7, even when the grayscale level of the data voltage changes rapidly from white grayscale to black grayscale, the light-emitting element ED can be turned off sufficiently quickly in the next time period (e.g., the eighth time period P8). Therefore, even when the image changes rapidly from white grayscale to black grayscale, the image corresponding to the black grayscale level can be accurately represented.

[0200] In other words, to improve the hysteresis of the first transistor T1, the second node N2 must be maintained at a high voltage (e.g., bias voltage - threshold voltage of the first transistor T1) in the previous time period (e.g., the sixth time period P6). In this case, when the grayscale level changes from white to black, it may be difficult to properly represent the black grayscale level. To solve this problem, the voltage of the second node N2 can be pre-discharged to a low voltage (e.g., initialization voltage VINT) in the seventh time period P7 before the emission time period (e.g., the eighth time period P8).

[0201] Next, the following will refer to Figure 6 and Figure 14 Describe the operation of pixel PX in the eighth time period P8.

[0202] Figure 14 It is used for explanation Figure 5 The pixel PX in Figure 6 The diagram shows the operations in the eighth time slot, P8.

[0203] like Figure 6As shown, in the eighth time period P8, both the first transmit signal EM1 and the second transmit signal EM2 can have valid levels. In the eighth time period P8, the initialization gate signal GI, the compensation gate signal GC, the write gate signal GW, and the bias gate signal GB can all have invalid levels.

[0204] The first transmit signal EM1, which is at an active level, can be transmitted to the gate electrode of the fifth transistor T5 through the first transmit line EML1. Therefore, the fifth transistor T5 can be turned on.

[0205] The second transmit signal EM2, which is at an effective level, can be transmitted to the gate electrode of the sixth transistor T6 through the second transmit line EML2. Therefore, the sixth transistor T6 can be turned on.

[0206] The write gate signal GW, which is at an inactive level, can be transmitted to the gate electrode of the second transistor T2 through the write gate line GWL. Therefore, the second transistor T2 can be turned off.

[0207] The compensation gate signal GC, which is at an inactive level, can be transmitted to the gate electrode of the third transistor T3 through the compensation gate line GCL. Therefore, the third transistor T3 can be turned off.

[0208] The initialization gate signal GI, which is at an inactive level, can be transmitted to the gate electrode of the fourth transistor T4 through the initialization gate line GIL. Therefore, the fourth transistor T4 can be turned off.

[0209] The bias gate signal GB, which is at an inactive level, can be transmitted to the gate electrode of the seventh transistor T7 through the bias gate line GBL. Therefore, the seventh transistor T7 can be turned off.

[0210] Meanwhile, the first transistor T1 can be kept on by the gate-source voltage held by the capacitor Cst.

[0211] In the eighth time period P8, when the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned on, the drive current Isd can be supplied to the light-emitting element ED through the turned-on first transistor T1, fifth transistor T5, and sixth transistor T6. Therefore, the light-emitting element ED can emit light according to the drive current Isd. Here, the gate-source voltage held by the capacitor Cst includes the threshold voltage of the first transistor T1. Therefore, the magnitude of the drive current Isd flowing to the light-emitting element ED through the turned-on first transistor T1 can be determined based on the data voltage and the threshold voltage of the first transistor T1. Therefore, the drive current Isd supplied to the light-emitting element ED can accurately reflect the magnitude of the data voltage. In this way, since the drive current Isd of each pixel PX is determined by compensating for the different threshold voltages of the first transistor T1 of the pixel PX, the brightness difference between pixels PX caused by the difference in threshold voltage between the first transistor T1 of the pixel PX can be reduced or minimized. Therefore, the image quality of the display device 10 can be improved.

[0212] According to one or more embodiments, because the voltage of the second node N2 discharges to the initialization voltage VINT in the previous time period (e.g., the seventh time period P7) and thus remains at a low voltage, the voltage difference between the anode of the light-emitting element ED (e.g., the anode connected to the drain electrode of the sixth transistor T6) and the cathode of the light-emitting element ED can be kept relatively small in the eighth time period P8. In other words, the voltage of the anode of the light-emitting element ED can be kept sufficiently low during the eighth time period P8. Therefore, as described above, even if the gray level of the data voltage changes rapidly from white gray level to black gray level in adjacent frame time periods, the voltage of the anode of the light-emitting element ED can be reduced rapidly. Therefore, an image representing the black gray level can be accurately obtained.

[0213] On the other hand, when the grayscale level changes from black to white, because the first transistor T1 has already been turned on by the data voltage of the white grayscale level to allow a large current to flow, even when the voltage of the second node N2 discharges to a low voltage such as the initialization voltage VINT, the voltage of the anode of the light-emitting element ED can increase sufficiently quickly from the black grayscale level to the large voltage corresponding to the white grayscale level. Therefore, the image quality of the display device 10 can be improved. Furthermore, because the black grayscale level can be improved in this way, the swing width of the data voltage can be reduced, thereby improving the power consumption of the display device 10.

[0214] Furthermore, according to one or more embodiments, because the fourth transistor T4 is located between the drain electrode of the first transistor T1 and the initialization voltage line VIL, the voltage difference between the drain electrode voltage of the first transistor T1 and the initialization voltage VINT is low. Therefore, the leakage current of the fourth transistor T4 (e.g., cutoff leakage current) can be reduced or minimized. Thus, even when driving the display device 10 at a low frequency, images can be displayed without flickering.

[0215] Figure 15 The simulated waveforms of the first transmit signal EM1, the second transmit signal EM2, the bias gate signal GB, the compensation gate signal GC, the initialization gate signal GI, the write gate signal GW, the voltage Vs_T1 of the source electrode of the first transistor T1, the voltage Vg_T1 of the gate electrode of the first transistor T1, the voltage Vd_T1 of the drain electrode of the first transistor T1, the voltage Va of the anode of the light-emitting element ED, and the current i_ED of the light-emitting element ED are shown.

[0216] Figure 15 The first transmit signal EM1, the second transmit signal EM2, the bias gate signal GB, the compensation gate signal GC, the initialization gate signal GI, and the write gate signal GW can respectively correspond to the above Figure 6 The first transmit signal EM1, the second transmit signal EM2, the bias gate signal GB, the compensation gate signal GC, the initialization gate signal GI, and the write gate signal GW.

[0217] The voltage Vs_T1 of the source electrode of the first transistor T1, the voltage Vg_T1 of the gate electrode of the first transistor T1, the voltage Vd_T1 of the drain electrode of the first transistor T1, the voltage Va of the anode of the light-emitting element ED, and the current i_ED of the light-emitting element ED can be changed according to the above signals in each of the first time period P1, the second time period P2, the third time period P3, the fourth time period P4, the fifth time period P5, the sixth time period P6, and the seventh time period P7.

[0218] Figure 16 The diagram shows simulated waveforms used to explain aspects of the display device 10 according to one or more embodiments.

[0219] Figure 16 The simulated waveforms of the voltage Vd_T1 (hereinafter referred to as the drain voltage) of the drain electrode (e.g., the second node N2) of the first transistor T1 and the simulated waveforms of the voltage Va_T1 (hereinafter referred to as the anode voltage) of the light-emitting element ED are shown.

[0220] exist Figure 16In this context, the drain voltage Vd_T1 can be divided into a first drain voltage Vd_T1_A and a second drain voltage Vd_T1_B. For example, the first drain voltage Vd_T1_A can be the drain voltage of the first transistor T1 detected in a first pixel including the fourth transistor T4, and the second drain voltage Vd_T1_B can be the drain voltage of the first transistor T1 detected in a second pixel excluding the fourth transistor T4.

[0221] exist Figure 16 In this context, the anode voltage Va_T1 can be divided into a first anode voltage Va_T1_A and a second anode voltage Va_T1_B. For example, the first anode voltage Va_T1_A can be the voltage of the anode detected in a first pixel including the fourth transistor T4, and the second anode voltage Va_T1_B can be the voltage of the anode detected in a second pixel excluding the fourth transistor T4.

[0222] like Figure 16 As shown, the first drain voltage Vd_T1_A can drop to a significantly low voltage during the seventh period P7. This is because, as described above, the initialization voltage VINT is applied to the second node N2 through the fourth transistor T4, which is turned on during the seventh period P7. On the other hand, the second drain voltage Vd_T1_B can remain at a relatively high voltage.

[0223] like Figure 16 As shown, with the sixth transistor T6 turned on in the eighth period P8, a drain voltage (e.g., the first drain voltage Vd_T1_A or the second drain voltage Vd_T1_B) can be applied to the anode of the light-emitting element ED. In the eighth period P8, the first anode voltage Va_T1_A can drop to a low voltage corresponding to a near-black grayscale level. This is because, as mentioned above, the first anode voltage Va_T1_A has already dropped to a low voltage in the seventh period P7. On the other hand, the second anode voltage Va_T1_B can be maintained at a higher voltage than the first anode voltage Va_T1_A in the eighth period P8. This is because the second drain voltage Vd_T1_B is not discharged in the seventh period P7 and is thus maintained at a relatively high voltage.

[0224] Therefore, even when the gray level of the data voltage changes rapidly from white gray level to black gray level, the light-emitting element ED of the first pixel (e.g., the first pixel including the fourth transistor T4) can be turned off at a sufficiently fast speed in the eighth time period P8. Therefore, even when the image changes rapidly from white gray level to black gray level, the display device 10 according to one or more embodiments, including the first pixel, can accurately represent the image corresponding to the black gray level.

[0225] Figure 17It is a plan view of the pixel array of the display device 10 according to one or more embodiments. Figure 18 yes Figure 17 The plan view of only the first pattern layer 111. Figure 19 yes Figure 17 The plan view of only the second pattern layer 222. Figure 20 yes Figure 17 The plan view of only the third pattern layer 333. Figure 21 yes Figure 17 The plan view of only the fourth pattern layer 444. Figure 22 yes Figure 17 The plan view of only the fifth pattern layer 555. Figure 23 yes Figure 17 The plan view of only the sixth pattern layer 666. Figure 24 yes Figure 17 The plan view of only the seventh pattern layer 777. Figure 25 yes Figure 17 The plan view of only the eighth pattern layer 888. Figure 26 yes Figure 17 The plan view of only the second pattern layer 222 and the third pattern layer 333. Figure 27 yes Figure 17 The plan view of only the fifth pattern layer 555 and the sixth pattern layer 666.

[0226] The first pattern layer 111 can be located on the substrate SUB along the third direction DR3. For example, in Figure 17 and Figure 18 In the example shown, the first pattern layer 111 may include a light-blocking layer BML. The light-blocking layer BML may be located on the substrate SUB to cover the stacked region between the first gate electrode GE1 and the first active layer ACT1 (e.g., the channel region of the first transistor T1). In other words, the light-blocking layer BML may be located on the substrate SUB to be stacked with the channel region of the first transistor T1, which serves as a driving transistor.

[0227] The light-blocking layer BML can be made of a metallic material such as chromium (Cr) or molybdenum (Mo), or it can be made of black ink or black dye. When the light-blocking layer BML is made of a metallic material, it can be supplied with a constant power. Therefore, the light-blocking layer BML can be non-electrically floated, and the electrical characteristics of the transistors (e.g., the first transistor T1) on the light-blocking layer BML can be stabilized.

[0228] The second pattern layer 222 can be located on the first pattern layer 111 along the third direction DR3. For example... Figure 17 and Figure 19 In the example shown, the second pattern layer 222 may include the first active layer ACT1.

[0229] The first active layer ACT1 can provide the source electrode SE1 and drain electrode DE1 of the first transistor T1, the source electrode SE2 and drain electrode DE2 of the second transistor T2, the source electrode SE5 and drain electrode DE5 of the fifth transistor T5, the source electrode SE6 and drain electrode DE6 of the sixth transistor T6, and the source electrode SE7 and drain electrode DE7 of the seventh transistor T7.

[0230] The first active layer ACT1 can be a semiconductor layer made of low-temperature polycrystalline silicon (LTPS).

[0231] The third pattern layer 333 may be located on the second pattern layer 222 along the third direction DR3. An insulating layer may be located between the second pattern layer 222 and the third pattern layer 333. For example, in... Figure 17 and Figure 20 In the example shown, the third pattern layer 333 may include a first gate electrode GE1, a second gate electrode GE2, a fifth gate electrode GE5, a sixth gate electrode GE6, a seventh gate electrode GE7, a write gate line GWL, an initialization voltage line VIL, and a bias gate line GBL.

[0232] The write gate line GWL may include a second gate electrode GE2. For example, a portion of the write gate line GWL may correspond to the second gate electrode GE2. The write gate line GWL and the second gate electrode GE2 may be integrally formed with each other.

[0233] The bias gate line GBL may include a seventh gate electrode GE7. For example, a portion of the bias gate line GBL may correspond to the seventh gate electrode GE7. The bias gate line GBL and the seventh gate electrode GE7 may be integrally formed together.

[0234] like Figure 17 and Figure 26 As shown, the first gate electrode GE1, the second gate electrode GE2, the fifth gate electrode GE5, the sixth gate electrode GE6, and the seventh gate electrode GE7 can be stacked with the first active layer ACT1. The channel regions of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be formed in the stacked region between the first gate electrode GE1, the second gate electrode GE2, the fifth gate electrode GE5, the sixth gate electrode GE6, and the seventh gate electrode GE7 and the first active layer ACT1.

[0235] like Figure 26 As shown, the first transistor T1 may include a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0236] The second transistor T2 may include a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0237] The fifth transistor T5 may include a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0238] The sixth transistor T6 may include a sixth gate electrode GE6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0239] The seventh transistor T7 may include a seventh gate electrode GE7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0240] The fourth pattern layer 444 may be located on the third pattern layer 333 along the third direction DR3. An insulating layer may be located between the third pattern layer 333 and the fourth pattern layer 444. For example, in... Figure 17 and Figure 21 In the example shown, the fourth pattern layer 444 may include a third opposing gate electrode GEb3, a fourth opposing gate electrode GEb4, and a capacitor electrode CPE.

[0241] like Figure 17 and Figure 27 In the example shown, the third opposing gate electrode GEb3 can be stacked with the second-first active layer ACT2-1 and the third gate electrode GE3. For example, the third opposing gate electrode GEb3 can face the third gate electrode GE3 and the second-first active layer ACT2-1 can be placed between them.

[0242] As in Figure 17 and Figure 27 In the example shown, the fourth opposing gate electrode GEb4 can be stacked with the second-second active layer ACT2-2 and the fourth gate electrode GE4. For example, the fourth opposing gate electrode GEb4 can face the fourth gate electrode GE4 and the second-second active layer ACT2-2 can be placed between them.

[0243] like Figure 17 As shown, the capacitor electrode CPE can be stacked with the first gate electrode GE1. A capacitor Cst can be formed in the stacked region between the capacitor electrode CPE and the first gate electrode GE1. For example, the first gate electrode GE1 and the capacitor electrode CPE can correspond to the first electrode and the second electrode of the capacitor Cst, respectively. Additionally, the capacitor electrode CPE can have / define a hole 40 penetrating it in a third-direction DR3. The first gate electrode GE1 can be connected to the third source electrode SE3 of the third transistor T3 through the hole 40 of the capacitor electrode CPE, the lower gate connection electrode GCEa, and the upper gate connection electrode GCEb. Furthermore, the capacitor electrode CPE can be connected to the fifth source electrode SE5 of the fifth transistor T5 through the lower drive voltage line VDLa, which will be described later.

[0244] The fifth pattern layer 555 can be located on the fourth pattern layer 444 along the third direction DR3. An insulating layer can be located between the fourth pattern layer 444 and the fifth pattern layer 555. (As in...) Figure 17 and Figure 22 In the example shown, the fifth pattern layer 555 may include a second active layer ACT2. The second active layer ACT2 may include an active layer ACT2-1 (2-1) and an active layer ACT2-2 (2-2).

[0245] Active layer ACT2-1 (2-1) can provide the channel region, third source electrode SE3, and third drain electrode DE3 of the third transistor T3. Active layer ACT2-2 (2-2) can provide the channel region, fourth source electrode SE4, and fourth drain electrode DE4 of the fourth transistor T4.

[0246] The second active layer ACT2 can be, for example, an oxide semiconductor.

[0247] The sixth pattern layer 666 can be located on the fifth pattern layer 555 along the third direction DR3. An insulating layer can be located between the fifth pattern layer 555 and the sixth pattern layer 666. (As in...) Figure 17 and Figure 23 In the example shown, the sixth pattern layer 666 may include a third gate electrode GE3, a fourth gate electrode GE4, a lower gate connection electrode GCEa, a compensation gate line GCL, an initialization gate line GIL, a first emitter line EML1, a second emitter line EML2, and a bias voltage line VBL.

[0248] like Figure 17 and Figure 27 As shown, the third gate electrode GE3 can be stacked with the second-first active layer ACT2-1, and the fourth gate electrode GE4 can be stacked with the second-second active layer ACT2-2. The channel regions of the third transistor T3 and the fourth transistor T4 can be formed in the stacked regions between the third gate electrode GE3 and the second-first active layer ACT2-1, and the fourth gate electrode GE4 and the second-second active layer ACT2-2.

[0249] The third transistor T3 may include a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3.

[0250] The fourth transistor T4 may include a fourth gate electrode GE4, a fourth source electrode SE4, and a fourth drain electrode DE4.

[0251] The lower gate connection electrode GCEa can be connected to the first gate electrode GE1 through the contact hole of the insulating layer and the hole 40 of the capacitor electrode CPE.

[0252] The compensation gate line GCL may include a third gate electrode GE3. For example, a portion of the compensation gate line GCL may correspond to the third gate electrode GE3. The compensation gate line GCL and the third gate electrode GE3 may be integrally formed together.

[0253] The initial gate line (GIL) may include a fourth gate electrode (GE4). For example, a portion of the initial gate line (GIL) may correspond to the fourth gate electrode (GE4). The initial gate line (GIL) and the fourth gate electrode (GE4) may be integrally formed together.

[0254] The first emitter line EML1 can be connected to the fifth gate electrode GE5 through the contact hole in the insulating layer.

[0255] The second emitter line EML2 can be connected to the sixth gate electrode GE6 through the contact hole in the insulating layer.

[0256] The bias voltage line VBL can be connected to the seventh source electrode SE7 through the contact hole in the insulating layer.

[0257] The seventh pattern layer 777 can be located on the sixth pattern layer 666 along the third direction DR3. An insulating layer can be located between the sixth pattern layer 666 and the seventh pattern layer 777. (As in...) Figure 17 and Figure 24 In the example shown, the seventh pattern layer 777 may include a lower drive voltage line VDLa, a first auxiliary line VAL1, a second auxiliary line VAL2, an upper gate connection electrode GCEb, a lower anode connection electrode PCEa, an active connection electrode ACE, a data connection electrode DCE, and an initialization connection electrode ICE.

[0258] The lower driving voltage line VDLa can be stacked with the capacitor electrode CPE and the first gate electrode GE1. One side of the lower driving voltage line VDLa can be connected to the capacitor electrode CPE through contact holes in the insulating layer. The other side of the lower driving voltage line VDLa can be connected to the fifth source electrode SE5 through contact holes in the insulating layer. The lower driving voltage line VDLa can be connected to the upper driving voltage line VDLb, which will be described later. The lower driving voltage line VDLa and the upper driving voltage line VDLb can be connected to each other to form the driving voltage line VDL described above. For example, the driving voltage line VDL can include multiple lower driving voltage lines VDLa extending in a horizontal direction (e.g., the first direction DR1) and multiple upper driving voltage lines VDLb extending in a vertical direction (e.g., the second direction DR2). The driving voltage line VDL including the lower driving voltage lines VDLa and the upper driving voltage lines VDLb can have a grid shape.

[0259] One side of the first auxiliary line VAL1 can be connected to the lower drive voltage line VDLa within the data driver 220.

[0260] One side of the second auxiliary line VAL2 can be connected to the lower drive voltage line VDLa within the data driver 220.

[0261] One side of the upper gate connection electrode GCEb can be connected to the lower gate connection electrode GCEa through a contact hole in the insulating layer. The other side of the upper gate connection electrode GCEb can be connected to the third source electrode SE3 through a contact hole in the insulating layer.

[0262] One side of the active connection electrode ACE can be connected to the sixth source electrode SE6 of the first active layer ACT1 through the contact hole of the insulating layer. The other side of the active connection electrode ACE can be connected to the fourth drain electrode DE4 of the second-second active layer ACT2-2.

[0263] The lower anode connection electrode PCEa can be connected to the sixth drain electrode DE6 through the contact hole of the insulating layer.

[0264] The data connection electrode DCE can be connected to the second source electrode SE2 through the contact holes in the insulating layer.

[0265] One side of the initialization connection electrode ICE can be connected to the initialization voltage line VIL through the contact holes in the insulating layer. The other side of the initialization connection electrode ICE can be connected to the fourth source electrode SE4 through the contact holes in the insulating layer.

[0266] The eighth pattern layer 888 can be located on the seventh pattern layer 777 along the third direction DR3. An insulating layer can be located between the seventh pattern layer 777 and the eighth pattern layer 888. (As in...) Figure 17 and Figure 25 In the example shown, the eighth pattern layer 888 may include a data line DL, a line connection electrode VCE, an upper drive voltage line VDLb, and an upper anode connection electrode PCEb.

[0267] The data cable DL can be connected to the data connection electrode DCE through the contact holes in the insulation layer.

[0268] One side of the wire connection electrode VCE can be connected to the first auxiliary line VAL1 through the contact hole in the insulating layer. The other side of the wire connection electrode VCE can be connected to the second auxiliary line VAL2 through the contact hole in the insulating layer.

[0269] The upper driving voltage line VDLb can be connected to the lower driving voltage line VDLa through the contact hole of the insulating layer.

[0270] The upper anode connection electrode PCEb can be connected to the lower anode connection electrode PCEa through the contact holes in the insulating layer.

[0271] In one or more embodiments, a ninth pattern layer may be located on top of an eighth pattern layer 888 with an insulating layer therebetween. The ninth pattern layer may include, for example, an anode. The anode may be connected to the upper anode connection electrode PCEb through contact holes in the insulating layer.

[0272] Figure 28 This is a plan view of the seventh pattern layer 777 of a display device according to one or more embodiments. Figure 29 yes Figure 23 The sixth pattern layer 666 and Figure 28 The plan view of the seventh pattern layer 777.

[0273] Figure 28 The seventh pattern layer 777 and the above Figure 24 The difference in the seventh pattern layer 777 lies in the shape of the lower drive voltage line VDLa. Therefore, this difference will be mainly described below.

[0274] like Figure 28 As shown, the lower driving voltage line VDLa can extend further toward the second auxiliary line VAL2. According to one or more embodiments, the voltage of the gate electrode of the first transistor T1 (e.g., the third node N3) and the voltage of the anode of the light-emitting element ED (e.g., the drain electrode of the sixth transistor T6) can be initialized by a single transistor (e.g., the fourth transistor T4). Therefore, according to one or more embodiments, the number of transistors included in pixel PX can be reduced, which in turn increases the free area A of pixel PX. For example, as... Figure 24 As shown, the free region A can exist below the lower drive voltage line VDLa. Therefore, as Figure 28 As shown, the area of ​​the lower drive voltage line VDLa can be expanded by utilizing the vacant area A. For example, the lower drive voltage line VDLa may include an extended electrode VDLa11 located in the vacant area A. In this case, the resistance of the lower drive voltage line VDLa can be reduced. Therefore, the voltage drop (IR drop) can also be reduced, thus minimizing the deviation of the drive current Isd. Therefore, the image quality of the display device 10 can be improved.

[0275] like Figure 29 As shown, the extended electrode VDLa11 of the lower drive voltage line VDLa can be stacked with the first emitter line EML1, the second emitter line EML2 and the bias voltage line VBL.

[0276] According to one or more embodiments, even when the display device is driven at a low frequency, flicker can be reduced or minimized.

[0277] In addition, the display device according to one or more embodiments can reduce leakage current and voltage drop.

[0278] Furthermore, according to one or more embodiments of the display device, even when the image changes rapidly from a white grayscale level to a black grayscale level, it can accurately represent the image corresponding to the black grayscale level.

[0279] In addition, the display device according to one or more embodiments can reduce the swing width of the data voltage.

[0280] Therefore, the display device according to one or more embodiments can improve the image quality and power consumption of the display device.

[0281] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become more apparent to those skilled in the art upon reference to the claims.

[0282] The display device according to the embodiments can be applied to various electronic devices. An electronic device according to one embodiment includes the above-described display device, and may further include modules or devices with additional functions in addition to the display device.

[0283] Figure 30 This is a block diagram of an electronic device 50 according to one embodiment. (Refer to...) Figure 30 According to one embodiment, the electronic device 50 may include a display module 11, a processor 12, a memory 13, and a power module 14. The electronic device 50 may also include an input module 15, an output module (non-image output module) 16, and / or a communication module 17.

[0284] Electronic device 50 can output various information in the form of images through display module 11. When processor 12 executes an application stored in memory 13, the image information provided by the application can be provided to the user through display module 11. Power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of electronic device 50. Input module 15 can provide input information to processor 12 and / or display module 11. Output module 16 can receive information other than images (such as sound, touch, and light) sent from processor 12 and provide that information to the user. Communication module 17 is responsible for sending and receiving information between electronic device 50 and external devices, and may include receiving unit and sending unit.

[0285] At least one of the components of the electronic device 50 described above may be included in the display device according to the above embodiment. Furthermore, some modules functionally included in the electronic device 50 may be included in the display device, while other modules may be disposed separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be disposed within the electronic device 50 as other devices besides the display device.

[0286] Figure 31 , Figure 32 and Figure 33 These are schematic diagrams of electronic devices according to various embodiments. Figures 31 to 33 Examples of various electronic devices that utilize a display device according to an embodiment are shown.

[0287] Figure 31 Examples of electronic devices are shown, including a smartphone 10_1a, a tablet PC 10_1b, a laptop computer 10_1c, a TV 10_1d, and a desktop monitor 10_1e.

[0288] In addition to the display module, the smartphone 10_1a may also include an input module such as a touch sensor and a communication module. The smartphone 10_1a can process information received through the communication module or other input modules and display the information through the display module of the display device.

[0289] In the cases of tablet PC 10_1b, laptop computer 10_1c, TV 10_1d, and desktop monitor 10_1e, similar to smartphone 10_1a, they also include a display module and an input module, and in some cases may additionally include a communication module.

[0290] Figure 32 An example of an electronic device including a display module being used in a wearable electronic device is shown. The wearable electronic device may be smart glasses 10_2a, a head-mounted display 10_2b, a smartwatch 10_2c, etc.

[0291] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that emits a display image and a reflector that reflects the emitted display image and provides it to the user's eyes, thereby providing the user with virtual reality or augmented reality images.

[0292] The smartwatch 10_2c includes a biometric sensor as an input device and can provide the user with biometric information identified by the biometric sensor through a display module. Figure 33This illustrates an application of an electronic device, including a display module, in a vehicle. For example, the electronic device 10_3 can be applied to the vehicle's dashboard, central instrument panel, etc., or it can be applied to a CID (Central Information Display) placed on the vehicle's dashboard or an interior mirror display that replaces the side mirrors.

[0293] Those skilled in the art to which this disclosure pertains will understand that this disclosure may be implemented in other specific forms without altering its aspects. Therefore, it will be understood that the exemplary embodiments described above are illustrative in all respects and not restrictive. It will be understood that the scope of this disclosure is defined by the claims, not by the foregoing detailed description, and that all modifications and alterations derived from the claims and their equivalents fall within the scope of this disclosure.

Claims

1. A display device, the display device comprising: The first transistor is connected between the drive voltage line and the second node; The sixth transistor is connected between the second node and the common voltage line; A light-emitting element is connected between the sixth transistor and the common voltage line; as well as The fourth transistor is connected between the second node and the initialization voltage line.

2. The display device according to claim 1, wherein, The initialization voltage of the initialization voltage line is less than the driving voltage of the driving voltage line.

3. The display device according to claim 1, further comprising: The second transistor is connected between the data line and the first node; The third transistor is connected between the third node and the second node; The fifth transistor is connected between the drive voltage line and the first node; as well as The seventh transistor is connected between the bias voltage line and the first node. Wherein, the first transistor is connected between the first node and the second node, and The gate electrode of the first transistor is connected to the third node.

4. The display device according to claim 3, further comprising: Write the gate line, which is connected to the gate electrode of the second transistor; A compensation gate line is connected to the gate electrode of the third transistor; Initialize the gate line and connect it to the gate electrode of the fourth transistor; The first emitter line is connected to the gate electrode of the fifth transistor; The second emitter line is connected to the gate electrode of the sixth transistor; A bias gate line is connected to the gate electrode of the seventh transistor; as well as A capacitor is connected between the drive voltage line and the third node.

5. The display device according to claim 4, wherein, The write gate line is configured to transmit a write gate signal, the compensation gate line is configured to transmit a compensation gate signal, the initialization gate line is configured to transmit an initialization gate signal, the first emitter line is configured to transmit a first emitter signal, the second emitter line is configured to transmit a second emitter signal, the bias gate line is configured to transmit a bias gate signal, the drive voltage line is configured to transmit a drive voltage, the common voltage line is configured to transmit a common voltage, the initialization voltage line is configured to transmit an initialization voltage, and the bias voltage line is configured to transmit a bias voltage.

6. The display device according to claim 5, wherein, During the first time period, the second transmit signal and the initialization gate signal have valid levels, while the first transmit signal, the compensation gate signal, the write gate signal, and the bias gate signal have invalid levels.

7. The display device according to claim 6, wherein, During the second period following the first period, the compensation gate signal and the bias gate signal have valid levels, while the first transmit signal, the second transmit signal, the initialization gate signal, and the write gate signal have invalid levels.

8. The display device according to claim 7, wherein, In the third period following the second period, the initialization gate signal and the compensation gate signal have valid levels, and the first transmit signal, the second transmit signal, the write gate signal, and the bias gate signal have invalid levels.

9. The display device according to claim 8, wherein, In the fourth period following the third period, the compensation gate signal and the write gate signal have active levels, the first transmit signal, the second transmit signal, the initialization gate signal, and the bias gate signal have inactive levels, and the data voltage is provided to the data line.

10. The display device according to claim 9, wherein, In the fifth period following the fourth period, the compensation gate signal has an active level, and the first transmit signal, the second transmit signal, the initialization gate signal, the write gate signal, and the bias gate signal have inactive levels.

11. The display device according to claim 10, wherein, In the sixth period following the fifth period, the bias gate signal has an active level, and the first transmit signal, the second transmit signal, the initialization gate signal, the compensation gate signal, and the write gate signal have inactive levels.

12. The display device according to claim 11, wherein, In the seventh period following the sixth period, the initialization gate signal has an active level, and the first transmit signal, the second transmit signal, the compensation gate signal, the write gate signal, and the bias gate signal have inactive levels.

13. The display device according to claim 12, wherein, In the eighth period following the seventh period, the first transmit signal and the second transmit signal have valid levels, and the initialization gate signal, the compensation gate signal, the write gate signal, and the bias gate signal have invalid levels.

14. The display device according to claim 3, wherein, The fourth transistor includes a transistor of a different type from the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor.

15. The display device according to claim 14, wherein, The fourth transistor includes an n-type transistor, and the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor include p-type transistors.

16. The display device according to claim 14, wherein, The third transistor includes a transistor of the same type as the fourth transistor.

17. The display device according to claim 4, wherein, The driving voltage line includes: Lower drive voltage line; and An upper driving voltage line is located above the lower driving voltage line and is connected to the lower driving voltage line through contact holes in an insulating layer.

18. The display device according to claim 17, wherein, The lower drive voltage line includes an extended electrode.

19. The display device according to claim 18, wherein, The extended electrode is stacked with the first emitter line, the second emitter line, and the bias voltage line.

20. An electronic device, the electronic device including a display device, the display device comprising: The first transistor is connected between the drive voltage line and the second node; The sixth transistor is connected between the second node and the common voltage line; A light-emitting element is connected between the sixth transistor and the common voltage line; as well as The fourth transistor is connected between the second node and the initialization voltage line.

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