Driving and biasing circuit of pixel array

Abstract

The invention discloses a driving and biasing circuit of a pixel array, the pixel array is divided into M * N identical square sub-arrays, each pixel in each sub-array is provided with a driving branch, each driving branch comprises a current mirror PMOS tube MP0 and a switch PMOS tube MP1, the grid electrode of the current mirror PMOS tube MP0 is connected with a bias voltage VBP, the grid electrode of the switch PMOS tube MP1 is connected with the bias voltage VBP, and the grid electrode of the current mirror PMOS tube MP0 is connected with the bias voltage VBP. A grid electrode of the switch PMOS transistor MP1 is connected with a switch SW signal output by the data latch and switch control circuit, a drain electrode of the switch PMOS transistor MP1 is connected with a pixel, the bias branch comprises a first-stage current mirror array and a second-stage current mirror array which are connected, and the first-stage current mirror array is used for copying a reference current IREF into M * N parts and outputting an IBIAS current; and a second-stage current mirror array is arranged in each sub-array and is used for receiving IBIAS current and outputting bias voltage VBP, and the bias voltage VBP is connected with the driving branch in each sub-array.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of OLED micro display driving control, and in particular to a pixel array driving and biasing circuit. BACKGROUND

[0002] Micro-LED display technology has a significant competitive advantage in the high-end display market due to its excellent performance, and is experiencing unprecedented development opportunities. The biggest advantage of Micro-LED display is that it can achieve extremely high brightness, and has wide application prospects in micro-projection and intelligent lighting. However, high brightness means high power consumption and high current density, which puts higher requirements on the design of display driving chips.

[0003] The photoelectric properties of Micro-LED greatly limit its display driving method. The external quantum efficiency and the wavelength of light emission of Micro-LED change with the current. Especially when the current is small, the external quantum efficiency will decrease sharply with the decrease of the current, and the wavelength shift of red and green Micro-LED is also obvious. At the same time, compared with OLED and other light-emitting devices, the volt-ampere characteristic of Micro-LED is steep, and it is difficult to accurately control the brightness by voltage. These mean that the PAM (Pulse Amplitude Modulation) technology of controlling gray scale by controlling the current flowing through the light-emitting device is difficult to well apply in Micro-LED display driving. Under a larger constant current, the PWM (Pulse Width Modulation) technology of controlling gray scale by controlling the light-emitting time is a feasible solution. This constant large current PWM driving method can keep the energy conversion efficiency and the light-emitting wavelength of Micro-LED at the best state.

[0004] Due to the parasitic resistance between the power line and the common cathode line (usually a negative voltage power line) of Mirco-LED, a larger voltage drop often occurs in the application of large current. In the basic PWM driving structure with only one switching MOS tube, this power supply voltage drop will directly affect the voltage difference between the anode and cathode of Mirco-LED, causing serious display non-uniformity. The existing solution is to add a current mirror MOS tube between the switching MOS tube and the power line to minimize the impact of the common cathode negative voltage power supply voltage drop on the voltage difference between the anode and cathode of Mirco-LED. However, this method is still sensitive to anode voltage drop, and also introduces other factors that cause display non-uniformity, such as mismatch of the current mirror MOS tube. SUMMARY

[0005] Technical purposes: In view of the defects in the prior art, the application discloses a driving and biasing circuit of a pixel array, a biasing branch is divided into two stages, the number of single-stage current mirror replication is reduced, and the first-stage current mirror array is always kept in an open working state, so that the response speed of the pixel switch can be improved, and the display uniformity can be improved.

[0006] Technical scheme: In order to achieve the above technical purposes, the application adopts the following technical scheme.

[0007] A driving and biasing circuit of a pixel array comprises a driving branch and a biasing branch. The pixel array is divided into M*N identical square sub-arrays, each pixel in each sub-array is provided with a driving branch, the driving branch comprises a current mirror PMOS tube MP0 and a switch PMOS tube MP1, the source stage of the current mirror PMOS tube MP0 is connected with a pixel area power supply VLED, the gate of the current mirror PMOS tube MP0 is connected with a biasing voltage VBP, the biasing voltage VBP is transmitted and output through the biasing branch; the drain of the current mirror PMOS tube MP0 is connected with the source stage of the switch PMOS tube MP1, the gate of the switch PMOS tube MP1 is connected with a switch SW signal output by a data latch and a switch control circuit, and the drain of the switch PMOS tube MP1 is connected with a pixel, for controlling whether the pixel emits light. The biasing branch comprises a first-stage current mirror array and a second-stage current mirror array connected with each other. The first-stage current mirror array is used for copying the reference current IREF into M*N parts and outputting an IBIAS current; each sub-array is provided with a second-stage current mirror array, which is used for receiving the IBIAS current and outputting a biasing voltage VBP, the biasing voltage VBP is connected with the driving branch in each sub-array, and then each pixel in each sub-array is controlled.

[0008] Furthermore, the first-stage current mirror array comprises a reference circuit and M*N replication circuits; the reference circuit is connected with the reference current IREF, each replication circuit has the same structure, the reference circuit and each replication circuit form a common-source and common-gate current mirror, each replication circuit copies one part of the reference current, and the current output of the final IBIAS is controlled to be 1-4 times the current IREF.

[0009] Further, the reference circuit comprises NMOS tubes MN3-MN5; the drain of NMOS tube MN4 is connected with reference current IREF; the gate of NMOS tube MN4 is connected with the drain of NMOS tube MN4, the source of NMOS tube MN4 is connected with the drain of NMOS tube MN5, the gate of NMOS tube MN5 is connected with the drain of NMOS tube MN5, the source of NMOS tube MN5 is grounded; the drain of NMOS tube MN5 is connected with the drain of NMOS tube MN3, the source of NMOS tube MN3 is grounded, and the gate of NMOS tube MN3 is connected with enable signal EN.

[0010] Further, the copy circuit comprises PMOS tubes MP2-MP4, NMOS tubes MN0-MN2, NMOS tubes MN6-MN16; The gate of NMOS tube MN6 is connected with reference current IREF, and the drain of NMOS tube MN6 outputs IBIAS current; the source of NMOS tube MN6 is connected with the drain of NMOS tube MN7, the gate of NMOS tube MN7 is connected with the gate of NMOS tube MN5 in the reference circuit, and the source of NMOS tube MN7 is grounded; The drain of NMOS tube MN8 outputs IBIAS current; the source of NMOS tube MN8 is connected with the drain of NMOS tube MN9, the gate of NMOS tube MN9 is connected with the gate of NMOS tube MN5, and the source of NMOS tube MN9 is grounded; the gate of NMOS tube MN8 is connected with the source of NMOS tube MN0, the drain of NMOS tube MN14 and the drain of PMOS tube MP2; the drain of NMOS tube MN0 is connected with reference current IREF, and the gate of NMOS tube MN0 is connected with first control signal T0; the source of NMOS tube MN14 is grounded, and the gate of NMOS tube MN14 is connected with first control signal T0; the source of PMOS tube MP2 is connected with reference current IREF, and the gate of PMOS tube MP2 is connected with first control signal T0; The drain of NMOS tube MN10 outputs IBIAS current; the source of NMOS tube MN10 is connected with the drain of NMOS tube MN11, the gate of NMOS tube MN11 is connected with the gate of NMOS tube MN5, and the source of NMOS tube MN11 is grounded; the gate of NMOS tube MN10 is connected with the source of NMOS tube MN1, the drain of NMOS tube MN15 and the drain of PMOS tube MP3; the drain of NMOS tube MN1 is connected with reference current IREF, and the gate of NMOS tube MN1 is connected with second control signal T1; the source of NMOS tube MN15 is grounded, and the gate of NMOS tube MN15 is connected with second control signal T1; the source of PMOS tube MP3 is connected with reference current IREF, and the gate of PMOS tube MP3 is connected with second control signal T1; The drain of the NMOS transistor MN12 outputs an IBIAS current; the source of the NMOS transistor MN12 is connected to the drain of the NMOS transistor MN13, the gate of the NMOS transistor MN13 is connected to the gate of the NMOS transistor MN5, and the source of the NMOS transistor MN13 is grounded; the gate of the NMOS transistor MN12 is connected to the source of the NMOS transistor MN2, the drain of the NMOS transistor MN16, and the drain of the PMOS transistor MP4; the drain of the NMOS transistor MN2 is connected to a reference current IREF, and the gate of the NMOS transistor MN2 is connected to a second control signal T1; the source of the NMOS transistor MN16 is grounded, and the gate of the NMOS transistor MN16 is connected to the second control signal T1; the source of the PMOS transistor MP4 is connected to the reference current IREF, and the gate of the PMOS transistor MP4 is connected to the second control signal T1.

[0011] Further, the structure of the second-stage current mirror array includes PMOS transistors MP5-MP16 and NMOS transistors MN14-MN20; the PMOS transistors MP5-MP8 are used to form a current mirror with the current mirror PMOS transistor MP0 in the driving branch of each sub-array, and the PMOS transistors MP5-MP8 are reference transistors, the drains of which are connected to the IBIAS current output by the first-stage current mirror array, and the sources of which are connected to the pixel region power supply VLED.

[0012] Further, the gates of the PMOS transistors MP5 are connected to a first control unit, the first control unit includes an NMOS transistor MN17 and PMOS transistors MP15-MP16, the gates of the NMOS transistor MN17 and the PMOS transistor MP15 are connected to an enable signal EN, the source of the NMOS transistor MN17 is connected to the drain of the PMOS transistor MP15 and to the IBIAS current, the drain of the NMOS transistor MN17 is connected to the source of the PMOS transistor MP15 and to the gate of the PMOS transistor MP5 and the source of the PMOS transistor MP16, the drain of the PMOS transistor MP16 is grounded, and the gate of the PMOS transistor MP16 is connected to the enable signal EN; the PMOS transistor MP5 is controlled by the enable signal EN to remain in a default on state, and the gate of the PMOS transistor MP5 outputs a bias voltage VBP.

[0013] Further, the gates of the PMOS transistors MP6-MP8 are connected to a second control unit. The second control unit structure corresponding to the PMOS tube MP6 includes the NMOS tube MN18 and the PMOS tubes MP9 and MP12, the gate of the NMOS tube MN18 and the PMOS tube MP9 is connected with the first control signal T0, the source of the NMOS tube MN18 is connected with the drain of the PMOS tube MP9 and is connected with the IBIAS current, the drain of the NMOS tube MN18 is connected with the source of the PMOS tube MP9 and is connected with the gate of the PMOS tube MP6 and the drain of the PMOS tube MP12, the source of the PMOS tube MP12 is connected with the pixel area power supply VLED, and the gate of the PMOS tube MP12 is connected with the second control signal T1. The second control unit structure corresponding to the PMOS tube MP7 includes the NMOS tube MN19 and the PMOS tubes MP10 and MP13, the gate of the NMOS tube MN19 and the PMOS tube MP10 is connected with the second control signal T1, the source of the NMOS tube MN19 is connected with the drain of the PMOS tube MP10 and is connected with the IBIAS current, the drain of the NMOS tube MN19 is connected with the source of the PMOS tube MP10 and is connected with the gate of the PMOS tube MP7 and the drain of the PMOS tube MP13, the source of the PMOS tube MP13 is connected with the pixel area power supply VLED, and the gate of the PMOS tube MP13 is connected with the second control signal T1. The second control unit structure corresponding to the PMOS tube MP8 includes the NMOS tube MN20 and the PMOS tubes MP11 and MP14, the gate of the NMOS tube MN20 and the PMOS tube MP11 is connected with the second control signal T1, the source of the NMOS tube MN20 is connected with the drain of the PMOS tube MP11 and is connected with the IBIAS current, the drain of the NMOS tube MN20 is connected with the source of the PMOS tube MP11 and is connected with the gate of the PMOS tube MP8 and the drain of the PMOS tube MP14, the source of the PMOS tube MP14 is connected with the pixel area power supply VLED, and the gate of the PMOS tube MP14 is connected with the second control signal T1.

[0014] Furthermore, the PMOS tubes MP5 to MP8 and the current mirror PMOS tube MP0 are of the same size.

[0015] Furthermore, each subarray is divided into a digital logic region and an analog current replication region; the switch PMOS tube MP1 and the data latch and switch control circuit are located in the digital logic region, and the current mirror PMOS tube MP0 is located in the analog current replication region; in each analog current replication region, the current mirror PMOS tube MP0 and the replication PMOS tubes, i.e., the PMOS tubes MP5 to MP8, are centrally and symmetrically arranged.

[0016] Beneficial effects: (1) In the pixel array driving and biasing circuit of the application, the structure of the current mirror PMOS added in the driving branch makes the circuit have low requirements for the load end, and in the case that the cathode voltage of the Micro-LED is low enough to enable the current mirror PMOS to work in the saturation region, the voltage drop of the cathode voltage and the deviation of the impedance of the Micro-LED itself will not have obvious influence on the current output by the pixel driving, and the display uniformity can be greatly improved; (2) In the pixel array driving and biasing circuit of the application, the biasing branch is divided into two stages, the number of single-stage current mirror replication is reduced, and the first-stage current mirror array is always kept in an open working state, so that the response speed of the pixel switch can be improved, and the display uniformity can be improved; (3) In the pixel array driving and biasing circuit of the application, the voltage drop of the power supply line gradually increases from the periphery to the center of the pixel array, the second-stage current mirror array in the biasing branch adopts a square grid partition, the reference PMOS and the replicated PMOS are located in the same sub-array, compared with the simple row-column partition, the influence of the voltage drop of the power supply line is greatly reduced, and the display uniformity is improved; and in the square sub-array layout, the current mirror PMOS is not placed according to the actual position of the pixel, but all the pixel circuits are scattered and arranged in partitions, so that the current mirror PMOS can be concentrated as much as possible, and the environment is relatively uniform, and the uniformity is further improved. At the same time, the layout space utilization can be improved; (4) In the pixel array driving and biasing circuit of the application, the number of reference PMOS in the biasing branch is increased and uniformly distributed, which can reduce the display unevenness caused by MOS mismatch and voltage drop of the power supply line in a small area; a plurality of working modes are set, the performance of the output is changed by selecting the current transmission ratio and the number of MOS in parallel in the current mirror, and in the case that different load Micro-LEDs are connected, more kinds of use scene requirements can be met, and the adaptation range of the driving chip is greatly improved; (5) Compared with PAM, the brightness gray scale adjustment mode of PWM is adopted in the application, the constant current is obtained through the current mirror PMOS in the driving branch and the reference current generation and replication circuit, the Micro-LED can always maintain a constant driving current when lighting, the switching PMOS, the data latch and the switching control circuit control the pixel switching time, the energy conversion efficiency and the light emitting wavelength are kept in the best state, and the brightness gray scale adjustment is more linear; (6) The application is achieved by using a conventional CMOS process. SRAM (static random access memory) can be used for storage in the pixel, the arrangement of the pixel is more flexible, no capacitor is needed, the process is simple, the cost is low, and it is easy to implement. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1This is a schematic diagram of a pixel array driving and biasing circuit according to an embodiment of the present invention; Figure 2 This is a structural diagram of the first-stage current mirror array in the bias branch of an embodiment of the present invention; Figure 3 This is a structural diagram of the second-stage current mirror array in the bias branch of an embodiment of the present invention; Figure 4 This is one embodiment of the partitioned pixel array analog current replication region arrangement method of the present invention; Figure 5 These are schematic diagrams illustrating four different working modes in embodiments of the present invention; Figure 6 A block diagram of a pixel array driving and biasing circuit structure according to an embodiment of the present invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application. Example

[0019] As attached Figure 1 and attached Figure 6 As shown, a pixel array driving and biasing circuit of this embodiment includes a driving branch and a biasing branch. The pixel array is divided into M×N identical square subarrays. Each pixel in each subarray has a driving branch, which includes a current mirror PMOS transistor MP0 and a switching PMOS transistor MP1. The source of the current mirror PMOS transistor MP0 is connected to the pixel area power supply VLED, and the gate of the current mirror PMOS transistor MP0 is connected to the bias voltage VBP. The bias voltage VBP is transmitted and output through the reference current generation and replication circuit. The drain of the current mirror PMOS transistor MP0 is connected to the source of the switching PMOS transistor MP1. The gate of the switching PMOS transistor MP1 is connected to the switching signal SW output by the data latch and switching control circuit, and the drain of the switching PMOS transistor MP1 is connected to the pixel output terminal Micro-LED to control whether the pixel emits light.

[0020] Among them, the current mirror PMOS tube MP0 selects a low-voltage device, and the size and width-length ratio are as large as possible within the allowable range to realize smaller mismatch error, stronger over-current capacity and lower power consumption, and the switch PMOS tube MP1 selects a higher voltage device to enhance the voltage resistance and reduce the leakage, while the width-length ratio is as large as possible within the allowable range to support larger current and reduce the loss of power consumption.

[0021] The present application keeps the gate-source voltage V GS of each current mirror PMOS tube consistent, so that the current output by each pixel is consistent.

[0022] The data latch and switch control circuit is composed of SRAM and logic gates, and is used to control whether the pixel emits light or not. The data latch and switch control circuit is realized by the prior art, and will not be described here. The data latch and switch control circuit is used to store the gray scale data of the pixel and open the switch PMOS tube according to time, and controls the gray scale of the output end Micro-LED in the PWM mode. The switch PMOS tube only has two working states of opening and closing, and needs a large width-length ratio to reduce the voltage drop caused by the opening resistance between the source and the drain, thereby reducing the power consumption. At the same time, since the voltage difference between the source and the drain is large in the off state, a PMOS tube with a higher voltage can be used to prevent over-voltage and reduce leakage.

[0023] The driving branch composed of the current mirror PMOS tube MP0 and the switch PMOS tube MP1 can keep the driving current of the Micro-LED constant when it is lit, and can keep the energy conversion efficiency and the light-emitting wavelength in the best state, and the brightness and gray scale adjustment is also more linear. At the same time, the voltage drop of the cathode voltage and the deviation of the impedance of the Micro-LED itself will not have a significant impact on the current output by the pixel driving, and the display uniformity can be greatly improved.

[0024] The reference current generation and replication circuit includes a reference current generation circuit and a bias branch; the reference current generation circuit is used to generate a reference current IREF; the reference current generation circuit includes a connected bandgap reference circuit and a voltage-to-current circuit, wherein the bandgap reference circuit is used to generate a temperature-independent reference voltage VREF, and the voltage-to-current circuit is used to convert the reference voltage VREF into the reference current IREF through an adjustable resistor. In the present application, the reference current generation circuit is realized by the prior art, and will not be described here.

[0025] Among them, the reference current can be adjusted through the adjustable resistor, so that in addition to the PWM light adjustment, another light adjustment mode is added. However, due to the characteristics of the Micro-LED, this light adjustment mode will cause a certain degree of deviation in the light-emitting efficiency and the wavelength. Here, the adjustment is mainly to keep the energy conversion efficiency and the light-emitting wavelength of the Micro-LED in the best state. The finally obtained reference current is replicated to the entire pixel array through the current mirror network.

[0026] The bias branch includes a first-stage current mirror array and a second-stage current mirror array that are connected. The first-stage current mirror array is used to copy the reference current IREF into several sub-arrays, i.e., M×N parts, and output the IBIAS current. Each sub-array has a second-stage current mirror array, which is used to receive the IBIAS current and output the bias voltage VBP. The bias voltage VBP is connected to the drive branch in each sub-array, thereby controlling each pixel in each sub-array. As attached Figure 2 As shown, the first-stage current mirror array includes a reference circuit and M×N replica circuits. The reference circuit is connected to the reference current IREF. Each replica circuit has the same structure. The reference circuit and each replica circuit form a common-source common-gate current mirror. Each replica circuit replicates the reference current and controls the final IBIAS current output to be 1 to 4 times the current of IREF.

[0027] The reference circuit includes NMOS transistors MN3-MN5; NMOS transistors MN4-MN5 are reference transistors, with the drain of NMOS transistor MN4 connected to the reference current IREF. The gate of NMOS transistor MN4 is connected to the drain of NMOS transistor MN4, the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN5, the gate of NMOS transistor MN5 is connected to the drain of NMOS transistor MN5, and the source of NMOS transistor MN5 is grounded; the drain of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3, the source of NMOS transistor MN3 is grounded, and the gate of NMOS transistor MN3 is connected to the enable signal EN; the operation of the first-stage current mirror array is controlled by NMOS transistor MN3.

[0028] Each replication circuit has the same structure, including: PMOS transistors MP2~MP4, NMOS transistors MN0~MN2, and NMOS transistors MN6~MN16; NMOS transistors MN4~MN5 in the reference circuit and NMOS transistors MN6~MN13 in each replication circuit form a common-source, common-gate current mirror, wherein: The gate of NMOS transistor MN6 is connected to the reference current IREF, and the drain of NMOS transistor MN6 outputs the IBIAS current; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN7 is grounded. The drain of the NMOS transistor MN8 outputs an IBIAS current; the source of the NMOS transistor MN8 is connected with the drain of the NMOS transistor MN9, the gate of the NMOS transistor MN9 is connected with the gate of the NMOS transistor MN5, and the source of the NMOS transistor MN9 is grounded; the gate of the NMOS transistor MN8 is connected with the source of the NMOS transistor MN0, the drain of the NMOS transistor MN14 and the drain of the PMOS transistor MP2; the drain of the NMOS transistor MN0 is connected with a reference current IREF, and the gate of the NMOS transistor MN0 is connected with a first control signal T0; the source of the NMOS transistor MN14 is grounded, and the gate of the NMOS transistor MN14 is connected with the first control signal T0; the source of the PMOS transistor MP2 is connected with the reference current IREF, and the gate of the PMOS transistor MP2 is connected with the first control signal T0; The drain of the NMOS transistor MN10 outputs an IBIAS current; the source of the NMOS transistor MN10 is connected with the drain of the NMOS transistor MN11, the gate of the NMOS transistor MN11 is connected with the gate of the NMOS transistor MN5, and the source of the NMOS transistor MN11 is grounded; the gate of the NMOS transistor MN10 is connected with the source of the NMOS transistor MN1, the drain of the NMOS transistor MN15 and the drain of the PMOS transistor MP3; the drain of the NMOS transistor MN1 is connected with a reference current IREF, and the gate of the NMOS transistor MN1 is connected with a second control signal T1; the source of the NMOS transistor MN15 is grounded, and the gate of the NMOS transistor MN15 is connected with the second control signal T1; the source of the PMOS transistor MP3 is connected with the reference current IREF, and the gate of the PMOS transistor MP3 is connected with the second control signal T1; The drain of the NMOS transistor MN12 outputs an IBIAS current; the source of the NMOS transistor MN12 is connected with the drain of the NMOS transistor MN13, the gate of the NMOS transistor MN13 is connected with the gate of the NMOS transistor MN5, and the source of the NMOS transistor MN13 is grounded; the gate of the NMOS transistor MN12 is connected with the source of the NMOS transistor MN2, the drain of the NMOS transistor MN16 and the drain of the PMOS transistor MP4; the drain of the NMOS transistor MN2 is connected with a reference current IREF, and the gate of the NMOS transistor MN2 is connected with a second control signal T1; the source of the NMOS transistor MN16 is grounded, and the gate of the NMOS transistor MN16 is connected with the second control signal T1; the source of the PMOS transistor MP4 is connected with the reference current IREF, and the gate of the PMOS transistor MP4 is connected with the second control signal T1; The NMOS tubes MN6-MN7, the NMOS tubes MN8-MN9, the NMOS tubes MN10-MN11 and the NMOS tubes MN12-MN13 each copy a reference current, the MN6-MN7 path keeps default conduction, the MN8-MN9, MN10-MN11 and MN12-MN13 paths are selected to be conducted or not under the control of the T0 and T1 two control signals through MN0-2, MP2-4 and MP14-16, and the current output of the IBIAS is 1-4 times the current of IREF; the number of the output IBIAS is consistent with the number of the subarray, that is, the number of the subarray is the same, and each subarray corresponds to a copy circuit, that is, there is one IBIAS and the corresponding MN6-13, so as to ensure that the current of each IBIAS is consistent. In the work, the first-stage current mirror is always kept open, and the response speed of the pixel switch can be improved.

[0029] In order to improve the uniformity and the response speed of the switch pixel, the current mirror array in the application is divided into two stages, and the whole pixel array is divided into M*N same square small arrays; the first-stage current mirror network copies the reference current M*N times, and the second-stage current mirror network copies into each pixel again.

[0030] As shown in the accompanying drawings, Figure 3 The structure of the second-stage current mirror array includes PMOS tubes MP5-16 and NMOS tubes MN14-20; the PMOS tubes MP5-8 are used to form a current mirror with the current mirror PMOS tube MP0 in each subarray driving branch, the PMOS tubes MP5-8 are reference tubes, the drains are connected with the IBIAS current output by the first-stage current mirror array, and the sources are connected with the pixel area power supply VLED; The gates of the PMOS tubes MP5 are connected with the first control unit, and the gates of the PMOS tubes MP6-8 are connected with the second control unit; The first control unit includes an NMOS tube MN17 and PMOS tubes MP15-16, the gates of the NMOS tube MN17 and the PMOS tube MP15 are connected with an enable signal EN, the source of the NMOS tube MN17 is connected with the drain of the PMOS tube MP15 and the IBIAS current, the drain of the NMOS tube MN17 is connected with the source of the PMOS tube MP15 and the gate of the PMOS tube MP5, the source of the PMOS tube MP16, the drain of the PMOS tube MP16 is grounded, and the gate of the PMOS tube MP16 is connected with the enable signal EN; the PMOS tube MP5 keeps default conduction under the control of the enable signal EN, and the gate outputs a bias voltage VBP; The second control unit structure corresponding to the PMOS tube MP6 includes the NMOS tube MN18 and the PMOS tubes MP9 and MP12, the gates of the NMOS tube MN18 and the PMOS tube MP9 are connected with the first control signal T0, the source of the NMOS tube MN18 is connected with the drain of the PMOS tube MP9 and is connected with the IBIAS current, the drain of the NMOS tube MN18 is connected with the source of the PMOS tube MP9 and is connected with the gate of the PMOS tube MP6 and the drain of the PMOS tube MP12, the source of the PMOS tube MP12 is connected with the pixel area power supply VLED, and the gate of the PMOS tube MP12 is connected with the second control signal T1.

[0031] The second control unit structure corresponding to the PMOS tube MP7 includes the NMOS tube MN19 and the PMOS tubes MP10 and MP13, the gates of the NMOS tube MN19 and the PMOS tube MP10 are connected with the second control signal T1, the source of the NMOS tube MN19 is connected with the drain of the PMOS tube MP10 and is connected with the IBIAS current, the drain of the NMOS tube MN19 is connected with the source of the PMOS tube MP10 and is connected with the gate of the PMOS tube MP7 and the drain of the PMOS tube MP13, the source of the PMOS tube MP13 is connected with the pixel area power supply VLED, and the gate of the PMOS tube MP13 is connected with the second control signal T1.

[0032] The second control unit structure corresponding to the PMOS tube MP8 includes the NMOS tube MN20 and the PMOS tubes MP11 and MP14, the gates of the NMOS tube MN20 and the PMOS tube MP11 are connected with the second control signal T1, the source of the NMOS tube MN20 is connected with the drain of the PMOS tube MP11 and is connected with the IBIAS current, the drain of the NMOS tube MN20 is connected with the source of the PMOS tube MP11 and is connected with the gate of the PMOS tube MP8 and the drain of the PMOS tube MP14, the source of the PMOS tube MP14 is connected with the pixel area power supply VLED, and the gate of the PMOS tube MP14 is connected with the second control signal T1.

[0033] Wherein, the PMOS tubes MP5~MP8 and the current mirror PMOS tube MP0 are the same size; the PMOS tubes MP5~MP8 are used for dividing the IBIAS current; the PMOS tubes MP6~MP8 are selected to be turned on or not under the control of the first control signal T0 and the second control signal T1 through the NMOS tubes MN18-MN20 and the PMOS tubes MP9-MP14, so that the current output of the current mirror PMOS tube MP0 is 1 times, 1 / 2 times, 1 / 3 times or 1 / 4 times of the IBIAS current. In combination with the first and second current mirror arrays, the current replicated by the driving branch of the final pixel circuit is always equal to the reference current IREF output by the reference current generating circuit. The design of multiple reference tubes can reduce the display unevenness caused by MOS tube mismatch and small area power line voltage drop. MN17, MP15~16 can control the bias voltage VBP to be 0 through the enable signal EN. In the case of bias voltage VBP being 0, the entire current mirror array does not work, and the pixel output current is directly related to the load, which can save power consumption in special use scenarios.

[0034] Each subarray is divided into a digital logic region and an analog current replication region. The switch PMOS tube MP1 and the data latch and switch control circuit are located in the digital logic region, which has lower requirements for matching and power supply and is only responsible for controlling the conduction or not of the analog current replication region and the output end Micro-LED. The current mirror PMOS tube MP0 is located in the analog current replication region. In each analog current replication region, there are independent reference PMOS tubes, i.e. MP0 and replication PMOS tubes, i.e. MP5~MP8, so that the source power voltages of the reference and replication PMOS tubes are relatively consistent. In this way, under the same bias voltage, the source-drain voltages are as consistent as possible, so that the drain currents of each replication PMOS tube are as consistent as possible. The current mirror PMOS tube MP0 and the replication PMOS tube, i.e. MP5~MP8, can be placed centrally and symmetrically. The more concentrated the placement area is, the closer to the square it is, so that the power supply voltage drop in this area is smaller. At the same time, the number of reference PMOS tubes can be increased, which can greatly reduce the influence of PMOS tube mismatch on pixel uniformity under the condition of increasing a small amount of power consumption, and can also improve the corresponding speed and anti-aliasing capability of the pixel. Finally, the reference PMOS tubes can be uniformly distributed in various parts of the analog current replication region, so that the average source voltage of each reference PMOS tube is closer to the average source voltage of the replication PMOS tube, thereby further reducing the influence of internal power supply voltage drop in each small array module. The current mirror PMOS tube normally works in the saturation region and should be as large as possible to reduce the replication current deviation caused by mismatch. At the same time, dummy is added around to make each current mirror PMOS tube in a relatively consistent environment.

[0035] The application scenarios of micro-LED display are various, and the requirements and priorities of various performance indicators such as brightness, uniformity, refresh rate and power consumption are different. In the same pixel driving array and bias network, multiple working modes can also be set. The performance of the output is changed by selecting the current transmission ratio and the number of MOS tubes in parallel in the current mirror. In this way, the same driving chip can meet the needs of more use scenarios when accessing different load micro-LEDs, greatly improving the adaptation range of the driving chip.

[0036] Figure 1 is a schematic diagram of a pixel array of an embodiment of the present application. Figure 4 Figure 1 is a schematic diagram of a pixel array of an embodiment of the present application.

[0037] Figure 1 is a schematic diagram of a pixel array of an embodiment of the present application. Figure 5 Figure 1 is a schematic diagram of a pixel array of an embodiment of the present application.

[0038] Table 1 Comparison of four different working modes

[0039] 4 working modes can be selected by T1, T0 two control signals in the embodiments are 00, 01, 10, 11. The main difference is that the IBIAS copied by the first-stage current mirror is multiple of the reference current IREF. Among them, T1, T0 are 00, which is the lowest power consumption single-tube replication mode, IBIAS is equal to IREF. At this time, the power consumption of the entire bias network is the lowest. But due to the small input current, the data signal fluctuation has a higher impact on the output current, and the response speed of the pixel switch is slower. At the same time, since there is only one reference tube in the second-stage current mirror array, the MOS tube mismatch has a greater impact on the replication accuracy, and the power supply voltage drop resistance is poor in small arrays. However, due to the overall structure of the two-stage current mirror replication, and the second-stage current mirror is placed according to the chessboard grid, there will still be no obvious large-area display unevenness. This working mode is suitable for low refresh rate and not very high pixel uniformity requirement scene. As the multiple of IBIAS is the multiple of the reference current IREF, the bias array power consumption increases in proportion, and the performance of the pixel driving array and the bias network is improved. T1, T0 are 01 and 10, which correspond to double-tube replication and triple-tube replication in Table 1 respectively; T1, T0 are 11, which is the highest performance four-tube replication mode, IBIAS is 4 times IREF. In the four-tube replication mode, the display unevenness caused by MOS tube mismatch and small area power line voltage drop can be reduced to the maximum. Large input current can improve the resistance of output current to data signal fluctuation and improve the response speed. The performance of the pixel driving array and the bias network is the best. Although the bias network power consumption is 4 times that of the single-tube replication mode, but the display uniformity improvement benefit is obvious. And the bias network power consumption accounts for a small proportion of the entire pixel driving array power consumption, in the embodiment of the application, only accounts for 1 / 100~1 / 25. This working mode is suitable for high refresh rate and extremely high display uniformity requirement scene. Figure 4

[0040] The above only describes the preferred embodiments of the present application, and it should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which improvements and refinements should also be considered as the protection scope of the present application.​

Claims

1. A driving and biasing circuit for a pixel array, characterized in that, Includes drive branches and bias branches; The pixel array is divided into M×N identical square subarrays. Each pixel in each subarray has a driving branch, which includes a current mirror PMOS transistor MP0 and a switching PMOS transistor MP1. The source of the current mirror PMOS transistor MP0 is connected to the pixel area power supply VLED, and the gate of the current mirror PMOS transistor MP0 is connected to the bias voltage VBP. The bias voltage VBP is transmitted and output through the reference current generation and replication circuit. The drain of the current mirror PMOS transistor MP0 is connected to the source of the switching PMOS transistor MP1. The gate of the switching PMOS transistor MP1 is connected to the switching signal SW output by the data latch and switching control circuit, and the drain of the switching PMOS transistor MP1 is connected to the output terminal Micro-LED to control whether the pixel emits light. The reference current generation and replication circuit includes a reference current generation circuit and a bias branch; The reference current generation circuit is used to generate the reference current IREF; The bias branch includes a first-stage current mirror array and a second-stage current mirror array that are connected. The first-stage current mirror array is used to copy the reference current IREF into M×N copies and output the IBIAS current. Each subarray has a second-stage current mirror array, which is used to receive the IBIAS current and output the bias voltage VBP. The bias voltage VBP is connected to the drive branch in each subarray, thereby controlling each pixel in each subarray.

2. The driving and biasing circuit for a pixel array according to claim 1, characterized in that, The first-stage current mirror array includes a reference circuit and M×N replica circuits; The reference circuit is connected to the reference current IREF. Each replica circuit has the same structure. The reference circuit and each replica circuit form a common source cascode current mirror. Each replica circuit copies the reference current and controls the final IBIAS current output to be 1 to 4 times the current of IREF.

3. The driving and biasing circuit for a pixel array according to claim 1, characterized in that, The reference circuit includes NMOS transistors MN3 to MN5; the drain of NMOS transistor MN4 is connected to the reference current IREF; the gate of NMOS transistor MN4 is connected to the drain of NMOS transistor MN4, the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN5, the gate of NMOS transistor MN5 is connected to the drain of NMOS transistor MN5, and the source of NMOS transistor MN5 is grounded; the drain of NMOS transistor MN5 is connected to the drain of NMOS transistor MN3, the source of NMOS transistor MN3 is grounded, and the gate of NMOS transistor MN3 is connected to the enable signal EN.

4. The driving and biasing circuit for a pixel array according to claim 1, characterized in that, The replication circuit includes: PMOS transistors MP2~MP4, NMOS transistors MN0~MN2, and NMOS transistors MN6~MN16; The gate of NMOS transistor MN6 is connected to the reference current IREF, and the drain of NMOS transistor MN6 outputs the IBIAS current; the source of NMOS transistor MN6 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7 is connected to the gate of NMOS transistor MN5 in the reference circuit, and the source of NMOS transistor MN7 is grounded. The drain of NMOS transistor MN8 outputs the IBIAS current; the source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN9, the gate of NMOS transistor MN9 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN9 is grounded; the gate of NMOS transistor MN8 is connected to the source of NMOS transistor MN0, the drain of NMOS transistor MN14, and the drain of PMOS transistor MP2; the drain of NMOS transistor MN0 is connected to the reference current IREF, and the gate of NMOS transistor MN0 is connected to the first control signal T0; the source of NMOS transistor MN14 is grounded, and the gate of NMOS transistor MN14 is connected to the first control signal T0; the source of PMOS transistor MP2 is connected to the reference current IREF, and the gate of PMOS transistor MP2 is connected to the first control signal T0. The drain of NMOS transistor MN10 outputs the IBIAS current; the source of NMOS transistor MN10 is connected to the drain of NMOS transistor MN11, the gate of NMOS transistor MN11 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN11 is grounded; the gate of NMOS transistor MN10 is connected to the source of NMOS transistor MN1, the drain of NMOS transistor MN15, and the drain of PMOS transistor MP3; the drain of NMOS transistor MN1 is connected to the reference current IREF, and the gate of NMOS transistor MN1 is connected to the second control signal T1; the source of NMOS transistor MN15 is grounded, and the gate of NMOS transistor MN15 is connected to the second control signal T1; the source of PMOS transistor MP3 is connected to the reference current IREF, and the gate of PMOS transistor MP3 is connected to the second control signal T1. The drain of NMOS transistor MN12 outputs the IBIAS current; the source of NMOS transistor MN12 is connected to the drain of NMOS transistor MN13, the gate of NMOS transistor MN13 is connected to the gate of NMOS transistor MN5, and the source of NMOS transistor MN13 is grounded; the gate of NMOS transistor MN12 is connected to the source of NMOS transistor MN2, the drain of NMOS transistor MN16, and the drain of PMOS transistor MP4; the drain of NMOS transistor MN2 is connected to the reference current IREF, and the gate of NMOS transistor MN2 is connected to the second control signal T1; the source of NMOS transistor MN16 is grounded, and the gate of NMOS transistor MN16 is connected to the second control signal T1; the source of PMOS transistor MP4 is connected to the reference current IREF, and the gate of PMOS transistor MP4 is connected to the second control signal T1.

5. The driving and biasing circuit for a pixel array according to claim 1, characterized in that, The structure of the second-stage current mirror array includes PMOS transistors MP5~MP16 and NMOS transistors MN14~MN20. PMOS transistors MP5~MP8 are used to form a current mirror with the current mirror PMOS transistor MP0 in the driving branch of each sub-array. PMOS transistors MP5~MP8 are reference transistors. The drain of each is connected to the IBIAS current output by the first-stage current mirror array, and the source is connected to the pixel area power supply VLED.

6. The driving and biasing circuit for a pixel array according to claim 5, characterized in that, The gates of PMOS transistors MP5 are all connected to the first control unit, which includes NMOS transistors MN17 and PMOS transistors MP15-MP16. The gates of NMOS transistors MN17 and MP15 are connected to the enable signal EN. The source of NMOS transistor MN17 is connected to the drain of PMOS transistor MP15 and connected to the IBIAS current. The drain of NMOS transistor MN17 is connected to the source of PMOS transistor MP15 and to the gate of PMOS transistor MP5 and the source of PMOS transistor MP16. The drain of PMOS transistor MP16 is grounded, and the gate of PMOS transistor MP16 is connected to the enable signal EN. PMOS transistor MP5 remains on by default under the control of the enable signal EN, and its gate output bias voltage VBP.

7. The driving and biasing circuit for a pixel array according to claim 5, characterized in that, The gates of PMOS transistors MP6 to MP8 are all connected to the second control unit; The second control unit structure corresponding to PMOS transistor MP6 includes NMOS transistor MN18, PMOS transistor MP9, and PMOS transistor MP12. The gates of NMOS transistor MN18 and PMOS transistor MP9 are connected to the first control signal T0. The source of NMOS transistor MN18 is connected to the drain of PMOS transistor MP9 and connected to the IBIAS current. The drain of NMOS transistor MN18 is connected to the source of PMOS transistor MP9 and connected to the gate of PMOS transistor MP6 and the drain of PMOS transistor MP12. The source of PMOS transistor MP12 is connected to the pixel area power supply VLED. The gate of PMOS transistor MP12 is connected to the second control signal T1. The second control unit structure corresponding to PMOS transistor MP7 includes NMOS transistor MN19, PMOS transistor MP10, and PMOS transistor MP13. The gates of NMOS transistor MN19 and PMOS transistor MP10 are connected to the second control signal T1. The source of NMOS transistor MN19 is connected to the drain of PMOS transistor MP10 and connected to the IBIAS current. The drain of NMOS transistor MN19 is connected to the source of PMOS transistor MP10 and connected to the gate of PMOS transistor MP7 and the drain of PMOS transistor MP13. The source of PMOS transistor MP13 is connected to the pixel area power supply VLED. The gate of PMOS transistor MP13 is connected to the second control signal T1. The second control unit structure corresponding to PMOS transistor MP8 includes NMOS transistor MN20, PMOS transistor MP11, and PMOS transistor MP14. The gates of NMOS transistor MN20 and PMOS transistor MP11 are connected to the second control signal T1. The source of NMOS transistor MN20 is connected to the drain of PMOS transistor MP11 and connected to the IBIAS current. The drain of NMOS transistor MN20 is connected to the source of PMOS transistor MP11 and connected to the gate of PMOS transistor MP8 and the drain of PMOS transistor MP14. The source of PMOS transistor MP14 is connected to the pixel area power supply VLED, and the gate of PMOS transistor MP14 is connected to the second control signal T1.

8. The driving and biasing circuit for a pixel array according to claim 5, characterized in that, PMOS transistors MP5~MP8 and current mirror PMOS transistor MP0 have the same dimensions.

9. The driving and biasing circuit for a pixel array according to claim 5, characterized in that, Each subarray is divided into a digital logic region and an analog current replication region; the switching PMOS transistor MP1 and the data latch and switching control circuit are located in the digital logic region, and the current mirror PMOS transistor MP0 is located in the analog current replication region; in each analog current replication region, the current mirror PMOS transistor MP0 and the replication PMOS transistors, namely PMOS transistors MP5~MP8, are centrally and symmetrically placed.

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