Memory circuit, voltage supply circuit and operation method thereof

Abstract

The present disclosure provides a memory circuit, a voltage providing circuit and an operating method thereof. The memory circuit comprises a memory array and a voltage supply circuit. The memory array comprises a plurality of memory units. The voltage providing circuit provides an operating voltage for one or more of the plurality of memory cells, the operating voltage being shifted from a first voltage domain to a second voltage domain. The voltage providing circuit includes a voltage detector, and the voltage detector is configured to receive a first supply voltage in a first voltage domain, is powered by a second supply voltage in a second voltage domain, and provides a first control signal. The first control signal is used to determine whether the operating voltage is equal to the second supply voltage in the first logic state or equal to the second supply voltage in the second logic state.

Description

Technical Field

[0001] This disclosure relates to a memory circuit, a voltage supply circuit, and a method of operation thereof. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). These improvements in integration density primarily stem from the continuous reduction in the size of the smallest feature, allowing more components to be integrated into a given area. Summary of the Invention

[0003] This disclosure provides a memory circuit including a memory array and a voltage supply circuit. The memory array includes a plurality of memory cells. The voltage supply circuit provides an operating voltage to one or more of the plurality of memory cells, the operating voltage being shifted from a first voltage domain to a second voltage domain. The voltage supply circuit includes a voltage detector for receiving a first supply voltage in the first voltage domain, powered by a second supply voltage in the second voltage domain, and providing a first control signal. The first control signal is used to determine whether the operating voltage is equal to the second supply voltage in a first logic state or equal to the second supply voltage in a second logic state.

[0004] This disclosure provides a voltage supply circuit including a voltage detector, a logic gate, and a first n-type transistor. The voltage detector is powered by a first supply voltage in a first voltage domain and is used to receive a second supply voltage in a second voltage domain and provide a first control signal, wherein the first supply voltage in a logic high state is higher than the second supply voltage in a logic high state. The logic gate is used to provide a second control signal based on the first control signal, wherein the first control signal and the second control signal are in the first voltage domain. The first n-type transistor has a gate terminal for receiving the second control signal via a first inverter, a drain terminal coupled to an output node for providing an operating voltage to a memory circuit, and a source terminal coupled to ground. When the first supply voltage is in a logic high state and the second supply voltage is in a logic low state, the second control signal is output in a logic high state through the logic gate.

[0005] This disclosure provides an operational method for providing an operating voltage to a memory circuit, comprising the following steps: receiving a first supply voltage transitioning in a first voltage domain and a second supply voltage transitioning in a second voltage domain, wherein the first voltage domain is different from the second voltage domain; after identifying a memory circuit configured in a first operating mode, providing an operating voltage equal to the second supply voltage having a first logic state; after identifying a memory circuit configured in a second operating mode, providing an operating voltage equal to the second supply voltage having a second logic state; and after identifying a memory circuit configured in a third operating mode, providing an operating voltage equal to the second supply voltage having a first logic state. In the first operating mode, the first supply voltage and the second supply voltage each have a second logic state; in the second operating mode, the first supply voltage and the second supply voltage each have a second logic state; and in the third operating mode, the first supply voltage and the second supply voltage each have a first logic state and a second logic state, respectively. Attached Figure Description

[0006] The embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1 An exemplary block diagram of a memory circuit according to some embodiments is shown;

[0008] Figure 2 Illustrations based on some embodiments Figure 1 An exemplary schematic diagram of a memory cell in a memory circuit;

[0009] Figure 3 Illustrations based on some embodiments and Figure 1 An exemplary circuit diagram of a voltage supply circuit coupled to or integrated with memory circuitry;

[0010] Figure 4 The illustrations are included according to some embodiments. Figure 3 An exemplary circuit diagram of a voltage detector in a voltage supply circuit;

[0011] Figure 5 Illustrations based on some embodiments and Figure 1 An exemplary circuit diagram of a voltage supply circuit coupled to or integrated with memory circuitry;

[0012] Figure 6 Illustrations based on some embodiments and Figure 1 An exemplary circuit diagram of a voltage supply circuit coupled to or integrated with memory circuitry;

[0013] Figure 7 Illustrations based on some embodiments and Figure 1 An exemplary circuit diagram of a voltage supply circuit coupled to or integrated with memory circuitry;

[0014] Figure 8 Illustrations based on some embodiments and Figure 1 An exemplary circuit diagram of a voltage supply circuit coupled to or integrated with memory circuitry;

[0015] Figure 9 Illustrations based on some embodiments and Figure 1 An exemplary circuit diagram of a voltage supply circuit coupled to or integrated with memory circuitry;

[0016] Figure 10 Illustrations based on some embodiments and Figure 1 An exemplary circuit diagram of a voltage supply circuit coupled to or integrated with memory circuitry;

[0017] Figure 11 Illustrations based on some embodiments and Figure 1 Exemplary circuit diagrams of voltage supply circuits coupled to or integrated with memory circuitry; and

[0018] Figure 12 An exemplary flowchart illustrating a method for providing an operating voltage to a memory circuit according to some embodiments is shown.

[0019] [Symbol Explanation]

[0020] 100: Memory Circuit

[0021] 102: Memory Array

[0022] 103: Memory Unit / Fuse Unit

[0023] 104: Line Decoder

[0024] 106: Column Decoder

[0025] 108: Input / Output (I / O) Circuits

[0026] 110: Logic control circuit

[0027] 202: Fuse Resistor

[0028] 204: Access Transistor

[0029] 300: Voltage supply circuit

[0030] 301: Voltage Detector / Component

[0031] 302: Inverter / Component

[0032] 304: NAND gate / component

[0033] 305, 307, 309, 311, 315: Signals

[0034] 306, 310: Inverters / Components

[0035] 308: Level shifter / component

[0036] 312: NOR gates / components

[0037] 314: Inverter

[0038] 316: Pull-up transistor

[0039] 318: Pull-down transistor

[0040] 405: Inverter

[0041] 410: Pull-up transistor

[0042] 420: Pull-down transistor

[0043] 430: Transistor

[0044] 440: Schmitt trigger

[0045] 500: Voltage supply circuit

[0046] 501: Voltage Detector / Component

[0047] 502, 504, 506, 508: Components

[0048] 510: Inverter / Component

[0049] 512: NOR gate / component

[0050] 514, 516, 518: Inverters / Components

[0051] 517, 519, 521, 523, 525: Signals

[0052] 520: Level shifter / component

[0053] 522, 524, 526, 528: Inverters / Components

[0054] 527, 529: Signals

[0055] 530: First pull-up transistor / component

[0056] 532: Second pull-up transistor / component

[0057] 534: First pull-down transistor / component

[0058] 536: Second pull-down transistor / component

[0059] 600: Voltage supply circuit

[0060] 601: Voltage Detector / Component

[0061] 602, 604, 606, 608, 610: Components

[0062] 612, 614, 616, 618, 620: Components

[0063] 622, 624, 626, 628, 630: Components

[0064] 632, 634, 636: Components

[0065] 700: Voltage Supply Circuit

[0066] 701: Component

[0067] 702, 704, 706, 708, 710: Components

[0068] 712, 714, 716, 718, 720: Components

[0069] 722, 724, 726, 728: Components

[0070] 730: Pull-up transistor / component

[0071] 732: Pull-down transistor / component

[0072] 800: Voltage Supply Circuit

[0073] 801: Voltage Detector / Component

[0074] 802, 804, 806, 808, 810: Components

[0075] 812, 814, 816: Components

[0076] 818: Inverter / Component

[0077] 820: Level shifter / component

[0078] 822, 824, 826, 828: Inverters / Components

[0079] 830: Level shifter / component

[0080] 832, 834, 836, 838: Inverters / Components

[0081] 840, 842, 844: Pull-up transistors / components

[0082] 846, 848, 850: Pull-down transistors / components

[0083] 900: Voltage supply circuit

[0084] 901: Voltage Detector / Component

[0085] 902, 904, 906, 908, 910: Components

[0086] 912, 914, 916, 918, 920: Components

[0087] 922, 924, 926, 928, 930: Components

[0088] 932, 934, 936, 938, 940: Components

[0089] 942, 944, 946, 948, 950: Components

[0090] 1000: Voltage supply circuit

[0091] 1002: Inverter

[0092] 1004: NAND Gate

[0093] 1006, 1008: Inverters

[0094] 1010: Level shifter

[0095] 1012: p-type transistor

[0096] 1014: n-type transistor

[0097] 1016: p-type transistor

[0098] 1018, 1020, 1022, 1024: Inverters

[0099] 1025A, 1025B: Input signals

[0100] 1026: NAND Gate

[0101] 1028: Inverter

[0102] 1100: Voltage supply circuit

[0103] 1101: Voltage Detector

[0104] 1102, 1104, 1106, 1108: Components

[0105] 1110, 1112, 1114, 1116: Components

[0106] 1118, 1120, 1122, 1124: Components

[0107] 1126, 1128, 1130, 1132: Components

[0108] 1134, 1136: Components

[0109] 1139A, 1139B: Input signals

[0110] 1140: NAND gate / inverter

[0111] 1142, 1144, 1146, 1148: Inverters

[0112] 1200: Operating Instructions

[0113] 1210, 1220, 1230, 1240: Operations

[0114] BL: Bitline

[0115] C1~C N :List

[0116] DIS: Control Signal

[0117] HVDD: Mid-range supply voltage / Second mid-range supply voltage

[0118] LVDD: Mid-range supply voltage / First mid-range supply voltage

[0119] MVDD: Mid-range supply voltage / Third mid-range supply voltage

[0120] PD, PS, PS18: Control signals

[0121] Psvqb, psvqb_i: Control signals

[0122] R1~R M :OK

[0123] VDD: First supply voltage

[0124] VDD_OK: Control signal

[0125] VDDQ: Operating voltage

[0126] VQPS: Second supply voltage

[0127] WL: Character Line Detailed Implementation

[0128] The following disclosure provides numerous different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0129] Furthermore, for ease of description, this document uses spatially relative terms (such as "below," "below," "lower," "above," "upper," "top," "bottom," and similar) to describe the relationship between one element or feature illustrated in the figures and another element (or features) or feature (or features). In addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations) and therefore the spatially relative descriptive terms used herein can be interpreted similarly.

[0130] As we move faster and faster toward next-generation technology nodes, system input / output (I / O) requirements typically involve transmitting signals between integrated circuit chips and components with large capacitances, such as connections associated with printed circuit board traces and cables. These connections require greater drive power and voltage than the communication occurring within the integrated circuit chip. I / O devices interface faster, smaller signals from the main chip to these other, higher-capacitance components and typically transmit signals at higher voltages. As a non-limiting example, memory circuits (e.g., fuse memory circuits or other one-time programmable (OTP) memory circuits) often rely on I / O circuits to provide high voltages for the operation of the memory circuits (e.g., programming, erasing, etc.).

[0131] A voltage supply circuit is one of many I / O circuits operatively coupled to a memory circuit and capable of providing a desired operating voltage (e.g., a relatively high operating voltage). Such a voltage supply circuit typically includes a level shifter that shifts the level of the supply voltage from one voltage domain to another. For example, when the memory cells of the memory circuit are configured in programmable mode, the voltage supply circuit typically provides the memory cells with an operating voltage shifted from a first (e.g., lower) voltage domain to a second (e.g., higher) voltage domain. The voltage supply circuit can receive a first supply voltage and a second supply voltage, both of which are logic high but located in the first and second voltage domains respectively, and provides the memory cells with an operating (e.g., programmable) voltage equal to the second supply voltage in the logic high state.

[0132] However, in some situations, the first supply voltage may be incorrectly provided in a logic low state, while the second supply voltage is provided in a logic high state. Therefore, existing voltage supply circuitry may provide an operating voltage equal to the same second supply voltage in a logic high state, causing memory circuitry malfunction. For example, if the first supply voltage is in a logic low state, various circuit elements powered by the first supply voltage (e.g., control circuitry) may fail to function properly. By providing a high operating voltage to the memory cells when these control circuits are malfunctioning, the memory cells may be incorrectly programmed. Therefore, existing voltage supply circuitry for memory circuitry is not entirely satisfactory in certain scenarios.

[0133] This disclosure provides various embodiments of a voltage supply circuit operatively coupled to a memory array, for example, providing an operating voltage to the memory array based on a configured operating mode of the memory array. In some embodiments, the voltage supply circuit may include a voltage sensor for receiving a first supply voltage and being powered by a second supply voltage. When the first supply voltage is detected to be provided in a logic low state and the second supply voltage is provided in a logic high state, the voltage sensor may provide a control signal to a logic gate (e.g., a NOR gate) of the voltage supply circuit to force the output stage of the voltage supply circuit to provide an operating voltage (e.g., ground voltage) equal to the second supply voltage in a logic low state. Therefore, even if the first / second supply voltage has an erroneous logic state, as disclosed herein, the voltage supply circuit can force the operating voltage down to ground voltage, thereby preventing further failure of the coupled memory array.

[0134] Figure 1 A memory circuit 100 according to various embodiments is illustrated. Figure 1In the illustrated embodiment, memory circuitry 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuitry 108, and logic control circuitry 110. Although Figure 1 Not shown, but the components of memory circuit 100 can be operatively coupled to each other and to logic control circuit 110. Although in Figure 1 In the illustrated embodiments, for clarity, each element is depicted as a separate block; however, in some other embodiments, Figure 1 Some or all of the components shown can be integrated together. For example, I / O circuitry 108 can be embedded (or integrated) in memory array 102.

[0135] Memory array 102 is a hardware element for storing data. In one embodiment, memory array 102 is embodied as a semiconductor memory device. Memory array 102 includes a plurality of memory cells (or other storage cells) 103. Memory array 102 includes a plurality of rows R1 to R2, each extending in a first direction (e.g., the X direction). M and each of the multiple columns C1 to C2 extending in the second direction (e.g., the Y direction) N Each row / column may contain one or more conductive structures. In some embodiments, each memory cell 103 is configured at the intersection of the corresponding row and the corresponding column and can operate according to the voltage or current passing through the individual conductive structures of the row and column.

[0136] According to various embodiments of this disclosure, each memory cell 103 can be implemented as a one-time programmable (OTP) memory cell. For example, memory cell 103 can be a fuse cell, comprising at least a series-coupled fuse resistor and an access transistor. However, it should be understood that memory cell 103 can be implemented as any of various other memory configurations, such as a static random access memory (SRAM) cell, a phase-change random access memory (PCRAM) cell, a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, or the like, while remaining within the scope of this disclosure. Reference will be made below to... Figure 2 A detailed description of the memory unit 103 configured as an electric fuse unit.

[0137] Row decoder 104 is a hardware element that receives row addresses of memory array 102 and asserts conductive structures (e.g., word lines) at those row addresses. Column decoder 106 is a hardware element that receives column addresses of memory array 102 and asserts one or more conductive structures (e.g., bit lines, source lines) at those column addresses. I / O circuitry 108 is a hardware element that can access (e.g., read, program) each memory cell 103 asserted via row decoder 104 and column decoder 106. Logic control circuitry 110 is a hardware element that can control coupled elements (e.g., memory array 102, row decoder 104, column decoder 106, I / O circuitry 108).

[0138] Figure 2 A memory cell 103 configured as an electric fuse unit according to some embodiments is illustrated. Figure 1 An exemplary configuration of the fuse unit 103 is provided below. The fuse unit 103 is implemented as a 1T1R configuration, for example, a fuse resistor 202 serially connected to the access transistor 204. However, it should be understood that any other fuse configuration exhibiting fuse characteristics may be used by the fuse unit 103, such as a 2-diodes-1-resistor (2D1R) configuration, a many-transistors-one-resistor (manyT1R) configuration, etc., while remaining within the scope of this disclosure.

[0139] The fuse resistor 202 is formed of one or more metal structures. For example, the fuse resistor 202 may be one of multiple interconnect structures in one of multiple metallization layers disposed above the access transistor 204. The access transistor 204 may be formed above the main surface of the semiconductor substrate, a configuration sometimes referred to as part of a front-end-of-line (FEOL) process. During the FEOL process, multiple metallization layers are typically formed, each of which contains multiple interconnect (e.g., metal) structures; this configuration is sometimes referred to as part of a back-end-of-line (BEOL) process.

[0140] When the fuse resistor 202 (of the fuse unit 103) is a metallic structure, it may exhibit, for example, an initial resistance value (or resistivity) at the time of manufacture. To program the fuse unit 103, an access transistor 204 (if embodied as an n-type transistor) is turned on, and a signal corresponding to a logic high state (e.g., a voltage) is applied to the gate of the access transistor 204 via the word line (WL). Simultaneously or subsequently, a sufficiently high voltage (e.g., a program voltage) is applied via the bit line (BL) to one of the terminals of the fuse resistor 202. When the access transistor 204 is turned on to provide (e.g., programmable) a path from BL through the fuse resistor 202 and the access transistor 204 to the source line (SL), this high voltage signal can burn out a portion of the corresponding metallic structure (fuse resistor 202), thereby changing the fuse resistor 202 from a first state (e.g., short-circuited) to a second state (e.g., open-circuited). Therefore, the fuse unit 103 can irreversibly transition from a first logic state (e.g., logic 0) to a second logic state (e.g., logic 1), which can be read out by applying a relatively low voltage signal to BL and turning on the access transistor 204 to provide (e.g., read) a path. In various embodiments of this disclosure, such a high programmable voltage shifted upward from the first voltage domain to the second voltage domain can be provided by the voltage supply circuitry of the I / O circuitry 108, which will be discussed in further detail below.

[0141] Figure 3 An exemplary circuit diagram of a voltage supply circuit 300 for an I / O circuit 108 according to some embodiments is shown. The voltage supply circuit 300 provides an operating voltage VDDQ for a programmable fuse unit 103. The voltage supply circuit 300 provides an operating voltage VDDQ shifted from a first voltage domain to a second voltage domain. The first voltage domain is within a range between a ground voltage and a first supply voltage VDD; and the second voltage domain is within a range between a ground voltage and a second supply voltage VQPS. The first supply voltage VDD is equal to 0V when provided in a logic low state and is equal to approximately 0.75V when provided in a logic high state; while the second supply voltage VQPS is equal to 0V when provided in a logic low state and is equal to approximately 1.8V when provided in a logic high state.

[0142] In some embodiments, the voltage providing circuit 300 may include a voltage detector (e.g., Figure 4A voltage detector 301 is used to detect whether a first supply voltage VDD has been correctly provided. If the voltage detector identifies that the first supply voltage VDD is provided in a logic low state and the second supply voltage VQPS is provided in a logic high state (e.g., 0V and 1.8V respectively), then the voltage detector 301 can provide a control signal to the logic gate of the voltage supply circuit 300 to forcibly pull the operating voltage VDDQ to 0V. Details of the voltage detector 301 will be discussed below.

[0143] First refer to Figure 3 The voltage supply circuit 300 includes an inverter 302, a NAND gate 304, an inverter 306, a level shifter 308, an inverter 310, a NOR gate 312, an inverter 314, a pull-up transistor 316, a pull-down transistor 318, and a voltage sensor 301. In some embodiments, the inverter 302, NAND gate 304, and inverter 306 can operate in a first voltage domain (e.g., between 0V and 0.75V); and the inverter 310, NOR gate 312, inverter 314, pull-up transistor 316, pull-down transistor 318, and voltage sensor 301 can operate in a second voltage domain (e.g., between 0V and 1.8V).

[0144] Inverter 302 may receive a control signal PD (e.g., via a first control pin) and provide the inverted control signal PD to one of the inputs of NAND gate 304. NAND gate 304 may receive another control signal PS (e.g., via a second control pin) and perform a NAND operation on the inverted control signal PD and the control signal PS to provide signal 305. In some embodiments, when the coupled fuse unit 103 is configured in read mode, both control signals PD and PS are in a logic low state (i.e., PD = 0 and PS = 0); and when the coupled fuse unit 103 is configured in program mode, control signals PD and PS are in a logic low state and a logic high state (i.e., PD = 0 and PS = 1), respectively. The control signals PD and PS, having individual logic states, may be provided in a first voltage domain. For example, when configured in a logic high state, control signals PD / PS are provided at 0.75V; and when configured in a logic low state, control signals PD / PS are provided at 0V.

[0145] Inverter 306 provides signal 307 to level shifter 308 by inverting signal 305, which has undergone logic NAND operation. Level shifter 308 shifts signal 307 (e.g., its voltage is 0V when it is logic low, or its voltage is 0.75V when it is logic high) to provide signal 309 (e.g., its voltage is 0V when it is logic low, or its voltage is 1.8V when it is logic high). For example, when signal 307 is received by level shifter 308 in a logic high state, level shifter 308 can provide signal 309 in a logic high state, where signal 307 and signal 309 are approximately 0.75V and 1.8V, respectively. Inverter 310 provides signal 311 to one input of NOR gate 312 by inverting signal 309. NOR gate 312 can receive another input signal (e.g., control signal VDD_OK) and perform a logic NOR operation on signal 311 and control signal VDD_OK to provide control signal DIS. Inverter 314 can provide signal 315 by inverting control signal DIS. The gate of pull-up transistor 316 can receive signal 315, and the gate of pull-down transistor 318 can also receive signal 315. In addition, the source of pull-up transistor 316 (which may be implemented as a p-type transistor) can be connected to a second supply voltage VQPS, and the source of pull-down transistor 318 (which may be implemented as an n-type transistor) can be connected to ground, wherein the respective drains of pull-up transistor 316 and pull-down transistor 318 are connected to each other at the output node to provide operating voltage VDDQ.

[0146] Next, refer to Figure 4 , Figure 4An exemplary circuit diagram of a voltage detector 301 according to some embodiments is shown. The voltage detector 301 includes an inverter 405 formed by a pull-up transistor 410, a pull-down transistor 420, a transistor 430, and a Schmitt trigger 440. The pull-up transistor 410 and the pull-down transistor 420 may be implemented as p-type and n-type transistors, respectively. The source terminal of the pull-up transistor 410 may be connected to a second supply voltage VQPS, and the source terminal of the pull-down transistor 420 may be connected to ground. The respective gate terminals of the pull-up transistor 410 and the pull-down transistor 420 are connected to each other to operably serve as inputs to the inverter 405, and the respective drain terminals of the pull-up transistor 410 and the pull-down transistor 420 are connected to each other to operably serve as outputs to the inverter 405. The input terminal of the inverter 405 is used to receive a first supply voltage VDD and is coupled to ground via a transistor 430 gated by a control signal DIS. The output of inverter 405 is connected to the input of Schmitt trigger 440, which is operable as a power noise filter. Schmitt trigger 440 provides a control signal VDD_OK by filtering a logic-inverted first supply voltage VDD. For example, the control signal VDD_OK may be in a logic-high state when the first supply voltage VDD and the second supply voltage VQPS are in logic-low and logic-high states, respectively.

[0147] In operation, the voltage supply circuit 300 provides an operating voltage VDDQ (e.g., approximately 1.8V) equal to the second supply voltage VQPS in a logic high state when the coupled memory cell 103 is being programmed; and provides an operating voltage VDDQ (e.g., approximately 0V) equal to the second supply voltage VQPS in a logic low state when the coupled memory cell 103 is being read. Furthermore, in read mode, both the first supply voltage VDD and the second supply voltage VQPS are in a logic high state (i.e., VDD = 1 and VQPS = 1), and both the control signal PD and the control signal PS are in a logic low state (i.e., PD = 0 and PS = 0). Therefore, the signal 307 input to the level shifter 308 is in a logic low state, and the signal 309 output from the level shifter 308 is also in a logic low state. Next, NOR gate 312 outputs a control signal DIS in a logic low state, causing pull-up transistors 316 and 318, which are operably used as inverters, to output an operating voltage VDDQ equal to approximately 0V. In program mode, control signals PD and PS are in logic low and logic high states, respectively (i.e., PD = 0 and PS = 1). Therefore, signal 307 input to level shifter 308 is in a logic high state, and signal 309 output from level shifter 308 is also in a logic high state. Next, NOR gate 312 outputs a control signal DIS in a logic high state, causing pull-up transistors 316 and 318, which are operably used as inverters, to output an operating voltage VDDQ equal to approximately 1.8V.

[0148] In some scenarios, the first supply voltage VDD and the second supply voltage VQPS may (e.g., incorrectly) be in logic low and logic high states respectively (i.e., VDD = 0 and VQPS = 1), while the control signals PD and PS can be in any arbitrary logic combination. When VDD = 0, the inverter 405 of the voltage detector 301 can output a logic high control signal VDD_OK by inverting the first supply voltage VDD. Therefore, the NOR gate 312 can then output a logic low control signal DIS, regardless of the logic combination of the control signals PD and PS. Thus, the pull-up transistor 316 and pull-down transistor 318, which are operably inverters, can output an operating voltage VDDQ equal to approximately 0V.

[0149] Table 1 below summarizes the various combinations of the logic states of the first supply voltage VDD, the second supply voltage VQPS, the operating voltage VDDQ, the control signal VDD_OK, and the control signal DIS. For example, when the operating voltage VDDQ is in a logic low state, the operating voltage VDDQ is equal to the second supply voltage VQPS in a logic high state (e.g., approximately 1.8V); and when the operating voltage VDDQ is in a logic low state, the operating voltage VDDQ is equal to the second supply voltage VQPS in a logic low state (e.g., approximately 0V).

[0150] VDD VQPS VDDQ VDD_OK DIS 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 1

[0151] Table 1.

[0152] Figure 5 An exemplary circuit diagram of a voltage supply circuit 500 for an I / O circuit 108 according to some embodiments is shown. The voltage supply circuit 500 provides an operating voltage VDDQ for a programmable fuse unit 103. Similar to voltage supply circuit 300 ( Figure 3 The voltage supply circuit 500 can provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0V to about 0.75V) to a second voltage domain (e.g., from 0V to about 1.8V). The difference is that the voltage supply circuit 500 can arrange its components (e.g., transistors) in a stacked structure to reduce the voltage drop between any terminals of each transistor. Therefore, the following discussion of the voltage supply circuit 500 will focus on its differences.

[0153] With voltage supply circuit 300 ( Figure 3 In contrast, the voltage supply circuit 500 also includes elements 501, 502, 504, 506, 508, 510, and 512, which are similar to elements 301, 302, 304, 306, 308, 310, and 312, respectively, except for the following differences. For example, element 508 (e.g., a level shifter) is used to shift a first voltage domain in the range of 0V to a first supply voltage VDD (e.g., about 0.75V) to another (third) voltage domain in the range of 0V to a mid-range supply voltage MVDD (e.g., about 0.9V). In such embodiments, the mid-range supply voltage MVDD may be configured as 1 / 2 × VQPS. In another example, elements 510 (e.g., an inverter), 512 (e.g., a NOR gate), and 501 (e.g., a voltage sensor) operate at the mid-range supply voltage MVDD. In other words, the inverter 510, NOR gate 512, and voltage detector 501 can operate in a third voltage domain from 0V to approximately 0.9V.

[0154] For example, it may include Figure 4The voltage detector 501 of the illustrated component can couple its inverter between the mid-range supply voltage MVDD and the ground voltage. Therefore, the voltage detector 501 can receive a first supply voltage VDD in a first voltage domain (from 0V to about 0.75V) and output a control signal VDD_OK in a third voltage domain (from 0V to about 0.9V). For example, the voltage detector 501 can output a logic high control signal VDD_OK (e.g., about 0.9V) when it detects that the first supply voltage VDD is in a logic low state and the mid-range supply voltage MVDD is in a logic high state.

[0155] The voltage supply circuit 500 may further include inverters 514, 516, 518, level shifter 520, 522, 524, 526, 528, a first pull-up transistor 530, a second pull-up transistor 532, a first pull-down transistor 534, and a second pull-down transistor 536. In some embodiments, inverters 514, 516, and 518 may operate in a third voltage domain. Inverter 514 can provide a control signal psvqb by inverting the control signal DIS provided by NOR gate 512. Inverter 516 can provide signal 517 by inverting the control signal psvqb. Inverter 518 can provide signal 519 by inverting signal 517. As described above regarding voltage detector 301 ( Figures 3 to 4 As discussed above, the NOR gate 512 can receive the control signal VDD_OK, which is in a logic high state, when it detects that the first supply voltage VDD is in a logic low state and the intermediate supply voltage MVDD is in a logic high state.

[0156] Level shifter 520 can shift a third voltage domain in the range of 0V to the mid-range supply voltage MVDD (approximately 0.9V) to another (fourth) voltage domain in the range of the mid-range supply voltage MVDD (approximately 0.9V) to the second supply voltage VQPS (approximately 1.8V). For example, level shifter 520 can shift a control signal psvqb (e.g., between 0V and approximately 0.9V) and provide signal 521 (e.g., between approximately 0.9V and approximately 1.8V). Inverter 522 can provide signal 523 by inverting signal 521. Inverter 524 can provide signal 525 by inverting signal 523. Inverter 526 can provide signal 527 by inverting signal 525. Inverter 528 can provide signal 529 by inverting signal 527. Therefore, when the control signal psvqb is in a logic high state (e.g., about 0.9V), the signal 529 can be in a logic high state (e.g., about 1.8V).

[0157] The gate of the first pull-up transistor 530 can receive signal 529, the gate of the second pull-up transistor 532 can receive the mid-range supply voltage MVDD, the gate of the first pull-down transistor 534 can receive the mid-range supply voltage MVDD, and the gate of the second pull-down transistor 536 can receive signal 519. Furthermore, the source of the first pull-up transistor 530 (which may be implemented as a p-type transistor) can be connected to the second supply voltage VQPS, and its drain is connected to the source of the second pull-up transistor 532 (which may be implemented as a p-type transistor). The source of the second pull-down transistor 536 (which may be implemented as an n-type transistor) can be connected to ground, and its drain is connected to the source of the first pull-down transistor 534 (which may be implemented as an n-type transistor). The respective drains of the second pull-up transistor 532 and the first pull-down transistor 534 are connected to each other at the output node to provide the operating voltage VDDQ.

[0158] Figure 6 An exemplary circuit diagram of a voltage supply circuit 600 for an I / O circuit 108 according to some embodiments is shown. The voltage supply circuit 600 provides an operating voltage VDDQ for a programmable fuse unit 103. The voltage supply circuit 600 is substantially similar to the voltage supply circuit 500. Figure 5 Both can provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0V to about 0.75V) to a second voltage domain (e.g., from 0V to about 1.8V) via a stacked structure. The difference lies in that the voltage sensor (e.g., voltage sensor 601) of the voltage supply circuit 600 can be powered by another intermediate supply voltage HVDD. In such embodiments, the intermediate supply voltage HVDD can be configured as 2 / 3 × VQPS, while the intermediate supply voltage MVDD remains configured as 1 / 2 × VQPS. For the sake of brevity, the following discussion of the voltage supply circuit 600 will focus on its differences.

[0159] With voltage supply circuit 500 ( Figure 5 In comparison, the voltage supply circuit 600 also includes components 601, 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632, 634, and 636, which are similar to components 501, 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, and 536, respectively. The difference is that it may include... Figure 4The voltage detector 601 of the illustrated component can couple its inverter between the mid-range supply voltage HVDD (e.g., about 1.2V) and ground. Therefore, the voltage detector 601 can receive a first supply voltage VDD in a first voltage domain (from 0V to about 0.75V) and output a control signal VDD_OK in another voltage domain (from 0V to about 1.2V). For example, the voltage detector 601 can output a logic high control signal VDD_OK (e.g., about 1.2V) when it detects that the first supply voltage VDD is logic low and the mid-range supply voltage HVDD is logic high.

[0160] Figure 7 An exemplary circuit diagram of a voltage supply circuit 700 for an I / O circuit 108 according to some embodiments is shown. The voltage supply circuit 700 provides an operating voltage VDDQ for a programmable fuse unit 103. The voltage supply circuit 700 is substantially similar to the voltage supply circuit 600. Figure 6 Both can provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0V to about 0.75V) to a second voltage domain (e.g., from 0V to about 1.8V) via a stacked structure. The difference lies in that the voltage supply circuit 700 may have fewer pull-up transistors and fewer pull-down transistors at its output stage. Therefore, the following discussion of the voltage supply circuit 700 will focus on its differences.

[0161] With voltage supply circuit 600 ( Figure 6 In comparison, the voltage supply circuit 700 also includes components 701, 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, 724, 726, 728, 730, and 732, which are similar to components 601, 602, 604, 606, 608, 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, and 636, respectively. It should be noted that the voltage supply circuit 700 includes a pull-up transistor 730 and a pull-down transistor 732 at its output stage, these transistors being interconnected through their drain terminals to provide the operating voltage VDDQ.

[0162] Figure 8 An exemplary circuit diagram of a voltage supply circuit 800 for an I / O circuit 108 according to some embodiments is shown. The voltage supply circuit 800 provides an operating voltage VDDQ for a programmable fuse unit 103. The voltage supply circuit 800 is substantially similar to the voltage supply circuit 500. Figure 5Both can provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0V to about 0.75V) to a second voltage domain (e.g., from 0V to about 1.8V) via a stacked structure. The difference lies in that the components of the voltage supply circuit 800 can be powered by separate intermediate-range supply voltages LVDD and HVDD. Generally, the second supply voltage VQPS is higher than the intermediate-range supply voltage HVDD, which is higher than the intermediate-range supply voltage LVDD, which is higher than the ground voltage. For example, the intermediate-range supply voltage LVDD can be configured as 1 / 3 × VQPS, and the intermediate-range supply voltage HVDD can be configured as 2 / 3 × VQPS. For simplicity, the following discussion of the voltage supply circuit 800 will focus on its differences.

[0163] With voltage supply circuit 500 ( Figure 5 In contrast, the voltage supply circuit 800 also includes components 801, 802, 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, 824, 826, and 828, which, except for the following differences, are similar to components 501, 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, and 528, respectively. For example, it may include... Figure 4 The voltage detector 801 of the illustrated component can couple its inverter between a first mid-range supply voltage LVDD (e.g., about 0.6V) and ground. Therefore, the voltage detector 801 can receive the first supply voltage VDD in a first voltage domain (from 0V to about 0.75V) and output a control signal VDD_OK in another (third) voltage domain (from 0V to about 0.6V). The voltage detector 801 can output a logic high control signal VDD_OK (e.g., about 0.6V) when it detects that the first supply voltage VDD is logic low and the first mid-range supply voltage LVDD is logic high. In another example, a level shifter 820 is used to shift the control signal psvqb from a third voltage domain (e.g., from 0V to about 0.6V) to yet another (fourth) voltage domain. In some embodiments, the fourth voltage domain may range from the first mid-range supply voltage LVDD (e.g., about 0.6V) to a second mid-range supply voltage HVDD of about 1.2V. Therefore, inverters 822, 824, 826, and 828, which are coupled to the output of level shifter 820, can operate in the fourth voltage domain.

[0164] Additionally, the voltage supply circuit 800 includes a level shifter 830, inverters 832, 834, 836, and 838, pull-up transistors 840, 842, and 844, and pull-down transistors 846, 848, and 850. The level shifter 830 can receive a control signal psvqb_i in a fourth voltage domain (approximately 0.6V to 1.2V) from the inverter 822 and shift it to another (fifth) voltage domain. In some embodiments, the fifth voltage domain may range from a second mid-range supply voltage HVDD (e.g., approximately 1.2V) to a second supply voltage VQPS (e.g., approximately 1.8V). Therefore, inverters 832, 834, 836, and 838 coupled to the output of the level shifter 830 can operate in the fifth voltage domain.

[0165] Pull-up transistors 840, 842, 844, 846, 848, and 850 can still be coupled between the second supply voltage VQPS and the ground voltage, wherein the drain terminals of pull-up transistors 844 and 846 are connected to each other to provide the operating voltage VDDQ. Specifically, the gate of pull-up transistor 840 can be used to receive the signal output from inverter 838 (from about 1.2V to about 1.8V in the fifth voltage domain); the gate of pull-up transistor 842 can be used to receive the second intermediate supply voltage HVDD (from about 0.6V to about 1.2V in the fourth voltage domain); the gates of pull-up transistor 844 and pull-down transistor 846 can be used to receive the signal output from inverter 828 (from about 0.6V to about 1.2V in the fourth voltage domain); the gate of pull-down transistor 848 can be used to receive the first intermediate supply voltage LVDD (from 0V to about 0.6V in the third voltage domain); and the gate of pull-down transistor 850 can be used to receive the signal output from inverter 818 (from 0V to about 0.6V in the third voltage domain).

[0166] Figure 9 An exemplary circuit diagram of a voltage supply circuit 900 for an I / O circuit 108 according to some embodiments is shown. The voltage supply circuit 900 provides an operating voltage VDDQ for a programmable fuse unit 103. The voltage supply circuit 900 is substantially similar to the voltage supply circuit 800. Figure 8Both can provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0V to about 0.75V) to a second voltage domain (e.g., from 0V to about 1.8V) via a stacked structure. The difference lies in that the voltage sensor (e.g., voltage sensor 901) of the voltage supply circuit 900 can be powered by a third intermediate supply voltage MVDD. Generally, the second supply voltage VQPS is higher than the intermediate supply voltage HVDD, which is higher than the intermediate supply voltage MVDD, which is higher than the intermediate supply voltage LVDD, which is higher than the ground voltage. For example, the intermediate supply voltage LVDD can be configured as 1 / 3 × VQPS, the intermediate supply voltage MVDD can be configured as 1 / 2 × VQPS, and the intermediate supply voltage HVDD can be configured as 2 / 3 × VQPS. For simplicity, the following discussion of the voltage supply circuit 900 will focus on its differences.

[0167] With voltage supply circuit 800 ( Figure 8 In comparison, the voltage supply circuit 900 also includes components 901, 902, 904, 906, 908, 910, 912, 914, 916, 918, 920, 922, 924, 926, 928, 930, 932, 934, 936, 938, 940, 942, 944, 946, 948, and 950, which are similar to components 801, 802, 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, 824, 826, 828, 830, 832, 834, 836, 838, 840, 842, 844, 846, 848, and 850, the difference being that it may include... Figure 4 The voltage detector 901 of the illustrated component may couple its inverter between the mid-range supply voltage MVDD (e.g., about 0.9V) and ground. Therefore, the voltage detector 901 may receive a first supply voltage VDD in a first voltage domain (from 0V to about 0.75V) and output a control signal VDD_OK in another voltage domain (from 0V to about 0.9V). For example, when the voltage detector 901 detects that the first supply voltage VDD is in a logic low state and the mid-range supply voltage MVDD is in a logic high state, it outputs a control signal VDD_OK (e.g., about 0.9V) in a logic high state.

[0168] Figure 10 An exemplary circuit diagram of a voltage supply circuit 1000 for I / O circuit 108 according to some embodiments is shown. The voltage supply circuit 1000 provides an operating voltage VDDQ for the programmable fuse unit 103. Similar to voltage supply circuit 300 ( Figure 3The voltage supply circuit 1000 can provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0V to about 0.75V) to a second voltage domain (e.g., from 0V to about 1.8V). The difference is that the voltage supply circuit 1000 can provide another control signal PS18 via another pin. Therefore, the following discussion of the voltage supply circuit 1000 will focus on its differences.

[0169] As shown in the figure, the voltage supply circuit 1000 includes inverter 1002, NAND gate 1004, inverter 1006, inverter 1008, level shifter 1010, p-type transistor 1016, p-type transistor 1012, n-type transistor 1014, inverter 1018, inverter 1020, inverter 1022, inverter 1024, NAND gate 1026, and inverter 1028. In some embodiments, inverter 1002, NAND gate 1004, inverter 1006, and inverter 1008 can operate in a first voltage domain, and p-type transistor 1012, n-type transistor 1014, p-type transistor 1016, inverter 1018, inverter 1020, inverter 1022, inverter 1024, NAND gate 1026, and inverter 1028 can operate in a second voltage domain, wherein level shifter 1010 shifts the first voltage domain to the second voltage domain.

[0170] During operation (when the coupled memory cell 103 is configured in program mode), control signals PD, PS, and PS18 are provided in logic low, logic high, and logic high states, respectively (i.e., PD = 0, PS = 1, PS18 = 1). Therefore, input signals 1025A and 1025B received by NAND gate 1026 are both provided in a logic high state, causing inverter 1028 to output an operating voltage VDDQ equal to the second supply voltage VQPS (e.g., approximately 1.8V) in the logic high state. For example, when PD = 0 and PS = 1, NAND gate 1004 outputs a signal in a logic high state, causing level shifter 1010 to receive an input signal in a logic low state (e.g., 0V in the first voltage domain) and provide an output signal also in a logic low state (e.g., 0V in the second voltage domain). An inverter formed by p-type transistor 1012 and n-type transistor 1014 can output the input signal 1025B in a logic high state. On the other hand, when PS18 = 1, the inverter chain consisting of inverters 1018, 1020, 1022, and 1024 can output an input signal 1025A in a logic high state. After receiving two input signals in a logic high state, NAND gate 1026 can output a signal in a logic low state, which is then inverted to a logic high state by inverter 1028.

[0171] In certain scenarios, when the coupled memory cell 103 is configured in program mode but PS18 = 1 and PS = 0, the voltage supply circuit 1000 can output an operating voltage VDDQ equal to the second supply voltage VQPS (e.g., at 0V) which is in a logic low state. This scenario may occur when the first supply voltage VDD is not properly provided. For example, when PS = 0, the input signal 1025B received by the NAND gate 1026 becomes logic low, causing the NAND gate 1026 to output a signal with a logic high state. Therefore, the inverter 1028 provides an operating voltage VDDQ (e.g., at 0V) in a logic low state.

[0172] Figure 11 An exemplary circuit diagram of a voltage supply circuit 1100 for an I / O circuit 108 according to some embodiments is shown. The voltage supply circuit 1100 provides an operating voltage VDDQ for a programmable fuse unit 103. Similar to voltage supply circuit 500 ( Figure 5 The voltage supply circuit 1100 can provide an operating voltage VDDQ shifted from a first voltage domain (e.g., from 0V to about 0.75V) to a second voltage domain (e.g., from 0V to about 1.8V). The difference is that the voltage supply circuit 1100 can receive another control signal PS18 via another pin. Therefore, the following discussion of the voltage supply circuit 1100 will focus on its differences.

[0173] Similar to voltage supply circuit 500, voltage supply circuit 1100 also includes components 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 1122, 1124, 1126, 1128, 1130, 1132, 1134, and 1136, which are similar to components 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, and 536, respectively. Additionally, voltage supply circuit 1100 includes NAND gate 1140 and inverters 1142, 1144, 1146, and 1148. NAND gate 1140 is used to receive input signals 1139A and 1139B via an inverter chain consisting of inverters 1142, 1144, 1146, and 1148 and a voltage detector 1101, respectively, and provides control signal psvqb by performing logic NAND operations on input signals 1139A and 1139B. For example, input signal 1139B can be the same as control signal DIS, and control signal DIS is only in a logic high state when both the first supply voltage VDD and the second supply voltage VQPS (or the power supply mid-range supply voltage MVDD) are in a high logic state; and input signal 1139A can have the same logic state as the received control signal PS18.

[0174] Figure 12 A flowchart illustrating an operation method 1200 for providing an operating voltage to a memory circuit according to some embodiments is shown. The operation of operation method 1200 can be performed by the elements described above (e.g., Figures 3 to 11 The operation method 1200 is performed accordingly, and therefore, some of the reference numerals used above may be reused in the following discussion of the operation method 1200. Furthermore, it should be understood that the operation method 1200 has been simplified, and therefore, it can be... Figure 12 Additional operations are provided before, during, and after operation method 1200, and this article only briefly describes some of the other operations.

[0175] Operation method 1200 begins with operation 1210. In operation 1210, a first supply voltage that transitions in a first voltage domain and a second supply voltage that transitions in a second voltage domain are received, wherein the first voltage domain is different from the second voltage domain. Using voltage supply circuit 300 as a non-limiting example, voltage supply circuit 300 can receive a first supply voltage (e.g., a first supply voltage VDD) and a second supply voltage (e.g., a second supply voltage VQPS) having separate logic states. The first supply voltage can transition in a first voltage domain (e.g., from 0V to a first supply voltage VDD that can be set to about 0.75V), and the second supply voltage can transition in a second voltage domain different from the first voltage domain (e.g., from 0V to a second supply voltage VQPS that can be set to about 1.8V). For example, when provided in a logic high state, voltage supply circuit 300 can receive a first supply voltage equal to 0.75V; and when provided in a logic low state, voltage supply circuit 300 can receive a first supply voltage equal to 0V. Similarly, when provided in a logic high state, the voltage supply circuit 300 can receive a second supply voltage equal to 1.8V; and when provided in a logic low state, the voltage supply circuit 300 can receive a second supply voltage equal to 0V.

[0176] Operation method 1200 continues to operation 1220. In operation 1220, after identifying a memory circuit configured in a first operation mode, an operating voltage equal to a second supply voltage having a first logic state is provided. Continuing the above example, when the coupled memory circuit (e.g., memory cell 103) is configured in read mode, the voltage supply circuit 300 can provide an operating voltage VDDQ (e.g., 0V) equal to the second supply voltage in a logic low state. In some embodiments, the voltage supply circuit 300 can determine that the memory circuit is in read mode by identifying that both control signals PD and PS are configured in a logic low state and both the first supply voltage VDD and the second supply voltage VQPS are provided in a logic high state.

[0177] Operation method 1200 continues to operation 1230. In operation 1230, after identifying a memory circuit configured in a second operation mode, an operating voltage equal to a second supply voltage having a second logic state is provided. Continuing the above example, when the coupled memory circuit (e.g., memory cell 103) is configured in program mode, the voltage supply circuit 300 can provide an operating voltage VDDQ equal to the second supply voltage in a logic high state, for example, 1.8V. In some embodiments, the voltage supply circuit 300 can determine that the memory circuit is in program mode by identifying that the control signal PD is configured in a logic low state, the control signal PS is configured in a logic high state, and both the first supply voltage VDD and the second supply voltage VQPS are provided in a logic high state.

[0178] Operation method 1200 continues to operation 1240. In operation 1240, after identifying a memory circuit configured in a third operation mode, an operating voltage equal to a second supply voltage having a first logic state is provided. Continuing the above example, when the coupled memory circuit (e.g., memory cell 103) is configured in a non-program mode or a non-read mode (sometimes referred to as a valid mode or transition mode), the voltage supply circuit 300 can provide an operating voltage VDDQ equal to the second supply voltage in a logic low state, for example, 0V. For example, such a transition mode may occur during the switching between read mode and program mode, wherein the second supply voltage VQPS has reached a logic high state, but the first supply voltage VDD remains in a logic low state. In some embodiments, the voltage supply circuit 300 can determine that the memory circuit is in a valid state by identifying that control signals PD and PS are not configured, the first supply voltage VDD is provided in a logic low state, and the second supply voltage VQPS is provided in a logic high state.

[0179] In one embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a memory array and a voltage supply circuit. The memory array includes a plurality of memory cells. The voltage supply circuit provides an operating voltage to one or more of the plurality of memory cells, the operating voltage being shifted from a first voltage domain to a second voltage domain. The voltage supply circuit includes a voltage detector, which receives a first supply voltage in the first voltage domain, is powered by a second supply voltage in the second voltage domain, and provides a first control signal. The first control signal determines whether the operating voltage is equal to the second supply voltage in a first logic state or equal to the second supply voltage in a second logic state.

[0180] In some embodiments of the memory circuit, the voltage supply circuit further includes a NOR gate, a first inverter, and a second inverter. The NOR gate receives a first control signal and provides a second control signal. The first inverter receives the second control signal and provides a third control signal. The second inverter receives the third control signal and provides an operating voltage. Each of the NOR gate, the first inverter, and the second inverter is powered by a second supply voltage.

[0181] In some embodiments of the memory circuit, the voltage detector includes a third inverter powered by a second supply voltage, the third inverter being used to receive the first supply voltage and provide a first control signal.

[0182] In some embodiments of the memory circuit, when the first supply voltage and the second supply voltage are provided in the first logic state and the second logic state, respectively, the first control signal is provided in the second logic state, such that the voltage supply circuit provides an operating voltage equal to the second supply voltage in the first logic state.

[0183] In some embodiments of the memory circuit, the voltage detector further includes an n-type transistor coupled between the input of the third inverter and ground voltage. The gate of the n-type transistor is connected to a second control signal, which is determined based on a logic NOR operation performed on the first control signal.

[0184] In some embodiments of the memory circuit, when both the first supply voltage and the second supply voltage are provided in the second logic state, the second control signal remains in the second logic state.

[0185] In some embodiments of the memory circuit, the voltage detector further includes a Schmitt trigger coupled to the output of a third inverter.

[0186] In some embodiments of memory circuitry, multiple memory cells each include a one-time programmable memory cell.

[0187] In another embodiment of this disclosure, a voltage supply circuit is disclosed. The voltage supply circuit includes a voltage detector, a logic gate, and a first n-type transistor. The voltage detector is powered by a first supply voltage in a first voltage domain and is used to receive a second supply voltage in a second voltage domain and provide a first control signal, wherein the first supply voltage in a logic high state is higher than the second supply voltage in a logic high state. The logic gate is used to provide a second control signal based on the first control signal, wherein the first control signal and the second control signal are in the first voltage domain. The first n-type transistor has a gate terminal for receiving the second control signal via a first inverter, a drain terminal coupled to an output node for providing an operating voltage to a memory circuit, and a source terminal coupled to ground. When the first supply voltage is in a logic high state and the second supply voltage is in a logic low state, the second control signal is output in a logic high state through the logic gate.

[0188] In some embodiments of the voltage supply circuit, the logic gates include NOR logic gates.

[0189] In some embodiments of the voltage supply circuit, the voltage supply circuit further includes a first p-type transistor. The first p-type transistor has a gate terminal for receiving a second control signal via a first inverter, a drain terminal connected to an output node, and a source terminal connected to a first supply voltage.

[0190] In some embodiments of the voltage supply circuit, the voltage supply circuit further includes a level shifter. The level shifter is used to shift the signal from the second voltage domain to the first voltage domain.

[0191] In some embodiments of the voltage supply circuit, depending on the logic state of the second control signal, the operating voltage supplied at the output node is equal to the first supply voltage in the logic high state or the first supply voltage in the logic low state.

[0192] In some embodiments of the voltage supply circuit, the voltage supply circuit further includes a second n-type transistor, a first p-type transistor, and a second p-type transistor. The second n-type transistor has a gate terminal for receiving a first supply voltage, a drain terminal connected to an output node, and a source terminal connected to the drain terminal of the first n-type transistor. The first p-type transistor has a gate terminal for receiving the first supply voltage, a drain terminal connected to an output node, and a source terminal coupled to a third supply voltage in a third voltage domain. The third supply voltage is higher than the first supply voltage. The second p-type transistor has a gate terminal for receiving a third control signal, a drain terminal connected to the source terminal of the first p-type transistor, and a source terminal connected to the third supply voltage.

[0193] In some embodiments of the voltage supply circuit, depending on the logic state of the second control signal and the logic state of the third control signal, the operating voltage provided at the output node is equal to the third supply voltage in the logic high state or the third supply voltage in the logic low state, and the third control signal is in the third voltage domain.

[0194] In some embodiments of the voltage supply circuit, the voltage supply circuit further includes a first quasi-shifter and a second quasi-shifter. The first quasi-shifter is used to shift the signal from a second voltage domain to a first voltage domain. The second quasi-shifter is used to shift the signal from the first voltage domain to a third voltage domain.

[0195] In some embodiments of the voltage supply circuit, the voltage detector includes an inverter powered by a first supply voltage. The inverter has an input for receiving a second supply voltage and an output for providing a first control signal.

[0196] In some embodiments of the voltage supply circuit, the voltage detector further includes a second n-type transistor coupled between the input of the inverter and the ground voltage. The gate of the second n-type transistor is used to receive a second control signal.

[0197] In another embodiment of this disclosure, an operational method for providing an operating voltage to a memory circuit is disclosed, comprising the following steps: receiving a first supply voltage transitioning in a first voltage domain and a second supply voltage transitioning in a second voltage domain, wherein the first voltage domain is different from the second voltage domain; after identifying a memory circuit configured in a first operating mode, providing an operating voltage equal to the second supply voltage having a first logic state; after identifying a memory circuit configured in a second operating mode, providing an operating voltage equal to the second supply voltage having a second logic state; and after identifying a memory circuit configured in a third operating mode, providing an operating voltage equal to the second supply voltage having a first logic state. In the first operating mode, the first supply voltage and the second supply voltage each have a second logic state; in the second operating mode, the first supply voltage and the second supply voltage each have a second logic state; and in the third operating mode, the first supply voltage and the second supply voltage each have a first logic state and a second logic state, respectively.

[0198] In some embodiments of the operating method, the second supply voltage in the second logic state is higher than the first supply voltage in the second logic state.

[0199] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term “about” may indicate, for example, the value of a given quantity that varies within 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0200] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can at any time design or modify other programs and structures based on the content of this disclosure to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A memory circuit, comprising: A memory array including a plurality of memory cells; and A voltage providing circuit to provide an operating voltage for one or more of the plurality of memory cells, the operating voltage shifted from a first voltage domain to a second voltage domain; wherein the voltage providing circuit includes a voltage detector, and wherein the voltage detector is to receive a first supply voltage in the first voltage domain, powered by a second supply voltage in the second voltage domain, and provide a first control signal to determine whether the operating voltage is equal to the second supply voltage in a first logic state or equal to the second supply voltage in a second logic state. wherein the voltage providing circuit further includes:

2. The memory circuit of claim 1, wherein, a NOR gate to receive the first control signal and provide a second control signal; a first inverter to receive the second control signal and provide a third control signal; and a second inverter to receive the third control signal and provide the operating voltage; wherein each of the NOR gate, the first inverter, and the second inverter is powered by the second supply voltage. wherein the voltage detector includes a third inverter powered by the second supply voltage to receive the first supply voltage and provide the first control signal.

3. The memory circuit of claim 1, wherein, wherein when the first supply voltage and the second supply voltage are provided in the first logic state and the second logic state, respectively, the first control signal is provided in the second logic state, such that the voltage providing circuit provides the operating voltage equal to the second supply voltage in the first logic state.

4. The memory circuit of claim 3, wherein, wherein the voltage detector further includes an n-type transistor coupled between an input of the third inverter and a ground voltage, wherein a gate terminal of the n-type transistor is connected to a second control signal determined based on a logical NOR operation on the first control signal.

5. The memory circuit of claim 3, wherein, wherein when the first supply voltage and the second supply voltage are both provided in the second logic state, the second control signal remains in the second logic state.

6. The memory circuit of claim 5, wherein, wherein the voltage detector further includes a Schmitt trigger coupled to an output of the third inverter.

7. The memory circuit of claim 5, wherein, wherein the plurality of memory cells each include a one-time programmable memory cell.

8. The memory circuit of claim 1, wherein, A voltage detector powered by a first supply voltage in a first voltage domain, the voltage detector to receive a second supply voltage in a second voltage domain and provide a first control signal, wherein the first supply voltage in a logic high state is higher than the second supply voltage in the logic high state; 9. A voltage supply circuit, characterized by a logic gate to provide a second control signal based on the first control signal, wherein the first control signal and the second control signal are in the first voltage domain; and a first n-type transistor having a gate terminal to receive the second control signal via a first inverter, a drain terminal coupled to an output node for providing an operating voltage to a memory circuit, and a source terminal coupled to a ground voltage; ​ ​ wherein the second control signal is output by the logic gate in the logic high state when the first supply voltage has the logic high state and the second supply voltage has a logic low state.

10. An operating method for providing an operating voltage to a memory circuit, the operating method comprising: comprising the steps of: receiving a first supply voltage transitioning in a first voltage domain and a second supply voltage transitioning in a second voltage domain, wherein the first voltage domain is different than the second voltage domain; providing an operating voltage equal to the second supply voltage having a first logic state upon identifying a memory circuit configured in a first operating mode; providing the operating voltage equal to the second supply voltage having a second logic state upon identifying the memory circuit configured in a second operating mode; and providing the operating voltage equal to the second supply voltage having the first logic state upon identifying the memory circuit configured in a third operating mode; wherein in the first operating mode, the first supply voltage and the second supply voltage each have the second logic state, wherein in the second operating mode, the first supply voltage and the second supply voltage each have the second logic state, and wherein in the third operating mode, the first supply voltage and the second supply voltage have the first logic state and the second logic state, respectively.

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