Operation method of memory and operation device of memory

Abstract

The invention discloses an operation method of a memory and an operation device of the memory. The method is applied to a control unit of a field-programmable gate array, the field-programmable gate array further comprises a plurality of cache units, each data cache unit is used for storing different operation types of data on a memory, and the method comprises the following steps: responding to an operation instruction for operating the memory; acquiring a data cache amount and a data amount threshold value of each cache unit in the plurality of cache units; according to the data cache amount of each cache unit and the data volume threshold value of each cache unit, determining a target operation type which is allowed to operate the memory at the current moment, the target operation type comprising a read operation or a write operation; and executing the operation of the target operation type on the memory according to the target data volume threshold value, wherein the target data volume threshold value is the data volume threshold value of the cache unit of the target operation type. According to the scheme provided by the embodiment of the invention, the effective bandwidth of the memory can be improved, and the risk of data packet loss is reduced.

Description

Technical Field

[0001] This application belongs to the field of field-programmable gate array (FPGA) control technology, and particularly relates to a memory operation method and a memory operation device. Background Technology

[0002] DDR (Double Data Rate) memory is a common storage solution widely used in various computer systems and embedded devices. To effectively utilize the high-speed read and write characteristics of DDR memory, it is usually necessary to implement DDR memory read and write operations through FPGA (Field Programmable Gate Array).

[0003] However, in related technologies, address lines and data lines are typically used together to enable FPGAs to read and write data in DDR memory. In scenarios where high DDR memory read / write speeds are required, frequent read / write operations on DDR memory can reduce the effective bandwidth of the DDR memory and even cause data loss. Summary of the Invention

[0004] This application provides a memory operation method and a memory operation device, which can improve the effective bandwidth of the memory and reduce the risk of data packet loss.

[0005] In a first aspect, embodiments of this application provide a memory operation method applied to a control unit of a field-programmable gate array (FPGA). The FPGA further includes: multiple cache units, each data cache unit storing data for different types of operations on the memory. The method includes: in response to an operation instruction to operate on the memory, obtaining the data cache amount and data amount threshold of each cache unit; determining a target operation type that is currently allowed to operate on the memory based on the data cache amount and the data amount threshold of each cache unit, the target operation type including a read operation or a write operation; and performing an operation of the target operation type on the memory according to the target data amount threshold, wherein the target data amount threshold is the data amount threshold of the cache unit corresponding to the target operation type.

[0006] Secondly, embodiments of this application provide a memory operation device, which includes a control unit of a field-programmable gate array (FPGA) and a memory. The FPGA includes multiple cache units and a control unit. The FPGA is connected to the memory and is used to write data to or read data from the memory. The multiple cache units include a read cache unit and a write cache unit. The read cache unit is used to cache data read from the memory, and the write cache unit is used to cache data to be written to the memory. The multiple cache units are connected to the control unit, which is used to execute the memory operation method as described in the first aspect.

[0007] Thirdly, embodiments of this application provide an electronic device, which includes: a processor and a memory storing computer program instructions; the processor executes the computer program instructions to implement the memory operation method as described in the first aspect.

[0008] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the memory operation method as described in the first aspect.

[0009] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform the memory operation method as described in the first aspect.

[0010] As described above, in this embodiment, memory read / write control is implemented through a control unit in the FPGA. This process is only related to the amount of data cached in the FPGA's cache unit, the data volume threshold, and the type of operation performed on the memory. That is, memory read / write control can be achieved simply by considering the aforementioned data cache amount, data volume threshold, and operation type. Compared to related technologies that combine address lines and data lines for control, this not only simplifies the logic interface for memory control but also enables automatic control of the internal logic flow of the FPGA. This makes the logic control between the FPGA and the memory simpler, the data flow interface more convenient, and the memory read / write bandwidth utilization higher. Furthermore, in this embodiment, memory read / write control is only triggered when the amount of data cached in the cache unit meets certain conditions. When frequent memory access is required, this method can reduce the memory read / write frequency, increase the effective bandwidth of the memory, improve the utilization rate of the memory read / write bandwidth, and thus reduce the risk of data loss.

[0011] Therefore, the solution provided in this application embodiment can improve the effective bandwidth of the memory and reduce the risk of data packet loss. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of a memory operation device provided in one embodiment of this application; Figure 2 This is a flowchart illustrating a memory operation method provided in another embodiment of this application; Figure 3 This is a schematic flowchart of an overall operation method of a memory provided in another embodiment of this application; Figure 4 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0014] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0015] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0016] To facilitate understanding, before explaining the solution provided in this application, the background of the solution provided in this application will be explained first.

[0017] In related technologies, address lines and data lines are usually combined to implement the control logic for FPGA to access DDR memory, so that the FPGA can read and write data in DDR memory according to the read and write addresses.

[0018] In applications that do not require data address space partitioning but need large caches, frequent control of DDR memory can lead to overly complex FPGA internal logic design and easily cause exceptions. Secondly, in applications with high DDR read / write speed requirements, frequent access to DDR memory can reduce the actual effective bandwidth of DDR and even cause data loss. Thirdly, in data flow applications, the combination of address and data lines is not conducive to data interface communication between modules, affecting the overall layout and routing of the FPGA and hindering the modularization of the control interface.

[0019] To address the problems of the prior art, embodiments of this application provide a memory operation method and a memory operation apparatus. In this embodiment, the memory operation apparatus includes a field-programmable gate array (FPGA) control unit and a memory, wherein the FPGA includes multiple cache units and a control unit.

[0020] In one embodiment, Figure 1 A schematic diagram of the structure of the memory operation device provided in an embodiment of this application is shown, such as... Figure 1 As shown, the operating device includes a field-programmable gate array (FPGA) 10 and a memory 20. The memory 20 is a RAM (Random Access Memory) device to be controlled, which can be a random access memory, such as a memory composed of one or more of DDR2, DDR3, DDR4, and QDR (Quad Data Rate) memory. In this embodiment, the FPGA 10 is connected to the memory 20, and the FPGA 10 is used to write data to or read data from the memory 20, thereby realizing the read and write control of the memory 20 by the FPGA 10.

[0021] In one embodiment, such as Figure 1 As shown, the field-programmable gate array 10 includes multiple cache units 101, a control unit 102, and a driver 103.

[0022] In this embodiment of the application, the plurality of cache units 101 may include a read cache unit and a write cache unit, wherein the read cache unit is used to cache data read from the memory 20, and the write cache unit is used to cache data to be written to the memory 20.

[0023] As an example, the cache unit can be a FIFO (First In First Out) module, where the FIFO module can implement data buffering, cross-clock domain conversion, and simplified interface, etc. In the embodiments of this application, the read cache unit can be a read FIFO, that is, a FIFO that caches data read from memory 20; correspondingly, the write cache unit can be a write FIFO, that is, a FIFO that caches data to be written to memory 20.

[0024] In one embodiment, such as Figure 1 As shown, multiple cache units 101 are connected to a control unit 102, wherein the control unit 102 is used to execute the memory operation method provided in the embodiments of this application.

[0025] In this embodiment, the control unit 102 can serve as the intelligent control center of the field programmable gate array 10. It can automatically adjust the read and write cycle of the memory 20 according to the interface data rate corresponding to the current cache unit 101, the interface data rate corresponding to the memory 20, and the custom working mode of the memory 20, so as to maximize the bandwidth utilization of the memory 20 and improve the smoothness of the read and write data rate of the memory 20.

[0026] It should be noted that, in the above example, the custom operating mode of memory 20 may include, but is not limited to, write operation priority and read operation priority.

[0027] In one embodiment, such as Figure 1 As shown, the field-programmable gate array 10 also includes a driver 103, which is connected between the control unit 102 and the memory 20. In this embodiment, the driver 103 is equivalent to a control driver for address lines and data lines. It can write data in the write FIFO to the memory 20 according to the address, or read data from the memory 20 according to the address and cache it in the read FIFO, according to the DDR control protocol format.

[0028] In one example, for a data write operation to memory 20, the data to be written to memory 20 enters the control unit 102 from the write FIFO, and then is written to memory 20 via driver 103. For a data read operation to memory 20, the data read from memory 20 enters the read FIFO via driver 103 and then via control unit 102, allowing other modules to read the relevant data from the read FIFO.

[0029] Based on the data flow of the above data write and data read operations, in this embodiment of the application, the external interface of the field-programmable gate array presents a "single FIFO interface". Compared with the control method of address lines + data lines, the memory operation device provided in this embodiment of the application simplifies the control logic interface of the memory, making the control logic interface of the memory simpler, the logic control simpler, the data flow interface more convenient, and the read and write bandwidth utilization higher.

[0030] The following is Figure 1 The control unit in this application is the execution subject, and the operation method of the memory provided in the embodiments of this application is described.

[0031] In one embodiment, Figure 2 A flowchart illustrating an embodiment of the memory operation method provided in this application is shown. Figure 2 As shown, the method includes the following steps S201 to S203: Step S201: In response to an operation instruction to operate on the memory, the data cache amount and data amount threshold of each cache unit in the plurality of cache units are obtained.

[0032] In step S201, the operation instruction can be an instruction sent by other modules upstream of the FPGA to instruct the FPGA to perform data operations on the memory. For example, in a vehicle scenario, the memory stores the vehicle's operating data. When the vehicle controller needs to read the vehicle's operating data for processing and analysis, the vehicle controller can send an operation instruction to the FPGA, so that the FPGA's control unit can perform data reading or data writing operations on the memory according to the operation instruction.

[0033] In step S201, the data cache amount of the cache unit is the amount of cached data in the cache unit. For example, for a write FIFO, the corresponding data cache amount is the amount of data to be written to the memory; for a read FIFO, the corresponding data cache amount is the amount of data read from the memory and cached in the read FIFO.

[0034] As an example, each cache unit is equipped with a data count counter, which can calculate the number of data items in the current cache unit and report it to the control unit in the FPGA in real time, so that the control unit can obtain the amount of data cached in the corresponding cache unit.

[0035] It should be noted that in the embodiments of this application, each cache unit has a corresponding data volume threshold. This data volume threshold is used to characterize the total amount of data written to or read from the memory at one time, and the data volume threshold is used to characterize the operation threshold for the FPGA to perform read and write operations on the memory. For example, for a write FIFO, the data volume threshold is the total amount of data written to the memory at one time. That is, when the data cache amount in the write FIFO reaches the data volume threshold, the FPGA writes the data in the write FIFO to the memory at one time. For a read FIFO, the data volume threshold is the total amount of data read from the memory at one time. For example, when the remaining cache amount in the read FIFO is greater than the data volume threshold, the FPGA reads the data of the data volume threshold from the memory and caches it in the read FIFO.

[0036] Furthermore, it should be noted that in this embodiment, the data volume threshold of the cache unit can be set according to actual scenario requirements. The data volume threshold of the cache unit can also be determined based on the interface data rate of the cache unit, the interface data rate of the memory, and the total memory capacity of the memory, wherein the interface data rate of the cache unit is less than the interface data rate of the memory. For example, in scenarios where the stability of data writing to the memory needs to be guaranteed, the data volume threshold of the write FIFO can be reduced to decrease the data writing cycle of the memory; considering the limited memory capacity, the data volume threshold of the write FIFO will not be unconditionally reduced, but rather a lower limit is set based on the memory capacity of the memory.

[0037] Step S202: Determine the target operation type that is allowed to operate on the memory at the current moment based on the data cache amount of each cache unit and the data amount threshold of each cache unit.

[0038] In step S202, the target operation type includes either a read operation or a write operation. For example, if the data buffer size of the write FIFO is greater than a data size threshold, it can be determined that the FPGA can perform a write operation on the memory. Similarly, if the remaining buffer size, determined by the data buffer size of the read FIFO, is greater than a data size threshold, it can be determined that the FPGA can perform a read operation on the memory.

[0039] Step S203: Perform the target operation type operation on the memory according to the target data volume threshold.

[0040] In step S203, the target data volume threshold is the data volume threshold of the cache unit corresponding to the target operation type. For example, if the target operation type is a write operation, the target data volume threshold is the data volume threshold of the write FIFO; if the target operation type is a read operation, the target data volume threshold is the data volume threshold of the read FIFO.

[0041] Once the target data volume threshold is determined, the FPGA can perform corresponding operations on the memory. For example, if the target operation type is a write operation, the FPGA writes the target data volume threshold data to the memory; if the target operation type is a read operation, the FPGA reads the target data volume threshold data from the memory.

[0042] Therefore, in this embodiment of the application, the FPGA will only perform read or write operations on the memory when the amount of data cached in the cache unit meets certain conditions. Moreover, the amount of data for the read or write operation is the target data amount threshold. That is, when the amount of data cached in the cache unit meets certain conditions, a certain amount of data will be written into the memory at once, or a certain amount of data will be read out of the memory at once, so as to reduce the read and write frequency of the memory and improve the read and write bandwidth of the memory.

[0043] Based on the scheme defined in steps S201 to S203 above, it can be understood that in this embodiment, memory read / write control is implemented through the control unit in the FPGA. This process is only related to the amount of data cached in the cache unit of the FPGA, the data volume threshold, and the type of operation performed on the memory. That is, memory read / write control can be achieved through the aforementioned data cache amount, data volume threshold, and operation type. Compared with the control method combining address lines and data lines in related technologies, this not only simplifies the logic interface of memory control but also realizes automatic control of the internal logic flow of the FPGA, making the logic control between the FPGA and the memory simpler, the data flow interface more convenient, and the memory read / write bandwidth utilization higher. In addition, in this embodiment, memory read / write control is only triggered when the amount of data cached in the cache unit meets certain conditions. When frequent memory access is required, this method can reduce the memory read / write frequency, increase the effective bandwidth of the memory, improve the utilization rate of the memory read / write bandwidth, and thus reduce the risk of data packet loss.

[0044] Therefore, the solution provided in this application embodiment can improve the effective bandwidth of the memory and reduce the risk of data packet loss.

[0045] The implementation process of the method provided in the embodiments of this application is described below.

[0046] In this embodiment of the application, the plurality of cache units include at least a write cache unit and a read cache unit, that is Figure 1 The read FIFO and write FIFO in the middle.

[0047] After the control unit obtains the data cache amount of each cache unit, the control unit determines the target operation type that is allowed to operate on the memory at the current moment based on the data cache amount of each cache unit and the data amount threshold of each cache unit.

[0048] Specifically, the control unit first obtains the total cache amount corresponding to the read cache unit. Then, based on the data cache amount corresponding to the read cache unit and the total cache amount corresponding to the read cache unit, it determines the remaining cache amount corresponding to the read cache unit. It compares the write data cache amount of the write cache unit with the write data amount threshold corresponding to the write cache unit to obtain the first comparison result. It compares the remaining cache amount of the read cache unit with the read data amount threshold corresponding to the read cache unit to obtain the second comparison result. Based on the first comparison result and the second comparison result, the target operation type can be determined.

[0049] In the above embodiments, the total cache size corresponding to the read cache unit is preset. The control unit can obtain it from the operation instructions or from the configuration file corresponding to the FPGA. The configuration file corresponding to the FPGA includes the total cache size of each cache unit in the FPGA.

[0050] It should be noted that for the read cache unit, the FPGA will only trigger the data read operation on the memory when the remaining cache amount of the read cache unit is sufficient. Therefore, after obtaining the data cache amount of the read cache unit, it is also necessary to calculate the remaining cache amount of the read cache unit.

[0051] In addition, in this embodiment of the application, by comparing the write data cache amount of the write cache unit with the write data amount threshold, it can be determined whether a write operation can be performed on the memory at the current moment; correspondingly, by comparing the cache remaining amount of the read cache unit with the read data amount threshold, it can be determined whether a read operation can be performed on the memory at the current moment.

[0052] By comparing the first comparison result and the second comparison result, it can be determined whether read and write operations can be performed on the memory. When it is determined that read or write operations can be performed on the memory, batch data can be read or written to the memory, reducing the read and write frequency of the memory and increasing the read and write bandwidth of the memory.

[0053] In one specific embodiment, during the process of determining the target operation type, the control unit also considers the read operation address and write operation address corresponding to the read and write operations. Then, by using the read operation address, write operation address, and data volume threshold (read data volume threshold, write data volume threshold), the control unit determines the target operation type that can be operated on at the current moment, so as to improve the accuracy of the target operation type and improve the stability of memory read and write.

[0054] Specifically, the controller obtains the read operation address for reading from the memory and the write operation address for writing to the memory; when the read operation address and the write operation address are different, it obtains the operation priority corresponding to the memory; when the write data cache size is greater than the write data size threshold and the remaining cache size is greater than the read data size threshold, it determines the operation with the higher operation priority as the target operation type.

[0055] As an example, when the read and write addresses of the memory are different, if the write data cache size of the write cache unit is greater than the write data size threshold, it indicates that a write operation can be performed on the memory; if the remaining cache size of the read cache unit is greater than the read data size threshold, it indicates that a read operation can be performed on the memory. In this case, the control unit prioritizes operations with higher priority. For example, if the write operation has priority, the control unit prioritizes writing to the memory; if the read operation has priority, the control unit prioritizes reading from the memory.

[0056] When both write and read operations in the memory meet the triggering conditions, the operation type for the memory can be determined according to the operation priority. This can ensure the normal execution of data operations in the memory and reduce the risk of data loss.

[0057] Furthermore, by combining operation priority and data volume thresholds, the memory read / write rate can be adjusted. For example, in scenarios where the memory read / write rates are inconsistent, if other upstream control units (e.g., the vehicle controller) need to perform stable data write operations to the memory, the control unit will prioritize writing data from the write FIFO to the memory. For read operations, the read operation will only be performed when the remaining buffer in the read FIFO meets the condition. Similarly, in scenarios where the memory read / write rates are inconsistent, if other upstream control units (e.g., the vehicle controller) need to perform stable data read operations to the memory, the control unit will prioritize reading data from the memory and storing it in the read FIFO in real time. For write operations, the write operation will only be performed when the data buffer in the write FIFO meets the condition.

[0058] In one embodiment, if the write data cache size is less than or equal to the write data size threshold, and the remaining cache size is greater than the read data size threshold, the control unit determines the read operation as the target operation type. That is, when a write operation in the memory does not meet the triggering conditions, but a read operation does, the control unit prioritizes executing the read operation.

[0059] If the write data cache size is greater than the write data size threshold, and the remaining cache size is less than or equal to the read data size threshold, the control unit will determine the write operation as the target operation type. That is, when a write operation in the memory meets the triggering conditions, but a read operation does not, the control unit will prioritize executing the write operation.

[0060] When a certain type of operation does not meet the triggering condition, another operation that meets the triggering condition is executed first, which can improve the efficiency of operations on memory and thus improve the data read and write efficiency of memory.

[0061] In another embodiment, the address state corresponding to a read or write operation may also be considered during the process of determining the target operation type for the memory to improve the data read and write stability of the memory.

[0062] Specifically, the control unit first obtains the read operation address for reading the memory and the write operation address for writing the memory; if the read operation address and the write operation address are the same, it obtains the address status of the read operation address or the write operation address; and determines the target operation type based on the first comparison result, the second comparison result, and the address status.

[0063] In the above embodiments, the address status includes whether the read operation address or write operation address stores data.

[0064] It should be noted that reading data from an address where no data is stored can lead to a memory overflow, while writing data to an address that already contains data will overwrite the existing data at that address, potentially causing subsequent data processing errors. To mitigate the risk of these problems, in this embodiment, the target operation type is determined based on the comparison result corresponding to the read / write cache unit and the address status of the read or write operation address.

[0065] In one embodiment, the field-programmable gate array (FPGA) further includes a driver connected to the memory. The driver performs read and write operations on the memory according to the memory's corresponding control protocol. In this scenario, when the address status indicates that data is stored at the read or write address, and the remaining cache size is less than or equal to a read data size threshold, the control unit controls the driver to enter a waiting state until the remaining cache size exceeds the read data size threshold, and then determines the target operation type as a read operation. That is, when the operation addresses corresponding to read and write operations are the same, if data is stored at that operation address and the read operation trigger condition is met, the control unit can perform a read operation on the memory. After completing the read operation, if there is no data at the corresponding operation address in the memory, the control unit performs a write operation on the memory, thereby avoiding the aforementioned data overwriting problem. If data is stored at that operation address but the read operation trigger condition is not met, the control unit does not perform a read or write operation on the memory, but waits until the read operation trigger condition is met before performing a read operation on the memory.

[0066] If the address status indicates that no data is stored at the read or write operation address, and the write data buffer size is less than or equal to the write data size threshold, the control unit controls the driver to enter a waiting state until the write data buffer size exceeds the write data size threshold, and then determines the target operation type as a write operation. That is, when the operation addresses corresponding to read and write operations are the same, if no data is stored at that address but the write operation trigger condition is met, the control unit can perform a write operation on the memory. After the write operation is completed, if data exists at the corresponding operation address in the memory, the control unit then performs a read operation on the memory, thus avoiding the aforementioned memory overflow problem. If no data is stored at that operation address, and the write operation trigger condition is also met, the control unit will not perform a write operation on the memory, but will wait until the write operation trigger condition is met before performing a write operation on the memory.

[0067] In one embodiment, after determining the target operation type as a write operation, the control unit also obtains the data write rate corresponding to the write operation and the data read rate corresponding to the read operation; if the sum of the data write rate and the data read rate is less than the data operation rate corresponding to the memory, the data of the write data amount threshold in the write cache unit is written to the memory; after the preset time of completing the write operation, the data of the read data amount threshold is read from the memory and written to the read cache unit.

[0068] In one example, when the data read rate of the read FIFO is equal to the data write rate of the write FIFO, and their sum is less than the data operation rate corresponding to the actual effective bandwidth of the memory, the FPGA can read the data written by the write operation from a certain address in the memory after a certain period of time following the writing of data to that address. Correspondingly, after reading data from that address, the FPGA can write data to that address again, thus achieving autonomous high-speed data transfer.

[0069] In one embodiment, the control unit may also perform address management on the memory before performing an operation of the target operation type on the memory based on a target data volume threshold.

[0070] Specifically, when the target operation type is a write operation, the control unit detects whether the write operation address corresponding to the write operation is outside the first address space range; if the write operation address corresponding to the write operation is outside the first address space range, the data at the write operation address in the memory is overwritten based on the target data volume threshold.

[0071] In the above embodiments, the first address space range is determined by the read operation address corresponding to the read operation and the address space corresponding to the memory. The upper limit of the first address space range can be the address determined by the read operation address and the upper limit of the address space of the memory. That is, the write operation address corresponding to the write operation cannot be greater than the upper limit of the first address space range, so as to reduce the risk of data being overwritten.

[0072] In one embodiment, when the target operation type is a read operation, the control unit detects whether the read operation address corresponding to the read operation is outside the second address space range; if the read operation address corresponding to the read operation is outside the second address space range, the control unit generates an exception prompt message.

[0073] In the above embodiments, the second address space range is determined by the write operation address corresponding to the write operation. The upper limit of the second address space range can be the write operation address; that is, the read operation address corresponding to the read operation cannot exceed the upper limit of the second address space range to reduce the risk of memory overflow. If the read operation address exceeds the second address space range, an error occurs in the data read operation by the control unit. In this case, the control unit can generate an error message to remind relevant personnel to perform an error check.

[0074] This concludes the introduction of the methods provided in the embodiments of this application.

[0075] In one embodiment, Figure 3 A flowchart illustrating the overall process of the method provided in the embodiments of this application is shown, as follows: Figure 3 As shown, the method includes the following steps S301 to S304: Step S301: The data volume counters in the read FIFO and write FIFO are automatically counted, and the data buffer volume in the read FIFO and write FIFO is monitored in real time.

[0076] In step S302, the control unit obtains the data buffer amount from the read FIFO and write FIFO, and makes dynamic decisions based on the memory's operating mode (i.e., read operation priority, write operation priority) and the status of read and write addresses to determine the type of operation to be performed on the memory.

[0077] Step S303: The driver writes data to or reads data from the memory according to the DDR memory control protocol format, and performs address management on the memory.

[0078] Step S304: The control unit reports the status information of the operating memory. The control unit can output some important status information in the current logic process to other modules, such as running status error information, DDR initialization failure information, data flow rate mismatch error information, etc.

[0079] As can be seen from the above, the solution provided in this application can simplify the control logic of the DDR interface. Compared with the control method of address lines + data lines, the simplified DDR control logic interface is more concise, the internal logic flow of the module is automatically controlled, the board-level logic control is simpler, the data flow interface is more convenient to connect, and the read and write bandwidth utilization is higher.

[0080] Figure 4 A schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application is shown.

[0081] The electronic device may include a processor 401 and a memory 402 storing computer program instructions.

[0082] Specifically, the processor 401 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0083] Memory 402 may include mass storage for data or instructions. For example, and not limitingly, memory 402 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 402 may include removable or non-removable (or fixed) media. Where appropriate, memory 402 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 402 is non-volatile solid-state memory.

[0084] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods according to one aspect of this disclosure.

[0085] The processor 401 reads and executes computer program instructions stored in the memory 402 to implement any of the memory operation methods in the above embodiments.

[0086] In one example, the electronic device may also include a communication interface 403 and a bus 410. For example, Figure 4 As shown, the processor 401, memory 402, and communication interface 403 are connected through bus 410 and complete communication with each other.

[0087] The communication interface 403 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0088] Bus 410 includes hardware, software, or both, that couples components of an electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 410 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0089] Furthermore, in conjunction with the memory operation methods described in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. This computer-readable storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the memory operation methods described in the above embodiments.

[0090] Furthermore, in conjunction with the memory operation methods described in the above embodiments, this application embodiment can provide a computer program product for implementation. When the instructions in this computer program product are executed by the processor of an electronic device, the electronic device performs the memory operation method as described in any of the above embodiments.

[0091] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0092] The functional modules shown in the above-described block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0093] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0094] The foregoing flowcharts and / or block diagrams of memory operation methods and means according to embodiments of the present disclosure have described various aspects of the present disclosure. It should be understood that each block and combination of blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block and combination of blocks in the block diagrams and / or flowcharts can also be implemented by dedicated hardware performing the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0095] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for operating a memory, characterized in that, A control unit applied to a field-programmable gate array (FPGA), the FPGA further comprising: multiple cache units, each data cache unit for storing data for different types of operations on the memory, the method comprising: In response to an operation instruction that operates on the memory, the data cache size and data size threshold of each of the plurality of cache units are obtained; Based on the data cache size of each cache unit and the data size threshold of each cache unit, the target operation type that is allowed to operate on the memory at the current moment is determined, and the target operation type includes read operation or write operation; The target operation type is performed on the memory according to the target data volume threshold, wherein the target data volume threshold is the data volume threshold of the cache unit corresponding to the target operation type.

2. The method according to claim 1, characterized in that, The plurality of cache units include at least a write cache unit and a read cache unit, wherein determining the target operation type allowed to operate on the memory at the current moment based on the data cache size of each cache unit and the data size threshold of each cache unit includes: Obtain the total cache size corresponding to the read cache unit; The remaining cache amount corresponding to the read cache unit is determined based on the data cache amount corresponding to the read cache unit and the total cache amount corresponding to the read cache unit; The write data cache amount of the write cache unit is compared with the write data amount threshold corresponding to the write cache unit to obtain the first comparison result; The second comparison result is obtained by comparing the remaining cache amount of the read cache unit with the read data amount threshold corresponding to the read cache unit; The target operation type is determined based on the first comparison result and the second comparison result.

3. The method according to claim 2, characterized in that, Determining the target operation type based on the first comparison result and the second comparison result includes: Obtain the read operation address for reading the memory and the write operation address for writing the memory; If the read operation address and the write operation address are different, obtain the operation priority corresponding to the memory; If the write data cache size is greater than the write data size threshold and the remaining cache size is greater than the read data size threshold, the operation with the higher operation priority is determined as the target operation type.

4. The method according to claim 3, characterized in that, The method further includes: If the write data cache size is less than or equal to the write data size threshold, and the remaining cache size is greater than the read data size threshold, the read operation is determined as the target operation type. If the write data cache size is greater than the write data size threshold and the remaining cache size is less than or equal to the read data size threshold, the write operation is determined as the target operation type.

5. The method according to claim 2, characterized in that, Determining the target operation type based on the first comparison result and the second comparison result includes: Obtain the read operation address for reading the memory and the write operation address for writing the memory; When the read operation address and the write operation address are the same, obtain the address status of the read operation address or the write operation address, wherein the address status includes whether the read operation address or the write address stores data; The target operation type is determined based on the first comparison result, the second comparison result, and the address status.

6. The method according to claim 5, characterized in that, The field-programmable gate array further includes a driver connected to the memory, the driver being used to perform read and write operations on the memory according to the control protocol corresponding to the memory, wherein determining the target operation type based on the first comparison result, the second comparison result, and the address status includes: When the address status indicates that data is stored in the read operation address or the write operation address, and the remaining cache amount is less than or equal to the read data amount threshold, the driver is controlled to enter a waiting state until the remaining cache amount is greater than the read data amount threshold, and the target operation type is determined to be the read operation; If the address status indicates that no data is stored in the read operation address or the write operation address, and the write data cache size is less than or equal to the write data size threshold, the driver is controlled to enter a waiting state until the write data cache size is greater than the write data size threshold, and the target operation type is determined to be the write operation.

7. The method according to claim 6, characterized in that, After determining the target operation type as the write operation, the method further includes: Obtain the data write rate corresponding to the write operation and the data read rate corresponding to the read operation; If the sum of the data write rate and the data read rate is less than the data operation rate corresponding to the memory, the data of the write data amount threshold in the write cache unit is written to the memory; After a preset time has elapsed since the write operation was completed, the data of the read data volume threshold is read from the memory and stored in the read cache unit.

8. The method according to any one of claims 1 to 7, characterized in that, Before performing the operation of the target operation type on the memory according to the target data volume threshold, the method further includes: When the target operation type is the write operation, it is detected whether the write operation address corresponding to the write operation is outside the first address space range, which is determined by the read operation address corresponding to the read operation and the address space corresponding to the memory. If the write operation address corresponding to the write operation is outside the first address space range, the data at the write operation address in the memory is overwritten based on the target data volume threshold.

9. The method according to any one of claims 1 to 7, characterized in that, Before performing the operation of the target operation type on the memory according to the target data volume threshold, the method further includes: When the target operation type is the read operation, it is detected whether the read operation address corresponding to the read operation is outside the second address space range, which is determined by the write operation address corresponding to the write operation. If the address corresponding to the read operation is outside the range of the second address space, an exception message is generated.

10. An operating device for a memory, characterized in that, The operating device includes a control unit of a field-programmable gate array (FPGA) and a memory. The FPGA includes multiple cache units and a control unit. The field-programmable gate array is connected to the memory and is used to write data into the memory or read data from the memory; The plurality of cache units include a read cache unit and a write cache unit. The read cache unit is used to cache data read from the memory, and the write cache unit is used to cache data to be written to the memory. The plurality of cache units are connected to the control unit, which is used to execute the method described in any one of claims 1 to 9.

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