Memory cells including dual anti-fuse devices, memory structures, and methods of operation

Abstract

The invention relates to a memory cell including a dual anti-fuse device, a memory structure, and a method of operation. A memory cell is disclosed that includes a dual anti-fuse device between a first pass-gate transistor and a second pass-gate transistor. A dual antifuse device includes first and second antifuses having a common terminal and also each having an additional terminal opposite the common terminal. The first pass-gate transistor is connected between the first bit line and an additional terminal for the first pass-gate transistor. The second pass gate transistor is connected between the second bit line and an additional terminal of the second pass gate transistor. A common terminal of the first and second antifuses and gates of the first and second pass-gate transistors are connected to a word line. A memory structure including an array of such memory cells and related methods of operation are also disclosed. Within the array, different word line and bit line bias conditions may be employed to reliably perform program or read operations for selected antifuses in selected cells.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to one-time programmable (OTP) memory, and more particularly to embodiments of memory cells including dual-antifuse devices, memory structures including arrays of such memory cells, and associated methods of operation. BACKGROUND

[0002] Objectives of modern integrated circuit design include, but are not limited to, improved performance, reduced area, and reduced power consumption. Often, a design change related to one of these objectives can result in an undesirable tradeoff with respect to one or more of the other objectives. For example, when it is necessary to reliably retain data during repeated power-up and power-down cycles, memory structures including one-time programmable (OTP) memory cells are often employed. Conventional OTP memory cells include devices such as fuses or antifuses. To reduce area consumption, dual-antifuse devices have been developed for storing two bits of data, thereby reducing memory structure area. However, the results of read and / or program operations within such memory structures can be less reliable due to, for example, potential shorts within the array. SUMMARY

[0003] Embodiments of memory cells, memory structures including arrays of such memory cells, and associated methods of operation are disclosed herein.

[0004] More particularly, disclosed embodiments of memory cells can include dual-antifuse devices. The dual-antifuse device can include a first antifuse and a second antifuse having a common terminal connected to a word line. The dual-antifuse device can also include a first pass gate transistor having a gate connected to the word line, and a second pass gate transistor having a gate also connected to the word line. The first pass gate transistor can also be connected between a first bit line and the first antifuse, while the second pass gate transistor can be connected between the second antifuse and a second bit line.

[0005] Embodiments of the disclosed memory structure can include an array of memory cells arranged in rows and columns. The memory structure can also include word lines for the rows, respectively; and bit line pairs (i.e., a first bit line and a second bit line) for the columns, respectively. Each memory cell in the array can include a dual antifuse device. The dual antifuse device can include a first antifuse and a second antifuse having a common terminal connected to a word line for a row. The dual antifuse device can also include a first pass gate transistor having a gate connected to the word line for the row, and a second pass gate transistor having a gate also connected to the word line for the row. The first pass gate transistor can also be connected between a first bit line for a column and the first antifuse, while the second pass gate transistor can be connected between the second antifuse and a second bit line for the column.

[0006] Embodiments of the disclosed method can include providing a memory structure. The memory structure can include an array of memory cells arranged in rows and columns. The memory structure can also include word lines for the rows, respectively; and bit line pairs (i.e., a first bit line and a second bit line) for the columns, respectively. Each memory cell in the array can include a dual antifuse device. The dual antifuse device can include a first antifuse and a second antifuse having a common terminal connected to a word line for a row. The dual antifuse device can also include a first pass gate transistor having a gate connected to the word line for the row, and a second pass gate transistor having a gate also connected to the word line for the row. The first pass gate transistor can also be connected between a first bit line for a column and the first antifuse, while the second pass gate transistor can be connected between the second antifuse and a second bit line for the column. The method can also include selectively and individually performing operations on selected antifuses of selected memory cells in the array.

[0007] It should be noted that all aspects, examples, and features of the disclosed embodiments mentioned in the summary above can be combined in any technically possible manner. That is, two or more aspects of any of the disclosed embodiments, including those described in the summary section, can be combined to form implementations not specifically described herein. The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0008] The disclosure will be better understood from the following detailed description taken in conjunction with the accompanying drawings, which are not necessarily drawn to scale, in which:

[0009] Figure 1 FIG. 1 is a schematic diagram illustrating an embodiment of a memory structure and an embodiment of a memory cell within an array of memory cells in the disclosed memory structure;

[0010] Figure 2 FIG. 2 is a cross-sectional view illustrating one example of a dual antifuse device that can be incorporated in a memory cell of the embodiments disclosed herein;

[0011] Figure 3 FIG. 3 is a table illustrating example word line and bit line bias conditions that can be employed during operation of the embodiments disclosed herein; and

[0012] Figure 4 and Figure 5 FIG. 4 is a flowchart illustrating a method of operating the embodiments disclosed herein. DETAILED DESCRIPTION

[0013] As noted above, conventional OTP memory cells include a device such as a fuse or antifuse. To reduce area consumption, dual antifuse devices have been developed to store two bits of data, thereby reducing memory structure area. However, the results of read and / or program operations within such memory structures can be less reliable due to, for example, potential shorts within the array.

[0014] In view of the foregoing, embodiments of a memory cell including a dual antifuse device connected between a first pass gate transistor and a second pass gate transistor are disclosed herein. Specifically, the dual antifuse device can include a first antifuse and a second antifuse. Each antifuse can have two terminals, including a common terminal (i.e., shared terminal) with the other antifuse and an additional terminal opposite the common terminal. The first pass gate transistor can have a source / drain region electrically connected to a first bit line and the additional terminal of the first antifuse, respectively. Similarly, the second pass gate transistor can have a source / drain region electrically connected to a second bit line and the additional terminal of the second antifuse, respectively. Further, the common terminals of the first and second antifuses and the gates of the first and second pass gate transistors can be electrically connected to a word line. Embodiments of a memory structure including an array of such memory cells and associated methods of operation are also disclosed herein. Within the array, the memory cells can be arranged in rows and columns, and different word line and bit line bias conditions can be employed in order to perform program or read operations on any selected antifuse in any selected memory cell. As discussed in greater detail below, such operations can be achieved without encountering reliability issues such as IR drops due to shorts as a result of the inclusion of the first and second pass gate transistors within each memory cell and as a result of the disclosed word line and bit line bias conditions for program and read operations.

[0015] Figure 1is a schematic diagram illustrating an embodiment of the disclosed dual antifuse memory cell 101 (also referred to herein as a memory cell or cell) and a memory structure 100 including an array of such cells 101. Within the array, the cells 101 can be arranged in columns (see, e.g., columns CO-Cn) and rows (see, e.g., rows RO-Rm).

[0016] The memory structure 100 can also include word lines (WLO-WLm) for the rows, respectively. That is, a word line for a row can be connected to all cells within that row. The memory structure 100 can also include first and second bit lines (BLO.s1 and BLO.s2-BLn.s1 and BLn.s2) for the columns. That is, both the first and second bit lines for a column can be connected to all cells within that column.

[0017] Each cell 101 can include a dual antifuse device 110. The dual antifuse device 110 can include a first antifuse 111a and a second antifuse 111b. For the purposes of this disclosure, an antifuse refers to a two-terminal electrical device that is programmable once, which initially has a high resistance state, and which can be programmed (once) to a low resistance state. Thus, an antifuse can effectively be used to store a single bit (e.g., a logic “0” when in the unprogrammed, high resistance state, a logic “1” when in the programmed, low resistance state, or vice versa). With such a dielectric antifuse, typically, programming can be achieved by applying a sufficiently high programming voltage (VPGM) to one terminal (i.e., one conductor), and a ground voltage (e.g., 0.0 volts (V)), such that the dielectric layer between the two conductors breaks down due to the current flow, thereby forming a conductive path or filament(s) that electrically connects the two conductors.

[0018] In the dual antifuse device 110 included in the cell 101, the first and second antifuses 111a-111b can share a common terminal 115 (also referred to herein as a shared terminal). Further, the first antifuse 111a can have a first additional terminal 112a opposite the common terminal 115, and the second antifuse 111b can have a second additional terminal 112b opposite the common terminal 115 and isolated from the first additional terminal 112a.

[0019] Figure 2is a diagram showing a cross-section of one example of a dual antifuse device 110 that can be incorporated into the cell 101. The dual antifuse device 110 can be formed on a semiconductor layer 201. The semiconductor layer 201 can be, for example, a single crystalline silicon substrate, or, alternatively, a single crystalline substrate of any other suitable semiconductor material (e.g., silicon germanium, etc.). That is, the dual antifuse device 110 can be a bulk semiconductor structure, as shown. Alternatively, the semiconductor layer 201 can be a semiconductor layer of a semiconductor-on-insulator structure.

[0020] The semiconductor layer 201 can include a first surface (a bottom surface) and a second surface (a top surface) opposite the bottom surface. The dual antifuse device 110 can also include first and second conductive regions 212a-b within the semiconductor layer 201 and adjacent the second surface, and a trench 205 extending into the semiconductor layer 201 from the second surface and laterally between and immediately adjacent to the first and second conductive regions 212a-b. As shown, the trench 205 can have a depth that is greater than a depth of the first and second conductive regions 212a-b. The trench 205 can have a lower portion and an upper portion above the lower portion. The lower portion can be filled with one or more layers of isolation material 206 (e.g., silicon dioxide, silicon nitride, silicon oxynitride, etc.). A gate stack can be located above and immediately adjacent to the isolation material 206. For example, a dielectric layer 213 (e.g., a relatively thin layer of silicon dioxide, a high-k dielectric layer (i.e., a layer of material having a dielectric constant (k) greater than the k of silicon dioxide (i.e., k > 3.9), or a layer(s) of any other suitable dielectric material) can be conformally lined on the upper portion of the trench 205 and can also laterally extend above the first and second conductive regions 212a-b only partially onto the second surface of the semiconductor layer 201. A conductive poly semiconductor layer 214 (e.g., a doped polysilicon layer or a doped layer of some other suitable poly semiconductor material) can be located on the dielectric layer 213. Thus, the gate stack can include a narrow portion located within the upper portion of the trench 205 and a wide portion located above the narrow portion. A gate sidewall spacer 217 can be located above the second surface of the semiconductor layer 201 laterally adjacent to a sidewall of the wide portion of the gate stack. For example, the first and second conductive regions 212a-b and the conductive poly semiconductor layer 214 can be doped to have N-type conductivity at a relatively high level of electrical conductivity.

[0021] As shown, the first and second conductive regions 212a-212b and the trench 205 therebetween can be located within a well region 202. For the purposes of this disclosure, a well region refers to a region of semiconductor material that is doped (e.g., by a dopant implantation process or any other suitable doping process) to have a particular conductivity type. If the first and second conductive regions 212a-212b are N-type conductive regions, then the well region 202 can be a P-type well region (P-well), and thus, the first and second conductive regions 212a-212b are electrically isolated from one another.

[0022] Within this dual antifuse device 110, the first antifuse 111a includes the first conductive region 212a, the conductive poly crystalline semiconductor layer 214, and a first portion of the dielectric layer 213 located between the first conductive region 212a and the conductive poly crystalline semiconductor layer 214. Similarly, the second antifuse 111b includes the second conductive region 212b, the conductive poly crystalline semiconductor layer 214, and a second portion of the dielectric layer 213 located between the second conductive region 212b and the conductive poly crystalline semiconductor layer 314. Thus, the conductive poly crystalline semiconductor layer 214 is the common terminal 115 between the first and second antifuses 111a-111b, the first conductive region 212a is the additional terminal 112a of the first antifuse 111a, and the second conductive region 212b is the additional terminal 112b of the second antifuse 111b.

[0023] Dual antifuse devices similar to the dual antifuse device shown above and Figure 2 are known in the art. Accordingly, additional details thereof and the process technology for forming such devices are omitted from this specification so that the reader can focus on the salient aspects of the present disclosure related to overall memory cell configuration, memory array configuration, and method of operation. It should be noted that the dual antifuse device 110 shown above and Figure 2 is provided for illustrative purposes and is not intended to be limiting. Alternatively, any other suitable type of dual antifuse device in which the first and second antifuses 111a-111b share a common terminal can be employed in the cell 101.

[0024] Referring again to Figure 1Each cell 101 can also include a first pass gate transistor 120 and a second pass gate transistor 130. The first pass gate transistor 120 can include a first channel region 123 between first source / drain regions and a first gate 125 adjacent to the first channel region 123. The second pass gate transistor 130 can include a second channel region 133 between second source / drain regions 132 and a second gate 135 adjacent to the second channel region 133. The first and second pass gate transistors 120 and 130 can be N-type field effect transistors (NFETs). That is, the first and second channel regions 123, 133 can be intrinsic channel regions (i.e., undoped channel regions) or P-type channel regions (i.e., P- channel regions) having a relatively low level of conductivity. The first and second source / drain regions 122, 132 can be N-type source / drain regions (i.e., N+ source / drain regions) having a relatively high level of conductivity.

[0025] Within each cell 101, the common terminal 115 of the first and second antifuses 111a-111b of the dual antifuse device 110 and the first and second gates 125 and 135 of the first and second pass gate transistors 120 and 130 can be electrically connected to a word line (WL) for a row (R) containing the given cell. Further, the first source / drain regions 122 of the first pass gate transistor 120 can be electrically connected to a first bit line (BL.s1) and an additional terminal 112a of the first antifuse 111a for a column (C) containing the given cell, respectively. Similarly, the second source / drain regions 132 of the second pass gate transistor 130 can be electrically connected to a second bit line (BL.s2) and an additional terminal 112b of the second antifuse 111b for the column (C) containing the given cell, respectively.

[0026] In some embodiments, the dual antifuse device 110 can be configured as shown in Figure 2 and can also be laterally positioned between and immediately adjacent to the first pass gate transistor 120 and the second pass gate transistor 130 on the same semiconductor layer 201. While not specifically shown, it should be appreciated that, in these embodiments, the first conductive region 212a and the first source / drain regions 122 of the first pass gate transistor 120 can be a common / shared N+ region in the semiconductor layer. Similarly, the second conductive region 212b and the second source / drain regions 132 of the second pass gate transistor 130 can be a common / shared N+ region in the semiconductor layer. Alternatively, any other suitable electrical connection between the first source / drain regions 122 and the first antifuse 111a and between the second source / drain regions 132 and the second antifuse 111b can be employed.

[0027] Referring again to Figure 1In the memory structure 100, the first antifuse 111a and the second antifuse 111b in the dual antifuse device 110 of any given primitive 101 in such primitive array can be selectively and individually programmed (e.g., once) and selectively and individually read (e.g., multiple times).

[0028] More specifically, the memory structure 100 may further include: a controller 190; and peripheral circuitry 191-193, which communicates with the controller 190, is connected to the word lines and bit lines of the array, and is configured to facilitate memory primitive operations (e.g., one-time programming and repeated read operations) in response to control signals from the controller 190. The peripheral circuitry may include a row control block 192 electrically connected to the word lines (WL0-WLm) for rows (R0-Rm). The row control block 192 may be a conventional row control block, including row address decoding logic, voltage drivers, etc., for biasing the word lines, as described below. The peripheral circuitry may also include a column control block 191 electrically connected to the first bit line (BL0.s1-BLn.s1) and the second bit line (BL0.s2-BLn.s2) for columns (C0-Cm). The column control block 191 may include column and side address decoding logic, voltage drivers, etc., for biasing the first and second bit lines, as described below. The peripheral circuitry may further include a sense circuit 193 electrically connected to the first bit line (BL0.s1-BLn.s1) and the second bit line (BL0.s2-BLn.s2). The sense circuit 193 may be configured to sense changes in electrical parameters (e.g., voltage or current changes) on the bit lines during a read operation. Memory controllers, row control blocks, column control blocks, and sense circuitry are well known in the art. Therefore, their details are omitted in this specification so that the reader can focus on the prominent aspects relevant to the overall memory cell configuration, memory array configuration, and operation methods in the disclosed embodiments.

[0029] Figure 3 This is a table showing example word line bias conditions and bit line bias conditions that can be applied by row control block 192 and column control block 191 during programming operations of selected antifuse (111a or 111b) in dual antifuse device 110 for selected primitive 101 and during reading operations of selected antifuse (111a or 111b) in dual antifuse device 110 for selected primitive 101. Figure 4 and Figure 5 The flowcharts illustrate methods for operating the disclosed memory structure 100, particularly methods for performing a one-time programming operation and methods for performing a read operation.

[0030] Combination Figure 4 Flowchart Reference Figure 3The table. For programming operations, the antifuse within the dual antifuse device 110 of the primitive 101 (e.g., 111a or 111b) can be selected (see process 402). That is, one side of the row, column, and column can be selected, and the controller 190 can provide address signals to the row control block 192 and the column control block 191. In response, the row control block 192 can apply a programming voltage (VPGM) to a specific word line connected to the selected primitive (i.e., to the word line for the row containing the selected primitive), and can also apply 0.0V to all other word lines (see process 404). Furthermore, the column control block 191 can apply 0.0V to a specific bit line connected to the selected antifuse (via a transmission gate transistor), and can also apply VPGM to all other bit lines (see process 406). Thus, during this programming operation, the common terminal 115 of the first and second antifuses in the selected primitive receives VPGM, and the gates of the first and second transmission gate transistors in the selected primitive receive VPGM. Furthermore, the bit line on the side of the selected base cell adjacent to the selected antifuse is at 0.0V, while the bit line on the opposite side of the selected base cell is at VPGM. Therefore, only the transmission gate transistors connected to the selected antifuse and the bit line at 0.0V will conduct, allowing current to flow for programming the selected antifuse. All other transmission gate transistors remain off. It should be noted that VPGM can be relatively high, especially at levels sufficient to cause breakdown of the dielectric layer in the selected antifuse.

[0031] Combination Figure 5 Flowchart Reference Figure 3The table. For read operations, the antifuse within the dual antifuse device 110 of element 101 (e.g., 111a or 111b) can be selected (see process 502). That is, one side of the row, column, and column can be selected, and the controller 190 can provide address signals to the row control block 192 and the column control block 191. In response, the row control block 192 can apply a first positive supply voltage (VDD) to a specific word line connected to the selected element (i.e., to the word line for the row containing the selected element), and can also apply 0.0V to all other word lines (see process 504). It should be noted that VDD can be relatively low, particularly at or above the threshold voltage (VT) level of the first and second transmission gate transistors 120 and 130, but low enough to avoid breakdown of the antifuse dielectric layer. Furthermore, column control block 191 can apply 0.0V to a specific bit line connected to the selected antifuse (via a transmission gate transistor), and can also apply a second positive supply voltage (e.g., at 2*VDD) to all other bit lines (see process 506). Therefore, during a read operation, the common terminal of the first and second antifuses receives VDD, and the gates of the first and second transmission gate transistors of the selected element also receive VDD. Additionally, the bit line on the side of the selected element adjacent to the selected antifuse is at 0.0V, and the bit line on the opposite side of the selected element is at 2*VDD. Therefore, only the transmission gate transistor between the selected antifuse and the 0.0V bit line is turned on. During this read operation, sensing circuit 193 can sense changes in electrical parameters (e.g., current or voltage) representing the stored logic value on the bit lines connected to the selected antifuse (see process 508). For example, if the selected antifuse has not been programmed (i.e., if it remains in a high-resistance state), the current flowing to the bit line will be blocked, causing the voltage level on that bit line to remain low (e.g., indicating a stored logic value of "0"). However, if the selected antifuse has been programmed (i.e., switched to a low-resistance state), current will flow through the selected antifuse and the transmission gate transistor to the bit line, and the voltage level on that bit line will be pulled up (e.g., indicating a stored logic value of "1").

[0032] It should be noted that in some embodiments, VPGM can be 3 times or more of VDD. For example, in some embodiments, VDD = 1.5V, 2*VDD = 3.0V, and VPGM ≥ 4.5V.

[0033] It should be understood that in the methods and structures described above, semiconductor materials refer to materials whose conductivity can be altered by doping with impurities. Examples of semiconductor materials include, for instance, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon carbide germanium, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements such as aluminum (Al), gallium (Ga), or indium (In) with group V elements such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). Pure semiconductor materials, more specifically, semiconductor materials that are not doped with impurities to increase conductivity (i.e., undoped semiconductor materials) are referred to in the art as intrinsic semiconductors. Semiconductor materials that are doped with impurities to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as extrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same substrate. That is, extrinsic silicon is more conductive than intrinsic silicon; extrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different types of conductivity (e.g., P-type and N-type conductivity) can be achieved using different impurities (i.e., different dopants), and the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with group III dopants such as boron (B) or indium (In) to achieve P-type conductivity, while silicon-based semiconductor materials are typically doped with group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different levels of conductivity depend on the relative concentration levels of one or more dopants in a given semiconductor region.

[0034] It should be understood that the terminology used herein is for describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Moreover, as used herein, when oriented and shown in figures, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “under,” “under,” “above,” “overlapping,” “parallel,” “vertical,” etc., are intended to describe relative positions (unless otherwise stated), and terms such as “touches,” “directly contacts,” “adjacent,” “directly adjacent,” “closely adjacent,” etc., are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, when elements are oriented and shown in a figure, to indicate that one element is located to the side of another element, rather than above or below it. For example, an element laterally adjacent to another element will be beside the other element, an element laterally directly adjacent to another element will be directly beside the other element, and an element laterally surrounding another element will be adjacent to and bound to the outer wall of the other element. All corresponding structures, materials, actions, and equivalents of the means or steps plus functional elements in the following claims are intended to include any structures, materials, or actions used to perform a function in combination with other elements of the specific claims.

[0035] The methods described above are used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with either surface-mount or buried interconnects, or both). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes the integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0036] The descriptions of various disclosed embodiments are given for illustrative purposes and are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications of techniques found in the market, or improvements to techniques, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: A dual antifuse device includes a first antifuse and a second antifuse, wherein the first antifuse and the second antifuse have a common terminal connected to a word line; A first transmission gate transistor is connected between the first bit line and the first antifuse; and A second transmission gate transistor is connected between the second antifuse and the second bit line, wherein the gates of the first transmission gate transistor and the second transmission gate transistor are connected to the word line.

2. The structure according to claim 1, wherein, The dual anti-fuse device includes: The first and second conductive regions are located within the semiconductor layer. The semiconductor layer has a first surface and a second surface opposite to the first surface. Wherein, the first conductive region and the second conductive region are adjacent to the second surface, and The first conductive region is electrically isolated from the second conductive region; A trench extending from the second surface into the semiconductor layer, wherein the trench is laterally located between and adjacent to the first conductive region and the second conductive region, wherein the trench has a lower portion filled with an insulating material and an upper portion located above the lower portion; A dielectric layer, lining the upper portion of the trench above the insulating material, and extending laterally over the first and second conductive regions onto the second surface; and A conductive polycrystalline semiconductor layer is located on the dielectric layer.

3. The structure according to claim 2, in, The first antifuse includes a first conductive region, a conductive polycrystalline semiconductor layer, and a first portion of the dielectric layer located between the first conductive region and the conductive polycrystalline semiconductor layer. The second antifuse includes a second conductive region, a conductive polycrystalline semiconductor layer, and a second portion of the dielectric layer located between the second conductive region and the conductive polycrystalline semiconductor layer. The common terminal includes the conductive polycrystalline semiconductor layer.

4. The structure according to claim 2, wherein, The first conductive region, the second conductive region, and the conductive polycrystalline semiconductor layer have N-type conductivity.

5. The structure according to claim 1, wherein, The first transmission gate transistor and the second transmission gate transistor include N-type field-effect transistors.

6. The structure according to claim 1, wherein, The first and second antifuse wires are individually programmable and readable.

7. A structure comprising: An array of primitives arranged in rows and columns; Word lines used for the lines; as well as The first and second lines for the column, wherein each primitive includes: A dual antifuse device includes a first antifuse and a second antifuse, wherein the first antifuse and the second antifuse have a common terminal connected to a word line for a row; A first transmission gate transistor is connected between the first bit line for the column and the first antifuse; and A second transmission gate transistor is connected between the second antifuse and the second bit line for the column, wherein the gates of the first and second transmission gate transistors are connected to the word line.

8. The structure according to claim 7, wherein, The dual anti-fuse device includes: The first and second conductive regions are located within the semiconductor layer. The semiconductor layer has a first surface and a second surface opposite to the first surface. Wherein, the first conductive region and the second conductive region are adjacent to the second surface, and The first conductive region is electrically isolated from the second conductive region; A trench extending from the second surface into the semiconductor layer, wherein the trench is laterally located between and adjacent to the first conductive region and the second conductive region, wherein the trench has a lower portion filled with an insulating material and an upper portion located above the lower portion; A dielectric layer, lining the upper portion of the trench above the insulating material, and extending laterally over the first and second conductive regions onto the second surface; and A conductive polycrystalline semiconductor layer is located on the dielectric layer.

9. The structure according to claim 8, in, The first antifuse includes a first conductive region, a conductive polycrystalline semiconductor layer, and a first portion of the dielectric layer located between the first conductive region and the conductive polycrystalline semiconductor layer. The second antifuse includes a second conductive region, a conductive polycrystalline semiconductor layer, and a second portion of the dielectric layer located between the second conductive region and the conductive polycrystalline semiconductor layer. The common terminal includes the conductive polycrystalline semiconductor layer.

10. The structure according to claim 8, wherein, The first conductive region, the second conductive region, and the conductive polycrystalline semiconductor layer have N-type conductivity.

11. The structure according to claim 7, wherein, The first transmission gate transistor and the second transmission gate transistor include N-type field-effect transistors.

12. The structure according to claim 7, wherein, The first and second antifuse wires of each element in the array are individually programmable and readable.

13. The structure according to claim 7 further includes peripheral circuitry, the peripheral circuitry comprising: A column control block, which is connected to the first bit line and the second bit line; as well as Line control block, which is connected to the word line; as well as The controller communicates with the column control block and the row control block.

14. The structure according to claim 13, wherein, The column control block and the row control block are configured to apply programming bias conditions to the word line and the first bit line and the second bit line during programming of a selected antifuse in a selected primitive, wherein the programming bias conditions include: Apply a programming voltage to a specific word line connected to the selected primitive; Apply 0.0V to a specific bit line of the selected antifuse connected to the selected primitive via a specific transmission gate transistor; Apply 0.0 volts (V) to all other word lines; and Apply the programming voltage to all other bit lines.

15. The structure according to claim 13, wherein, The column control block and the row control block are configured to apply read bias conditions to the word line and the first bit line and the second bit line during a read of a selected antifuse in a selected primitive in a specific row and a specific column, wherein the read bias conditions include: A first positive power supply voltage is applied to a specific word line connected to the selected primitive; Apply 0.0V to a specific bit line of the selected antifuse connected to the selected primitive via a specific transmission gate transistor; Apply 0.0 volts (V) to all other word lines; and A second positive power supply voltage is applied to all other bit lines, wherein the second positive power supply voltage is at least twice the first positive power supply voltage.

16. A method comprising: A structure is provided, wherein the structure includes: An array of primitives arranged in rows and columns; The word line used for the row; and The first and second lines for the column, wherein each primitive includes: A dual antifuse device includes a first antifuse and a second antifuse, wherein the first antifuse and the second antifuse have a common terminal connected to a word line for a row; A first transmission gate transistor is connected between the first bit line for the column and the first antifuse; and A second transmission gate transistor is connected between the second antifuse and a second bit line for the column, wherein the gates of the first and second transmission gate transistors are connected to the word line; and Selective and individual operation is performed on selected antifuses for selected elements in the array.

17. The method according to claim 16, wherein, Performing the operation selectively and individually includes performing programming operations for selected antifuses in selected primitives through the following steps: Apply a programming voltage to a specific word line connected to the selected primitive; Apply 0.0V to a specific bit line of the selected antifuse connected to the selected primitive via a specific transmission gate transistor; Apply 0.0 volts (V) to all other word lines; and Apply the programming voltage to all other bit lines.

18. The method according to claim 16, wherein, Performing the operation selectively and individually includes performing a read operation on a selected antifuse in a selected primitive by means of the following steps: A first positive power supply voltage is applied to a specific word line connected to the selected primitive; Apply 0.0V to a specific bit line of the selected antifuse connected to the selected primitive via a specific transmission gate transistor; Apply 0.0 volts (V) to all other word lines; as well as A second positive power supply voltage is applied to all other bit lines, wherein the second positive power supply voltage is at least twice the first positive power supply voltage.

19. The method according to claim 18, wherein, Performing the reading operation also includes sensing parameter changes on the specific positioning line.

20. The method according to claim 16, in, The dual anti-fuse device includes: The first and second conductive regions are located within the semiconductor layer. The semiconductor layer has a first surface and a second surface opposite to the first surface. Wherein, the first conductive region and the second conductive region are adjacent to the second surface, and The first conductive region is electrically isolated from the second conductive region; A trench extending from the second surface into the semiconductor layer, wherein the trench is laterally located between and adjacent to the first conductive region and the second conductive region, wherein the trench has a lower portion filled with an insulating material and an upper portion located above the lower portion; A dielectric layer, lining the upper portion of the trench above the insulating material, and extending laterally over the first and second conductive regions onto the second surface; and A conductive polycrystalline semiconductor layer is located on the dielectric layer. The first antifuse includes a first conductive region, a conductive polycrystalline semiconductor layer, and a first portion of the dielectric layer located between the first conductive region and the conductive polycrystalline semiconductor layer. The second antifuse includes a second conductive region, a conductive polycrystalline semiconductor layer, and a second portion of the dielectric layer located between the second conductive region and the conductive polycrystalline semiconductor layer. The common terminal includes the conductive polycrystalline semiconductor layer.

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