Enhanced electromigration storage element applied to nonvolatile memory

Abstract

The invention discloses an enhanced electromigration storage element applied to a nonvolatile memory. During a programming action, two different voltages are provided to the gate terminal of the FinFET transistor or the GAA transistor at the same time. Furthermore, the threshold voltage of the FinFET transistor or the GAA transistor is changed by utilizing an electromigration mechanism. Accordingly, the memory element may be brought into a programmed state or an unprogrammed state. In the reading operation, the same voltage is supplied to the gate end of the FinFET transistor or the GAA transistor, and the storage state of the storage element is judged according to the reading current generated by the FinFET transistor or the GAA transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to a non-volatile memory, and in particular, to an enhanced electromigration storage device for a non-volatile memory. BACKGROUND

[0002] It is well known that non-volatile memory (NVM) has been widely used in various electronic products. For example, SD card, solid state drive (SSD), and the like. The non-volatile memory includes a memory cell array. The memory cell array is composed of a plurality of memory cells. Furthermore, each memory cell has a storage device. For example, the storage device is an antifuse transistor.

[0003] The antifuse transistor determines the storage state of the antifuse transistor according to the state of the gate dielectric layer. When the gate dielectric layer of the antifuse transistor is not ruptured, the storage device is in a first storage state. The memory cell is programmed to cause the gate dielectric layer of the antifuse transistor to rupture, and the storage device becomes a second storage state. Furthermore, once the gate dielectric layer of the antifuse transistor is ruptured, the storage device cannot return to the first storage state.

[0004] For example, US Patent No. 12,289,883 discloses an one time programming memory cell with fin field-effect transistor using physically unclonable function technology. The storage device in the one time programming memory cell is a fin field-effect transistor (hereinafter referred to as FinFET transistor). Please refer to Figure 1A 、 Figure 1B and Figure 1C which are illustrated as a perspective view, a top view and a cross-sectional view along the AB dashed line of the FinFET transistor. The FinFET transistor M FIN includes a gate structure, a drain / source contact layer 130, 140, and fins 112, 114, 116, 118.

[0005] A gate structure is located on the insulating layer 110. The gate structure covers the middle regions of the fins 112, 114, 116, 118. The gate structure includes a gate conductive layer 120 and gate dielectric layers 122, 124, 126, 128. The gate dielectric layers 122, 124, 126, 128 respectively cover the middle regions and lateral surfaces of the fins 112, 114, 116, 118, and the gate conductive layer 120 covers the gate dielectric layers 122, 124, 126, 128. Further, a drain / source contact layer 130 electrically contacts the first side regions of the fins 112, 114, 116, 118, and a drain / source contact layer 140 electrically contacts the second side regions of the fins 112, 114, 116, 118.

[0006] The gate conductive layer 120 serves as a gate terminal of the FinFET transistor M FIN , the drain / source contact layer 130 serves as a first drain / source terminal of the FinFET transistor M FIN , and the drain / source contact layer 140 serves as a second drain / source terminal of the FinFET transistor M FIN . Of course, the number of fins in the FinFET transistor M FIN is not limited, as long as the number of fins is greater than or equal to one. Further, two FinFET transistors can have various connection relationships.

[0007] Please refer to Figure 2 , which is a schematic diagram of two FinFET transistors. Compared with Figure 1A the single FinFET transistor M FIN , Figure 2 the drain / source contact layer 130 electrically contacts the first side regions of the fins 112, 114, the drain / source contact layer 140 electrically contacts the second side regions of the fins 112, 114. The drain / source contact layer 156 electrically contacts the first side regions of the fins 116, 118, and the drain / source contact layer 158 electrically contacts the second side regions of the fins 116, 118. The drain / source contact layer 130 does not electrically contact the drain / source contact layer 156, and the drain / source contact layer 140 does not electrically contact the drain / source contact layer 158. Thus, two FinFET transistors M FIN1 , M FIN2 are formed. Each of the FinFET transistors M FIN1 , M FIN2 includes two fins, and the two FinFET transistors M FIN1 , M FIN2 share the gate conductive layer 120.

[0008] US 2023 / 0371249A1 discloses an antifuse-type one time programming memory cell with gate-all-around. In the one time programming memory cell, a memory element is a gate-all-around (GAA) transistor. Please refer to Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D which are illustrated as a perspective view, a top view, cross-sectional views along ab dashed line and along cd dashed line of a GAA transistor. The GAA transistor M GAA includes a gate structure 220, drain / source structures 232, 236 and a nanowire 230.

[0009] The gate structure 220 is located on an insulating layer 210. The gate structure includes two spacers 252, 246, a gate dielectric layer 222 and a gate conductive layer 224. The gate dielectric layer 222 surrounds a middle region of the nanowire 230, the gate conductive layer 224 surrounds the gate dielectric layer 222, and the gate conductive layer 224 is located on the insulating layer 210. In addition, a first side region of the nanowire 230 is surrounded by the spacer 252, a second side region of the nanowire 230 is surrounded by the spacer 246, and the spacers 252, 246 are located on a semiconductor substrate sub. Furthermore, the drain / source structure 232 electrically contacts a first end of the nanowire 230, and the drain / source structure 236 electrically contacts a second end of the nanowire 230.

[0010] The gate conductive layer 224 serves as a gate terminal of the GAA transistor M GAA , the drain / source structure 232 serves as a first drain / source terminal of the GAA transistor M GAA , and the drain / source structure 236 serves as a second drain / source terminal of the GAA transistor M GAA . Of course, the number of nanowires in the GAA transistor is not limited, as long as the number of nanowires is greater than or equal to 1. Furthermore, two GAA transistors can have various connection relationships.

[0011] Please refer to Figure 4 which is illustrated as a schematic diagram of two GAA transistors. Compared with Figure 3A a single GAA transistor M GAA . In Figure 4In some embodiments, the gate structure further includes a gate dielectric layer 284. The nanowire 290 passes through the gate structure 220, the gate dielectric layer 284 surrounds a middle region of the nanowire 290, and the gate conductive layer 224 surrounds the gate dielectric layer 284. Further, the drain / source structure 292 electrically contacts a first end of the nanowire 290, and the drain / source structure 296 electrically contacts a second end of the nanowire 290. The drain / source structure 232 does not electrically contact the drain / source structure 292, and the drain / source structure 236 does not electrically contact the drain / source structure 296. Thus, two GAA transistors M GAA1 GAA2 may be formed. Each of the GAA transistors M GAA1 GAA2 includes two nanowires, and the two GAA transistors M GAA1 GAA2 share the gate conductive layer 224.

[0012] When changing the storage state, the storage cell of the prior art non-volatile memory needs to receive a high operation voltage. For example, when performing a programming operation on the storage cell, the storage cell receives a program voltage, such as a program voltage of 8V~12V, and a program current of about several hundred mA is generated.

[0013] Since the program voltage is greater than the supply voltage received by a general IC chip, such as a supply voltage of 1.2V. Therefore, a charge pump is usually designed in the non-volatile memory to boost the supply voltage to a higher operation voltage. It is well known that the charge pump occupies a very large layout area of the IC chip. SUMMARY

[0014] ​​​A storage element of a non-volatile memory includes: a first fin field effect transistor including a first fin, a gate structure, a first drain / source contact layer, and a second drain / source contact layer; wherein the gate structure includes a first gate dielectric layer, a first conductive layer, and a second conductive layer; wherein the first gate dielectric layer covers a middle region and two side surfaces of the first fin, the first conductive layer covers the first gate dielectric layer, the second conductive layer covers the first conductive layer, the first drain / source contact layer electrically contacts a first side region of the first fin, and the second drain / source contact layer electrically contacts a second side region of the first fin; a first wire located at a first side of the gate structure, and the first wire electrically connects to a first side of the second conductive layer; and a second wire located at a second side of the gate structure, and the second wire electrically connects to a second side of the second conductive layer; wherein during a program operation, the first wire receives a first voltage, and the second wire receives a second voltage; wherein a program current flows from the first wire to the second wire through the first conductive layer and the second conductive layer, and the first voltage is greater than the second voltage; wherein during a read operation, at least one of the first wire and the second wire receives a control voltage, the first drain / source contact layer receives a third voltage, the second drain / source contact layer receives a fourth voltage, and the third voltage is greater than the fourth voltage; wherein a first read current flows from the first drain / source contact layer to the second drain / source contact layer through a channel region of the first fin field effect transistor, and a storage state of the storage element is determined according to the first read current; wherein a difference between the first voltage and the second voltage is equal to a program voltage, and a difference between the third voltage and the fourth voltage is equal to a read voltage.

[0015] The present application relates to a memory element of a non-volatile memory, comprising: a first wrap-around gate transistor, comprising: a first nanowire, a gate structure, a first drain / source structure and a second drain / source structure, and the gate structure comprises: a first gate dielectric layer, a first conductive layer and a second conductive layer; wherein the first gate dielectric layer surrounds a middle region of the first nanowire, the first conductive layer surrounds the first gate dielectric layer, the second conductive layer surrounds the first conductive layer, the first drain / source structure electrically contacts a first side region of the first nanowire, and the second drain / source structure electrically contacts a second side region of the first nanowire; a first wire, located at a first side of the gate structure, and the first wire is electrically connected to a first side of the second conductive layer; and a second wire, located at a second side of the gate structure, and the second wire is electrically connected to a second side of the second conductive layer; wherein in a programming operation, the first wire receives a first voltage, and the second wire receives a second voltage; wherein a programming current flows from the first wire to the second wire through the first conductive layer and the second conductive layer, and the first voltage is different from the second voltage; wherein in a reading operation, at least one of the first wire and the second wire receives a control voltage, the first drain / source structure receives a third voltage, the second drain / source structure receives a fourth voltage, and the third voltage is greater than the fourth voltage; wherein a first reading current flows from the first drain / source structure to the second drain / source structure through a channel region of the first wrap-around gate transistor, and a storage state of the memory element is determined according to the first reading current; wherein the difference between the first voltage and the second voltage is equal to a programming voltage, and the difference between the third voltage and the fourth voltage is equal to a reading voltage.

[0016] For a better understanding of the above and other aspects of the present application, a preferred embodiment will be described in detail below with reference to the accompanying drawings: BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1A 、 Figure 1B And Figure 1C is a perspective view, a top view and a cross-sectional view along the AB dashed line of a FinFET transistor;

[0018] Figure 2 is a schematic diagram of two FinFET transistors;

[0019] Figure 3A 、 Figure 3B 、 Figure 3C And Figure 3D is a perspective view, a top view, a cross-sectional view along the ab dashed line and a cross-sectional view along the cd dashed line of a GAA transistor;

[0020] Figure 4Schematic diagram of two GAA transistors

[0021] Figure 5A Cross-sectional view of a gate structure of an enhanced electromigration memory element of the first embodiment of the present invention

[0022] Figure 5B Plan view of an enhanced electromigration memory element of the first embodiment of the present invention

[0023] Figure 6A Schematic diagram of a programming operation for the memory element of the first embodiment

[0024] Figure 6B And Figure 6C Schematic diagram of a read operation for the memory element of the first embodiment

[0025] Figure 7A Cross-sectional view of a gate structure of an enhanced electromigration memory element of the second embodiment of the present invention

[0026] Figure 7B Plan view of an enhanced electromigration memory element of the second embodiment of the present invention

[0027] Figure 8A Schematic diagram of a programming operation for the memory element of the second embodiment

[0028] Figure 8B And Figure 8C Schematic diagram of a read operation for the memory element of the second embodiment

[0029] Figure 9A Cross-sectional view of a gate structure of an enhanced electromigration memory element of the third embodiment of the present invention

[0030] Figure 9B Plan view of an enhanced electromigration memory element of the third embodiment of the present invention

[0031] Figure 10A Schematic diagram of a programming operation for the memory element of the first embodiment

[0032] Figure 10B And Figure 10C Schematic diagram of a read operation for the memory element of the third embodiment

[0033] Figure 11A Cross-sectional view of a gate structure of an enhanced electromigration memory element of the fourth embodiment of the present invention

[0034] Figure 11B Plan view of an enhanced electromigration memory element of the fourth embodiment of the present invention

[0035] Figure 12ASchematic diagram for programming operation of the storage element of the fourth embodiment;

[0036] Figure 12B With Figure 12C Schematic diagram for read operation of the storage element of the fourth embodiment;

[0037] Figure 13A Top view of the enhanced electromigration storage element of the fifth embodiment of the present application;

[0038] Figure 13B Top view of the enhanced electromigration storage element of the sixth embodiment of the present application;

[0039] Figure 13C Top view of the enhanced electromigration storage element of the seventh embodiment of the present application;

[0040] Figure 13D Top view of the enhanced electromigration storage element of the eighth embodiment of the present application; and

[0041] Figure 13E Top view of the enhanced electromigration storage element of the ninth embodiment of the present application.

[0042] Symbol explanation:

[0043] 110, 210, 510, 610, 705: insulating layer

[0044] 112, 114, 116, 118, 512, 612, 614: fin

[0045] 120, 224: gate conductive layer

[0046] 122, 124, 126, 128, 222, 284, 522, 622, 624, 722, 822, 824: gate dielectric layer

[0047] 130, 140, 156, 158, 562, 566, 662, 664, 666, 668: drain / source contact layer

[0048] 220: gate structure

[0049] 230, 290, 712, 812, 814: nanowire

[0050] 252, 246, 752, 762, 852, 862: spacer

[0051] 232, 236, 292, 296, 782, 792, 882, 884, 892, 894: drain / source structures

[0052] 500, 600, 700, 800, 900, 910, 920, 930, 940: memory elements

[0053] 532, 542, 542a, 542b, 542c, 542d, 632, 634, 642, 732, 742, 832, 834, 842: conductive layers

[0054] 545, 545a, 545b, 547, 547a, 547b, 547c, 546d, 561, 565, 645, 647, 661, 663, 665, 667, 747, 745, 781, 791, 845, 847, 881, 883, 891, 893: conductive lines

[0055] 912: heat dissipating metal layer

[0056] 922: heating layer DETAILED DESCRIPTION

[0057] Electromigration (EM) is a phenomenon in which the movement of electrons in an electrically conducting material transfers their kinetic energy to the metal ions of the conductor, causing the ions to move in the opposite direction of the electric field and gradually migrate, resulting in atomic diffusion and loss of the conductor. The present disclosure utilizes the mechanism of electromigration to design a memory element of a non-volatile memory cell. For example, the memory element can be a Fin Field Effect Transistor (FinFET) or a Gate-All-Around (GAA) transistor.

[0058] Basically, the threshold voltage of a FinFET and a GAA transistor is determined according to the material and thickness of a work function metal layer. The gate voltage received by the gate terminal of a FinFET and a GAA transistor is used to control the turn on and turn off of the FinFET and the GAA transistor. That is, one skilled in the art does not provide different voltages to the gate terminals of a FinFET and a GAA transistor at the same time.

[0059] The present application utilizes a FinFET transistor or a GAA transistor as a storage element in a memory cell. During a program operation, two different voltages are simultaneously applied to the gate terminals of the FinFET transistor or the GAA transistor. Furthermore, the threshold voltage of the FinFET transistor or the GAA transistor is changed by utilizing the mechanism of electromigration, so that the storage element can exhibit a programmed state or an unprogrammed state. During a read operation, the same voltage is applied to the gate terminals of the FinFET transistor or the GAA transistor, and the storage state of the storage element is determined according to the read current generated by the FinFET transistor or the GAA transistor.

[0060] Please refer to Figure 5A , which is a cross-sectional view of a gate structure of an enhanced electromigration storage element according to a first embodiment of the present application. Figure 5B is a top view of an enhanced electromigration storage element according to the first embodiment of the present application. Furthermore, the enhanced electromigration storage element 500 will be simply referred to as the storage element 500 hereinafter, and the storage element 500 is designed in a memory cell of a non-volatile memory.

[0061] The storage element 500 of the first embodiment includes a FinFET transistor M FIN with wires 545, 547. The FinFET transistor M FIN is located above a semiconductor substrate sub and an insulating layer 510. The FinFET transistor M FIN of the first embodiment is similar to Figure 1C the FinFET transistor M FIN , but only has one fin 512. Of course, the fins 512 of the FinFET transistor M FIN inside the storage element 500 are not limited to only one. The FinFET transistor M FIN includes the fin 512, a gate structure, and two drain / source contact layers 562, 566. The gate structure includes a gate dielectric layer 522 and two conductive layers 532, 542. The gate dielectric layer 522 covers the middle region and the two side surfaces of the fin 512, the conductive layer 532 covers the gate dielectric layer 512, and the conductive layer 542 covers the conductive layer 532. That is, the gate conductive layers of the FinFET transistor M FIN are composed of the conductive layers 532, 542. Among them, the conductive layer 532 is a work function metal layer. For example, the material of the conductive layer 532 is titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl). In addition, the material of the conductive layer 542 can also be the same as that of the conductive layer 532.

[0062] Furthermore, a conducting line 545 is formed over the first side of the gate structure, and the conducting line 545 is electrically connected to the first side of the conductive layer 542. A conducting line 547 is formed over the second side of the gate structure, and the conducting line 547 is electrically connected to the second side of the conductive layer 542. Basically, a contact hole can be formed over both sides of the conductive layer 542, and the conducting lines 545, 547 can be formed by filling the contact hole with metal. Similarly, a conducting line 561 can be additionally formed to be electrically connected to the drain / source contact layer 562, and a conducting line 565 can be additionally formed to be electrically connected to the drain / source contact layer 566.

[0063] The present application utilizes the mechanism of electromigration to perform a programming operation. During the programming operation, different voltages are provided to the two conducting lines 545, 547. Thus, a programming current flows between the two conducting lines 545, 547. Since the electrons in the programming current flow through the conductive layers 542, 532, the conductive layer 532 gradually migrates against the electric field, causing the thickness of the conductive layer 532 to change. That is, the present application utilizes the mechanism of electromigration to cause the thickness of the functional metal layer to change, thereby changing the threshold voltage of the FinFET transistor M FIN .

[0064] In addition, during the programming operation, the two drain / source contact layers 562, 566 of the FinFET transistor M FIN may not be provided with any bias. That is, during the programming operation, the two conducting lines 561, 565 can be floating.

[0065] Please refer to Figure 6A , which shows a schematic diagram of performing a programming operation on the storage element of the first embodiment. Before the programming operation is performed, the storage element 500 is in an unprogrammed state. When the programming operation is performed on the storage element 500, different voltages are provided to the two conducting lines 545, 547. For example, a programming voltage V PGM is provided to the conducting line 545, and a ground voltage (GND) is provided to the conducting line 547, so that the voltage difference between the two conducting lines 545, 547 is the programming voltage V PGM . At this time, the conducting line 545 can be regarded as an anode, and the conducting line 547 can be regarded as a cathode, so that a programming current I PGM flows through the conductive layers 532, 542.

[0066] As shown in Figure 6A , the programming current I PGMcurrent flows from the conductive layer 532, 542 to the conductive line 547. Generally, the electromigration starts at the cathode, i.e., the conductive line 547. Due to the mechanism of electromigration, the metal ions in the conductive layer 532, 542 near the cathode migrate against the electric field, i.e., to the right. Thus, after the programming action, the thickness of the conductive layer 532 shown by the left slant line becomes thinner, causing the threshold voltage of the FinFET transistor M FIN to change, and the storage state of the storage element 500 becomes a programmed state. For example, before the programming action, the threshold voltage of the FinFET transistor M FIN is 0.5 V. After the programming action, the threshold voltage of the FinFET transistor M FIN changes to 0.3 V.

[0067] According to the first embodiment of the present application, when the programming current I PGM is about 100 μA or more, the threshold voltage of the FinFET transistor M FIN may change about 0.2-0.3 V. Since the resistance value of the conductive layer 532, 542 is very low, the programming voltage V PGM is very low. For example, a programming voltage V PGM of about 1.5-2.5 V can perform the programming action. Compared with the programming action of the prior art non-volatile memory which needs a high programming voltage (e.g., 8-12 V), the storage element 500 of the present application has the advantages of low programming voltage and low programming current. That is, the non-volatile memory composed of the storage element 500 of the present application can perform the programming action without a too high programming voltage V PGM . Furthermore, since the non-volatile memory does not need to design a charge pump to provide a high programming voltage V PGM , the layout area of the whole non-volatile memory can be greatly reduced.

[0068] Please refer to Figure 6B and Figure 6C which show the schematic diagrams of the read action of the storage element of the first embodiment. For example, Figure 6B the storage element 500 of the FinFET transistor M FIN has a threshold voltage of 0.5 V. Figure 6C the storage element 500 of the FinFET transistor M FIN has a threshold voltage of 0.3 V.

[0069] When the read action is performed on the storage element 500, the same control voltage V CTRLto the two wires 545, 547, so no current flows between the two wires 545, 547. In addition, a different voltage is provided to the two wires 561, 565. For example, a read voltage V RD is provided to the wire 561, and a ground voltage (GND) is provided to the wire 565, so that the voltage difference between the two wires 561, 565 is the read voltage V RD . For example, the read voltage V RD is 1.0 V.

[0070] According to a first embodiment of the present application, during a read operation, a control voltage V CTRL of 0.4 V is provided to the two wires 545, 547, so no current flows between the two wires 545, 547. As shown in FIG. 5B, because the control voltage V Figure 6B is less than the threshold voltage (0.5 V) of the FinFET transistor M FIN , the FinFET transistor M FIN is turned off, and the read current I RD between the two wires 561, 565 is very small, almost zero. In addition, as shown in FIG. 5C, because the control voltage V CTRL is greater than the threshold voltage (0.3 V) of the FinFET transistor M FIN , the FinFET transistor M FIN is turned on. Therefore, the FinFET transistor M FIN produces a large read current I RD , and the read current I RD flows from the wire 561, through the drain / source contact layer 562, the channel region of the FinFET transistor M FIN , the drain / source contact layer 566, to the wire 565. Of course, in other embodiments, during a read operation, the control voltage V CTRL may be provided to one of the two wires 545, 547, and the other one of the two wires 545, 547 is floating.

[0071] Furthermore, the storage state of the storage element can be determined by using a sensing circuit. For example, a current comparator (not shown) is designed in the non-volatile memory as the sensing circuit. A first input terminal of the current comparator receives the read current I RD , a second input terminal of the current comparator receives a reference current I REF , and an output terminal of the current comparator generates an output signal. When the read current I RD is greater than the reference current I REF , the current comparator outputs a first logic level output signal, which represents that the storage element 500 is in a programmed state. Conversely, when the read current I RD is less than the reference current I REF , the current comparator outputs a second logic level output signal, which represents that the storage element 500 is in an erased state.RD less than the reference current I REF , the current comparator outputs an output signal of the second logic level, indicating that the storage element 500 is in the unprogrammed state. That is, Figure 6B the FinFET transistor M FIN generates a very small (close to zero) read current I RD , so the storage element 500 is determined to be in the unprogrammed state. On the other hand, Figure 6C the FinFET transistor M FIN generates a relatively large read current I RD , so the storage element 500 is determined to be in the programmed state.

[0072] Of course, in other embodiments, a reference memory cell including a reference storage element similar to the storage element 500 can also be designed in the nonvolatile memory. Figure 5A The reference storage element can be in the unprogrammed state or the programmed state. During the read operation, the reference storage element receives the control voltage V CTRL and the read voltage V RD , and outputs a reference current I REF .

[0073] Furthermore, the sensing circuit in the nonvolatile memory receives the read current I RD and the reference current I REF , and determines the storage state of the storage element according to the difference between the read current I RD and the reference current I REF .

[0074] For example, the reference storage element is in the unprogrammed state. Therefore, when the difference between the read current I RD and the reference current I REF is less than a certain value, the storage element is determined to be in the unprogrammed state. On the other hand, when the difference between the read current I RD and the reference current I REF is greater than the certain value, the storage element is determined to be in the programmed state.

[0075] Alternatively, the reference storage element is in the programmed state. Therefore, when the difference between the read current I RD and the reference current I REF is less than a certain value, the storage element is determined to be in the programmed state. On the other hand, when the difference between the read current I RD and the reference current I REF is greater than the certain value, the storage element is determined to be in the unprogrammed state.

[0076] Please refer to Figure 7AThe diagram shown is a cross-sectional view of the gate structure of an enhanced electromigration memory element according to a second embodiment of the present invention. Figure 7B This is a top view of an enhanced electromigration memory element according to a second embodiment of the present invention. The memory element 600 includes two FinFET transistors M. FINA M FINB Furthermore, the storage element 600 is designed in a differential memory cell of a non-volatile memory.

[0077] The storage element 600 in the second embodiment includes a FinFET transistor M. FINA FinFET transistor M FINB With wires 645 and 647. FinFET transistor M FINA M FINB Located above the semiconductor substrate sub and the insulating layer 610. FinFET transistor M FINA M FINB The structure is similar to Figure 2 FinFET transistor M FIN1 M FIN2 The structure, but FinFET transistor M FINA M FINB Each has only one fin, 612, and 614. Of course, the storage element 600 contains an internal FinFET transistor M. FINA M FINB Fins 612 and 614 are not limited to having only one. FinFET transistor M FINA Includes: fin 612, gate structure, and two drain / source contact layers 662 and 666. FinFET transistor M FINB It includes: a fin 614, a gate structure, and two drain / source contact layers 664 and 668. The gate structure includes: gate dielectric layers 622 and 624, and conductive layers 632, 634, and 642. Gate dielectric layer 622 covers the middle region of fin 612 and its two side surfaces; gate dielectric layer 624 covers the middle region of fin 614 and its two side surfaces; conductive layer 632 covers gate dielectric layer 622; conductive layer 634 covers gate dielectric layer 624; and conductive layer 642 covers conductive layers 632 and 634. In other words, the FinFET transistor M... FINA M FINB The gate conductive layer is composed of conductive layers 632, 634, and 642, and the two FinFET transistors M FINA M FINBThe conductive layer 642 is shared. The conductive layers 632, 634 are work function metal layers. For example, the materials of the conductive layers 632, 634 are titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl). In addition, the material of the conductive layer 642 can also be the same as the conductive layers 632, 634.

[0078] Furthermore, a wire 645 is formed above the first side of the gate structure, and the wire 645 is electrically connected to the first side of the conductive layer 642. A wire 647 is formed above the second side of the gate structure, and the wire 647 is electrically connected to the second side of the conductive layer 642. Similarly, a wire 661 can also be additionally formed to be electrically connected to the drain / source contact layer 662, a wire 665 is formed to be electrically connected to the drain / source contact layer 666, a wire 663 is formed to be electrically connected to the drain / source contact layer 664, and a wire 667 is formed to be electrically connected to the drain / source contact layer 668.

[0079] The present application utilizes the mechanism of electromigration to perform a programming action. During the programming action, different voltages are provided to the two wires 645, 647, so that a programming current is generated between the two wires 645, 647. Since the electrons in the programming current flow through the conductive layers 632, 634, 642, the conductive layer 632 gradually migrates in the opposite direction of the electric field, causing the thickness of the conductive layer 632 to change. That is, the present application utilizes the mechanism of electromigration to cause the thickness of the work function metal layer to change, thereby changing the threshold voltage of the FinFET transistor M FINA .

[0080] In addition, during the programming action, the two drain / source contact layers 662, 666 of the FinFET transistor M FINA and the two drain / source contact layers 664, 668 of the FinFET transistor M FINB do not need to be provided with any bias. That is, the wires 661, 665, 663, 667 can be floating.

[0081] Please refer to Figure 8A , which shows a schematic diagram of performing a programming action on the storage element of the second embodiment. Before the programming action is performed, the storage element 600 is in an unprogrammed state. When the programming action is performed on the storage element 600, different voltages are provided to the two wires 645, 647. For example, a programming voltage V PGM is provided to the wire 645, and a ground voltage (GND) is provided to the wire 647, so that the voltage difference between the two wires 645, 647 is the programming voltage V PGM . That is, the wire 645 can be regarded as an anode, and the wire 647 can be regarded as a cathode, so that a programming current I PGM flows through the conductive layers 632, 634, 642.

[0082] like Figure 8A As shown, the programming current I is represented by the dashed line. PGM The current flows from wire 645 through conductive layers 632, 634, and 642 to wire 647. Generally, electromigration begins at the cathode (i.e., wire 647). Due to the mechanism of electromigration, metal ions in conductive layers 632 and 642 near the cathode migrate in the opposite direction of the electric field (i.e., to the right). Therefore, after programming, the thickness of conductive layer 632 (shown by the diagonal line on the left) thins, causing the FinFET transistor M... FINA The threshold voltage changes, and the storage state of storage element 600 becomes the programming state. For example, before the programming operation, the FinFET transistor M... FINA M FINB The threshold voltage for all is 0.5V. After programming, the FinFET transistor M... FINA The threshold voltage is changed to 0.3V, and the FinFET transistor M... FINB The threshold voltage is maintained at 0.5V. Of course, in other embodiments, after the programming operation is completed, the thickness of the conductive layer 634 on the left and right sides may also increase, making the FinFET transistor M... FINB The threshold voltage changes and is greater than 0.5V.

[0083] According to a second embodiment of the present invention, when the programming current I PGM When the current is above approximately 100 μA, the FinFET transistor M FINA The threshold voltage can be changed by approximately 0.2~0.3V. Because the resistance of conductive layers 632, 634, and 642 is very low, the programming voltage V... PGM Very low. For example, a programming voltage of approximately 1.5V to 2.5V. PGM Programming can then be performed. Compared to existing non-volatile memories that require higher programming voltages (e.g., 8V~12V), the storage element 600 of this invention has the advantages of low programming voltage and low programming current. In other words, the non-volatile memory composed using the storage element 600 of this invention does not require a very high programming voltage V. PGM Programming can then be completed. Furthermore, since non-volatile memory does not require a high programming voltage V... PGM By designing a charge pump, the overall layout area of ​​the non-volatile memory can be significantly reduced.

[0084] Please refer to Figure 8B and Figure 8C The diagram illustrates a reading operation of the storage element in the second embodiment. For example, Figure 8B The memory element 600 is in an unprogrammed state, and the FinFET transistor M...FINA M FINB The threshold voltage is 0.5V. Figure 8C The memory element 600 is in a programmed state, and the FinFET transistor M... FINA The threshold voltage is 0.3V, FinFET transistor M FINB The threshold voltage is 0.5V.

[0085] When performing a read operation on storage element 600, the same control voltage V is provided. CTRL The current flows through two wires 645 and 647, so no current is generated between wires 645 and 647. Additionally, different voltages are supplied to two wires 661 and 665, and different voltages are supplied to two wires 663 and 667. For example, a reading voltage V is provided. RD Ground voltage (GND) is provided to conductors 661 and 663, and to conductors 665 and 667. Therefore, the voltage difference between the two conductors 661 and 665 is the read voltage V. RD The voltage difference between the two wires 663 and 667 is the reading voltage V. RD For example, reading voltage V RD The voltage is 1.0V. In other embodiments, during the read operation, at least one of the two wires 645 and 647 can also receive the control voltage V. CTRL That's all.

[0086] According to a second embodiment of the present invention, during the reading operation, the control voltage is set to V. CTRL The voltage is 0.4V, supplied to two wires 645 and 647, so no current is generated between wires 645 and 647. For example... Figure 8B As shown, due to the control voltage V CTRL Smaller than FinFET transistor M FINA M FINB The threshold voltage (0.5V) of the FinFET transistor M is so high that... FINA M FINB Turn off, read the current I between the two wires 661 and 665. RDA The reading current I between the two wires 663 and 667 is very small, almost zero. RDB Very small, almost zero. Additionally, such as... Figure 8C As shown, due to the control voltage V CTRL Larger than FinFET transistor M FINA The threshold voltage (0.3V), control voltage V CTRL Smaller than FinFET transistor M FINB The threshold voltage (0.5V) of the FinFET transistor M is so high that... FINAturn on, FinFET transistor M FINB turn off. Thus, FinFET transistor M FINA generates a large read current I RDA flowing from wire 661 through drain / source contact layer 662, channel region of FinFET transistor M FINA , drain / source contact layer 666 to wire 665. In addition, FinFET transistor M FINB turn off, the read current I RDB between wire 663 and wire 667 is very small, almost zero.

[0087] Furthermore, the sensing circuit in the non-volatile memory can receive two read currents I RDA and I RDB and determine the storage state of the storage element according to the difference between the two read currents I RDA and I RDB . For example, when the difference between the two read currents I RDA and I RDB is less than a certain value, the storage element is determined to be in an unprogrammed state. When the difference between the two read currents I RDA and I RDB is greater than a certain value, the storage element is determined to be in a programmed state. That is, Figure 8B FinFET transistor M FINA M FINB generates a very small (close to zero) read current I RDA , I RDB , so the storage element 600 is determined to be in an unprogrammed state. Whereas Figure 8C FinFET transistor M FINA generates a large read current I RDA , FinFET transistor M FINB generates a very small (close to zero) read current I RDB , so the storage element 600 is determined to be in a programmed state.

[0088] Please refer to Figure 9A , which shows a cross-sectional view of a gate structure of an enhanced electromigration storage element of a third embodiment of the present application. Figure 9B is a top view of an enhanced electromigration storage element of a third embodiment of the present application. The enhanced electromigration storage element 700 is hereinafter referred to as storage element 700, and the storage element 700 is designed in a storage cell of a non-volatile memory.

[0089] The storage element 700 in the third embodiment includes a GAA transistor M. GAA With two wires 745 and 747. GAA transistor M GAA Located above the semiconductor substrate sub and the insulating layer 705, the GAA transistor M GAA The structure is similar to Figure 3C GAA transistor M GAA1 GAA transistor M GAA There is only one nanowire 712. Of course, the memory element 700 contains an internal GAA transistor M. GAA The nanowire is not limited to a single one. GAA transistor M GAA This includes: two drain / source structures 782 and 792, a gate structure, and a nanowire 712. Furthermore, the GAA transistor M... GAA The gate structure includes: spacers 752 and 762, a gate dielectric layer 722, and conductive layers 732 and 742. The gate dielectric layer 722 surrounds the central region of the nanowire 712, the conductive layer 732 surrounds the gate dielectric layer 722, and the conductive layer 742 surrounds the conductive layer 732. In other words, the GAA transistor M... GAA The gate conductive layer is composed of conductive layers 732 and 742. Conductive layer 732 is a work function metal layer. For example, the material of conductive layer 732 is titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl). Alternatively, the material of conductive layer 742 can be the same as conductive layer 732.

[0090] Furthermore, a wire 745 is formed above the first side of the gate structure and is electrically connected to the first side of the conductive layer 742. A wire 747 is formed above the second side of the gate structure and is electrically connected to the second side of the conductive layer 742. Similarly, a wire 781 may also be formed to electrically connect to the drain / source structure 782, and a wire 791 may be formed to electrically connect to the drain / source contact layer 792.

[0091] This invention utilizes electromigration to perform programming. During programming, different voltages are applied to two wires 745 and 747, generating a programming current between them. Because electrons in this programming current flow through conductive layers 742 and 732, conductive layer 732 gradually migrates in the opposite direction of the electric field, causing a change in its thickness. In other words, this invention uses electromigration to create a change in the thickness of the functional metal layer, thereby altering the thickness of the GAA transistor M. GAA The critical voltage limit.

[0092] Additionally, during programming, the GAA transistor M... GAAThe two drain / source structures 782 and 792 do not require any bias voltage. In other words, when programming, the wires 781 and 791 can be floated.

[0093] Please refer to Figure 10A The diagram illustrates the programming operation of the storage element in the first embodiment. Before programming, the storage element 700 is in an unprogrammed state. When programming the storage element 700, different voltages are supplied to two wires 745 and 747. For example, a programming voltage V is provided. PGM A ground voltage (GND) is provided to conductor 745, and a ground voltage (GND) is provided to conductor 747. This ensures that the voltage difference between the two conductors 745 is the programmed voltage V. PGM In other words, wire 745 can be considered as the anode, and wire 747 can be considered as the cathode, so that the programming current I... PGM It flows through conductive layers 732 and 742.

[0094] like Figure 10A As shown, the programming current I is represented by the dashed line. PGM The current flows from wire 745 through conductive layers 732 and 742 to wire 747. Generally, electromigration begins at the cathode (i.e., wire 747). Due to the mechanism of electromigration, metal ions in the conductive layers 732 and 742 near the cathode migrate in the opposite direction of the electric field (i.e., to the right). Therefore, after the programming operation, the thickness of conductive layer 732 (shown by the diagonal line on the left) thins, causing the GAA transistor M... GAA The threshold voltage changes, and the storage state of storage element 700 becomes the programming state. For example, before the programming operation, GAA transistor M... GAA The threshold voltage is 0.5V. After programming, the GAA transistor M... GAA The threshold voltage is changed to 0.3V. In other embodiments, the thickness of the right side of the conductive layer 732 may also increase after the programming operation.

[0095] According to a third embodiment of the present invention, when the programming current I PGM When the current is above approximately 100μA, the GAA transistor M GAA The threshold voltage can be changed by approximately 0.2~0.3V. Because the resistance of conductive layers 732 and 742 is very low, the programming voltage V... PGM Very low. For example, a programming voltage of approximately 1.5V to 2.5V. PGMThe programming operation can be performed. Compared with the programming operation of the conventional nonvolatile memory which requires a high programming voltage (e.g., 8V ~ 12V), the storage element 700 has the advantages of low programming voltage and low programming current. That is, the nonvolatile memory composed of the storage element 700 of the present application does not need a high programming voltage V PGM The programming operation can be performed. Furthermore, since the nonvolatile memory does not need a charge pump for providing a high programming voltage V PGM , the layout area of the entire nonvolatile memory can be greatly reduced.

[0096] Please refer to Figure 10B and Figure 10C which show a schematic diagram of the read operation of the storage element of the third embodiment. For example, Figure 10B The storage element 700 of GAA has a threshold voltage of 0.5V. Figure 10C The storage element 700 of GAA has a threshold voltage of 0.3V.

[0097] During the read operation of the storage element 700, the same control voltage V CTRL is provided to the two wires 745, 747, and no current will flow between the two wires 745, 747. Furthermore, different voltages are provided to the two wires 781, 791. For example, a read voltage V RD is provided to the wire 781, and a ground voltage (GND) is provided to the wire 791. Thus, the voltage difference between the two wires 781, 791 is the read voltage V RD . For example, the read voltage V RD is 1.0V. In other embodiments, at least one of the two wires 745, 747 can receive the control voltage V CTRL during the read operation.

[0098] According to the third embodiment of the present application, the control voltage V CTRL is set to 0.4V and provided to the two wires 745, 747, and no current will flow between the two wires 745, 747. As shown in Figure 10B , since the control voltage V CTRL is less than the threshold voltage (0.5V) of the GAA transistor M GAA , the GAA transistor M GAA is turned off, and the read current I RD between the two wires 781, 791 is very small and almost zero. In addition, as shown in Figure 10C , since the control voltage VCTRL Larger than GAA transistor M GAA The threshold voltage (0.3V) of the GAA transistor M is so that... GAA Turn on. Therefore, GAA transistor M GAA Generates a large read current I RD The wire 781 passes through the drain / source structure 782 and the GAA transistor M. GAA The channel region, drain / source connection 792, flows to wire 791. Similarly, the storage state of storage element 700 can be determined by the read current I. RD The size determines this.

[0099] Please refer to Figure 11A The diagram shown is a cross-sectional view of the gate structure of an enhanced electromigration memory element according to a fourth embodiment of the present invention. Figure 11B This is a top view of an enhanced electromigration memory element according to a fourth embodiment of the present invention. The memory element 800 includes two GAA transistors M. GAAA M GAAB Furthermore, the storage element 800 is designed within the differential storage cell of the non-volatile memory.

[0100] The storage element 800 of the fourth embodiment includes a GAA transistor M. GAAA GAA transistor M GAAB With two wires, 845 and 847. GAA transistor M GAAA M GAAB Located above the semiconductor substrate sub and the insulating layer 805. GAA transistor M GAAA M GAAB The structure is similar to Figure 4 GAA transistor M GAA1 M GAA2 The structure of the GAA transistor M. GAAA M GAAB Each contains only one nanowire, 812 or 814. Of course, the memory element 800 contains a GAA transistor M. GAAA M GAAB The nanowire is not limited to a single one. GAA transistor M GAAA Includes: two drain / source structures 882 and 892, a gate structure, and a nanowire 812. GAA transistor M GAAA The gate structure includes: spacers 852 and 862, a gate dielectric layer 822, and conductive layers 832 and 842. GAA transistor M GAAB Includes: two drain / source structures 884 and 894, a gate structure, and a nanowire 814. GAA transistor M GAABThe gate structure of the GAA transistor M GAAA includes the spacer 852, 862, the gate dielectric layer 824, and the conductive layer 834, 842. The gate dielectric layer 822 surrounds the middle region of the nanowire 812, the gate dielectric layer 824 surrounds the middle region of the nanowire 814, the conductive layer 832 surrounds the gate dielectric layer 822, the conductive layer 834 surrounds the gate dielectric layer 824, and the conductive layer 842 surrounds the conductive layer 832, 834. That is, the GAA transistor M GAAB includes the gate dielectric layer 822, 824, and the conductive layer 832, 834, 842. GAAA The gate conductive layer of the GAA transistor M GAAB includes the conductive layer 832, 834, 842. The conductive layer 832, 834 is a work function metal layer. For example, the material of the conductive layer 832, 834 is titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl). In addition, the material of the conductive layer 842 can also be the same as the conductive layer 632, 634.

[0101] Furthermore, the conductive line 845 is formed above the first side of the gate structure, and the conductive line 845 is electrically connected to the first side of the conductive layer 842. The conductive line 847 is formed above the second side of the gate structure, and the conductive line 847 is electrically connected to the second side of the conductive layer 842. Similarly, the conductive line 881 can also be formed to be electrically connected to the drain / source structure 882, the conductive line 891 can be formed to be electrically connected to the drain / source structure 892, the conductive line 883 can be formed to be electrically connected to the drain / source structure 884, and the conductive line 893 can be formed to be electrically connected to the drain / source structure 894.

[0102] The present application utilizes the mechanism of electromigration to perform the programming action. During the programming action, different voltages are provided to the two conductive lines 845, 847, so that a programming current is generated between the two conductive lines 845, 847. Since the electrons in the programming current flow through the conductive layer 832, 834, 842, the conductive layer 832 gradually migrates in the opposite direction of the electric field, causing the thickness of the conductive layer 832 to change. That is, the present application utilizes the mechanism of electromigration to cause the thickness of the work function metal layer to change, thereby changing the threshold voltage of the GAA transistor M GAAA .

[0103] In addition, during the programming action, the two drain / source structures 882, 892 of the GAA transistor M GAAA and the two drain / source structures 884, 894 of the GAA transistor M GAAB do not need to be provided with any bias. That is, during the programming action, the conductive lines 881, 883, 891, 893 can be floating.

[0104] Please refer to Figure 12AThe diagram illustrates the programming operation of a storage element according to the fourth embodiment. Before programming, the storage element 800 is in an unprogrammed state. When programming the storage element 800, different voltages are supplied to two wires 845 and 847. For example, a programming voltage V is provided. PGM A ground voltage (GND) is provided to conductor 845 and to conductor 847, such that the voltage difference between the two conductors 845 and 847 is the programmed voltage V. PGM In other words, wire 845 can be considered as the anode, and wire 847 can be considered as the cathode, so that the programming current I... PGM It flows through conductive layers 832, 834, and 842.

[0105] like Figure 12A As shown, the programming current I is represented by the dashed line. PGM The current flows from wire 845 through conductive layers 832, 834, and 842 to wire 847. Generally, electromigration begins at the cathode (i.e., wire 847). Due to the mechanism of electromigration, metal ions in conductive layers 832 and 842 near the cathode migrate in the opposite direction of the electric field (i.e., to the right). Therefore, after programming, the thickness of conductive layer 832 (shown by the diagonal line on the left) thins, causing the GAA transistor M... GAAA The threshold voltage changes, and the storage state of storage element 800 becomes the programming state. For example, before the programming operation, GAA transistor M... GAAA M GAAB The threshold voltage for all transistors is 0.5V. After programming, the GAA transistor M... GAAA The threshold voltage changes to 0.3V, GAA transistor M GAAB The threshold voltage is maintained at 0.5V. Of course, in other embodiments, after the programming operation is completed, the thickness of the conductive layer 834 on the left and right sides may also increase, making the GAA transistor M... GAAB The threshold voltage changes and is greater than 0.5V.

[0106] According to a fourth embodiment of the present invention, when the programming current I PGM When the current is above approximately 100μA, the GAA transistor M GAAA The threshold voltage can be changed by approximately 0.2~0.3V. Because the resistance of the conductive layers 832, 834, and 842 is very low, the programming voltage V... PGM Very low. For example, a programming voltage of approximately 1.5V to 2.5V. PGMThe programming operation can be performed. Compared with the programming operation of the conventional nonvolatile memory which requires a high programming voltage (e.g., 8V ~ 12V), the storage element 800 has the advantages of low programming voltage and low programming current. That is, the nonvolatile memory composed of the storage element 800 of the present application does not require a high programming voltage V PGM The programming operation can be performed. Furthermore, since the nonvolatile memory does not require a charge pump for providing a high programming voltage V PGM , the layout area of the entire nonvolatile memory can be greatly reduced.

[0107] Please refer to Figure 12B and Figure 12C which are shown as a schematic diagram of the read operation of the storage element of the fourth embodiment. For example, Figure 12B The storage element 800 of GAAA , M GAAB has a threshold voltage of 0.5V. Figure 12C The storage element 800 of GAAA has a threshold voltage of 0.3V, and the GAA transistor M GAAB has a threshold voltage of 0.5V.

[0108] When the read operation is performed on the storage element 800, the same control voltage V CTRL is provided to the two conductive lines 845, 847, or the control voltage V CTRL is provided to one of the two conductive lines 845, 847. Furthermore, different voltages are provided to the two lines 881, 891, and different voltages are provided to the two conductive lines 883, 893. For example, a read voltage V RD is provided to the conductive lines 881, 883, and a ground voltage (GND) is provided to the conductive lines 891, 893. Thus, the voltage difference between the two conductive lines 881, 891 is the read voltage V RD , and the voltage difference between the two conductive lines 883, 893 is the read voltage V RD . For example, the read voltage V RD is 1.0V.

[0109] According to the fourth embodiment of the present application, the control voltage V CTRL is set to 0.4V and provided to the two conductive lines 845, 847 during the read operation. As shown in Figure 12B , since the control voltage V CTRL is less than the threshold voltage (0.5V) of the GAA transistors M GAAA , M GAAB , the GAA transistors M GAAA , MGAAB Turn off, read the current I between the two wires 881 and 891. RDA The reading current I between the two wires 883 and 893 is very small, almost zero. RDB Very small, almost zero. Additionally, such as... Figure 12C As shown, due to the control voltage V CTRL Larger than GAA transistor M GAAA The threshold voltage (0.3V), control voltage V CTRL Smaller than GAA transistor M GAAB The threshold voltage (0.5V) of the GAA transistor M is so that... GAAA Turn on, GAA transistor M GAAB Therefore, GAA transistor M is turned off. GAAA Generates a large read current I RDA The wire 881 passes through the drain / source structure 882 and the GAA transistor M. GAAA The channel region, drain / source structure 892, flows to wire 891. Additionally, GAA transistor M... GAAB Turn off, read the current I between the two wires 883 and 893. RDB It is very small, almost zero. Similarly, the storage state of storage element 800 can be determined by the read current I. RDA I RDB The size determines this.

[0110] Furthermore, the present invention can also modify the structures of storage elements 500, 600, 700, and 800 in the first to fourth embodiments to enhance the electromigration effect, resulting in a greater difference in the threshold voltage of the transistors before and after the programming operation. The modified structure of storage element 500 in the first embodiment is described below. Moreover, the modification method of storage element 500 in the first embodiment can also be applied to storage elements 600, 700, and 800 in the second to fourth embodiments.

[0111] Please refer to Figure 13A The diagram shown is a top view of an enhanced electromigration memory element according to a fifth embodiment of the present invention. Compared to the memory element 500 of the first embodiment, in the memory element 900 of the fifth embodiment, the cross-sectional areas of the contact holes connected to the first and second sides of the conductive layer 542 are different. That is, the cross-sectional area of ​​the contact hole serving as the anode is larger than the cross-sectional area of ​​the contact hole serving as the cathode. For example, assuming that the cross-sectional area of ​​each contact hole is the same, the number of wires designed for the anode is greater than the number of wires designed for the cathode.

[0112] like Figure 13AAs shown, two wires 545a, 545b are electrically connected to the first side of the conductive layer 542, and during a programming operation, the two wires 545a, 545b act as an anode and receive a programming voltage V PGM . Further, a single wire 547 is electrically connected to the second side of the conductive layer 542, and during a programming operation, the wire 547 acts as a cathode and receives a ground voltage (GND). Thus, during a programming operation, the total programming current input from the anode is concentrated at the cathode, causing electromigration to occur more easily, such that the threshold voltage difference of the FinFET transistor M FIN before and after a programming operation is larger. Of course, during a read operation, all of the wires 545a, 545b, 547 connected to the conductive layer 542 receive the same control voltage V CTRL .

[0113] Similarly, the modifications of the fifth embodiment memory element 900 can also be applied to the memory elements 600, 700, 800 of the second through fourth embodiments.

[0114] Please refer to Figure 13B , which illustrates a top view of an enhanced electromigration memory element of the sixth embodiment of the present application. Compared to the memory element 500 of the first embodiment, in the memory element 910 of the sixth embodiment, a heat dissipation metal layer 912 is formed above the first side of the conductive layer 542, and the heat dissipation metal layer 912 contacts the conductive layer 542. In other embodiments, the heat dissipation metal layer 912 can be a metal or an alloy to strengthen the grain bondary.

[0115] When the memory element 910 performs a programming operation, a programming current I PGM flows through the conductive layer 542, 532, causing the FinFET transistor M FIN to generate heat. Since the heat dissipation metal layer 912 is located above the first side of the conductive layer 542, the heat energy of the first side of the conductive layer 542 can be dissipated more quickly, increasing the heat gradient and thermal stress between the first and second sides of the conductive layer 542, and enhancing the EM efficiency, such that the threshold voltage difference of the FinFET transistor M FIN before and after a programming operation is larger.

[0116] Similarly, the modifications of the sixth embodiment memory element 910 can also be applied to the memory elements 600, 700, 800 of the second through fourth embodiments.

[0117] Referring to Figure 13C , a top view of an enhanced electromigration memory element of a seventh embodiment of the present application is shown. Compared to the memory element 500 of the first embodiment, in the memory element 920 of the seventh embodiment, a heating layer 922 is formed above the second side of the conductive layer 542, and the heating layer 922 does not contact the conductive layer 542. For example, the heating layer 922 is a resistive layer. Basically, the heating layer 922 is closer to the lower metal layer of the substrate used for the connection (i.e. interconnection) between the transistors and other elements in the electronic circuit layout. For example, the heating layer 922 can be the first metal layer or the second metal layer above the memory element 920.

[0118] When the memory element 910 performs a programming action, a programming current I PGM flows through the conductive layer 542, the conductive layer 532, and the heating layer 922, so that the FinFET transistor M FIN generates heat. Since the heating layer 922 is located at the second side of the conductive layer 542, the temperature of the second side of the conductive layer 542 is increased, the thermal gradient and the thermal stress between the first side and the second side of the conductive layer 542 are increased, so as to enhance the EM efficiency, and the difference of the threshold voltage of the FinFET transistor M FIN before and after the programming action is larger.

[0119] Similarly, the modification of the memory element 920 of the seventh embodiment can also be applied to the memory elements 600, 700, 800 of the second to fourth embodiments.

[0120] Referring to Figure 13D , a top view of an enhanced electromigration memory element of an eighth embodiment of the present application is shown. Compared to the memory element 500 of the first embodiment, in the memory element 930 of the eighth embodiment, the gate structure is an L-shaped gate structure, including a main branch and a sub-branch. The main branch covers the fin 512. The sub-branch extends from a first side of the main branch, and the sub-branch can be parallel to the fin 512, and the main branch and the sub-branch form a bend. Further, the conductive layer 542a of the sub-branch is electrically connected to the conductive layer 547a of the main branch. The conductive layer 542a of the main branch second side is electrically connected to the conductive layer 545.

[0121] When the memory element 930 performs a programming action, a programming current I PGM flows through the bend of the conductive layer 542a, which causes current crowding and generates thermal stress, which helps to enhance the EM efficiency, and the difference of the threshold voltage of the FinFET transistor MFIN The threshold voltage difference is larger.

[0122] Similarly, the modification of the eighth embodiment memory element 930 can also be applied to the second to fourth embodiments memory elements 600, 700, 800.

[0123] Referring to Figure 13E is shown as a top view of an enhanced electromigration memory element of the ninth embodiment of the present application. The enhanced electromigration memory element adds a heat sink at the cathode. Compared to the first embodiment memory element 500, in the ninth embodiment memory element 940, the gate structure is in an E-shape (or finger-type). The gate structure includes a main branch, a first sub-branch, and a second sub-branch. The first and second sub-branches are extended from the main branch and are located at two sides of the main branch. Part of the first sub-branch and part of the second sub-branch are parallel to the main branch. In addition, the main branch covers the fin 512, and the first and second sub-branches also cover the fin 512. Further, the gate structure includes a conductive layer 542b on the main branch, a conductive layer 542c on the first sub-branch, and a conductive layer 542d on the second sub-branch. A wire 545 is electrically connected to the first side of the conductive layer 542b of the main branch, and a wire 547b is electrically connected to the second side of the conductive layer 542b of the main branch. In addition, a wire 547c is electrically connected to the second side of the conductive layer 542c of the first branch. A wire 547d is electrically connected to the second side of the conductive layer 542d of the second branch.

[0124] When the memory element 940 performs a programming action, a programming current I PGM flows through the conductive layer 542b, the conductive layer 532, so that the FinFET transistor M FIN generates heat and generates thermal stress. The two sub-branches of the gate structure can improve the heat dissipation capability. Therefore, the heat gradient between the first and second sides of the conductive layer 542b is increased to enhance the EM efficiency, so that the threshold voltage difference of the FinFET transistor M FIN is larger before and after the programming action.

[0125] Similarly, the modification of the ninth embodiment memory element 940 can also be applied to the second to fourth embodiments memory elements 600, 700, 800.

[0126] From the above description, the present application proposes an enhanced electromigration memory element applied to a non-volatile memory. In a programming operation, two different voltages are simultaneously provided to the gate terminals of the FinFET transistor or the GAA transistor, and the threshold voltage of the FinFET transistor or the GAA transistor is changed by using the electromigration mechanism, so that the memory element can present different storage states. In a reading operation, the same voltage is simultaneously provided to the gate terminals of the FinFET transistor or the GAA transistor, and the storage state of the memory element is determined according to the reading current generated by the FinFET transistor or the GAA transistor.

[0127] In view of the above, while the application has been described in connection with what is presently considered to be the most practical and preferred embodiments, it is to be understood that the application is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements. Accordingly, the application is to be accorded the widest scope of the appended claims for the protection of suitable embodiments.

Claims

1. A storage element for a non-volatile memory, comprising: A first fin field-effect transistor includes: a first fin, a gate structure, a first drain / source contact layer, and a second drain / source contact layer; wherein the gate structure includes: a first gate dielectric layer, a first conductive layer, and a second conductive layer; wherein the first gate dielectric layer covers the middle region and two side surfaces of the first fin, the first conductive layer covers the first gate dielectric layer, the second conductive layer covers the first conductive layer, the first drain / source contact layer is electrically contacted to a first side region of the first fin, and the second drain / source contact layer is electrically contacted to a second side region of the first fin; A first conductive line is located on a first side of the gate structure, and the first conductive line is electrically connected to a first side of the second conductive layer; and The second wire is located on the second side of the gate structure and is electrically connected to the second side of the second conductive layer; During programming, the first wire receives a first voltage and the second wire receives a second voltage; the programming current flows from the first wire through the first conductive layer and the second conductive layer to the second wire, and the first voltage is greater than the second voltage. During the read operation, at least one of the first wire and the second wire receives a control voltage, the first drain / source contact layer receives a third voltage, the second drain / source contact layer receives a fourth voltage, and the third voltage is greater than the fourth voltage; wherein, the first read current flows from the first drain / source contact layer through the channel region of the first fin field-effect transistor to the second drain / source contact layer, and the storage state of the memory element is determined according to the first read current; The difference between the first voltage and the second voltage is equal to the programming voltage, and the difference between the third voltage and the fourth voltage is equal to the reading voltage.

2. The storage element as claimed in claim 1, wherein the first conductive layer is a work function metal layer, and the threshold voltage of the first fin field-effect transistor is determined according to the thickness of the work function metal layer.

3. The storage element as claimed in claim 2, wherein the material of the work function metal layer is titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum alloy (TiAl).

4. The storage element of claim 2, wherein during the programming operation, the programming current flows through the first conductive layer; and after the programming operation, the thickness of the first conductive layer changes such that the threshold voltage of the first fin field-effect transistor changes, and the threshold voltage of the first fin field-effect transistor is less than the control voltage.

5. The storage element of claim 1, wherein the first conductor is electrically connected to the second conductive layer via a first contact hole, the second conductor is electrically contacted to the second conductive layer via a second contact hole, and the cross-sectional area of ​​the first contact hole is larger than the cross-sectional area of ​​the second contact hole.

6. The memory element of claim 1, further comprising a third conductive line formed on the first side of the gate structure, and the third conductive line being electrically connected to the first side of the second conductive layer; wherein, During the programming operation, both the first wire and the third wire receive the first voltage.

7. The storage element of claim 1 further includes a heat dissipation metal layer located above the first side of the second conductive layer, and the heat dissipation metal layer being in contact with the second conductive layer.

8. The storage element of claim 1 further includes a heating layer located above the second side of the second conductive layer, and the heating layer not in contact with the second conductive layer.

9. The memory element of claim 1, wherein the gate structure includes a main branch and a sub-branch; wherein, The main branch covers the first fin and the sub-branch extends from the first side of the main branch; wherein the second wire is electrically connected to the second conductive layer of the sub-branch and the first wire is electrically connected to the second conductive layer on the second side of the main branch.

10. The memory element of claim 1, wherein the gate structure includes a main branch, a first sub-branch, and a second sub-branch; wherein, The first wire is electrically connected to the second conductive layer on the first side of the main branch, and the second wire is electrically connected to the second conductive layer on the second side of the main branch; wherein the main branch covers the first fin, the first sub-branch and the second sub-branch extend from the second side of the main branch, and both the first sub-branch and the second sub-branch cover the first fin.

11. The memory element of claim 1, further comprising a second fin field-effect transistor, wherein the second fin field-effect transistor comprises: The second fin, the gate structure, the third drain / source contact layer, and the fourth drain / source contact layer; wherein the gate structure further includes: a second gate dielectric layer and a third conductive layer; wherein the second gate dielectric layer covers the middle region and the two side surfaces of the second fin, the third conductive layer covers the second gate dielectric layer, the second conductive layer covers the third conductive layer, the third drain / source contact layer is electrically contacted to the first side region of the second fin, and the fourth drain / source contact layer is electrically contacted to the second side region of the second fin; During the read operation, the third drain / source contact layer receives the third voltage, and the fourth drain / source contact layer receives the fourth voltage; the second read current flows from the third drain / source contact layer through the channel region of the second fin field-effect transistor to the fourth drain / source contact layer, and the storage state of the storage element is determined according to the first read current and the second read current.

12. The memory element of claim 11, wherein during the programming operation, the programming current flows through the first conductive layer and the third conductive layer; and after the programming operation, the thickness of the first conductive layer and the third conductive layer changes such that the threshold voltages of the first fin field-effect transistor and the second fin field-effect transistor change, wherein the threshold voltage of the first fin field-effect transistor is less than the control voltage, and the threshold voltage of the second fin field-effect transistor is greater than the control voltage.

13. A storage element of a non-volatile memory, comprising: A first all-around gate transistor includes: a first nanowire, a gate structure, a first drain / source structure, and a second drain / source structure, wherein the gate structure includes: a first gate dielectric layer, a first conductive layer, and a second conductive layer; wherein the first gate dielectric layer surrounds the middle region of the first nanowire, the first conductive layer surrounds the first gate dielectric layer, the second conductive layer surrounds the first conductive layer, the first drain / source structure is electrically contacted on a first side region of the first nanowire, and the second drain / source structure is electrically contacted on a second side region of the first nanowire; A first conductive line is located on a first side of the gate structure, and the first conductive line is electrically connected to a first side of the second conductive layer; and The second wire is located on the second side of the gate structure and is electrically connected to the second side of the second conductive layer; During programming, the first wire receives a first voltage and the second wire receives a second voltage; the programming current flows from the first wire through the first conductive layer and the second conductive layer to the second wire, and the first voltage is greater than the second voltage. During a read operation, at least one of the first wire and the second wire receives a control voltage, the first drain / source structure receives a third voltage, the second drain / source structure receives a fourth voltage, and the third voltage is greater than the fourth voltage; wherein a first read current flows from the first drain / source structure through the channel region of the first all-around gate transistor to the second drain / source structure, and the storage state of the memory element is determined according to the first read current; The difference between the first voltage and the second voltage is equal to the programming voltage, and the difference between the third voltage and the fourth voltage is equal to the reading voltage.

14. The memory element of claim 13, wherein the first conductive layer is a work function metal layer, and the threshold voltage of the first all-around gate transistor is determined according to the thickness of the work function metal layer.

15. The memory element of claim 14, wherein during the programming operation, the programming current flows through the first conductive layer; and after the programming operation, the thickness of the first conductive layer changes such that the threshold voltage of the first all-around gate transistor changes, and the threshold voltage of the first all-around gate transistor is less than the control voltage.

16. The storage element of claim 13, wherein the first conductor is electrically connected to the second conductive layer via a first contact hole, the second conductor is electrically contacted to the second conductive layer via a second contact hole, and the cross-sectional area of ​​the first contact hole is larger than the cross-sectional area of ​​the second contact hole.

17. The memory element of claim 13, further comprising a third conductive line formed on the first side of the gate structure, and the third conductive line being electrically connected to the first side of the second conductive layer; wherein, During the programming operation, both the first wire and the third wire receive the first voltage.

18. The storage element of claim 13, further comprising a heat dissipation metal layer located above the first side of the second conductive layer, and the heat dissipation metal layer being in contact with the second conductive layer.

19. The storage element of claim 13, further comprising a heating layer located above the second side of the second conductive layer, wherein the heating layer is not in contact with the second conductive layer.

20. The memory element of claim 13, wherein the gate structure includes a main branch and a sub-branch; wherein, The main branch surrounds the first nanowire and the sub-branch extends from the first side of the main branch; wherein the second wire is electrically connected to the second conductive layer of the sub-branch and the first wire is electrically connected to the second conductive layer on the second side of the main branch.

21. The memory element of claim 13, wherein the gate structure includes a main branch, a first sub-branch, and a second sub-branch; wherein, The first wire is electrically connected to the second conductive layer on the first side of the main branch, and the second wire is electrically connected to the second conductive layer on the second side of the main branch; wherein the main branch surrounds the first nanowire, the first sub-branch and the second sub-branch extend from the second side of the main branch, and both the first sub-branch and the second sub-branch surround the first nanowire.

22. The memory element of claim 13, further comprising a second all-around gate transistor, wherein the second all-around gate transistor comprises: The second nanowire, the gate structure, the third drain / source structure, and the fourth drain / source structure, wherein the gate structure further includes: a second gate dielectric layer and a third conductive layer; wherein the second gate dielectric layer surrounds the middle region of the second nanowire, the third conductive layer surrounds the second gate dielectric layer, the second conductive layer surrounds the third conductive layer, the third drain / source structure is electrically contacted on a first side region of the second nanowire, and the fourth drain / source structure is electrically contacted on a second side region of the second nanowire; During the read operation, the third drain / source structure receives the third voltage, and the fourth drain / source structure receives the fourth voltage; the second read current flows from the third drain / source structure through the channel region of the second all-around gate transistor to the fourth drain / source structure, and the storage state of the storage element is determined according to the first read current and the second read current.

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