W-band fully differential active phase shifter with high linearity and low temperature fluctuation

Abstract

The invention discloses a W-band fully differential active phase shifter with high linearity and low temperature fluctuation. The W-band fully differential active phase shifter comprises a spiral differential quadratic coupler, an I-path high-linearity buffer amplifier, a Q-path high-linearity buffer amplifier, an I-path vector modulation circuit, a Q-path vector modulation circuit, a vector synthesis output circuit, a bias current array and a current source in quadratic correlation with temperature, wherein the spiral differential orthogonal coupler adopts two completely symmetrical spiral coupling line structures to reduce the area and generate differential orthogonal signals with high precision and low insertion loss; on the basis that the I-path high-linearity buffer amplifier and the Q-path high-linearity buffer amplifier isolate post-stage impedance fluctuation to the spiral differential quadrature coupler, the linearity of a circuit is improved through a source feedback resistor, and deterioration of the linearity of the whole phase shifter is avoided; the I-path vector modulation circuit and the Q-path vector modulation circuit both adopt a variable gain amplifier structure capable of realizing phase inversion, and have a larger gain control range and better linearity while realizing phase inversion; a common-base triode with a self-biased resistor is used as an output buffer stage to realize a vector synthesis function, and the structure can ensure relatively constant output impedance in different phase shift states so as to realize good output matching in all phase shift states; a current source in secondary correlation with the temperature is used for biasing, and the change of the gain of the whole circuit along with the temperature is compensated so as to reduce the temperature fluctuation.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of millimeter wave integrated circuits, and particularly relates to a W-band full-differential active phase shifter with high linearity and low temperature fluctuation. BACKGROUND

[0002] With the rapid growth of wireless communication demand, the millimeter wave frequency band, especially the W-band (75-110 GHz), has become a research hotspot for high data rate and high resolution radar applications due to its short wavelength and large bandwidth. However, millimeter wave systems face challenges such as severe signal attenuation and difficulty in penetrating obstacles. Phased array technology can achieve rapid beam adjustment and high-precision beamforming, and can also control multi-beam synthesis to improve transmit power, so it is widely used in millimeter wave communication and radar systems. As a key module in phased array systems, the performance of the phase shifter directly affects the beam scanning accuracy, power efficiency and linearity of the system, and a high-performance millimeter wave phase shifter is of great significance to the phased array system.

[0003] Common millimeter wave phase shifters are mainly divided into two categories: passive phase shifters and active phase shifters. Passive phase shifters control the phase state through passive devices, usually have lower power consumption and higher linearity, but have higher insertion loss and larger chip size commensurate with the number of control bits, and face problems such as low phase resolution, large gain and phase error. Active phase shifters based on vector synthesis architecture have relatively high gain, can achieve high-bit phase resolution and full 360° phase shift range in a small chip size, but have the disadvantages of large current consumption and low linearity. From the circuit characteristics and development trend of phase shifters, active phase shifters are more suitable for millimeter wave applications.

[0004] At high frequencies, the parasitic effects of triodes are more pronounced, and the layout routing and other factors have a more serious impact on circuit performance, so active phase shifters generally face problems such as large phase shift error, low linearity and large temperature fluctuation in W-band applications.

[0005] In the prior art, the application with publication number CN119696543A discloses an active phase shifter with temperature compensation, which slows down the change of the gain of the vector modulation module with temperature by designing a positive temperature coefficient current source that changes with temperature to achieve temperature compensation effect, but the application only introduces first-order temperature compensation, and the temperature compensation range does not cover the temperature range of 85°C~125°C. In addition, the application uses a traditional Gilbert cell structure, which cannot meet the application of high linearity. SUMMARY

[0006] In order to overcome the problems of the prior art, the purpose of the present application is to provide a high-linearity low-temperature fluctuation W-band fully differential active phase shifter applied in a transceiver link of a W-band phased array system; a spiral differential quadrature coupler is used to generate differential quadrature signals, which effectively reduces the circuit area while ensuring the generation of high-precision quadrature signals, and the module also has very low insertion loss, effectively ensuring the performance of the circuit in the W-band; in view of the impedance fluctuation problem of the vector modulation circuit under different gain states, a high-linearity buffer amplifier is designed to be inserted between the vector modulation circuit and the spiral differential coupler for isolation, which effectively reduces the amplitude and phase errors of the output differential quadrature signals of the spiral differential quadrature coupler due to load mismatch; in addition, the addition of the high-linearity buffer amplifier will not have a negative impact on the linearity of the circuit; the present application also designs a temperature quadratic related current source according to the change trend of the gain with temperature, and provides temperature quadratic related bias current and reference current for the high-linearity buffer amplifier and the bias current array to compensate for the gain fluctuation of the phase shifter with temperature, and the gain fluctuation of the phase shifter in the full temperature range (-40~125°C) is compensated to within 0.45dB.

[0007] In order to achieve the above-mentioned purpose, the technical scheme of the present application is as follows: The application discloses a W-band full-differential active phase shifter with high linearity and low temperature fluctuation, which comprises a spiral differential quadrature coupler 1, an I-path high linearity buffer amplifier 2a, a Q-path high linearity buffer amplifier 2b, an I-path vector modulation circuit 3a, a Q-path vector modulation circuit 3b, a vector synthesis output circuit 4, a bias current array 5 and a temperature quadratic correlation current source 6; the spiral differential quadrature coupler 1 is used for converting two differential input signals VIN+ and VIN- into four mutually orthogonal signals I+, I-, Q+ and Q-; the I-path high linearity buffer amplifier 2a is responsible for isolating the spiral differential quadrature coupler 1 and the I-path vector modulation circuit 3a and amplifying the signals I+ and I- into signals I+ and I-; the Q-path high linearity buffer amplifier 2b is responsible for isolating the spiral differential quadrature coupler 1 and the Q-path vector modulation circuit 3b and amplifying the signals Q+ and Q- into signals Q+ and Q-; the I-path vector modulation circuit 3a is responsible for modulating the amplitudes of the signals I+ and I-; the Q-path vector modulation circuit 3b is responsible for modulating the amplitudes of the signals Q+ and Q-; the vector synthesis output circuit 4 is responsible for vector synthesizing and outputting the signals I+ and I- after amplitude modulation by the I-path vector modulation circuit 3a and the signals Q+ and Q- after amplitude modulation by the Q-path vector modulation circuit 3b; the bias current array 5 is responsible for converting external six-bit digital control signals, thereby providing bias currents IBI+ and IBI- for the I-path vector modulation circuit 3a and bias currents IBQ+ and IBQ- for the Q-path vector modulation circuit 3b according to the control signals to change the gain and polarity of the output signals of the I-path vector modulation circuit 3a and the Q-path vector modulation circuit 3b so as to realize the vector modulation function; the temperature quadratic correlation current source 6 is responsible for providing temperature compensation bias currents IB1 and IB2 for the I-path high linearity buffer amplifier 2a and the Q-path high linearity buffer amplifier 2b respectively, and in addition, the temperature quadratic correlation current source 6 is also responsible for providing a temperature compensation reference current IREF for the bias current array 5, thereby compensating the fluctuation of the overall circuit gain of the phase shifter with temperature.

[0008] The spiral differential quadrature coupler 1 is composed of two groups of spiral winding coupling lines, and the lumped parameter equivalent circuit is composed of inductances L1-L4 and capacitances C1-C12; wherein inductances L1 and L2 constitute a group of windings, and there is an electromagnetic coupling relationship between them with a coupling coefficient k; inductances L3 and L4 constitute another group of windings, and there is also an electromagnetic coupling relationship between them with a coupling coefficient k; capacitances C1 and C2 are respectively connected between the same name terminals of inductances L1 and L2, representing the equivalent parasitic capacitance between inductances L1 and L2; capacitances C3 and C4 are respectively connected between the same name terminals of inductances L3 and L4, representing the equivalent parasitic capacitance between inductances L3 and L4; the first ends of capacitances C5 and C6 are grounded, and the second ends are respectively connected to the two ends of inductance L1, representing the equivalent parasitic capacitance of inductance L1 to ground; the first ends of capacitances C7 and C8 are grounded, and the second ends are respectively connected to the two ends of inductance L3, representing the equivalent parasitic capacitance of inductance L3 to ground; the first ends of capacitances C9 and C10 are grounded, and the second ends are respectively connected to the two ends of inductance L2, representing the equivalent parasitic capacitance of inductance L2 to ground; the first ends of capacitances C11 and C12 are grounded, and the second ends are respectively connected to the two ends of inductance L4, representing the equivalent parasitic capacitance of inductance L4 to ground.

[0009] The I-path high linearity buffer amplifier 2a comprises transistors Q1-Q7, inductors L5-L8, capacitors C13-C16 and resistors R1-R6; wherein the emitter of the transistor Q1 is grounded, the collector is connected to the first end of the resistor R1, serving as the tail current source of the I-path high linearity buffer amplifier 2a; the first end of the capacitor C13 is connected to the output signal I+ of the spiral differential quadrature coupler 1, the second end is connected to the first end of the inductor L5 and the first end of the capacitor C14; the second end of the inductor L5 is grounded; the first end of the capacitor C15 is connected to the output signal I- of the spiral differential quadrature coupler 1, the second end is connected to the first end of the inductor L6 and the first end of the capacitor C16; the second end of the inductor L6 is grounded; the emitter of the transistor Q2 is connected to the second end of the resistor R1 and the emitter of the transistor Q3, the base of the transistor Q2 is connected to the second end of the capacitor C14 and the first end of the resistor R2, the collector of the transistor Q2 is connected to the emitter of the transistor Q4; the base of the transistor Q3 is connected to the second end of the capacitor C16 and the first end of the resistor R3, the collector of the transistor Q3 is connected to the emitter of the transistor Q5; the base of the transistor Q4 is connected to the first end of the resistor R4, the collector of the transistor Q4 is connected to the second end of the resistor R4 and the first end of the inductor L7; the second end of the inductor L7 is connected to the power supply VDD; the base of the transistor Q5 is connected to the first end of the resistor R5, the collector of the transistor Q5 is connected to the second end of the resistor R5 and the first end of the inductor L8; the second end of the inductor L8 is connected to the power supply VDD; the emitter of the transistor Q6 is grounded, the base and the collector of the transistor Q6 are connected and connected to the base of the transistor Q1; the first end of the resistor R6 is connected to the collector of the transistor Q6, the second end of the resistor R6 is connected to the emitter of the biasing transistor Q7; the base and the emitter of the transistor Q7 are connected to the second end of the isolation resistor R2 and the second end of the isolation resistor R3, and the current IB1 is input from the collector of the transistor Q7.

[0010] The Q path high linearity buffer amplifier 2b comprises triodes Q8-Q14, inductors L9-L12, capacitors C17-C20 and resistors R7-R12; wherein the emitter of the triode Q8 is grounded, the collector of the triode Q8 is connected to the first end of the resistor R7, serving as the tail current source of the Q path high linearity buffer amplifier 2b; the first end of the capacitor C17 is connected to the output signal Q+ of the spiral differential quadrature coupler 1, and the second end is connected to the first end of the inductor L9 and the first end of the capacitor C18; the second end of the inductor L9 is grounded; the first end of the capacitor C19 is connected to the output signal Q- of the spiral differential quadrature coupler 1, and the second end is connected to the first end of the inductor L10 and the first end of the capacitor C20; the second end of the inductor L10 is grounded; the emitter of the triode Q9 is connected to the second end of the resistor R7 and the emitter of the triode Q10, the base of the triode Q9 is connected to the second end of the capacitor C18 and the first end of the resistor R8, and the collector of the triode Q9 is connected to the emitter of the triode Q11; the emitter of the triode Q10 is connected to the second end of the resistor R7 and the emitter of the triode Q9, the base of the triode Q10 is connected to the second end of the capacitor C20 and the first end of the resistor R9, and the collector of the triode Q10 is connected to the emitter of the triode Q12; the base of the triode Q11 is connected to the first end of the resistor R10, and the collector of the triode Q11 is connected to the second end of the resistor R10 and the first end of the inductor L11; the second end of the inductor L11 is connected to the power supply VDD; the base of the triode Q12 is connected to the first end of the resistor R11, and the collector of the triode Q12 is connected to the second end of the resistor R11 and the first end of the inductor L12; the second end of the inductor L12 is connected to the power supply VDD; the emitter of the triode Q13 is grounded, the base and the collector of the triode Q13 are connected and connected to the base of the triode Q8; the first end of the resistor R12 is connected to the collector of the triode Q13, and the second end is connected to the emitter of the triode Q14; the base and the emitter of the triode Q14 are connected to the second end of the resistor R8 and the second end of the resistor R9, and the current IB2 is input from the collector of the triode Q14.

[0011] The I channel vector modulation circuit 3a comprises triodes Q15-Q23, capacitor C21, capacitor C22, resistor R13 and resistor R14; input signal I+ is input to the base of triode Q15 through the first end of capacitor C21, input signal I- is input to the base of triode Q16 through the first end of capacitor C22; the emitter of triode Q15 is grounded, the base of triode Q15 and the second end of input capacitor C21 are connected to the first end of resistor R13, the collector of triode Q15 is connected to the emitters of triodes Q17 and Q18; the emitter of triode Q16 is grounded, the base of triode Q16 and the second end of capacitor C22 are connected to the first end of resistor R14, the collector of triode Q16 is connected to the emitters of triodes Q19 and Q20; the emitter of triode Q21 is grounded, the base of triode Q21 is connected to the first end of resistor R15, the collector of triode Q21 is connected to the second end of resistor R13, the second end of resistor R14, the second end of resistor R15, the emitter of triode Q22 and the emitter of triode Q23; the collectors of triodes Q17 and Q20 are connected to the emitter of triode Q33 of the next stage vector synthesis output circuit 4; the collectors of triodes Q18 and Q19 are connected to the emitter of triode Q34 of the next stage vector synthesis output circuit 4; the base and collector of triode Q22 are connected to the base of triode Q17 and the base of triode Q19 after being short-circuited; the base and collector of triode Q23 are connected to the base of triode Q18 and the base of triode Q20 after being short-circuited; current IBI+ is input from the collector of triode Q22, current IBI- is input from the collector of triode Q23.

[0012] The Q channel vector modulation circuit 3b comprises triodes Q24~Q32, capacitor C23, capacitor C24, resistor R15 and resistor R16; input signal Q+ is input to the base of triode Q24 through the first end of capacitor C23, input signal I- is input to the base of triode Q25 through the first end of capacitor C24; the emitter of triode Q24 is grounded, the base of triode Q24 is connected with the second end of input capacitor C23 and the first end of resistor R16, the collector of triode Q24 is connected with the emitters of triodes Q26 and Q27; the emitter of triode Q25 is grounded, the base of triode Q25 is connected with the second end of capacitor C24 and the first end of resistor R17, the collector of triode Q25 is connected with the emitters of triodes Q28 and Q29; the emitter of triode Q30 is grounded, the base of triode Q30 is connected with the first end of resistor R18, the collector of triode Q30 is connected with the second end of resistor R16, the second end of resistor R17, the second end of resistor R18, the emitter of triode Q31 and the emitter of triode Q32; the collectors of triodes Q27 and Q28 are connected with the emitter of triode Q33 of the next stage vector synthesis output circuit 4; the collectors of triodes Q26 and Q29 are connected with the emitter of triode Q34 of the next stage vector synthesis output circuit 4; the base and collector of triode Q31 are connected with the base of triode Q27 and the base of triode Q29 after being short-circuited; the base and collector of triode Q32 are connected with the base of triode Q26 and the base of triode Q28 after being short-circuited; current IBQ+ is input from the collector of triode Q31, current IBQ- is input from the collector of triode Q32.

[0013] The vector synthesis output circuit 4 comprises a transistor Q33, a transistor Q34, a resistor R19, a resistor R20, an inductor L13, an inductor L14, a capacitor C25 and a capacitor C26; the emitter of the transistor Q33 is connected with the collectors of the transistors Q17 and Q20 in the I-path vector modulation circuit 3a of the previous stage and the collectors of the transistors Q27 and Q28 in the Q-path vector modulation circuit 3b, the base of the transistor Q33 is connected with the first end of the resistor R19, the emitter of the transistor Q33 is connected with the second end of the resistor R19, the first end of the inductor L13 and the first end of the capacitor C25; the emitter of the transistor Q34 is connected with the collectors of the transistors Q18 and Q19 in the I-path vector modulation circuit 3a of the previous stage and the collectors of the transistors Q26 and Q29 in the Q-path vector modulation circuit 3b, the base of the transistor Q34 is connected with the first end of the resistor R20, the collector of the transistor Q34 is connected with the second end of the resistor R20, the first end of the inductor L14 and the first end of the capacitor C26; the second ends of the inductor L13 and the inductor L14 are connected with the power supply VDD; the second end of the capacitor C25 outputs the positive differential signal OUT+ after modulation, and the second end of the capacitor C26 outputs the negative differential signal OUT- after modulation.

[0014] The temperature quadratic current source 6 comprises PMOS tubes PM1~PM10, NMOS tubes NM1~NM5, transistors Q35~Q41 and resistors R23~R25; the sources of the PMOS tubes PM1~PM10 are connected to the power supply VDD; the gate and the drain of the PMOS tube PM1 are short-circuited, the drain of the PMOS tube PM1 is connected to the drains of the NMOS tubes NM1 and NM3; the gate of the PMOS tube PM2 is connected to the gate of the PMOS tube PM3 after being short-circuited with the drain of the PMOS tube PM2, the drain of the PMOS tube PM3 is connected to the drain of the NMOS tube NM2; the drain of the PMOS tube PM3 is connected to the gate of the NMOS tube NM3; the gate of the PMOS tube PM4 is connected to the gates of the PMOS tubes PM5 and PM6, the drain of the PMOS tube PM4 is connected to the drain of the NMOS tube NM4; the gate and the drain of the PMOS tube PM5 are short-circuited, the drain of the PMOS tube PM5 is connected to the drain of the NMOS tube NM5; the drain of the PMOS tube PM6 is connected to the collector of the transistor Q37; the gate of the PMOS tube PM7 is connected to the gates of the PMOS tubes PM8~PM10 after being short-circuited with the drain of the PMOS tube PM7, the drain of the PMOS tube PM7 is connected to the collector of the transistor Q41; the drain of the PMOS tube PM8 outputs the temperature compensation bias current IB1 to the I-channel high linearity buffer amplifier 2a; the drain of the PMOS tube PM9 outputs the temperature compensation bias current IB2 to the Q-channel high linearity buffer amplifier 2b; the drain of the PMOS tube PM10 outputs the temperature compensation reference current IREF to the bias current array 5; the sources of the NMOS tubes NM1~NM3 are connected to the ground; the gate of the NMOS tube NM1 is connected to the gate of the NMOS tube NM2 after being short-circuited with the drain of the NMOS tube NM1; the gate of the NMOS tube NM3 is connected to the drain of the PMOS tube PM3, the collector of the transistor Q35 and the source of the NMOS tube NM4; the gate of the NMOS tube NM4 is connected to the gate of the NMOS tube NM5 after being short-circuited with the drain of the NMOS tube NM4; the source of the NMOS tube NM5 is connected to the first end of the resistor R23; the base and the collector of the transistor Q35 are short-circuited, the emitter is connected to the ground; the base and the collector of the transistor Q36 are short-circuited, the collector is connected to the second end of the resistor R23 and the first end of the resistor R24; the second end of the resistor R24 is connected to the ground; the base of the transistor Q37 is connected to the base of the transistor Q38 after being short-circuited with the collector of the transistor Q37, the emitter of the transistor Q37 is connected to the collector of the transistor Q39; the base of the transistor Q39 is connected to the base of the transistor Q40 after being short-circuited with the collector of the transistor Q39, the emitter of the transistor Q39 is connected to the ground; the collector of the transistor Q38 is connected to the power supply VDD, the emitter of the transistor Q38 is connected to the collector of the transistor Q40, the first end of the resistor R25 and the base of the transistor Q41; the emitter of the transistor Q40 is connected to the ground; the second end of the resistor R25 is connected to the ground; the collector of the transistor Q41 is connected to the drain of the PMOS tube PM1, the emitter of the transistor Q41 is connected to the ground.

[0015] The present application has the following advantages over the prior art: 1. The present application uses a spiral differential quadrature coupler to generate differential quadrature signals, which uses a spiral winding coupling line structure that does not introduce additional resistive devices, thus having lower insertion loss; in addition, through spiral winding, the coupling line length is guaranteed to meet the performance requirements while greatly optimizing the layout area occupied by the coupling line, effectively ensuring the performance of the circuit in the W waveband.

[0016] 2. The present application addresses the impedance fluctuation problem of the vector modulation circuit under different gain states, and designs a high linearity buffer amplifier inserted between the vector modulation circuit and the spiral differential coupler for isolation; by using a differential common-emitter common-base architecture, the high linearity buffer amplifier achieves high isolation between the front and rear stages, effectively reducing the output differential quadrature signal amplitude and phase error caused by load mismatch of the spiral differential quadrature coupler; in addition, the high linearity buffer amplifier improves the linearity of the high linearity buffer amplifier through the emitter negative feedback resistor, and the introduction of the high linearity buffer amplifier does not negatively affect the linearity of the overall circuit of the phase shifter.

[0017] 3. The vector modulation circuit designed in the present application uses a variable gain amplifier structure that can realize phase inversion, which has high linearity and gain control range compared to the traditional Gilbert cell structure, and can also realize phase inversion of the output signal, so that the vector synthesis output signal can cover a 360° phase shift range.

[0018] 4. The present application addresses the gain fluctuation problem of the phase shifter with temperature, and according to the gain variation trend with temperature, a quadratic temperature coefficient current (IPTAT 2 ) generation circuit is added to the primary temperature coefficient current (IPTAT) generation circuit to design a temperature quadratic current source, which provides temperature quadratic bias current and reference current to the high linearity buffer amplifier and bias current array to compensate for the gain fluctuation of the phase shifter with temperature, and compensates the gain fluctuation of the phase shifter in the full temperature range (-40~125°C) to within 0.45dB.

[0019] In summary, the spiral differential quadrature coupler of the application adopts two completely symmetrical spiral coupling line structures to reduce the area and generate high-precision, low-insertion-loss differential quadrature signals; the I-path high-linearity buffer amplifier and the Q-path high-linearity buffer amplifier, on the basis of isolating the impedance fluctuation of the rear stage from the spiral differential quadrature coupler, improve the circuit linearity through the source feedback resistance to avoid the deterioration of the overall phase shifter linearity; the I-path vector modulation circuit and the Q-path vector modulation circuit both adopt a variable gain amplifier structure capable of realizing phase inversion, which has a larger gain control range and better linearity while realizing phase inversion; the common-base triode with resistance self-biasing is used as the output buffer stage to realize the vector sum function, and this structure can ensure relatively constant output impedance in different phase shift states to realize good output matching in all phase shift states; a temperature quadratic current source is used for biasing to compensate for the change of the overall circuit gain with temperature to reduce temperature fluctuation. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a structure block diagram of a high-linearity low-temperature fluctuation W-band full-differential six-bit active phase shifter provided by the embodiment of the application; Figure 2 is a circuit principle diagram of a radio frequency path part circuit provided by the embodiment of the application; Figure 3 is a circuit principle diagram of a temperature quadratic current source provided by the embodiment of the application; Figure 4 is a layout of a spiral differential quadrature coupler provided by the embodiment of the application; Figure 5 is a simulation result diagram of the gain and gain root mean square error of 64 phase shift states of the six-bit active phase shifter provided by the embodiment of the application; Figure 6 is a simulation result diagram of the phase and phase root mean square error of 64 phase shift states of the six-bit active phase shifter provided by the embodiment of the application; Figure 7 is a simulation result diagram of the linearity of the six-bit active phase shifter provided by the embodiment of the application; Figure 8 is a simulation result diagram of the change of the gain of the reference state of the six-bit active phase shifter with temperature provided by the embodiment of the application. DETAILED DESCRIPTION

[0021] The application will be further described in detail below in combination with specific embodiments, but the embodiments of the application are not limited thereto.

[0022] Reference Figure 1The application provides a high-linearity low-temperature fluctuation W-band full-differential active phase shifter structure, which comprises a spiral differential quadrature coupler 1, an I-path high-linearity buffer amplifier 2a, a Q-path high-linearity buffer amplifier 2b, an I-path vector modulation circuit 3a, a Q-path vector modulation circuit 3b, a vector synthesis output circuit 4, a bias current array 5 and a temperature quadratic correlation current source 6.

[0023] The spiral differential quadrature coupler 1 is used for converting two differential input signals VIN+ and VIN- into four quadrature signals I+, I-, Q+ and Q-; the I-path high-linearity buffer amplifier 2a is responsible for isolating the spiral differential quadrature coupler 1 and the I-path vector modulation circuit 3a and amplifying the in-phase branch differential signals I+ and I- into I+ and I-; the Q-path high-linearity buffer amplifier 2b is responsible for isolating the spiral differential quadrature coupler 1 and the Q-path vector modulation circuit 3b and amplifying the quadrature branch differential signals Q+ and Q- into Q+ and Q-; the I-path vector modulation circuit 3a is responsible for modulating the amplitudes of the in-phase differential signals I+ and I-; the Q-path vector modulation circuit 3b is responsible for modulating the amplitudes of the quadrature differential signals Q+ and Q-; the vector synthesis output circuit 4 is responsible for vector synthesizing and outputting the signals I+ and I- after amplitude modulation by the I-path vector modulation circuit 3a and the signals Q+ and Q- after amplitude modulation by the Q-path vector modulation circuit 3b; the bias current array 5 is responsible for converting external six-bit digital signals, thereby providing the I-path vector modulation circuit 3a with bias currents IBI+ and IBI- and the Q-path vector modulation circuit 3b with bias currents IBQ+ and IBQ- according to the control signals to change the gain and polarity of the output signals of different two modules to realize the vector modulation function; the temperature quadratic correlation current source 7 is responsible for providing the I-path high-linearity buffer amplifier 2a and the Q-path high-linearity buffer amplifier 2b with temperature quadratic correlation temperature compensation bias currents IB1 and IB2, and in addition, the temperature quadratic correlation current source 6 is also responsible for providing the bias current array 5 with a temperature quadratic correlation temperature compensation reference current IREF, thereby compensating the fluctuation of the overall circuit gain of the phase shifter with temperature.

[0024] Referring to Figure 2 A lumped parameter equivalent circuit of the spiral differential quadrature coupler 1 is given. Due to the symmetry of the circuit, the working principle of the spiral quadrature coupler is illustrated by taking the positive half equivalent circuit composed of the inductor L1, the inductor L2, the capacitor C1, the capacitor C2, the capacitor C5, the capacitor C6, the capacitor C9 and the capacitor C10 as an example; wherein the inductor L1 and the inductor L2 represent the equivalent inductances of the two coupled lines, which have equal inductance values L and a coupling coefficient k between them. The capacitor C1 and the capacitor C2 represent the parasitic capacitances between the two coupled lines, which have equal capacitance values C L-LCapacitor C5, capacitor C6, capacitor C9 and capacitor C10 represent the parasitic capacitance between the two coupling lines and the ground plane, and the capacitance values are all C L-GND . In order to decompose the input signal into equal-amplitude quadrature signals at the frequency ω, assuming that the characteristic impedance of the four ports is Z0, the coupling coefficient k, the inductance value L, the capacitance value C L-L and the capacitance value C L-GND should satisfy the following conditions: Referring to Figure 4 , a layout of a spiral differential quadrature coupler provided by an embodiment of the present application is composed of two completely symmetrical transformer-type quadrature couplers. The quadrature coupler adopts a spiral parallel winding structure to reduce the layout area. In order to reduce the insertion loss, the main traces adopt the secondary top layer thick metal, and the staggered traces adopt the secondary top layer thick metal. Since the lengths of the primary and secondary coils of the parallel winding transformer structure are not completely the same, the lengths of the primary and secondary coupling coils are properly adjusted in the layout to compensate for the imbalance of the winding. In addition, considering that the dielectric loss is high in the millimeter wave band, in order to reduce the insertion loss of the differential quadrature coupler and improve the electromagnetic interference shielding capability, a ground layer metal is added below the entire spiral differential quadrature coupler.

[0025] Continuing to refer to Figure 2 , a circuit schematic diagram of an I-path high-linearity buffer amplifier 2a and a Q-path high-linearity buffer amplifier 2b provided by an embodiment of the present application is given. Since the structures of the I-path high-linearity buffer amplifier 2a and the Q-path high-linearity buffer amplifier 2b are symmetrical, the working principles are completely the same, and they are respectively responsible for processing the signals of the in-phase branch and the quadrature branch and realizing isolation. Therefore, the working principle of the I-path high-linearity buffer amplifier 2a is analyzed. The transistor Q2 and the transistor Q4 constitute a common-emitter common-base amplifier, which has high isolation characteristics and can approximately reduce the influence of the voltage fluctuation at the output end on the input end by g m2 r o2 r o4 times, thereby effectively reducing the influence of the load impedance change on the input impedance, realizing the isolation between the modules, and also realizing the gain compensation of the active phase shifter. In addition, in order to ensure that the overall phase shifter has high linearity, the inserted buffer amplifier should also have high linearity to avoid negative effects on the linearity of the overall phase shifter. Therefore, the high-linearity buffer amplifier provided by the present application additionally adopts a shot-stage negative feedback resistor R1 to suppress the transconductance change of the transistor Q2 and the transistor Q3 on the basis of fully designing the bias and size of the transistor to ensure optimal linearity, thereby further improving the linearity of the buffer amplifier.

[0026] With reference to the accompanying drawings, the present application will be described in detail. Figure 2 The circuit schematic of the I-path vector modulation circuit 3a and the Q-path vector modulation circuit 3b provided by the embodiment of the present application is shown in FIG. 2. Since the I-path vector modulation circuit 3a and the Q-path vector modulation circuit 3b are completely symmetrical in structure and have the same working principle, both of them adopt a variable gain amplifier structure based on the improvement of the traditional Gilbert cell structure and capable of realizing phase inversion. Compared with the traditional Gilbert cell structure, the structure has a larger gain control range and a better linearity.

[0027] The working principle of the variable gain amplifier provided by the present application will be described below by taking the I-path vector modulation circuit 3a as an example. The bias currents IBI+ and IBI- are copied to the common-emitter transistors Q15 and Q16 and the common-base transistors Q17-Q20 through the current mirror circuit composed of the biasing transistors Q21-Q23. By controlling the bias current size to change the transconductance of the transistors Q15 and Q16, the gain of the amplifier can be controlled, thereby realizing the variable gain function. The common-base transistors Q17 and Q20 form a group and their bias current is IBI+, while the common-base transistors Q18 and Q19 form another group and their bias current is IBI-. In actual application, by changing the I-path bias current to flow into IBI+ or IBI- entirely, the two groups of common-base transistors are made to work alternately, thereby realizing the output phase 180° inversion function. Further, when the I-path bias circuit flows into IBI+ entirely, IBI- is zero, at this time the common-base transistors Q17 and Q20 are turned on and the common-base transistors Q18 and Q19 are turned off, and after amplification, I+ in the I-path differential current flows into the non-inverting branch of the vector synthesis output circuit 4 and I- flows into the inverting branch of the vector synthesis output circuit 4. Conversely, when the I-path bias circuit flows into IBI- entirely, IBI+ is zero, and after amplification, I+ in the I-path differential current flows into the inverting branch of the vector synthesis output circuit 4 and I- flows into the non-inverting branch of the vector synthesis output circuit 4.

[0028] To further illustrate the vector synthesis phase inversion principle of the present application, it is assumed that the I-path bias current flows into IBI+ entirely and the Q-path bias current flows into IBQ+ entirely, then I+ and Q+ flow into the non-inverting branch of the vector synthesis circuit 4. Assuming that the amplitudes of the signals I+ and I- after amplification by the I-path vector modulation circuit 3a are A1, the amplitudes of the signals Q+ and Q- after amplification by the Q-path vector modulation circuit 3b are A2, and the gain of the vector synthesis circuit 4 is A3, then the phase θ and the amplitude A of the final synthesis output are respectively: According to the above relationship, by properly adjusting the gain of the I-path vector modulation circuit 3a and the Q-path vector modulation circuit 3b, the phase of the output signal can be changed while the amplitude of the output signal is kept unchanged, and the phase of the output signal can cover the first quadrant. According to the structure of the I-path vector modulation circuit 3a and the Q-path vector modulation circuit 3b, by changing the polarity of the output signals of the two circuits, the phase of the output signal can be extended to the four quadrants, and a full 360° phase coverage can be achieved. Finally, by converting the six digital control signals into 63 groups of values of IBI+, IBI-, IBQ+ and IBQ- through the bias current array, 63 phase-shifting states with a step of 5.625° can be achieved.

[0029] With reference to Figure 2 , a circuit schematic of a vector synthesis circuit 4 provided by the embodiment of the present application is given, and the triode Q33 and the triode Q34 with self-biasing resistance are responsible for the vector synthesis of the in-phase branch and the differential branch respectively, and the inductors L13-L14 and the capacitors C25-C26 constitute an output matching network. Since the current flowing through the triode Q33 and the triode Q34 remains basically unchanged in all phase-shifting states, the working states of the two transistors remain unchanged, and thus the output impedance is constant. In addition, by properly adjusting the size of the triode Q33 and Q34 and adjusting the parameters of the output matching network, good output matching can be achieved in all phase-shifting states.

[0030] With reference to Figure 3 , a circuit schematic of a temperature-quadratic-related current source 6 provided by the embodiment of the present application is given, which mainly includes a starting circuit, an IPTAT generation circuit and an IPTAT 2 generation circuit three parts. In the temperature-quadratic-related current source circuit provided by the embodiment of the present application, there is a degenerate state in the bias circuit structure independent of the power supply. If the initial state of the circuit is in the degenerate state in which the transistor does not work, there is no current in the triode Q35, and at this time the PMOS tube PM3 in the starting circuit can inject current into the triode Q35 to make the circuit get rid of the degenerate state and start, and then the collector potential of Q35 rises to make the gate voltage of the NMOS tube NM3 rise to turn on, and the gate voltage of the NMOS tube NM1 is pulled down, and the NMOS tube NM2 is turned off, so that the PMOS tubes PM2 and PM3 are turned off, and the PMOS tube PM3 no longer injects current into the triode Q35, and the starting circuit is closed and no longer affects other circuits. The IPTAT generation circuit adopts the classical IPTAT generation circuit structure, and the generated IPTAT current is copied to the IPTAT 2 generation circuit through the current mirror tube PM6. Further, the IPTAT 2The principle of the current generation circuit generating a quadratic temperature-dependent current is as follows: the PMOS transistor PM6 replicates the linear temperature-dependent current generated by the IPTAT generation circuit to the branch in which the transistor Q37 is located, and the transistor Q37 and the transistor Q39 are both diode-connected, replicating the current of the branch to the transistor Q38 and the transistor Q40. According to the circuit connection relationship, the following relationship can be obtained: In addition, the V BE of the transistor is related to the drain current as follows, where V T is the thermal voltage Therefore, the expression of V BE is as follows: Since the sizes of the transistors Q37-Q39 are the same and are m times the size of the transistor Q40, the collector currents of the transistors Q37-Q39 are the same and are IPTAT, and the collector current of the transistor Q40 is 1 / m times the current of the transistors Q37-Q39, which is IPTAT / m. The reverse saturation current of a transistor is only related to the doping concentration of the transistor itself and the temperature, so the reverse saturation currents of the transistors Q37-Q41 are the same. Therefore, the following relationship is obtained: The collector current flowing through the transistor Q38 is equal to the collector current I C40 flowing through the transistor Q40, the current V BE41 / R 25 flowing through the resistor R25, and the base current I B41 flowing through the transistor Q41, and the base current I B41 of the transistor Q41 is negligible compared to the other two, so the following relationship is approximately obtained: By combining the above two equations, the expression of the collector current I C41 of the transistor Q41 is as follows: where R25 is a polysilicon resistor, and its temperature coefficient is very small, so its resistance value is approximately considered to be independent of temperature. According to the above equation, it can be seen that V BE41 / R25 in the denominator has a negative temperature coefficient, and IPTAT / m has a positive temperature coefficient. By appropriately adjusting the resistance value R 25 of R25 and the ratio m of the transistor area, the temperature coefficient of the denominator of the above equation can be close to zero, so that the collector current I C41The current approximately becomes a quadratic temperature-dependent current. The quadratic temperature-dependent current is copied to the bias current IB1 of the high linearity buffer amplifier 2a of the I path, the bias current IB2 of the high linearity buffer amplifier 2b of the Q path and the reference current IREF of the bias current array in a certain proportion through the current mirror composed of the PMOS tubes PM7-PM10.

[0031] The technical effects of the present application are further illustrated by simulation experiments: 1. Simulation conditions: In the frequency band of 91GHz-95GHz, the GF 130nm BiCMOS process model is adopted, the power supply voltage VDD is 3.3V, and the simulation is performed by using the Cadence simulation tool.

[0032] 2. Simulation content: Simulation 1: The phase characteristics of the circuit of the embodiment of the present application are simulated under the above conditions, and the results are shown in Figure 4 From the simulation results, it can be seen that the phase curves under 64 phase shift states are uniformly distributed, and according to the root mean square phase error curves under 64 phase shift states in the figure, it can be seen that the worst root mean square phase error is less than 2.7° in the simulation frequency band, which indicates that the present application realizes low phase shift phase error.

[0033] Simulation 2: The gain characteristics of the circuit of the embodiment of the present application are simulated under the above conditions, and the results are shown in Figure 5 From the simulation results, it can be seen that the gain curves under 64 phase shift states are concentratedly distributed, and according to the root mean square gain error curves under 64 phase shift states in the figure, it can be seen that the worst root mean square gain error is less than 0.6dB in the simulation frequency band, which indicates that the present application realizes low phase shift gain error.

[0034] Simulation 3: The temperature characteristics of the circuit of the embodiment of the present application are simulated under the above conditions, and the results are shown in Figure 6 From the simulation results, it can be seen that in the temperature range of-40°C-125°C, the gain fluctuation of the circuit of the present application under the phase shift reference state is less than 0.45dB, which indicates that the present application realizes low temperature fluctuation characteristics.

[0035] Simulation 4: The linearity of the circuit of the embodiment of the present application is simulated under the above conditions, and the results are shown in Figure 7 From the simulation results, it can be seen that the input 1dB compression point of the circuit of the present application is greater than 5dBm, which indicates that the present application realizes high linearity.

Claims

1. A W-band fully differential active phase shifter with high linearity and low temperature fluctuation, characterized in that: The system includes a spiral differential quadrature coupler (1), an I-channel high linearity buffer amplifier (2a), a Q-channel high linearity buffer amplifier (2b), an I-channel vector modulation circuit (3a), a Q-channel vector modulation circuit (3b), a vector synthesis output circuit (4), a bias current array (5), and a temperature-dependent quadratic current source (6); the spiral differential quadrature coupler (1) is used to convert two differential input signals VIN+ and VIN- into four mutually orthogonal signals I+, I-, Q+, and Q-; the I-channel high linearity buffer amplifier (2a ... a) is responsible for isolating the helical differential quadrature coupler (1) and the I-channel vector modulation circuit (3a) and amplifying the signals I+ and I- into signals I+' and I-'; Q-channel high linearity buffer amplifier (2b) is responsible for isolating the helical differential quadrature coupler (1) and the Q-channel vector modulation circuit (3b) and amplifying the signals Q+ and Q- into signals Q+' and Q-'; I-channel vector modulation circuit (3a) is responsible for modulating the amplitudes of signals I+' and I-'; Q-channel vector modulation circuit (3b) is responsible for modulating the amplitudes of signals Q+' and Q-'; The vector synthesis output circuit (4) is responsible for vector synthesis and output of the signals I+" and I-" after amplitude modulation by the I-path vector modulation circuit (3a) and the signals Q+" and Q-" after amplitude modulation by the Q-path vector modulation circuit (3b); The bias current array (5) is responsible for converting the external six-digit digital control signal, thereby providing bias currents IBI+ and IBI- to the I-channel vector modulation circuit (3a) and bias currents IBQ+ and IBQ- to the Q-channel vector modulation circuit (3b) according to the control signal to change the gain and polarity of the output signals of the I-channel vector modulation circuit (3a) and the Q-channel vector modulation circuit (3b) to realize the vector modulation function; the temperature-second related current source (6) is responsible for providing temperature-second related temperature compensation bias currents IB1 and IB2 to the I-channel high linearity buffer amplifier (2a) and the Q-channel high linearity buffer amplifier (2b) respectively. In addition, the temperature-second related current source (6) is also responsible for providing a temperature-second related temperature compensation reference current IREF to the bias current array (5), thereby compensating for the fluctuation of the overall circuit gain of the phase shifter with temperature.

2. The W-band fully differential active phase shifter with high linearity and low temperature fluctuation as described in claim 1, characterized in that: The spiral differential orthogonal coupler (1) consists of two sets of spiral winding coupling lines. Its lumped parameter equivalent circuit consists of inductors L1~L4 and capacitors C1~C12. Inductors L1 and L2 form one set of windings, and there is an electromagnetic coupling relationship between them with a coupling coefficient of k. Inductors L3 and L4 form another set of windings, and there is also an electromagnetic coupling relationship between them with a coupling coefficient of k. Capacitors C1 and C2 are connected across the same-name terminals of inductors L1 and L2, respectively, representing the equivalent parasitic capacitance between inductors L1 and L2. Capacitors C3 and C4 are connected across the same-name terminals of inductors L3 and L4, respectively. The first terminal of capacitors C5 and C6 is grounded, and the second terminal is connected to both ends of inductor L1, representing the equivalent parasitic capacitance from inductor L1 to ground. The first terminal of capacitors C7 and C8 is grounded, and the second terminal is connected to both ends of inductor L3, representing the equivalent parasitic capacitance from inductor L3 to ground. The first terminal of capacitors C9 and C10 is grounded, and the second terminal is connected to both ends of inductor L2, representing the equivalent parasitic capacitance from inductor L2 to ground. The first terminal of capacitors C11 and C12 is grounded, and the second terminal is connected to both ends of inductor L4, representing the equivalent parasitic capacitance from inductor L4 to ground.

3. The W-band fully differential active phase shifter with high linearity and low temperature fluctuation as described in claim 1, characterized in that: The I-channel high linearity buffer amplifier (2a) includes transistors Q1~Q7, inductors L5~L8, capacitors C13~C16, and resistors R1~R6; wherein the emitter of transistor Q1 is grounded, and the collector is connected to the first end of resistor R1, serving as the tail current source of the I-channel high linearity buffer amplifier (2a); the first end of capacitor C13 is connected to the output signal I+ of the spiral differential quadrature coupler (1), and the second end is connected to the first end of inductor L5 and the first end of capacitor C14; inductor L5 The second end is grounded; the first end of capacitor C15 is connected to the output signal I- of the spiral differential quadrature coupler (1), and the second end is connected to the first end of inductor L6 and the first end of capacitor C16; the second end of inductor L6 is grounded; the emitter of transistor Q2 is connected to the second end of resistor R1 and the emitter of transistor Q3, the base of transistor Q2 is connected to the second end of capacitor C14 and the first end of resistor R2, and the collector of transistor Q2 is connected to the emitter of transistor Q4; the transistor The base of transistor Q3 is connected to the second terminal of capacitor C16 and the first terminal of resistor R3. The collector of transistor Q3 is connected to the emitter of transistor Q5. The base of transistor Q4 is connected to the first terminal of resistor R4, and the collector of transistor Q4 is connected to the second terminal of resistor R4 and the first terminal of inductor L7. The second terminal of inductor L7 is connected to the power supply VDD. The base of transistor Q5 is connected to the first terminal of resistor R5, and the collector of transistor Q5 is connected to the second terminal of resistor R5 and the first terminal of inductor L8. The first terminal of the transistor is connected to the collector; the second terminal of the inductor L8 is connected to the power supply VDD; the emitter of transistor Q6 is grounded, and the base and collector of transistor Q6 are connected to the base of transistor Q1; the first terminal of resistor R6 is connected to the collector of transistor Q6, and the second terminal of resistor R6 is connected to the emitter of bias transistor Q7; the base and emitter of transistor Q7 are connected to the second terminals of isolation resistor R2 and isolation resistor R3, and the current IB1 is input from the collector of transistor Q7.

4. A W-band fully differential active phase shifter with high linearity and low temperature fluctuation as described in claim 1, characterized in that: The Q-channel high linearity buffer amplifier (2b) includes transistors Q8~Q14, inductors L9~L12, capacitors C17~C20, and resistors R7~R12. The emitter of transistor Q8 is grounded, and the collector of transistor Q8 is connected to the first end of resistor R7, serving as the tail current source of the Q-channel high linearity buffer amplifier 2b. The first end of capacitor C17 is connected to the output signal Q+ of the spiral differential quadrature coupler (1), and the second end is connected to the first end of inductor L9 and the first end of capacitor C18. The second end of inductor L9 is grounded. The first end of capacitor C19 is connected to the output signal Q- of the spiral differential quadrature coupler (1), and the second end is connected to the first end of inductor L10 and the first end of capacitor C20; the second end of inductor L10 is grounded; the emitter of transistor Q9 is connected to the second end of resistor R7 and the emitter of transistor Q10, the base of transistor Q9 is connected to the second end of capacitor C18 and the first end of resistor R8, the collector of transistor Q9 is connected to the emitter of transistor Q11; the emitter of transistor Q10 is connected to the second end of resistor R7. The transistor Q10 is connected to the emitter of transistor Q9; the base of transistor Q10 is connected to the second terminal of capacitor C20 and the first terminal of resistor R9; the collector of transistor Q10 is connected to the emitter of transistor Q12; the base of transistor Q11 is connected to the first terminal of resistor R10; the collector of transistor Q11 is connected to the second terminal of resistor R10 and the first terminal of inductor L11; the second terminal of inductor L11 is connected to power supply VDD; the base of transistor Q12 is connected to the first terminal of resistor R11; the collector of transistor Q12... The second terminal of resistor R11 and the first terminal of inductor L12 are connected; the second terminal of inductor L12 is connected to power supply VDD; the emitter of transistor Q13 is grounded, and the base and collector of transistor Q13 are connected to the base of transistor Q8; the first terminal of resistor R12 is connected to the collector of transistor Q13, and the second terminal is connected to the emitter of transistor Q14; the base and emitter of transistor Q14 are connected to the second terminals of resistor R8 and resistor R9, and current IB2 is input from the collector of transistor Q14.

5. A W-band fully differential active phase shifter with high linearity and low temperature fluctuation as described in claim 1, characterized in that: The I-channel vector modulation circuit (3a) includes transistors Q15~Q23, capacitors C21 and C22, resistors R13 and R14. The input signal I+' is input to the base of transistor Q15 through the first terminal of capacitor C21, and the input signal I-' is input to the base of transistor Q16 through the first terminal of capacitor C22. The emitter of transistor Q15 is grounded, and the base of transistor Q15 and the second terminal of input capacitor C21 are connected to the first terminal of resistor R13. The collector of transistor Q15 is connected to the emitters of transistors Q17 and Q18. The emitter of transistor Q16 is grounded, and the base of transistor Q16 and the second terminal of capacitor C22 are connected to the first terminal of resistor R14. The collector of transistor Q16 is connected to the emitters of transistors Q19 and Q20. The emitter of transistor Q21 is grounded, and the base of transistor Q21 is connected to resistor R15. The first terminal of transistor Q21 is connected to the second terminal of resistor R13, the second terminal of resistor R14, the second terminal of resistor R15, the emitter of transistor Q22, and the emitter of transistor Q23. The collectors of transistors Q17 and Q20 are connected to the emitter of transistor Q33 in the next-stage vector synthesis output circuit (4). The collectors of transistors Q18 and Q19 are connected to the emitter of transistor Q34 in the next-stage vector synthesis output circuit (4). The base and collector of transistor Q22 are shorted and then connected to the base of transistors Q17 and Q19. The base and collector of transistor Q23 are shorted and then connected to the base of transistors Q18 and Q20. Current IBI+ is input from the collector of transistor Q22, and current IBI- is input from the collector of transistor Q23.

6. A W-band fully differential active phase shifter with high linearity and low temperature fluctuation as described in claim 1, characterized in that: The Q-path vector modulation circuit (3b) includes transistors Q24~Q32, capacitors C23 and C24, resistors R15 and R16. The input signal Q+' is input to the base of transistor Q24 through the first terminal of capacitor C23, and the input signal I-' is input to the base of transistor Q25 through the first terminal of capacitor C24. The emitter of transistor Q24 is grounded, and its base is connected to the second terminal of input capacitor C23 and the first terminal of resistor R16. The collector of transistor Q24 is connected to the emitters of transistors Q26 and Q27. The emitter of transistor Q25 is grounded, and its base is connected to the second terminal of capacitor C24 and the first terminal of resistor R16. The collector of transistor Q25 is connected to the emitters of transistors Q28 and Q29. The emitter of transistor Q30 is grounded, and its base is connected to resistor R16. The first terminal of R18 is connected, the collector of transistor Q30 is connected to the second terminal of resistor R16, the second terminal of resistor R17, the second terminal of resistor R18, the emitter of transistor Q31, and the emitter of transistor Q32; the collectors of transistors Q27 and Q28 are connected to the emitter of transistor Q33 in the next stage vector synthesis output circuit (4); the collectors of transistors Q26 and Q29 are connected to the emitter of transistor Q34 in the next stage vector synthesis output circuit (4); the base and collector of transistor Q31 are shorted and then connected to the base of transistor Q27 and the base of transistor Q29; the base and collector of transistor Q32 are shorted and then connected to the base of transistor Q26 and the base of transistor Q28; the current IBQ+ is input from the collector of transistor Q31, and the current IBQ- is input from the collector of transistor Q32.

7. A W-band fully differential active phase shifter with high linearity and low temperature fluctuation as described in claim 1, characterized in that: The vector synthesis output circuit (4) includes transistors Q33 and Q34, resistors R19 and R20, inductors L13 and L14, capacitors C25 and C26; the emitter of transistor Q33 is connected to the collectors of transistors Q17 and Q20 in the previous stage I-channel vector modulation circuit (3a) and the collectors of transistors Q27 and Q28 in the Q-channel vector modulation circuit (3b); the base of transistor Q33 is connected to the first end of resistor R19; the emitter of transistor Q33 is connected to the second end of resistor R19, the first end of inductor L13, and the first end of capacitor C25; transistor Q34... The emitter of transistor 4 is connected to the collectors of transistors Q18 and Q19 in the previous stage I-channel vector modulation circuit (3a) and the collectors of transistors Q26 and Q29 in the Q-channel vector modulation circuit (3b). The base of transistor Q34 is connected to the first end of resistor R20. The collector of transistor Q34 is connected to the second end of resistor R20, the first end of inductor L14, and the first end of capacitor C26. The second ends of inductors L13 and L14 are connected to the power supply VDD. The second end of capacitor C25 outputs the modulated positive differential signal OUT+, and the second end of capacitor C26 outputs the modulated negative differential signal OUT-.

8. A W-band fully differential active phase shifter with high linearity and low temperature fluctuation as described in claim 1, characterized in that: The temperature-dependent current source (6) includes PMOS transistors PM1~PM10, NMOS transistors NM1~NM5, transistors Q35~Q41, and resistors R23~R25; the source of PMOS transistors PM1~PM10 is connected to the power supply VDD; the gate and drain of PMOS transistor PM1 are shorted, and the drain of PMOS transistor PM1 is connected to the drains of NMOS transistors NM1 and NM3; the gate and drain of PMOS transistor PM2 are shorted and then connected to the gate of PMOS transistor PM3, and the drain of PMOS transistor PM3 is connected to the drain of NMOS transistor NM2; the drain of PMOS transistor PM3 is connected to the gate of NMOS transistor NM3; the gate of PMOS transistor PM4 is connected to the PMOS transistor... The gates of transistors PM5 and PM6 are connected together; the drain of PMOS transistor PM4 is connected to the drain of NMOS transistor NM4; the gate and drain of PMOS transistor PM5 are shorted together, and the drain of PMOS transistor PM5 is connected to the drain of NMOS transistor NM5; the drain of PMOS transistor PM6 is connected to the collector of transistor Q37; the gate and drain of PMOS transistor PM7 are shorted together and then connected to the gates of PMOS transistors PM8~PM10; the drain of PMOS transistor PM7 is connected to the collector of transistor Q41; the drain of PMOS transistor PM8 outputs the temperature compensation bias current IB1 of the I-channel high linearity buffer amplifier (2a); the drain of PMOS transistor PM9 outputs the Q-channel high linearity buffer amplifier. The temperature compensation bias current IB2 of the device (2b); the drain output of PMOS transistor PM10 is given to the temperature compensation reference current IREF of the bias current array (5); the source of NMOS transistors NM1~NM3 is grounded; the gate and drain of NMOS transistor NM1 are shorted and then connected to the gate of NMOS transistor NM2; the gate of NMOS transistor NM3 is connected to the drain of PMOS transistor PM3, the collector of transistor Q35 and the source of NMOS transistor NM4; the gate and drain of NMOS transistor NM4 are shorted and then connected to the gate of NMOS transistor NM5; the source of NMOS transistor NM5 is connected to the first end of resistor R23; the base and collector of transistor Q35 are shorted and the emitter is grounded; the transistor The base and collector of transistor Q36 are shorted, and the collector is connected to the second terminal of resistor R23 and the first terminal of resistor R24; the second terminal of resistor R24 ​​is grounded. The base and collector of transistor Q37 are shorted and then connected to the base of transistor Q38; the emitter of transistor Q37 is connected to the collector of transistor Q39. The base and collector of transistor Q39 are shorted and then connected to the base of transistor Q40; the emitter of transistor Q39 is grounded. The collector of transistor Q38 is connected to power supply VDD; the emitter of transistor Q38 is connected to the collector of transistor Q40, the first terminal of resistor R25, and the base of transistor Q41; the emitter of transistor Q40 is grounded; the second terminal of resistor R25 is grounded.The collector of transistor Q41 is connected to the drain of PMOS transistor PM1, and the emitter of transistor Q41 is grounded.

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