Power line carrier communication chip function test method and system

Abstract

The invention provides a power line carrier communication chip function test method and system, and relates to the technical field of communication technology, and the method comprises the steps: constructing a power line channel simulation test platform, and simulating the voltage fluctuation and power rapid switching working condition in an actual power grid through dynamically adjusting the power output and load switching; in the power line channel simulation test platform, the dynamic sudden change process of the power grid impedance is simulated by controlling the change rate of the load current; the method comprises the following steps: generating an interference signal containing multiple times of characteristic harmonics based on a preset harmonic order proportional relation while simulating dynamic sudden change of impedance, establishing an amplitude proportional coefficient between a reference harmonic and a target harmonic, and coordinating and setting the amplitude of each harmonic according to the proportional relation of the corresponding order, so as to simulate the dynamic sudden change of the impedance. A plurality of characteristic harmonics with a predetermined proportional relationship are obtained, and an interference signal is coupled to a power line channel. The method can accurately simulate the severe channel condition of an actual power grid, and accurately evaluates the communication reliability of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication technology, in particular to a power carrier communication chip function test method and system. BACKGROUND

[0002] The power carrier communication technology has been widely applied to the intelligent power grid power consumption information collection, intelligent home control and other fields, and the actual power grid communication reliability of the core component power carrier communication chip directly determines the system operation stability.

[0003] In the actual power grid, the start and stop of high-power equipment and the operation of nonlinear loads can cause two key interference synergies: one is the dynamic mutation of the grid impedance, such as the sudden drop of the impedance caused by the rapid change of the load current when the industrial motor starts; the other is the composite interference of specific proportion multiple characteristic harmonics, such as the complex interference formed by the superposition of the 5th and 7th harmonics generated by the rectifier and frequency converter in a fixed amplitude ratio. These two kinds of interference together cause the sudden drop of the signal-to-noise ratio of the power line channel and the frequency selective fading, which seriously affects the performance of the chip carrier synchronization and equalization algorithm, and is the core factor restricting the actual reliability of the chip.

[0004] The existing test method has the following technical defects: only the impedance change or single harmonic interference can be simulated, and the above-mentioned synergistic interference environment cannot be reproduced. For example, a certain intelligent meter manufacturer uses the existing platform to test a certain type of chip, and the test results of the simulated static impedance and random noise meet the industry standard, but when the product is applied to the industrial park power distribution network, the impedance mutation caused by the start and stop of high-frequency motors is superimposed with the 5th and 7th harmonics (1:0.3 amplitude ratio) generated by the frequency converter, which causes the chip synchronization to lose lock, the equalization algorithm to converge slowly, and the data acquisition to fail, the communication to be interrupted and other problems. The existing method cannot simulate the synergistic interference scene, resulting in that the laboratory qualified chip frequently fails to meet the performance standard in actual application, and it is difficult to accurately evaluate the real communication reliability of the chip. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a power carrier communication chip function test method and system, which can accurately simulate the actual power grid harsh channel conditions and accurately evaluate the communication reliability of the chip.

[0006] To solve the above technical problems, the technical solution of the present application is as follows: In a first aspect, a power carrier communication chip function test method, the method comprising: constructing a power line channel simulation test platform, and simulating the voltage fluctuation and power rapid switching conditions in the actual power grid by dynamically adjusting the power supply output and load switching; In the power line channel simulation test platform, the dynamic mutation process of the grid impedance is simulated by controlling the change rate of the load current; While simulating the dynamic mutation of the impedance, based on a preset harmonic order proportion relationship, an interference signal containing multiple characteristic harmonics is generated; by establishing an amplitude proportion coefficient between a reference harmonic and a target harmonic, the amplitudes of the harmonics are set in accordance with the proportion relationship of the corresponding orders to obtain multiple characteristic harmonics with a predetermined proportion relationship, and the interference signal is coupled to the power line channel; Based on the synergistic effect of the multiple characteristic harmonics with the predetermined proportion relationship and the dynamic mutation process of the impedance, a coupled interference environment is formed in the test platform to reproduce the phenomena of sudden signal-to-noise ratio drop and frequency-selective fading in the actual channel; In the coupled interference environment, key communication performance indicators of the power line carrier communication chip are tested to obtain performance test data; Based on the performance test data, the carrier synchronization response of the chip, i.e., the power line carrier communication chip, is analyzed, the phase tracking behavior is evaluated by using a reference phase point and a phase offset angle and based on the coordinate transformation principle, and the adaptability of the chip to dynamic impedance changes and complex harmonic interference is evaluated in combination with the convergence characteristics of the equalization algorithm to finally determine the communication reliability of the chip under actual channel conditions.

[0007] Further, a power line channel simulation test platform is constructed, and by dynamically adjusting the power output and load switching, voltage fluctuations and power rapid switching conditions in the actual power grid are simulated, including: A voltage signal conforming to a preset fluctuation range is generated through the output voltage of the power supply of the test platform; Based on the voltage signal, the switching state of the load power between the preset low valley load and peak load is obtained by controlling the switching state of the resistance-capacitance-inductance hybrid load; According to the switching state of the load power, the parameter configuration of the load component is adjusted to form a load condition with a specific power factor characteristic; The voltage signal fluctuation characteristics, load power switching characteristics, and power factor characteristics of the load condition are systematically integrated to construct a comprehensive test environment that can accurately reproduce the actual power grid operation characteristics, i.e., correctly construct the power line channel simulation test platform.

[0008] Further, in the power line channel simulation test platform, the dynamic mutation process of the grid impedance is simulated by controlling the change rate of the load current, including: Based on the comprehensive test environment, the initial state of the grid impedance is set; According to the initial state, the dynamic mutation of the grid impedance is triggered by controlling the change rate of the load current; Based on the dynamic mutation, the rapid switching process of the grid impedance from a high impedance value to a low impedance value is monitored; By maintaining the rapid switching process, a dynamic impedance scenario with a preset change rate is formed.

[0009] Further, while simulating the dynamic mutation of the impedance, based on a preset harmonic order proportion relationship, a disturbance signal containing multiple characteristic harmonics is generated; by establishing an amplitude proportion coefficient between the reference harmonic and the target harmonic, the amplitudes of each harmonic are set in accordance with the proportion relationship of the corresponding order, to obtain multiple characteristic harmonics with a predetermined proportion relationship, and the disturbance signal is coupled to the power line channel, including: According to the time-varying characteristics of the dynamic impedance scene, the generation parameter configuration of each characteristic harmonic is determined; Based on the generation parameter configuration, the order proportion relationship between the reference harmonic and the target harmonic is constructed, and the amplitude mapping relationship is established based on the principle that the corresponding sides of similar triangles are proportional; According to the amplitude mapping relationship, the relative amplitude of each harmonic is determined by calculating the proportion coefficient of the corresponding order, to form multiple characteristic harmonics with a predetermined proportion relationship; The multiple characteristic harmonics with a predetermined proportion relationship are integrated into a composite disturbance signal, and the composite disturbance signal is coupled into the power line channel.

[0010] Further, based on the synergistic effect of the multiple characteristic harmonics with a predetermined proportion relationship and the dynamic mutation process of the impedance, a coupled interference environment is formed in the test platform to reproduce the signal-to-noise ratio drop and frequency selective fading phenomenon in the actual channel, including: The composite disturbance signal is superimposed with the dynamic impedance scene to produce a joint interference effect; Based on the joint interference effect, the dynamic change process of the signal-to-noise ratio in the power line channel is triggered; According to the dynamic change process of the signal-to-noise ratio, a frequency selective fading model is constructed; By integrating the joint interference effect, the dynamic change process of the signal-to-noise ratio, and the frequency selective fading model, a coupled interference environment is formed that can continuously reproduce the harsh conditions of the actual channel.

[0011] Further, in the coupled interference environment, the key communication performance indicators of the power line carrier communication chip are tested to obtain performance test data, including: In the coupled interference environment, the communication process of the power line carrier communication chip is triggered; Based on the communication process, the communication bit error rate, data transmission delay, and communication rate stability of the chip are monitored in real time to obtain real-time monitoring results; According to the real-time monitoring results, the adaptive switching performance of the chip under different modulation modes is recorded; The communication bit error rate, data transmission delay, communication rate stability, and adaptive switching performance are integrated to form a structured performance test data set.

[0012] Further, based on performance test data, analyze the carrier synchronization response of the chip, i.e. the power carrier communication chip, evaluate the phase tracking behavior by using the reference phase point and the phase offset angle, and based on the coordinate transformation principle, evaluate the adaptability of the chip to dynamic impedance changes and complex harmonic interference, and finally determine the communication reliability of the chip under actual channel conditions, including: Extract carrier synchronization response data from the performance test data set, and establish a phase tracking trajectory containing timing characteristics; Based on the phase tracking trajectory, use the reference phase point and the phase offset angle, and use the coordinate transformation principle in the graph point rotation algorithm to rotate and correct the phase of the received signal, to evaluate the phase synchronization performance; According to the phase synchronization performance, monitor the change process of the equalizer tap coefficient to analyze the convergence speed and stability of the equalization algorithm under dynamic impedance changes and complex harmonic interference, i.e. analyze the convergence characteristics of the equalization algorithm; Integrate the phase synchronization performance and the convergence characteristics of the equalization algorithm to build a chip adaptability evaluation mechanism and form a communication reliability determination result.

[0013] In a second aspect, a power carrier communication chip function test system includes: A construction module is configured to construct a power line channel simulation test platform, simulate voltage fluctuations and power fast switching conditions in the actual power grid by dynamically adjusting the power supply output and load switching; A simulation module is configured to simulate the dynamic mutation process of the power grid impedance by controlling the change rate of the load current in the power line channel simulation test platform; A processing module is configured to generate an interference signal containing multiple characteristic harmonics based on a predetermined harmonic order ratio relationship while simulating the dynamic mutation of the impedance; by establishing the amplitude ratio coefficient between the reference harmonic and the target harmonic, the amplitudes of each harmonic are set according to the corresponding order ratio relationship to obtain multiple characteristic harmonics with a predetermined ratio relationship, and the interference signal is coupled to the power line channel; A coordination module is configured to form a coupled interference environment in the test platform based on the coordinated action of the multiple characteristic harmonics with a predetermined ratio relationship and the dynamic mutation process of the impedance, to reproduce the signal-to-noise ratio drop and frequency selective fading phenomena in the actual channel; A test module is configured to test the key communication performance indicators of the power carrier communication chip in the coupled interference environment to obtain performance test data; The evaluation module is used for analyzing the carrier synchronization response of the chip, i.e., the power carrier communication chip, based on the performance test data, evaluating the phase tracking behavior by adopting a reference phase point and a phase offset angle and based on a coordinate transformation principle, combining the convergence characteristics of an equalization algorithm to evaluate the adaptability of the chip to dynamic impedance changes and complex harmonic interference, and finally determining the communication reliability of the chip under actual channel conditions.

[0014] In a third aspect, a computing device includes: one or more processors; a memory device storing one or more programs, which when executed by the one or more processors, cause the one or more processors to implement the method.

[0015] In a fourth aspect, a computer-readable storage medium stores a program, which when executed by a processor, implements the method.

[0016] The above scheme of the present application at least has the following beneficial effects: By constructing a power line channel simulation test platform, the power supply output and the load switching are dynamically adjusted, the load current change rate is controlled to simulate the dynamic mutation of the power grid impedance, and based on the preset harmonic order ratio relationship, a plurality of characteristic harmonic composite interference signals with a predetermined amplitude ratio are generated and coupled to the power line channel. With the synergistic effect of the two kinds of interference, the actual channel bad conditions are reproduced, and then the key communication performance indicators of the test chip are tested, and the phase tracking behavior and the convergence characteristics of the equalization algorithm are evaluated based on the coordinate transformation principle. Technical means effectively overcome the technical problems that the existing test methods cannot reproduce dynamic impedance mutation and specific proportional multiple characteristic harmonic synergistic interference environment, leading to the disconnection between laboratory tests and actual applications, making it difficult to accurately evaluate the real communication reliability of the chip, and further achieving the technical effects of accurately simulating the actual power grid bad channel conditions, truly exposing the potential performance defects of the chip, providing accurate basis for the research and development optimization and actual application selection of the power carrier communication chip, effectively improving the actual application reliability of the chip, and promoting the large-scale application of the power carrier communication technology. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a flowchart of a power carrier communication chip function test method provided by an embodiment of the present application.

[0018] Figure 2 is a schematic diagram of a power carrier communication chip function test system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be thoroughly understood and fully conveyed to those skilled in the art.

[0020] As Figure 1 shown, an embodiment of the present application proposes a power carrier communication chip function test method, the method comprising the following steps: Step 1, build a power line channel simulation test platform, simulate the voltage fluctuation and power fast switching working conditions in the actual power grid by dynamically adjusting the power output and load switching; Step 2, in the power line channel simulation test platform, simulate the dynamic mutation process of the grid impedance by controlling the change rate of the load current; Step 3, while simulating the dynamic mutation of the impedance, generate an interference signal containing multiple characteristic harmonics based on the preset harmonic order ratio relationship; by establishing the amplitude ratio coefficient between the reference harmonic and the target harmonic, the amplitudes of each harmonic are set according to the corresponding order ratio relationship, and the multiple characteristic harmonics with predetermined ratio relationship are obtained, and the interference signal is coupled to the power line channel; Step 4, based on the synergistic effect of the multiple characteristic harmonics with predetermined ratio relationship and the dynamic mutation process of the impedance, form a coupled interference environment in the test platform to reproduce the phenomena of sudden drop of signal-to-noise ratio and frequency selective fading in the actual channel; Step 5, in the coupled interference environment, test the key communication performance indicators of the power carrier communication chip, and obtain performance test data; Step 6, based on the performance test data, analyze the carrier synchronization response of the chip, i.e. the power carrier communication chip, evaluate the phase tracking behavior by using the reference phase point and the phase offset angle based on the coordinate transformation principle, combine the equalization algorithm convergence characteristics to evaluate the adaptability of the chip to dynamic impedance changes and complex harmonic interference, and finally determine the communication reliability of the chip under actual channel conditions.

[0021] In the embodiment of the application, by constructing a power line channel simulation test platform, dynamically simulating voltage fluctuation, power switching and dynamic mutation of power grid impedance, synchronously generating multiple characteristic harmonic interference signals with a predetermined proportional relationship and realizing the synergistic coupling of the two interferences, the adverse channel conditions that cause the signal-to-noise ratio to drop sharply and the frequency-selective fading in the actual power grid can be accurately reproduced. Combined with the key communication performance index test and the phase tracking evaluation based on the principle of coordinate transformation, the convergence characteristics analysis of the equalization algorithm, the adaptability of the power line carrier communication chip in the dynamic interference environment can be comprehensively and truly reflected, the disconnection problem between the existing test method and the actual application scene is effectively made up, not only the actual communication reliability of the chip can be accurately determined, but also the potential performance defects of the chip can be exposed in time, reliable data support is provided for the chip research and development optimization, performance improvement and actual application selection, and the running stability of the power line carrier communication system in the complex power grid environment is improved, and the large-scale promotion and application of the power line carrier communication technology are promoted.

[0022] In a preferred embodiment of the application, step 1 can include: Step 1.1, generate a voltage signal conforming to the preset fluctuation range through the output voltage of the power supply of the test platform, specifically including: selecting a power supply device with a voltage adjustment accuracy of plus or minus 0.1V and a response time less than or equal to 5ms, and the output frequency is stable at 50Hz power frequency, and it is compatible with common harmonic frequency bands of power grid; referring to the power quality standard, combining the voltage fluctuation characteristics caused by the start-stop of high-frequency motor in the industrial park distribution network, setting the voltage fluctuation interval to 88% to 108% of the rated voltage; using pulse width modulation technology, changing the duty cycle of the internal power conversion loop of the power supply device through high-frequency switching action, adjusting the output voltage amplitude and frequency in real time; collecting the output voltage data at a sampling frequency of 1kHz, using closed-loop feedback logic, dynamically correcting the duty cycle parameters according to the deviation between the measured value and the set value, to ensure that the generated voltage signal can reproduce both the instantaneous sharp rise and fall lasting for 20ms to 500ms, and also simulate long-term steady-state fluctuation.

[0023] Step 1.2, based on the voltage signal, by controlling the switching state of the resistance-inductance-capacitance hybrid load, so that the load power is quickly switched between the preset low valley load and peak load, the switching state of the load power is obtained, specifically including: connecting the resistive, inductive and capacitive loads in star connection mode into the test circuit, all loads are configured with electronic switches with on-off response time less than or equal to 2μs to avoid the generation of impact current during switching process; combining the load variation law of frequency converters, compressors and other devices in the industrial park, set the low valley load to 25% of the rated load, and the peak load to 105% of the rated load; based on the generated dynamic voltage signal, trigger the electronic switch action at the voltage zero crossing point to avoid the switching timing and voltage phase conflict; by changing the number of connected groups of resistive and inductive loads and the number of connected capacitive loads, the load power is quickly converted between the low valley and peak loads at a switching speed less than or equal to 10ms, the dynamic process of power mutation in the actual power grid is accurately reproduced, and the load switching characteristics in the industrial scene are matched.

[0024] Step 1.3, according to the switching state of the load power, adjust the parameter configuration of the load component to form a load working condition with specific power factor characteristics, specifically including: the resistive load uses a digital potentiometer to realize continuous adjustment with a step size of 0.1Ω, the inductive load realizes inductance adjustment with a step size of 0.1mH through linear movement of the magnetic core, and the capacitive load realizes step-by-step adjustment by combining multiple groups of 0.1μF film capacitors; based on the instantaneous reactive power detection principle, collect the load voltage and loop current signals at a sampling frequency of 1kHz, calculate the phase difference between them to obtain the real-time power factor; combining the power factor characteristics of industrial loads such as machine tools and fans, set the target power factor range to 0.75 to 0.92 lag, and the adjustment accuracy to plus or minus 0.01; according to the real-time detected power factor data, dynamically adjust the parameter ratio of resistance, inductance and capacitance, change the equivalent impedance angle of the load, and make the power factor of the load working condition stable in the target range, forming a characteristic consistent with the real power grid load power factor variation law.

[0025] Step 1.4, the fluctuation characteristics of the voltage signal, the switching characteristics of the load power and the power factor characteristics of the load working condition are integrated to build a comprehensive test environment capable of accurately reproducing the actual power grid operation characteristics, that is, a power line channel simulation test platform is correctly built, specifically including: a real-time interaction channel of voltage regulation, load switching, parameter adjustment and data acquisition links is established through a communication link with a transmission rate of 100 Mbps, to ensure the synchronous transmission of instructions and data of each link; according to the natural coupling logic of voltage variation, power fluctuation and power factor adjustment in the actual power grid, the operation timing of each link is coordinated, so that the amplitude variation of voltage fluctuation is synchronized with the timing of power switching, and the amplitude of power switching is matched with the adjustment amplitude of power factor; a power analyzer and a power quality monitor are used to collect the voltage, current and power data of the integrated test environment at a sampling interval of 100 ms, and the operation data of the actual industrial park distribution network is compared to set a deviation threshold less than or equal to 3%; according to the deviation, the amplitude step of voltage regulation, the combination mode of load switching and the adjustment amplitude of impedance parameters are dynamically corrected to eliminate the inherent error of the system; ensure that the comprehensive test environment built can reproduce the synergistic effect of voltage dynamic variation, power rapid switching and power factor dynamic adjustment in the actual power grid within 5s to 30s, and finally form a power line channel simulation test platform that is highly consistent with the real power grid working condition and stable and reliable.

[0026] In the embodiment of the application, the voltage signal meeting the preset fluctuation range is formed by the test platform power supply, combined with the resistance-capacitance-inductance hybrid load switching control, the rapid switching of the load power between the low valley and the peak load is realized, and the load parameters are adjusted according to the power switching state to form a specific power factor characteristic, and then the voltage fluctuation, power switching and power factor characteristics are integrated, which can accurately reproduce the core basic characteristics in the actual power grid operation, and build a comprehensive test environment highly consistent with the real power grid working condition, which provides a stable and reliable foundation for the simulation of complex interference scenes such as dynamic impedance mutation and composite harmonic interference, effectively avoids the deviation of chip test results caused by distortion of basic working condition simulation, ensures the practicability and accuracy of the power line channel simulation test platform, and lays a solid foundation for the overall functionality of chip functional testing.

[0027] In a preferred embodiment of the application, step 2 can include: Step 2.1, based on the comprehensive test environment, set the initial state of the grid impedance, specifically including: based on the constructed comprehensive test environment, first on-site monitoring of the industrial park power distribution network during off-peak hours and equipment not started, through the power quality analyzer to obtain the effective value and phase difference of voltage and current, and through calculation to obtain the equivalent impedance range in this scenario as 15Ω to 30Ω, impedance angle 30° to 45° lag; in the test loop, the resistive load uses a combination of multiple sets of 5Ω precision resistors in series and parallel, for example, 3 sets of 5Ω resistors in series can achieve a resistive component of 15Ω; the inductive load selects an adjustable inductance with a 0.1mH adjustment step, for example, when the target inductive reactance is 8Ω, a 25mH inductance is selected; the capacitive load uses a parallel combination of multiple sets of 0.1μF film capacitors, for example, 12 sets of 0.1μF capacitors in parallel can achieve a capacitive reactance of about 6.67μF, corresponding to a capacitive reactance of about 5Ω; after connecting these loads to the loop in a star connection mode, use the impedance analyzer to measure the equivalent impedance, if the measured value deviates from the target value, for example, the target is 20Ω, but the measured value is 22Ω, then fine-tune the inductive load inductance, increase 0.5mH to increase the inductive reactance to 8.5Ω, or reduce the capacitive load capacitance, reduce 1 set of capacitors to increase the capacitive reactance to 5.5Ω, until the equivalent impedance is stable at 20Ω±1Ω, impedance angle 35°±2°, to accurately set the initial state of the grid impedance consistent with the real grid light load condition.

[0028] Step 2.2, according to the initial state, trigger the dynamic mutation of the grid impedance by controlling the change rate of the load current, specifically including: according to the initial impedance state, first measure the initial load current through the current sensor, for example, 2A; use a step switching method combined with real-time feedback adjustment to control the change rate of the load current: the resistive load uses a step design of 5Ω per group, with an initial switching interval of 50ms, and simultaneously collects the loop current at a sampling frequency of 1kHz in real time; if the current change rate is less than 5A / s, for example, only 4A / s, then shorten the switching interval to 40ms; if it is higher than 10A / s, for example, up to 12A / s, then extend the switching interval to 60ms, so that the current change rate is stable at about 8A / s and lasts for 50ms; on this basis, reduce the inductive load inductance at a rate of 0.1mH / ms, for example, from 25mH to 20mH at this rate, while increasing the capacitive load capacitance at a rate of 0.1μF / ms, for example, from 6.67μF to 8.67μF at this rate, so that the loop equivalent impedance decreases rapidly with the increase of current, accurately reproducing the dynamic coupling process of current surge and impedance drop when industrial motor starts, triggering the dynamic mutation of the grid impedance.

[0029] Step 2.3, based on dynamic mutation, to monitor the rapid switching process of the grid impedance from high impedance value to low impedance value, specifically including: after the grid impedance dynamic mutation trigger, enable the voltage and current synchronous acquisition module with a sampling frequency of 1 kHz to obtain the instantaneous voltage and current values of the test loop in real time, and obtain the instantaneous impedance value by calculating the ratio of the voltage effective value to the current effective value; focus on monitoring the switching process of the impedance from the initial high value interval (15Ω to 30Ω) to the low value interval (3Ω to 8Ω), record the starting time of each switching, such as the time when the current change rate meets the standard, the ending time, such as the time when the impedance stabilizes at a low value, and the overall impedance change curve; by comparing the actual industrial motor starting impedance switching time, usually 100ms to 300ms, ensure that the impedance switching time interval in the test platform is controlled within this range, and the maximum fluctuation amplitude of the impedance during the switching process does not exceed ±0.5Ω, so as to accurately reproduce the rapidity and stability of the impedance mutation in the actual power grid.

[0030] Step 2.4, by maintaining the rapid switching process, a dynamic impedance scenario with a preset change rate is formed, specifically including: first, conduct field research on the start-stop cycle of high-frequency equipment in the industrial park, such as fans and small machine tool motors, and statistically obtain the average start-stop interval of 5s to 15s; in the test platform, when the impedance completes the switching from the high value interval 15Ω to 30Ω to the low value interval 3Ω to 8Ω and maintains for 200ms, adjust the load parameters in reverse at a rate of 0.3Ω / ms: reduce the number of connected resistive loads, increase the inductance of inductive loads, or reduce the capacitance of capacitive loads, so that the impedance rises to the high value interval and maintains for 200ms, thus forming a complete switching cycle; the total duration of each cycle needs to be controlled between 5s to 15s, and the impedance change rate needs to be kept at 0.1Ω / ms to 0.3Ω / ms; continue to run for 3 to 5 minutes, during which the stability of the cycle is monitored and verified in real time to ensure that the dynamic impedance scenario change cycle is completely consistent with the cycle characteristics of the actual power grid equipment frequent start-stop, providing a real impedance time-varying environment for the synergistic effect of multiple characteristic harmonic disturbances.

[0031] In the embodiment of the present application, the initial state of the grid impedance is set based on the constructed comprehensive test environment, which lays a stable and real grid-adapted foundation for dynamic mutation simulation. The dynamic mutation of the grid impedance is triggered by controlling the change rate of the load current, which accurately reproduces the sudden impedance change condition caused by the start-stop of high-power equipment in the actual grid. The rapid switching process of the grid impedance from high impedance value to low impedance value is monitored to ensure that the amplitude and timing of the impedance mutation meet the characteristics of the real scene, and the dynamic impedance scene with the preset change rate is maintained. This can provide a reliable impedance change basis for the subsequent cooperative coupling with the specific proportion of multiple characteristic harmonics, effectively reproduce the core characteristics of the dynamic impedance mutation in the actual grid, and help to accurately capture the performance of the power carrier communication chip when responding to the impedance mutation, providing key support for comprehensive evaluation of the communication reliability of the chip under complex interference.

[0032] In a preferred embodiment of the present application, step 3 can include: Step 3.1, according to the time-varying characteristics of the dynamic impedance scene, determine the generation parameter configuration of each characteristic harmonic, specifically including: first, by real-time monitoring of the formed dynamic impedance scene, record the switching period of 5s to 15s within the impedance interval of 3Ω to 30Ω, and the change rate of 0.1Ω / ms to 0.3Ω / ms of the impedance from high to low and from low to high in each period; combined with the operation data of the actual grid nonlinear load such as rectifier and frequency converter, determine that the characteristic harmonics to be simulated are 5 and 7, which have the highest frequency and largest amplitude ratio in the industrial park distribution network; the fundamental frequency is set to the grid standard 50Hz, so the 5th harmonic frequency is 5x50Hz=250Hz, and the 7th harmonic frequency is 7x50Hz=350Hz; according to the attenuation law of dynamic impedance to harmonic signal, when the impedance is in the low value interval of 3Ω to 8Ω, the harmonic attenuation is smaller, and the initial amplitude of 5th harmonic is set to 2V to 2.5V; when the impedance is in the high value interval of 15Ω to 30Ω, the harmonic attenuation is larger, and the initial amplitude of 5th harmonic is adjusted to 1.5V to 1.8V; at the same time, the amplitude adjustment coefficient is determined, that is, for every 1Ω decrease in impedance, the amplitude of 5th harmonic is increased by 0.1V, and for every 1Ω increase in impedance, the amplitude of 5th harmonic is decreased by 0.08V, to ensure that the generation parameters of each characteristic harmonic can be adapted in real time with the time-varying characteristics of the dynamic impedance.

[0033] Step 3.2, based on the generation parameter configuration, the order ratio relationship between the reference harmonic and the target harmonic is constructed, and the amplitude mapping relationship is established based on the principle that the corresponding sides of similar triangles are proportional, specifically including: based on the determined generation parameters, the 5th harmonic is selected as the reference harmonic and the 7th harmonic is selected as the target harmonic, because the order of these two harmonics in the actual power grid is most closely related and the proportion is stable; the order ratio relationship of the two is 5 to 7, that is, the order of the reference harmonic corresponds to 5 and the order of the target harmonic corresponds to 7; based on the principle that the corresponding sides of similar triangles are proportional, the order 5 of the reference harmonic and the order 7 of the target harmonic are taken as a pair of sides of a triangle, and the amplitude of the reference harmonic and the amplitude of the target harmonic are taken as another pair of sides of the triangle; first, the order 5 and the reference amplitude (such as 2V) of the reference harmonic are fixed, and then according to the amplitude ratio requirement of 5th and 7th harmonics 1 to 0.3 in the actual power grid, it is determined that the amplitude corresponding to the order 7 of the target harmonic needs to meet the mapping rule that the reference harmonic amplitude / target harmonic amplitude=reference harmonic order / target harmonic order, that is, 2V / target amplitude=5 / 7, through such a corresponding relationship, it is ensured that the proportion of the two pairs of sides is always consistent, thereby establishing a precise amplitude mapping relationship, so that the amplitude of the target harmonic can be adjusted in proportion with the change of the amplitude of the reference harmonic.

[0034] Step 3.3, according to the amplitude mapping relationship, the relative amplitude of each harmonic is determined by calculating the proportional coefficient of the corresponding order, and a plurality of characteristic harmonics with a predetermined proportional relationship are formed, specifically including: according to the established amplitude mapping relationship, first set the reference amplitude of the reference harmonic, i.e. the 5th harmonic, to 2V (corresponding to the low impedance interval); combined with the amplitude ratio requirement of 5th and 7th harmonics 1 to 0.3 in the actual power grid, the proportional coefficient of the target harmonic, i.e. the 7th harmonic, is calculated as 0.3, that is, the 7th harmonic amplitude=5th harmonic amplitude*0.3; thus the relative amplitude of the 7th harmonic in the low impedance interval is 2V*0.3=0.6V; when the dynamic impedance switches to the high value interval of 15Ω to 30Ω, the 5th harmonic amplitude is adjusted to 1.5V according to the adjustment coefficient of step 3.1, at this time the 7th harmonic amplitude is adjusted to 1.5V*0.3=0.45V; in the whole dynamic impedance change process, the real-time amplitude of the 7th harmonic is obtained by multiplying the current amplitude of the 5th harmonic by the fixed proportional coefficient 0.3, the predetermined proportional relationship of 1 to 0.3 is always maintained, and finally the 5th and 7th characteristic harmonics with stable proportion are formed.

[0035] Step 3.4, integrating multiple characteristic harmonics with a predetermined proportional relationship into a composite interference signal and coupling the composite interference signal into the power line channel, specifically comprising: connecting the obtained 5th and 7th characteristic harmonic signals to a signal synthesis unit, which controls the phase of the two harmonic signals through a synchronous clock to ensure that, when superimposed on the time axis, the frequency and phase relationship of the two is consistent with the characteristics of harmonic superposition in the actual power grid, avoiding proportion distortion due to phase deviation, to form a composite interference signal; adjusting the output impedance of the composite interference signal through an impedance matching network composed of adjustable resistance and capacitance, according to the real-time monitored equivalent impedance of the power line channel (3Ω to 30Ω), manually or automatically adjusting the resistance and capacitance values to control the deviation of the output impedance from the channel impedance within ±0.5Ω, preventing reflection loss during signal transmission; injecting the composite interference signal into the power line channel using a core-coupled transformer, with a transformer ratio of 1 to 1 to ensure that the signal amplitude is transmitted without attenuation, while controlling the power of the injected signal to be between 0.5W and 2W, which meets the typical power level of harmonic interference in the industrial park power distribution network, and finally realizes the synergistic effect of the composite interference signal and the dynamic impedance scenario, accurately reproducing the harsh channel conditions of the coexistence of two kinds of interference in the actual power grid.

[0036] In the embodiments of the present application, the generation parameter configuration of each characteristic harmonic is determined according to the time-varying characteristics of the dynamic impedance scenario, ensuring that the harmonic generation is adapted to the impedance variation law; based on the principle that the corresponding sides of similar triangles are proportional, the order ratio and amplitude mapping relationship of the reference harmonic and the target harmonic are constructed to ensure the accuracy of the amplitude ratio of each harmonic; the relative amplitude of each harmonic is determined by calculating the proportional coefficient to form multiple characteristic harmonics with a predetermined proportion, accurately reproducing the interference characteristics of the specific proportion composite harmonic in the actual power grid; then the composite interference signal is integrated and coupled into the power line channel, realizing the organic connection of complex harmonic interference and dynamic impedance scenario, effectively overcoming the defects that the existing test method cannot simulate specific proportion multiple characteristic harmonic interference, providing a precise and real power grid harmonic interference basis for the synergistic coupling of the two kinds of interference, and helping to comprehensively capture the performance of the power line carrier communication chip in the complex harmonic environment, further improving the authenticity and accuracy of chip communication reliability evaluation.

[0037] In a preferred embodiment of the present application, the above step 4 can include: Step 4.1, superimpose the composite interference signal on the dynamic impedance scenario to generate a combined interference effect, specifically including: using a signal coupling transformer with a synchronous trigger function to achieve time synchronization, connecting the switching control signal of the dynamic impedance scenario (such as the trigger instruction for changing the impedance from 15Ω to 3Ω) to the synchronous trigger port of the coupling device, which responds at a speed of microseconds; at the same time, the composite interference signal establishes clock synchronization with the trigger port to ensure that the amplitude adjustment instruction of the composite interference signal is issued synchronously when the dynamic impedance starts to switch; for example, when the dynamic impedance switching period is 8s, the process of the 5th harmonic in the composite interference signal rising from 1.5V to 2V completely overlaps with the process of the impedance falling from 15Ω to 3Ω on the time axis; during the superimposition process, the loop voltage and current waveforms are monitored in real time to ensure that the coupling time deviation of the composite interference signal and the dynamic impedance is less than 100μs, and finally the combined interference effect of the dynamic impedance mutation and the synergistic effect of the specific proportional harmonic interference is generated.

[0038] Step 4.2, based on the combined interference effect, trigger the dynamic change process of the signal-to-noise ratio in the power line channel, specifically including: based on the combined interference effect, collecting the useful signal power (stable at 5W) and the total power of the combined interference signal in the power line channel through high-precision power detection devices; when the dynamic impedance is in the low value interval and the composite harmonic amplitude is high, the total interference power rises from 2W to 8W; when the dynamic impedance is in the high value interval and the composite harmonic amplitude is low, the total interference power falls from 8W to 2W; the signal-to-noise ratio is calculated by the ratio of the useful signal power to the total interference power, thereby triggering the dynamic change process of the signal-to-noise ratio from 20dB to 5dB and then rising to 20dB, and the change rhythm is consistent with the 8s switching period of the dynamic impedance, which conforms to the real law that the signal-to-noise ratio suddenly drops when the interference in the actual power grid is enhanced.

[0039] Step 4.3, according to the dynamic change process of the signal-to-noise ratio, construct a frequency-selective fading model, specifically including: according to the dynamic change process of the signal-to-noise ratio, selecting the fundamental frequency 50Hz, the 5th harmonic 250Hz, and the 7th harmonic 350Hz as the key frequency points, and using a spectrum analyzer to measure the signal attenuation at each frequency point under different signal-to-noise ratios; when the signal-to-noise ratio drops to 5dB, the 250Hz signal attenuates by 10dB, the 350Hz signal attenuates by 12dB, and the 50Hz signal attenuates by 5dB; when the signal-to-noise ratio rises to 20dB, the 250Hz signal attenuates by 3dB, the 350Hz signal attenuates by 4dB, and the 50Hz signal attenuates by 1dB; based on these data, a correlation is established that the higher the signal-to-noise ratio, the smaller the high-frequency harmonic attenuation; the lower the signal-to-noise ratio, the more obvious the high-frequency harmonic attenuation, and a frequency-selective fading model that dynamically changes with the signal-to-noise ratio is fitted to accurately reflect the differentiated attenuation characteristics of different frequency signals in the actual power grid.

[0040] Step 4.4, by integrating the joint interference effect, the dynamic change process of signal-to-noise ratio and the frequency selective fading model, a coupled interference environment capable of continuously reproducing the actual channel bad conditions is formed, specifically including: connecting the joint interference effect, the dynamic change process of signal-to-noise ratio and the frequency selective fading model into a coordinated regulation system through the data interaction link; in the regulation system, the intensity change of the joint interference effect drives the real-time adjustment of the signal-to-noise ratio, and the change of the signal-to-noise ratio synchronously triggers the update of the frequency attenuation amount in the frequency selective fading model, and the three cyclically act in a period of 5s to 15s; during the period, the voltage waveform, the signal-to-noise ratio value and the frequency attenuation data in the coupled environment are continuously collected, and the same data in the same period of the industrial park power distribution network under bad working conditions, such as the morning peak, are collected; the key indicators of the two types of data are compared: the dynamic impedance variation range deviation is less than or equal to 3Ω, the composite harmonic amplitude deviation is less than or equal to 0.1V, the signal-to-noise ratio variation range deviation is less than or equal to 2dB, and the frequency attenuation amount deviation is less than or equal to 1dB; if all the indicator deviations are controlled within 5% and there is no data jump in continuous operation, it can be verified that the coupled interference environment formed can continuously reproduce the bad conditions of the coordinated action of dynamic impedance mutation, composite harmonic interference, signal-to-noise ratio drop and frequency selective fading in the actual channel, and provide a real test scene for the power carrier communication chip.

[0041] The specific construction and training process of the frequency selective fading model is as follows: The frequency selective fading model of the application is to reproduce the differentiated attenuation characteristics of different frequency signals under the coordinated action of the dynamic change of signal-to-noise ratio and the dynamic impedance mutation and the composite harmonic interference in the power line channel, The premise of model construction needs to clarify the core associated elements and data basis: first, determine the input and output dimensions of the model, the input variables focus on the key interference parameters of the test scene of the application, including the real-time signal-to-noise ratio of the power line channel, the current dynamic impedance value with a dynamic range of 5dB to 20dB, the real-time amplitude of the 5th harmonic, i.e. 250Hz, and the 7th harmonic, i.e. 350Hz, and the stable parameter of the fundamental frequency, i.e. 50Hz, and the signal attenuation amount of each core frequency point, focusing on the attenuation values of the fundamental frequency 50Hz, the 5th harmonic 250Hz and the 7th harmonic 350Hz, which are the core characteristic frequencies of the industrial park power distribution network and the key working frequency bands of the power carrier communication.

[0042] The data is derived from a coupling interference environment test. In the process of periodically switching the dynamic impedance in the range of 3Ω to 30Ω, the complex harmonic amplitude is proportionally changed, the ratio of 5 times to 7 times is 1 to 0.3, the signal power of each frequency point under different signal-to-noise ratios is continuously collected by a spectrum analyzer, the attenuation is calculated, the attenuation is the signal power without interference minus the signal power under interference, the impedance value and the harmonic amplitude at the corresponding time are recorded synchronously, the original data set containing the signal-to-noise ratio, the impedance value, the harmonic amplitude and the attenuation of each frequency is formed, and the data is highly consistent with the actual power grid harsh working conditions.

[0043] The model structure adopts the design idea of frequency correlation and working condition adaptation, does not depend on complex algorithms, and focuses on the original attenuation law of the invention. The modeling is split by frequency dimension, and the attenuation prediction branches of fundamental wave, 5th harmonic and 7th harmonic are established respectively, because the attenuation characteristics of the three types of frequencies under interference are significantly different, and the high-frequency harmonic attenuation is more obvious. Each branch takes signal-to-noise ratio as the core driving factor, and simultaneously integrates the correction terms of dynamic impedance value and harmonic amplitude. When the impedance decreases and the harmonic amplitude increases, the attenuation is positively corrected, and the attenuation increases; when the impedance increases and the harmonic amplitude decreases, the attenuation is inversely corrected, and the attenuation decreases, which conforms to the actual law that the lower the impedance, the stronger the interference, and the more significant the signal attenuation. The attenuation priority rules measured by the invention are embedded, under the same signal-to-noise ratio, the 7th harmonic attenuation is greater than the 5th harmonic attenuation, which is greater than the fundamental wave attenuation, which ensures that the model output conforms to the measured characteristics of weak high-frequency anti-interference ability and strong low-frequency anti-interference ability.

[0044] The training process of the model is based on the iterative calibration of the measured data: first, the data set is divided, and the original data set collected is divided into a training set and a verification set in a ratio of 7 to 3, the training set covers all working condition combinations, different signal-to-noise ratios, impedance values and harmonic amplitudes, and the verification set selects extreme working condition data, such as signal-to-noise ratio 5dB, impedance 3Ω and harmonic amplitude peak value, signal-to-noise ratio 20dB, impedance 30Ω and harmonic amplitude valley value, to ensure the comprehensiveness of training and verification. When setting the training target, the deviation between the model predicted attenuation and the measured attenuation is not more than 1dB as the core target, and this threshold is derived from the verification standard, which ensures that the model accuracy meets the reliability requirements of the test platform.

[0045] The model is trained by using the training set data in the iterative calibration process to learn the correlation between each input variable and the attenuation, and the attenuation coefficients in different signal-to-noise ratio intervals are calibrated. In the strong interference interval of 5dB to 10dB, the correction weight of the harmonic amplitude and the impedance value is strengthened. In the weak interference interval of 15dB to 20dB, the correction term is weakened, and the dominant role of the signal-to-noise ratio is highlighted. After each iteration, the prediction deviation is verified by using the verification set data. If the deviation of a certain frequency point exceeds 1dB, the measured data under the working condition is supplemented for retraining until the prediction deviation of all core frequency points is stabilized within the threshold. After the training is completed, the model is embedded into the signal processing module of the test platform to receive the signal-to-noise ratio, impedance value and harmonic amplitude data of the channel in real time, and output the prediction results of the attenuation at each frequency. The prediction results are compared with the measured attenuation of the spectrum analyzer in real time.

[0046] If the prediction deviation of more than 95% of the time in the continuous 1-hour operation does not exceed 1dB, and the deviation does not exceed 1.5dB in the transient process of dynamic impedance switching, such as 30Ω sudden drop to 3Ω, and signal-to-noise ratio sudden drop, such as 20dB to 5dB, the model passes the verification. If there is a working condition with excessive deviation, the measured data under the working condition is supplemented, such as the attenuation data under a specific impedance and harmonic combination, and the model correction term weight is fine-tuned to ensure that the model can adapt to all dynamic interference scenarios of the test platform. Finally, a complete frequency selective fading model is obtained, which realizes the core function of inputting real-time interference parameters and accurately outputting the attenuation at each frequency, and provides key technical support for the construction of the coupled interference environment.

[0047] In the embodiment of the present application, the composite interference signal and the dynamic impedance scene are superimposed to generate a joint interference effect, which accurately reproduces the core scene of dynamic impedance mutation and the synergistic effect of specific proportional multiple characteristic harmonics in the actual power grid, effectively making up for the technical defects that the existing test method cannot simulate the coupling of double interference; based on the joint interference effect, the dynamic change of the signal-to-noise ratio in the power line channel is triggered, which conforms to the real law that the signal-to-noise ratio suddenly drops when the interference is enhanced in the actual power grid; the frequency selective fading model is constructed according to the dynamic change process of the signal-to-noise ratio, which further restores the deterioration mechanism of the channel transmission characteristics; finally, by integrating the joint interference effect, the dynamic change of the signal-to-noise ratio and the frequency selective fading model, a coupled interference environment that can continuously reproduce the actual channel harsh conditions is formed, which provides a test condition highly consistent with the real application scene for the power carrier communication chip, and helps to comprehensively and accurately capture the carrier synchronization, equalization algorithm performance and communication stability of the chip under complex coupled interference, effectively improving the authenticity and effectiveness of the actual communication reliability evaluation of the chip, and providing accurate test basis for chip optimization and improvement.

[0048] In a preferred embodiment of the present application, the above step 5 can include: Step 5.1, in the coupling interference environment, triggering the communication process of the power carrier communication chip, specifically comprising: the sending end and the receiving end of the power carrier communication chip to be tested are connected to the power line channel of the coupling interference environment constructed by the twisted shielded wire respectively, and the shield layer is single-ended grounded to eliminate common-mode interference; the sending end prewrites a standard test data packet, which contains 1000 frames of continuous data, and each frame structure is that the first 32 bytes of the frame header contain the frame number and the starting identifier, 1024 bytes of service data simulate the voltage, current and power acquisition information in the smart grid, and the 32 bytes of check bits use CRC16 algorithm, the polynomial used in the algorithm is x 16 +x 15 +x 2 +1, wherein x is a bit position variable in a binary polynomial, and its index corresponds to the bit sequence number of a binary number, which is used to generate check bits by bit operation to detect data transmission errors; the working voltage of the chip is set to 3.3V, which is the typical working voltage, and the initial communication rate is 1Mbps, which is the nominal maximum rate of the chip, and the chip enable pin is used to send a start signal to trigger the chip to enter a continuous communication state; at this time, the dynamic impedance in the coupling interference environment is periodically switched from 3Ω to 30Ω, the composite harmonic is 5 times 2V and 7 times 0.6V, and the frequency selective fading is adjusted according to the signal-to-noise ratio, which synchronously acts on the communication link to ensure that the chip continuously completes the encoding, modulation, sending and receiving demodulation of data under the complex interference consistent with the actual industrial park power grid.

[0049] Step 5.2, based on the communication process, real-time monitoring of the chip communication error rate, data transmission delay and communication rate stability, get real-time monitoring results, including: based on the communication process, using a special error rate test module to connect the sending end and the receiving end, the module has real-time byte comparison function, the sending end every output a frame of data, the module is synchronous capture of original data and receiving end demodulated recovery data, through the byte by byte comparison of the difference between the two, statistics of the number of error bytes; set every 10 seconds for a statistical window, calculate the error byte number and the total byte number in the window ratio, get the communication error rate of this period, wherein the total byte number is the number of frames transmitted in 10 seconds multiplied by 1088 bytes, if there is no complete frame transmission in the window, it is marked as invalid value; through the time stamp unit with GPS synchronous function, the synchronization error of the unit is not more than 10 ns, the sending time stamp accurate to nanosecond is embedded in the frame header of each frame data in the sending end; the receiving end parses the time stamp, immediately records the local receiving time of the time stamp, the difference between the two is the transmission delay of single frame data, the delay value is calculated and stored in real time after each frame transmission is completed, finally the maximum value, the minimum value and the arithmetic mean value of all frame delays in each second are calculated; using the rate monitoring unit with sampling frequency of 1 kHz, real-time acquisition of the total byte number received by the receiving end per second, converted to the current communication rate, the calculation method is byte number multiplied by 8 and then divided by 1000, unit is kbps; compare the rate with the initial set 1 Mbps reference value of the chip, calculate the rate fluctuation amplitude per second, the calculation method is (measured rate-1000) / 1000x100%; all monitoring data are recorded in time sequence, accurate to millisecond, written into data log, forming multi-dimensional real-time monitoring results including error rate, transmission delay and rate stability.

[0050] Step 5.3, according to the real-time monitoring results, record the adaptive switching performance of the chip under different modulation modes, specifically including: according to the real-time monitoring results, combined with the characteristic parameters of the modulation mode in the chip manual, preset the switching trigger threshold of three kinds of modulation modes: when the error rate of the continuous 3 10-second windows exceeds 1%, trigger the switching from the high-speed modulation mode OFDM256QAM, 64 subcarriers, symbol rate 50kSymbol / s to the medium-speed mode OFDM64QAM, 64 subcarriers, symbol rate 50kSymbol / s; when the error rate rises to 5% and does not decrease for 2 consecutive windows, trigger the switching to the low-speed anti-interference mode BPSK, single carrier, symbol rate 12.5kSymbol / s; through the mode state output pin of the chip, high level represents 256QAM, medium level represents 64QAM, and low level represents BPSK, connect the digital oscilloscope sampling rate 1MHz to capture the level jump in real time, record the accurate time of each switching to the millisecond; at the same time, extract the error rate, transmission delay mean, and rate fluctuation amplitude of the last 10-second window before switching, and the same indicators of the first 10-second window after switching, compare and analyze the switching effect, such as whether the error rate is reduced to below 1% after switching from 256QAM to 64QAM, whether the delay mean value is reduced, and whether the rate is stable at about 1Mbps, record the trigger condition, mode type and performance index change trend of each switching, and present the adaptive switching performance of the chip under complex interference.

[0051] Step 5.4, integrate the communication bit error rate, data transmission delay, communication rate stability and adaptive switching performance to form a structured performance test data set, including: the real-time monitoring data and the real-time parameters of the coupled interference environment are recorded once every second, the current impedance value, the 5th and 7th harmonic amplitude, the signal-to-noise ratio is associated by time stamp to form a basic data chain; the communication bit error rate is classified and counted according to the modulation mode, the total duration, the average bit error rate, the arithmetic mean of all window bit error rates, the maximum bit error rate and the number of times the bit error rate exceeds the threshold are calculated; the data transmission delay is grouped according to the frame number, the distribution interval of each group delay is calculated, 0 to 50 ms, 50 to 100 ms, 100 ms and above, and the proportion of each interval, and the delay mean and standard deviation of each modulation mode are calculated; the communication rate stability takes the rate fluctuation amplitude of each mode as an index, and the time proportion of the fluctuation amplitude within plus or minus 5%, plus or minus 10%, and above plus or minus 10% is calculated, and the time when the maximum fluctuation amplitude occurs; the adaptive switching performance is sorted according to the logic chain of trigger threshold, pre-switching index, switching mode, post-switching index, and improvement effect, and whether each switching achieves the expected effect such as whether the bit error rate decreases to within the threshold is marked; finally, these classified statistical data are integrated into a structured table, the table contains seven dimensions of time accurate to seconds, impedance, harmonic amplitude, signal-to-noise ratio, modulation mode, bit error rate, transmission delay mean, distribution, rate stability fluctuation amplitude, proportion, switching performance trigger condition, and effect, forming a complete performance test data set.

[0052] In the embodiment of the present application, the power carrier communication chip is placed in a coupling interference environment that simulates the harsh conditions of the actual power grid to trigger the communication process. This can accurately reproduce the complex working conditions of the chip in the real application scenario, which are subject to the combined action of dynamic impedance mutation and composite harmonic interference. This effectively avoids the problem of disconnection between test results in the traditional laboratory static environment and actual application. Based on real-time monitoring of the chip's communication bit error rate, data transmission delay, and communication rate stability during the communication process, the performance of the chip under interference can be comprehensively captured from three core dimensions of communication accuracy, real-time performance, and continuity. For example, a sudden increase in the bit error rate can reflect the short board of the chip's anti-interference capability, and delay fluctuations can reveal the efficiency bottleneck of the chip in processing complex signals. Recording the adaptive switching performance of the chip under different modulation modes can further evaluate the chip's intelligent adjustment capability in dynamically adjusting the communication strategy to cope with channel deterioration, such as the timeliness and effectiveness of switching from a high-speed modulation mode to a low-speed mode with stronger anti-interference capability. The structured performance test dataset formed ultimately not only provides detailed performance short board analysis for chip design teams, helping to optimize carrier synchronization algorithms, equalization strategies, and modulation mode switching logic, but also provides systematic and practical reference data for chip selection, communication system compatibility design, and the development of related test standards in the industry, promoting the reliable landing and performance upgrade of power carrier communication technology in smart grid power consumption information collection, smart home control, and other fields.

[0053] In a preferred embodiment of the present application, step 6 can include: Step 6.1, extract the carrier synchronization response data from the performance test dataset to establish a phase tracking trajectory containing timing characteristics, specifically including: from the performance test dataset, filter out the original data related to carrier synchronization, including the receiver demodulation phase value of each frame of data, the preset reference phase value of the sender, the synchronization lock status flag bit, and the corresponding timestamp; wherein the receiver demodulation phase value is output by the chip's internal phase detector, the reference phase value is the initial phase of the sender's modulation fixed at 0 degrees, and the synchronization lock status flag bit is 1 when the synchronization is normal and 0 when the synchronization is lost; extract these data in chronological order, with a time granularity of 100 microseconds, calculate the phase error of each frame, which is the difference between the receiver demodulation phase value and the reference phase value, ranging from -180 degrees to 180 degrees; associate the calculated phase error with the corresponding time point one by one, with time as the horizontal axis in milliseconds and phase error as the vertical axis in degrees, draw a continuous curve in the coordinate system point by point to form a phase tracking trajectory containing timing characteristics; the trajectory needs to highlight the dynamic impedance switching time, such as the starting point of the 30Ω drop to 3Ω, the phase error jump corresponding to the moment of the composite harmonic amplitude mutation, such as the 5th harmonic rising from 1.5V to 2V, and the time nodes of synchronization lock and loss, to fully present the real-time variation law of the phase error under complex interference.

[0054] Step 6.2, based on the phase tracking trajectory, using the reference phase point and the phase offset angle, the received signal phase is corrected by using the coordinate transformation principle in the figure around point rotation algorithm to evaluate the phase synchronization performance, specifically including: based on the established phase tracking trajectory, the reference phase value 0 degrees of the sending end is selected as the reference phase point, which corresponds to the received phase under ideal state without interference; for the received phase value of each time point in the trajectory, the difference between it and the reference phase point is calculated to obtain the phase offset angle at that time, for example, when the received phase is 5 degrees, the offset angle is 5 degrees; when the received phase is -3 degrees, the offset angle is -3 degrees; using the coordinate transformation principle in the figure around point rotation algorithm, the received signal phase coordinates are corrected in reverse around the reference phase point as the rotation center; assuming that the received phase corresponds to the coordinates (r, θ) in the polar coordinate system, where r is the signal amplitude fixed and unchanged, and θ is the phase offset angle, then the corrected coordinates are (r, 0), and the phase offset is offset by this transformation; after correction, the deviation of the corrected phase from the reference phase point is counted, the absolute value of the deviation at all times within 1 second is calculated, the maximum value is taken as the maximum deviation, the arithmetic mean is taken as the average deviation, and the duration of the deviation exceeding 5 degrees is recorded; if the maximum deviation is less than 8 degrees, the average deviation is less than 3 degrees, and the overage duration is shorter than 20 milliseconds, it means that the phase synchronization performance is excellent; if the maximum deviation exceeds 15 degrees or the overage duration is longer than 50 milliseconds, it means that there is a lag or out-of-step problem in phase synchronization, so as to complete the quantitative evaluation of phase synchronization performance.

[0055] Step 6.3, according to the phase synchronization performance, by monitoring the change process of the equalizer tap coefficient, to analyze the convergence speed and stability of the equalization algorithm under the dynamic impedance change and complex harmonic interference, that is, to analyze the convergence characteristics of the equalization algorithm, specifically including: according to the evaluated phase synchronization performance, two key analysis intervals are divided; one is the phase synchronization fluctuation period, such as 0 to 500 milliseconds after the dynamic impedance switching, corresponding to the period when the phase error is more than 8 degrees, and the other is the phase synchronization stable period, such as the period when the phase error is less than 3 degrees for 300 milliseconds; through the debugging interface of the chip, real-time parameter reading is supported, and the tap coefficient of the equalizer is collected every 50 milliseconds in the two intervals; the tap coefficient is a set of continuous values, such as 16 coefficients corresponding to 16 taps, reflecting the compensation amplitude of the equalizer for different frequency components; when analyzing the convergence speed, the tap coefficient is recorded from the initial value, the default value of the chip after power-on, to the time when the change amount of the collected value for three consecutive times is less than 0.01 relative to the initial value, which is the convergence time; for example, the convergence time is 300 milliseconds in the fluctuation period and 150 milliseconds in the stable period, indicating that the convergence speed decreases slightly when the interference is strong, but it is still within a reasonable range; when analyzing the stability, the standard deviation of the tap coefficient in the stable period is calculated, and if the standard deviation is less than 0.02, it indicates that the coefficient fluctuation is small and the stability is good; at the same time, observe the harmonic amplitude synchronous promotion when the dynamic impedance decreases from 30Ω to 3Ω, the adjustment amplitude of the tap coefficient, such as the maximum coefficient from 0.5 to 0.8, if the adjustment amplitude is positively related to the interference intensity and can be quickly stabilized, it indicates that the equalization algorithm has strong adaptability to dynamic interference.

[0056] Step 6.4, the phase synchronization performance and the equalization algorithm convergence characteristics are integrated to build a chip adaptability evaluation mechanism, and a communication reliability determination result is formed, which specifically includes: the maximum deviation, the average deviation, and the over-deviation duration of the phase synchronization performance index are integrated with the equalization algorithm convergence characteristic index of the fluctuation period convergence time, the stable period convergence time, and the stable period coefficient standard deviation to build a chip adaptability evaluation mechanism; weights are assigned to each index, the phase synchronization performance accounts for 40%, of which the maximum deviation accounts for 15%, the average deviation accounts for 15%, and the over-deviation duration accounts for 10%; the equalization algorithm convergence characteristics account for 60%, of which the fluctuation period convergence time accounts for 20%, the stable period convergence time accounts for 20%, and the stable period coefficient standard deviation accounts for 20%; according to the requirement of the industrial park power grid on the communication reliability, such as the bit error rate needs to be lower than 1%, the qualified threshold of each index is set, the maximum deviation is less than or equal to 10 degrees, the average deviation is less than or equal to 5 degrees, the over-deviation duration is less than or equal to 30 milliseconds, the fluctuation period convergence time is less than or equal to 500 milliseconds, the stable period convergence time is less than or equal to 200 milliseconds, and the stable period coefficient standard deviation is less than or equal to 0.03; the test data is compared with the threshold, each index is scored according to the standard degree, 100 points for complete standard, and 0 points for complete non-standard, the comprehensive score is calculated according to the weight; the comprehensive score is greater than or equal to 90 points, which indicates that the chip has strong adaptability under complex interference; 70 points to 89 points is qualified, which basically meets the actual application requirement; less than 70 points is unqualified, and the synchronization and equalization algorithm needs to be optimized, and finally the communication reliability determination result including the comprehensive score, each index detail, and improvement suggestion is formed, In the embodiment of the application, by extracting carrier synchronization response data from the performance test data set and establishing a phase tracking trajectory containing timing characteristics, the timing law of the chip under the synergistic action of dynamic impedance change and complex harmonic interference can be accurately captured, providing a concrete data analysis basis for in-depth analysis of phase synchronization performance. Based on the phase tracking trajectory, the reference phase point and the phase deviation angle are used, and the coordinate transformation principle in the graphic point rotation algorithm is used to rotate and correct the phase of the received signal. This method can intuitively and accurately quantify the phase deviation, effectively avoiding the defects of traditional evaluation methods that cannot accurately depict the details of phase synchronization under dynamic interference, and effectively improving the accuracy and relevance of phase synchronization performance evaluation. By monitoring the change process of the equalizer tap coefficient to analyze the convergence speed and stability of the equalization algorithm, the core working characteristics of the equalization algorithm in a complex dynamic interference environment can be deeply mined, filling the gap in existing evaluations that only focus on surface communication indicators while ignoring the internal convergence mechanism of the algorithm, providing a direct technical basis for optimizing the equalization algorithm. Finally, the chip adaptability evaluation mechanism is constructed by comprehensively considering the phase synchronization performance and the convergence characteristics of the equalization algorithm, and the communication reliability determination result is no longer limited to the appearance evaluation of external communication indicators, but is deep into the adaptation ability level of the core algorithm of the chip, realizing the comprehensive and deep determination of the communication reliability of the chip in the actual power grid harsh working conditions, providing detailed support for the iterative optimization of the core algorithm of the chip, the perfection of the communication protocol and the accurate adaptation of the actual application scene, and effectively promoting the realization of more stable and reliable communication of the power carrier communication chip in the complex power grid environment.

[0057] As shown in Figure 2 The embodiment of the application also provides a power carrier communication chip function test system, which comprises: A construction module is configured to construct a power line channel simulation test platform, simulate voltage fluctuation and power rapid switching conditions in an actual power grid by dynamically adjusting power supply output and load switching, and the like. A simulation module is configured to simulate a dynamic mutation process of power grid impedance by controlling a change rate of load current in the power line channel simulation test platform. A processing module is configured to generate an interference signal containing multiple characteristic harmonics based on a preset harmonic order proportion relationship while simulating the dynamic mutation of impedance, coordinate set amplitudes of each harmonic according to the proportion relationship of corresponding orders by establishing an amplitude proportion coefficient between a reference harmonic and a target harmonic, and obtain multiple characteristic harmonics with a predetermined proportion relationship, and the like. A coordination module is configured to form a coupled interference environment in the test platform based on the synergistic action of the multiple characteristic harmonics with the predetermined proportion relationship and the dynamic mutation process of the impedance, and reproduce phenomena of sudden signal-to-noise ratio drop and frequency selective fading in an actual channel. The test module is used for testing key communication performance indexes of the power carrier communication chip in a coupling interference environment, and obtaining performance test data. The evaluation module is used for analyzing carrier synchronization response of the chip, i.e., the power carrier communication chip, based on the performance test data, evaluating phase tracking behavior by using a reference phase point and a phase offset angle and based on a coordinate transformation principle, combining equalization algorithm convergence characteristics, evaluating adaptability of the chip to dynamic impedance changes and complex harmonic interference, and finally determining communication reliability of the chip under actual channel conditions.

[0058] The above is the preferred embodiment of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should also be considered within the scope of protection of the present application.

Claims

1. A power line carrier communication chip function test method, characterized by, The method comprises: The power line channel simulation test platform is constructed by dynamically adjusting the power supply output and the load switching to simulate the voltage fluctuation and power fast switching working condition in the actual power grid; In the power line channel simulation test platform, the dynamic mutation process of the grid impedance is simulated by controlling the change rate of the load current; While simulating the dynamic mutation of the impedance, based on the preset harmonic order proportion relationship, an interference signal containing multiple characteristic harmonics is generated, the amplitude of each harmonic is set according to the proportion relationship of the corresponding order by establishing the amplitude proportion coefficient between the reference harmonic and the target harmonic, and the multiple characteristic harmonics with the predetermined proportion relationship are obtained, and the interference signal is coupled to the power line channel; Based on the synergistic effect of the multiple characteristic harmonics with the predetermined proportion relationship and the dynamic mutation process of the impedance, a coupled interference environment is formed in the test platform to reproduce the phenomena of signal-to-noise ratio drop and frequency selective fading in the actual channel; In the coupled interference environment, the key communication performance indicators of the power line carrier communication chip are tested to obtain performance test data; Based on the performance test data, the carrier synchronization response of the chip, i.e., the power line carrier communication chip, is analyzed, the phase tracking behavior is evaluated by using the reference phase point and the phase offset angle and based on the coordinate transformation principle, and the adaptability of the chip to the dynamic impedance change and complex harmonic interference is evaluated in combination with the convergence characteristics of the equalization algorithm to finally determine the communication reliability of the chip under the actual channel conditions.

2. The power line carrier communication chip function test method according to claim 1, wherein, The power line channel simulation test platform is constructed by dynamically adjusting the power supply output and the load switching to simulate the voltage fluctuation and power fast switching working condition in the actual power grid, comprising: A voltage signal conforming to the preset fluctuation range is generated through the output voltage of the power supply of the test platform; Based on the voltage signal, the switching state of the load power is obtained by controlling the switching state of the resistance-capacitance-inductance hybrid load to make the load power quickly switch between the preset low valley load and peak load; According to the switching state of the load power, the parameter configuration of the load component is adjusted to form a load working condition with a specific power factor characteristic; The fluctuation characteristics of the voltage signal, the switching characteristics of the load power, and the power factor characteristics of the load working condition are systematically integrated to construct a comprehensive test environment that can accurately reproduce the actual power grid operation characteristics, i.e., correctly construct the power line channel simulation test platform.

3. The power line communication chip function test method of claim 2, wherein, In the power line channel simulation test platform, the dynamic mutation process of the grid impedance is simulated by controlling the change rate of the load current, comprising: Based on the comprehensive test environment, the initial state of the grid impedance is set; According to the initial state, the dynamic mutation of the grid impedance is triggered by controlling the change rate of the load current; Based on the dynamic mutation, the rapid switching process of the grid impedance from high impedance value to low impedance value is monitored; By maintaining the rapid switching process, a dynamic impedance scenario with a preset change rate is formed.

4. The power line carrier communication chip function test method according to claim 3, wherein, The interference signal containing multiple characteristic harmonics is generated based on the preset harmonic order ratio relationship while simulating the dynamic mutation of the impedance, the amplitude ratio coefficient between the reference harmonic and the target harmonic is established, the amplitudes of the harmonics are coordinated according to the ratio relationship of the corresponding orders, the multiple characteristic harmonics with the predetermined ratio relationship are obtained, and the interference signal is coupled to the power line channel, including: According to the time-varying characteristics of the dynamic impedance scene, the generation parameter configuration of each characteristic harmonic is determined; Based on the generation parameter configuration, the order ratio relationship between the reference harmonic and the target harmonic is constructed, and the amplitude mapping relationship is established based on the principle that the corresponding sides of similar triangles are proportional; According to the amplitude mapping relationship, the relative amplitude of each harmonic is determined by calculating the proportional coefficient of the corresponding order, and the multiple characteristic harmonics with the predetermined ratio relationship are formed; The multiple characteristic harmonics with the predetermined ratio relationship are integrated into a composite interference signal, and the composite interference signal is coupled into the power line channel.

5. The method of claim 4, wherein, Based on the synergistic effect of the multiple characteristic harmonics with the predetermined ratio relationship and the dynamic mutation process of the impedance, a coupled interference environment is formed in the test platform to reproduce the signal-to-noise ratio drop and frequency selective fading phenomenon in the actual channel, including: The composite interference signal is superimposed with the dynamic impedance scene to produce a joint interference effect; Based on the joint interference effect, the dynamic change process of the signal-to-noise ratio in the power line channel is triggered; According to the dynamic change process of the signal-to-noise ratio, a frequency selective fading model is constructed; By integrating the joint interference effect, the dynamic change process of the signal-to-noise ratio, and the frequency selective fading model, a coupled interference environment is formed which can continuously reproduce the harsh conditions of the actual channel.

6. The method of claim 5, wherein, In the coupled interference environment, the key communication performance indicators of the power line carrier communication chip are tested to obtain performance test data, including: In the coupled interference environment, the communication process of the power line carrier communication chip is triggered; Based on the communication process, the communication bit error rate, data transmission delay, and communication rate stability of the chip are monitored in real time to obtain real-time monitoring results; According to the real-time monitoring results, the adaptive switching performance of the chip under different modulation modes is recorded; The communication bit error rate, data transmission delay, communication rate stability, and adaptive switching performance are integrated to form a structured performance test data set.

7. The method of claim 6, wherein the power carrier communication chip function test method is characterized by, Based on the performance test data, the carrier synchronization response of the chip, i.e., the power line carrier communication chip, is analyzed, the reference phase point and phase offset angle are used, and the phase tracking behavior is evaluated based on the coordinate transformation principle, combined with the convergence characteristics of the equalization algorithm, to evaluate the adaptive ability of the chip to dynamic impedance changes and complex harmonic interference, and finally determine the communication reliability of the chip in actual channel conditions, including: Carrier synchronization response data is extracted from the performance test data set to establish a phase tracking trajectory containing timing characteristics; Based on the phase tracking trajectory, the reference phase point and phase offset angle are used, and the received signal phase is rotated and corrected using the coordinate transformation principle in the graph point rotation algorithm to evaluate the phase synchronization performance; According to the phase synchronization performance, by monitoring the change process of the equalizer tap coefficient, the convergence speed and stability of the equalization algorithm under the dynamic impedance change and complex harmonic interference are analyzed, that is, the equalization algorithm convergence characteristics are analyzed. According to the phase synchronization performance and the equalization algorithm convergence characteristics, a chip adaptability evaluation mechanism is constructed, and a communication reliability determination result is formed.

8. A power line communication chip function test system, the system implementing the method of any one of claims 1 to 7, characterized in that, The method comprises the steps of: A construction module is configured to construct a power line channel simulation test platform, and simulate voltage fluctuation and power rapid switching conditions in an actual power grid by dynamically adjusting power supply output and load switching. An analog module is configured to simulate a dynamic mutation process of the power grid impedance by controlling the change rate of the load current in the power line channel simulation test platform. A processing module is configured to generate an interference signal containing multiple characteristic harmonics based on a preset harmonic order proportion relationship while simulating the dynamic mutation of the impedance. A coordination module is configured to form a coupled interference environment in the test platform based on the coordinated action of the multiple characteristic harmonics with the predetermined proportion relationship and the dynamic mutation process of the impedance, so as to reproduce the phenomena of sudden drop of signal-to-noise ratio and frequency-selective fading in an actual channel. A test module is configured to test key communication performance indicators of the power carrier communication chip in the coupled interference environment, and obtain performance test data. An evaluation module is configured to analyze the carrier synchronization response of the chip based on the performance test data, evaluate the phase tracking behavior by using a reference phase point and a phase offset angle based on the coordinate transformation principle, and evaluate the adaptability of the chip to the dynamic impedance change and the complex harmonic interference in combination with the equalization algorithm convergence characteristics, so as to finally determine the communication reliability of the chip under actual channel conditions.

9. A computing device, comprising: The method comprises the steps of: One or more processors; A storage device is configured to store one or more programs, when the one or more programs are executed by the one or more processors, so that the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a program which is executed by the processor to implement the method according to any one of claims 1 to 7.

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