Power line carrier communication chip function test method and system

By constructing a power line channel simulation test platform, voltage fluctuations and impedance changes are dynamically simulated to generate a predetermined proportion of harmonic interference signals. This solves the problem that existing test methods cannot simulate grid cooperative interference and enables accurate reliability assessment and optimization of power line carrier communication chips.

CN121530409APending Publication Date: 2026-02-13BEIJING QIANHONG TECHNOLOGY CO LTD
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Patent Information

Application Number
CN202511591231.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-11-03
Publication Date
2026-02-13

AI Technical Summary

Technical Problem

Existing power line carrier communication chip testing methods cannot simulate the dynamic changes in power grid impedance and the coordinated interference of multiple characteristic harmonics in a specific proportion in a real power grid. This leads to a disconnect between laboratory test results and actual applications, making it difficult to accurately assess the reliability of chip communication.

Method used

A power line channel simulation test platform was constructed. By dynamically adjusting the power output and load switching, voltage fluctuations and rapid power switching conditions were simulated, generating multiple characteristic harmonic interference signals with a predetermined ratio. Combined with the dynamic impedance change process, a coupled interference environment was formed to test the key communication performance indicators of the chip and evaluate its carrier synchronization response and equalization algorithm convergence characteristics.

Benefits of technology

Accurately simulating harsh channel conditions in actual power grids exposes potential performance defects in chips, providing precise data for chip optimization and practical application selection, improving communication reliability, and promoting the large-scale application of power line carrier communication technology.

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Abstract

The invention provides a power line carrier communication chip function test method and system, and relates to the technical field of communication technology, and the method comprises the steps: constructing a power line channel simulation test platform, and simulating the voltage fluctuation and power rapid switching working condition in an actual power grid through dynamically adjusting the power output and load switching; in the power line channel simulation test platform, the dynamic sudden change process of the power grid impedance is simulated by controlling the change rate of the load current; the method comprises the following steps: generating an interference signal containing multiple times of characteristic harmonics based on a preset harmonic order proportional relation while simulating dynamic sudden change of impedance, establishing an amplitude proportional coefficient between a reference harmonic and a target harmonic, and coordinating and setting the amplitude of each harmonic according to the proportional relation of the corresponding order, so as to simulate the dynamic sudden change of the impedance. A plurality of characteristic harmonics with a predetermined proportional relationship are obtained, and an interference signal is coupled to a power line channel. The method can accurately simulate the severe channel condition of an actual power grid, and accurately evaluates the communication reliability of the chip.
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