B code multi-channel consistency test method and device based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a B code multichannel consistency test method and device based on an FPGA, and relates to the technical field of time synchronization signal test.The method comprises the steps that parallel collection is conducted on B code signals to be tested through a plurality of independent differential input circuits, each channel is provided with a programmable amplifier and a filter, common-mode interference is suppressed, and the integrity of an input signal is ensured. Capturing a rising edge and a falling edge of each channel B code pulse by using a main clock and an independent timestamp register in the FPGA to generate pulse timestamp data; according to the FPGA-based B code multichannel consistency test method and device, the precision and reliability of B code signal test are remarkably improved, the multichannel synchronization verification capability and anti-interference performance are enhanced, and the FPGA-based B code multichannel consistency test method and device are suitable for application scenes with extremely high time synchronization requirements such as electric power, telecommunication, spaceflight and target ranges.

Description

Technical Field

[0001] This invention relates to the field of time synchronization signal testing technology, specifically to a method and apparatus for B-code multi-channel consistency testing based on FPGA. Background Technology

[0002] In the field of time synchronization signal testing, B-code signals are widely used in high-precision synchronization scenarios such as power systems, telecommunications systems, aerospace telemetry and control, and test ranges due to their stable structure and wide application.

[0003] However, traditional B-code testing devices are mostly based on discrete components and small-scale integrated circuits, which have significant shortcomings in application. On the one hand, the devices rely on multi-stage frequency divider circuits and independent timestamp modules to complete signal processing, resulting in complex structures and high debugging and maintenance costs. On the other hand, affected by the delay of the frequency divider circuit and clock jitter, their timestamp accuracy is usually only on the order of 200 ns, which is difficult to meet the requirements of nanosecond-level synchronization accuracy. In addition, traditional devices also have limitations in terms of multi-channel and anti-interference capabilities. On the one hand, they generally lack the ability to process multiple B-code channels simultaneously, especially in cross-device conformance verification, where quantitative analysis methods are lacking. On the other hand, the devices are sensitive to signal noise and have difficulty distinguishing between normal signal fluctuations and malicious interference or deceptive signal characteristics, thus affecting the accuracy and reliability of the test. Summary of the Invention

[0004] The purpose of this invention is to provide a method and apparatus for multi-channel consistency testing of B-code based on FPGA, thereby solving the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a multi-channel consistency testing method for B-code based on FPGA. The method includes parallel acquisition of the B-code signal under test through multiple independent differential input circuits. Each channel is equipped with a programmable amplifier and filter to suppress common-mode interference and ensure the integrity of the input signal. The rising and falling edges of the B-code pulses in each channel are captured using the FPGA's internal master clock and independent timestamp registers to generate pulse timestamp data. Based on the B-code frame structure, the frame header pulse is identified, and pulse width analysis is performed on the pulses within each frame, mapping the analysis results to corresponding binary information bits. Difference calculations are performed on the timestamps of the same numbered pulses from multiple channels, and the synchronization deviation between channels and across devices is quantified using sliding window statistics and multi-cycle synchronous sampling algorithms. Wavelet transform or other frequency domain analysis is performed on the acquired pulse sequences to extract high-frequency noise energy characteristics. When the noise energy exceeds a preset threshold, it is determined to be an interference or deception signal, and an alarm is output. A test report containing pulse parameters, consistency deviations, and abnormal events is generated based on the analysis results, and the raw data can be exported as an offline analysis file.

[0006] Preferably, the plurality of independent differential input circuits are opto-isolated differential interfaces, and each channel is configured with a programmable amplifier with adjustable gain and a bandpass filter to simultaneously suppress low-frequency common-mode interference and high-frequency noise.

[0007] Preferably, the main clock frequency inside the FPGA is 200 MHz, and frequency multiplication and phase compensation are performed through dual PLL circuits to ensure that the resolution of the generated pulse timestamp is better than 5 ns.

[0008] Preferably, in the pulse width parsing step, the fixed pulse width of the frame header pulse is used as a reference to normalize the pulse width of subsequent pulses, and the pulse width is mapped to logic 0 or logic 1 through threshold decision.

[0009] Preferably, the sliding window statistics use a sequence of continuous pulse timestamp differences with a window length of 10 frames. When the standard deviation within the window exceeds a preset threshold, a synchronization deviation anomaly alarm is triggered.

[0010] Preferably, the multi-cycle synchronous sampling algorithm introduces an initial calibration clock offset in cross-device scenarios and dynamically compensates for the offset during testing, thereby achieving consistency verification of B-code signals across devices.

[0011] Preferably, the wavelet transform employs a multi-scale decomposition method, and calculates high-frequency energy in the third-level decomposition coefficients. When the energy value exceeds the threshold of 1000, it is determined to be a potential interference or deception signal.

[0012] Preferably, the test report includes average synchronization deviation between channels, maximum deviation, consistency ratio, and anomaly statistics, and supports output in both structured text and binary data formats.

[0013] Preferably, the offline analysis file supports importing into the matching analysis software, and the correlation between the timestamp sequences of the channels is calculated by the Pearson correlation coefficient. When the correlation coefficient is less than 0.95, it is determined to be a synchronization anomaly.

[0014] An FPGA-based B-code multi-channel consistency testing device is used to implement the steps of the FPGA-based B-code multi-channel consistency testing method. The device includes:

[0015] The multi-channel signal acquisition module is used to acquire the B-code signal under test in parallel through multiple independent differential input circuits. Each channel is equipped with a programmable amplifier and filter to suppress common-mode interference and ensure the integrity of the input signal.

[0016] The timestamp generation module, located inside the FPGA, uses the master clock and an independent timestamp register to capture the rising and falling edges of the B-code pulses of each channel and generate pulse timestamp data.

[0017] The pulse width parsing module is used to identify the frame header pulse based on the B-code frame structure, and to perform pulse width parsing on the pulses in each frame, mapping the parsing results into the corresponding binary information bits.

[0018] The consistency analysis module is used to calculate the difference between the timestamps of the same numbered pulses in multiple channels, and to quantify the synchronization deviation between channels and across devices through sliding window statistics and multi-cycle synchronous sampling algorithms.

[0019] The interference detection module is used to perform wavelet transform or other frequency domain analysis on the acquired pulse sequence to extract high-frequency noise energy characteristics, and when the energy exceeds a preset threshold, it is determined to be an interference or deception signal and an alarm is output.

[0020] The results output module is used to generate test reports containing pulse parameters, consistency deviations, and abnormal events based on the analysis results, and supports exporting raw data as offline analysis files.

[0021] As can be seen from the above technical solution, the present invention has the following beneficial effects:

[0022] This FPGA-based B-code multi-channel consistency testing method and apparatus achieves nanosecond-level capture and analysis of multi-channel B-code pulses by integrating a high-frequency master clock and an independent timestamp register within the FPGA, significantly improving synchronization accuracy. It employs a differential input circuit combined with a programmable amplifier and filter to effectively suppress common-mode interference and ensure signal integrity. High-precision mapping of information bits is achieved using frame header recognition and pulse width analysis. The introduction of sliding window statistics and multi-cycle synchronous sampling algorithms quantifies synchronization deviations between channels and across devices, thus enabling multi-channel consistency verification. Combined with wavelet transform-based anti-interference analysis, it can distinguish normal signal fluctuations from interference or spoofing signals, improving test reliability. Furthermore, the method supports generating structured reports containing pulse parameters, consistency deviations, and abnormal events, and can export offline analysis files for easy data traceability and in-depth analysis. In summary, this invention not only significantly improves the accuracy and reliability of B-code signal testing but also enhances multi-channel synchronization verification capabilities and anti-interference performance, making it suitable for applications with extremely high time synchronization requirements, such as power, telecommunications, aerospace, and test ranges. Attached Figure Description

[0023] Figure 1 This is a flowchart of the FPGA-based B-code multi-channel consistency testing method of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] like Figure 1 As shown, this invention provides a technical solution: a multi-channel consistency testing method for B-code based on FPGA. The method includes parallel acquisition of the B-code signal under test through multiple independent differential input circuits. Each channel is equipped with a programmable amplifier and filter to suppress common-mode interference and ensure the integrity of the input signal. Using the FPGA's internal master clock and independent timestamp register, the rising and falling edges of the B-code pulses in each channel are captured to generate pulse timestamp data. Based on the B-code frame structure, the frame header pulse is identified, and the pulse width of each pulse within a frame is analyzed, mapping the analysis results to corresponding binary information bits. The difference between the timestamps of the same numbered pulses from multiple channels is calculated, and the synchronization deviation between channels and across devices is quantified using sliding window statistics and multi-cycle synchronous sampling algorithms. Wavelet transform or other frequency domain analysis is performed on the acquired pulse sequences to extract high-frequency noise energy characteristics. When the noise energy exceeds a preset threshold, it is determined to be an interference or deception signal, and an alarm is output. A test report containing pulse parameters, consistency deviations, and abnormal events is generated based on the analysis results, and the raw data can be exported as an offline analysis file.

[0026] This method first employs multiple physically isolated differential input circuits, each corresponding to a different channel under test. Each differential input circuit is directly connected to the B-code signal source under test, and a differential amplification structure is used to compare the voltages of the positive and negative terminals of the input signal to eliminate common-mode interference. Each channel integrates a programmable amplifier and a low-pass filter. The amplifier gain is set via an internal register in the FPGA, typically with 8 or 16 gain levels. The initial gain value is set to 1x based on the input signal amplitude, and during calibration, it is dynamically adjusted to be as close as possible to full-amplitude input based on the maximum signal amplitude. The filter cutoff frequency is determined based on the highest pulse frequency of the B-code, usually set to within twice the upper limit of the signal frequency. For example, when the B-code pulse frequency is 1 kHz, the filter cutoff frequency is set to 2 kHz to ensure signal integrity and suppress high-frequency interference.

[0027] The FPGA's internal master clock frequency is fixed at 100 MHz, which controls a globally synchronized timestamp counter. Each channel is configured with an independent timestamp register to capture the arrival times of the rising and falling edges of the input signal. After passing through the input stage, the signal enters the edge detection module. This module detects level transitions by comparing the sampled values ​​before and after. If a transition from low to high is detected, it is marked as a rising edge event, and the current timestamp is recorded; if a transition from high to low is detected, it is marked as a falling edge event, and the timestamp is also recorded. Each transition event records a complete data structure including the channel number, time value, and edge type.

[0028] Subsequently, the pulse width is calculated for the acquired rising and falling edge time pairs. The calculation method is as follows: the difference between each pair of adjacent rising and falling edge time values ​​is used to obtain the duration of the pulse, i.e., the pulse width. According to the definition of the B-code protocol, pulse width thresholds are set to correspond to the judgment criteria of logic "0" and logic "1" respectively. The pulse width range for logic "0" is set to 1000 to 2000 nanoseconds, and the pulse width range for logic "1" is set to 3000 to 4000 nanoseconds. If the pulse width value falls within a certain range, it is mapped to the corresponding binary bit. Frame header recognition is achieved by detecting continuous high-level pulses and fixed-length interval sequences. After a successful match, the frame parsing process begins, reconstructing the entire frame structure bit by bit.

[0029] To evaluate the consistency among multiple channels, pulse timestamps with the same frame number are aligned across channels. A sliding window length of 10 frames is set, and the timestamps of pulses at the same position in each frame within the window are calculated to differentiate between corresponding pulse timestamps in channel A and channel B. The average, standard deviation, and maximum deviation are then calculated and recorded as the synchronization deviation parameter within the current window. A multi-period synchronization sampling algorithm is employed, involving repeated statistical analysis across multiple consecutive frames to ensure the stability of the sampling results and resistance to transient interference.

[0030] When performing frequency domain analysis on pulse sequences, wavelet transform is employed. First, the raw sampling data of each channel within a specified time period is converted into a discrete-time sequence. Then, wavelet decomposition is performed on this sequence, selecting a fixed wavelet basis function and setting the decomposition level to 5. High-frequency coefficient energy values ​​are extracted from each level and accumulated. A fixed noise energy threshold is set, for example, 20% of the total energy value. When the high-frequency energy of a channel exceeds this threshold during a certain time period, an abnormal high-frequency interference signal is determined to exist within that time period. To avoid false alarms, the anomaly determination only takes effect when the high-frequency exceedance condition is met for three consecutive frames, subsequently triggering an alarm output.

[0031] Finally, the parsing results of all frames in each channel are summarized, including the timestamp, pulse width, binary value, inter-channel deviation parameters, and abnormal event records for each pulse, and uniformly imported into the FPGA's built-in report generation module. This module generates a report document according to a fixed structure, with fields including frame number, channel number, pulse sequence number, pulse time, pulse width value, parsing bit value, maximum inter-channel deviation, average deviation value, and abnormal flags. The report format is a comma-separated text file, and it supports exporting the original record file via serial port, USB interface, or SD card for offline review and analysis.

[0032] Multiple independent differential input circuits provide opto-isolated differential interfaces, and each channel is configured with a programmable amplifier with adjustable gain and a bandpass filter to simultaneously suppress low-frequency common-mode interference and high-frequency noise.

[0033] This embodiment further employs an opto-isolated differential interface as the signal input circuit for each channel. This interface converts the input B-code differential signal into an isolated electrical signal via a high-speed optocoupler. The isolation voltage level is designed to be above 2500 volts to ensure high insulation performance between channels and with the external environment. The optocoupler output is connected to a programmable amplifier with adjustable gain. The amplifier uses a digitally controlled potentiometer to construct the gain control circuit, with the gain range set from 0.5 to 10 times, the specific value automatically set according to the input signal amplitude. Each channel has an amplitude detection module that monitors the peak value of the input signal in real time and determines whether it is within the desired operating range through the FPGA's internal logic. If it is below the standard, the amplification factor is increased; if it exceeds the upper limit, the gain is decreased. The amplifier output signal enters a bandpass filter, which consists of a high-pass stage and a low-pass stage. The high-pass stage filters out low-frequency common-mode interference, with a fixed cutoff frequency of 100 Hz. The low-pass stage suppresses high-frequency noise, with a cutoff frequency set to 200 kHz. The entire bandpass filter adopts a passive RC structure, and the capacitor and resistor parameters are adjustable through multi-stage digital switches. Under FPGA control, the optimal filtering bandwidth can be dynamically set according to the noise characteristics of the detected signal. The filtered signal maintains waveform integrity while significantly suppressing low-frequency power supply interference and high-frequency radio frequency noise that may exist in the working environment, providing a stable and reliable basic signal source for subsequent edge capture and timestamp recording.

[0034] The FPGA's internal main clock frequency is 200 MHz, and frequency multiplication and phase compensation are performed through dual PLL circuits to ensure that the generated pulse timestamp resolution is better than 5 ns.

[0035] In this implementation, the initial frequency of the FPGA's internal master clock is set to 200 MHz, and an onboard crystal oscillator is used to distribute the clock to each logic module via a global clock tree. To further improve timestamp resolution and eliminate phase jitter between channels, a dual phase-locked loop (PLL) structure is adopted, i.e., two cascaded PLL circuits are configured on top of the master clock. The first-stage PLL multiplies the master clock to 1 GHz, serving as a high-precision time reference source and providing a counting reference for the edge detection module. The second-stage PLL performs phase adjustment and subdivision compensation on the multiplied signal to fine-tune the phase deviation introduced by wiring differences between different channels. Each channel is independently bound to the phase-calibrated clock branch to ensure logical edge capture synchronization. The 1 GHz master clock period is 1 nanosecond, and a 0.5 nanosecond time sampling step is achieved with a 5-bit compensation logic in conjunction with the timestamp counter. When capturing rising or falling edges, the current count value is the pulse timestamp. The theoretical maximum resolution is 1 nanosecond. After dual PLL clock distribution adjustment and phase matching optimization, the actual timestamp resolution can be guaranteed to be better than 5 nanoseconds, and the cross-channel time error can be controlled within 3 nanoseconds.

[0036] In the pulse width parsing step, the fixed pulse width of the frame header pulse is used as a reference to normalize the pulse width of subsequent pulses, and the pulse width is mapped to logic 0 or logic 1 through threshold decision.

[0037] In this embodiment, the frame header pulse in the B-code data frame is first identified. The frame header pulse is the first pulse in the frame structure, with a standard and fixed pulse width, such as 2000 nanoseconds, which serves as a normalization reference for the parsing of all subsequent pulses. During pulse width parsing, the time difference between each rising edge and its corresponding falling edge is calculated to obtain the original pulse width value of the current pulse. Then, this value is divided by the pulse width of the frame header pulse to obtain a normalized ratio, which reflects the relative length of the current pulse width relative to the frame header. Two normalization threshold ranges are set: if the ratio falls between 0.4 and 0.7, it is determined as logic 0; if the ratio falls between 1.4 and 1.7, it is determined as logic 1; if the ratio is not within the above range, it is marked as an invalid pulse or error signal and does not participate in subsequent bit decoding. Throughout this process, the pulse width of the frame header pulse is always used as a dynamic reference to compensate for the overall scaling or delay distortion that may occur during signal transmission or sampling, thereby enhancing the relative consistency and stability of the parsing.

[0038] The sliding window statistics use a sequence of continuous pulse timestamp differences with a window length of 10 frames. When the standard deviation within the window exceeds a preset threshold, a synchronization deviation alarm is triggered.

[0039] In this implementation, based on the pulse timestamp information parsed from each channel, and using the frame number as a reference, the time difference between pulses at the same position in multiple channels is extracted to construct a timestamp difference sequence. The sliding window length is set to 10 frames, meaning 10 consecutive pulses with the same number constitute one window. When a new frame of data is added, the sliding window advances one frame, old data is dequeued, and new data is enqueued, maintaining a constant number of data points within the window. Within each window, the 10 time difference data points are statistically analyzed. First, the average value is calculated, and then the degree of data fluctuation is evaluated using the standard deviation formula. The standard deviation is calculated by subtracting the average value from each difference, squaring the result, summing the results, taking the square root, and dividing by the window length. A standard deviation threshold of 5 nanoseconds is set. When the standard deviation calculated within the window exceeds this threshold, it is determined that the current channel pair has a significant synchronization deviation, i.e., an abnormal synchronization state, and an alarm signal is immediately output. The relevant alarm information includes the channel pair number where the abnormality occurred, the starting frame number, the standard deviation value, and the abnormality marker timestamp. The alarm event is also written to the abnormal record area for subsequent report generation module extraction and output.

[0040] The multi-cycle synchronous sampling algorithm introduces an initial calibration clock offset in cross-device scenarios and dynamically compensates for this offset during testing, thereby achieving consistency verification of B-code signals across devices.

[0041] In this embodiment, considering that when multiple FPGA devices acquire B-code signals from different sources, the sampling timestamps will not be directly comparable due to local clock offsets in each device. Therefore, an initial clock offset calibration step is performed before the test begins. This involves injecting a standard reference pulse signal into the input channels of all test devices and recording the timestamp value of the pulse in each device. One device is selected as the reference source, and the difference between the timestamps of the remaining devices and the timestamp of the reference device is the initial clock offset. This value is stored in the FPGA's calibration register in nanoseconds.

[0042] During subsequent formal testing, each device, after recording the B-code pulse timestamp, subtracted the stored offset from its local timestamp value to align with the reference timeline. This process was continuously executed across all channels and frames to ensure a unified reference for timestamps from different devices. To address potential temperature drift or clock drift, a periodic recalibration mechanism was designed. Every 1000 frames, a new set of reference pulses was injected, the calibration process was repeated, the latest offset was calculated, and compared with historical values. If the offset change exceeded 10 nanoseconds, the offset register was automatically updated, and the magnitude of the change was recorded in a dynamic compensation log. Based on this mechanism, the timestamp data acquired in each cycle underwent dynamic offset correction before being fed into a consistency verification algorithm for inter-channel time difference comparison. Ultimately, high-precision time alignment was achieved in cross-device, multi-source input environments, providing a precise foundation for subsequent synchronization deviation analysis.

[0043] Wavelet transform employs a multi-scale decomposition method and calculates high-frequency energy in the third-level decomposition coefficients. When the energy value exceeds the threshold of 1000, it is determined to be a potential interference or deception signal.

[0044] In this embodiment, to identify potential high-frequency interference or spoofing behavior in the B-code signal, wavelet transform analysis is further performed on the original waveform data after acquiring the pulse timestamp and pulse width. The wavelet transform uses a fixed wavelet basis function, such as the Daubechies wavelet, and performs a three-level decomposition operation. This involves sequentially passing the original sampled data through first-level, second-level, and third-level wavelet filter banks to obtain the low-frequency approximation coefficients and high-frequency detail coefficients at the corresponding scales. In the third-level decomposition, the high-frequency detail coefficient sequence is extracted, and the sum of squares of all coefficients in the sequence is calculated as the measurement result of the high-frequency energy value. This energy value represents the intensity of high-frequency disturbances in the corresponding frequency band.

[0045] A high-frequency energy threshold of 1000 is set. This value is an empirical value obtained through statistical analysis of a large amount of interference-free sample data, providing a basis for engineering verification. When the third-level high-frequency energy value of a channel exceeds this threshold, it is determined that the channel contains potential interference or deceptive signals within that sampling period. Upon confirmation, an alarm message is immediately generated, recording the corresponding channel number, energy value, frame number, and timestamp, and this information is transmitted to the host computer interface for real-time notification. If the threshold is exceeded for three consecutive sampling periods, it is further marked as a persistent anomaly, and the waveform data is written to the anomaly data buffer for subsequent manual analysis or algorithmic review.

[0046] The test report includes average synchronization deviation between channels, maximum deviation, consistency ratio, and anomaly statistics, and supports output in both structured text and binary data formats.

[0047] In this implementation, after completing all processing steps including B-code signal acquisition, pulse parsing, timestamp analysis, and interference detection, the test report generation module is activated to summarize and statistically analyze the key data recorded during the test. First, based on the sliding window and multi-cycle synchronous sampling algorithm, the timestamp difference data between all channels is statistically analyzed. The average synchronization deviation is the arithmetic mean of the corresponding pulse time differences between all channels over the entire test duration, expressed in nanoseconds; the maximum deviation is the maximum value among all time differences.

[0048] The consistency ratio is calculated as follows: The proportion of samples with synchronization deviations not exceeding a preset limit (e.g., 10 nanoseconds) out of all pulses is counted, and the result is expressed as a percentage to measure the overall time synchronization quality. Anomaly statistics include all alarm events triggered by wavelet transform, high-frequency energy detection, and synchronization deviation exceeding limits. These events are categorized and counted by channel number, frame number, and anomaly type, along with auxiliary information such as the anomaly occurrence time and the number of frames the event lasted.

[0049] Regarding report output, analysis results can be exported in two formats. The structured text format uses comma-separated value text, with fields including frame number, channel number, timestamp, pulse width, logical value, synchronization deviation, anomaly marker, and energy value, making it easy for users to view directly or open for analysis in general tools. The binary data format is used for efficient storage of raw sampling data and processing results. Defined by a specific data structure, it supports loading in dedicated offline analysis software for data playback, visualization, and secondary processing. After testing, users can select the export format, file naming rules, and output path through the control interface. Exported results can be saved locally or transferred externally via an interface.

[0050] The statistical analysis of average deviation, maximum deviation, and consistency ratio in the test report helps to comprehensively evaluate the accuracy and stability of multi-channel synchronization, which is especially suitable for applications with stringent timing requirements. Meanwhile, centralized archiving of abnormal events facilitates engineers' rapid location of problematic channels and analysis of fault causes. Support for both structured text and binary format output improves data versatility and professional usability, meeting the needs of different user groups in data reading and in-depth analysis, and enhancing operability and engineering adaptability.

[0051] The offline analysis file can be imported into the accompanying analysis software, and the correlation between the timestamp sequences of the channels can be calculated using the Pearson correlation coefficient. When the correlation coefficient is less than 0.95, it is judged as a synchronization anomaly.

[0052] In this embodiment, after completing the multi-channel B-code data acquisition and preliminary processing, the data, including timestamp sequences, pulse widths, logical bits, synchronization deviations, and anomaly markers, is packaged into an offline analysis file. This file is stored in a structured format, such as binary encapsulated data blocks, with a fixed data field order and length definition, enabling it to be recognized and parsed by the accompanying dedicated analysis software. After the user imports the target offline file into the software, the software automatically extracts the pulse timestamp sequence of each channel throughout the entire testing process and pairs all channels together to construct a timestamp sequence vector.

[0053] For any two channels, the analysis software calculates the Pearson correlation coefficient for their timestamp sequences. The calculation process includes: first, averaging the timestamp sequences of both channels; then, calculating the deviation of each timetamp from the average value for each channel; next, multiplying these deviations and summing them as the covariance; then, calculating the square root product of the sum of the squares of the deviations for each channel as the standardization factor; finally, dividing the covariance by the standardization factor to obtain the correlation coefficient. This correlation assessment is performed by default once every 100 consecutive frames to detect the consistency of the time series between channels at different stages.

[0054] When the correlation coefficient of any channel pair falls below the set threshold of 0.95, the software determines that the channel pair has a synchronization anomaly. It immediately highlights the channel pair in the results view, along with the anomaly's start frame number, duration (number of frames), and the specific correlation coefficient value. Simultaneously, the anomaly record is written to the report generation module for subsequent output. This method effectively identifies synchronization mismatch between channels caused by drift, loss of synchronization, or short-term lockout. Even if a single time difference does not exceed the sliding window alarm threshold, it can still reflect a decline in synchronization consistency from an overall trend perspective.

[0055] A B-code multi-channel consistency testing device based on FPGA is also provided, used to implement the steps of the aforementioned FPGA-based B-code multi-channel consistency testing method, the device comprising:

[0056] The multi-channel signal acquisition module is used to acquire the B-code signal under test in parallel through multiple independent differential input circuits. Each channel is equipped with a programmable amplifier and filter to suppress common-mode interference and ensure the integrity of the input signal.

[0057] The timestamp generation module, located inside the FPGA, uses the master clock and an independent timestamp register to capture the rising and falling edges of the B-code pulses of each channel and generate pulse timestamp data.

[0058] The pulse width parsing module is used to identify the frame header pulse based on the B-code frame structure, and to perform pulse width parsing on the pulses in each frame, mapping the parsing results into the corresponding binary information bits.

[0059] The consistency analysis module is used to calculate the difference between the timestamps of the same numbered pulses in multiple channels, and to quantify the synchronization deviation between channels and across devices through sliding window statistics and multi-cycle synchronous sampling algorithms.

[0060] The interference detection module is used to perform wavelet transform or other frequency domain analysis on the acquired pulse sequence to extract high-frequency noise energy characteristics, and when the energy exceeds a preset threshold, it is determined to be an interference or deception signal and an alarm is output.

[0061] The results output module is used to generate test reports containing pulse parameters, consistency deviations, and abnormal events based on the analysis results, and supports exporting raw data as offline analysis files.

[0062] The device's overall architecture is designed around an FPGA platform, combining multi-channel analog front-end, synchronous logic analysis, frequency domain processing, and data export functions to achieve a complete closed-loop operation for multi-channel consistency detection of B-code signals. The multi-channel signal acquisition module consists of multiple isolated differential input interfaces, each connected to a B-code input source. The signal enters the channel front-end via an opto-isolation circuit, and then passes through a programmable amplifier and a bandpass filter for gain adjustment and noise suppression. The amplifier gain is controlled by the FPGA, supporting multiple dynamic settings; the filter cutoff frequency is set according to the B-code pulse frequency to ensure high-fidelity input signals enter the FPGA logic area.

[0063] The timestamp generation module is integrated into the FPGA. The main clock frequency is set to 200 MHz, which is multiplied to 1 GHz through a two-stage phase-locked loop and phase compensation is performed to ensure that each channel has a unified time base and high-resolution sampling capability. This module uses an edge detection circuit to identify the rising and falling edges of each pulse and triggers the timestamp register to record the current clock count value, achieving pulse positioning with nanosecond-level accuracy.

[0064] The pulse width parsing module receives the timestamps of each rising and falling edge, calculates the pulse width by the difference, and normalizes the width of subsequent pulses based on the frame header pulse in the frame structure as the reference pulse width. The system compares the normalization result with a set threshold to determine the logical bit value corresponding to each pulse, thus achieving frame-level binary parsing.

[0065] The consistency analysis module performs interpolation on pulse timestamps with the same number in all channels, calculating their average, maximum, and standard deviation within a sliding window to determine the synchronization performance between channels. For cross-device scenarios, an initial clock offset calibration mechanism is introduced, and a dynamic compensation module is set up to periodically adjust the timestamp offset between devices to ensure time alignment of multi-source data. If the statistical results exceed the set range, an abnormal synchronization deviation is recorded.

[0066] The interference detection module performs multi-scale wavelet transform on the waveform data of each channel, extracts the high-frequency coefficients in the third-level decomposition, and calculates their energy values. If the energy value exceeds the set threshold of 1000, it is determined to be a potential interference or deception behavior, and an alarm signal is immediately triggered, the abnormal frame range is marked, and written to the abnormal buffer.

[0067] The results output module integrates the output information from the above modules to generate a test report, including fields such as frame number, timestamp, pulse width, logic value, channel deviation, synchronization ratio, and interference flags for each channel. The report supports exporting to structured text format and binary files, facilitating Pearson correlation assessment in the accompanying offline analysis software to further verify cross-channel timing consistency. When a correlation coefficient below 0.95 is detected, it is automatically marked as a synchronization anomaly, and an analysis record is generated.

[0068] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for multi-channel consistency testing of B-code based on FPGA, characterized in that, The method includes: The B-code signal under test is acquired in parallel through multiple independent differential input circuits. Each channel is equipped with a programmable amplifier and filter to suppress common-mode interference and ensure the integrity of the input signal. By utilizing the FPGA's internal master clock and independent timestamp register, the rising and falling edges of the B-code pulses in each channel are captured to generate pulse timestamp data. Based on the B-code frame structure, the frame header pulse is identified and the pulse width of the pulse in each frame is analyzed, and the analysis result is mapped to the corresponding binary information bits. The difference between the timestamps of the same numbered pulses in multiple channels is calculated, and the synchronization deviation between channels and between devices is quantified by sliding window statistics and multi-cycle synchronous sampling algorithm. The acquired pulse sequence is subjected to wavelet transform or other frequency domain analysis to extract high-frequency noise energy characteristics. When the noise energy exceeds a preset threshold, it is determined to be an interference or deception signal and an alarm is output. The system generates test reports based on the analysis results, including pulse parameters, consistency deviations, and abnormal events, and supports exporting raw data as offline analysis files.

2. The FPGA-based B-code multi-channel consistency testing method according to claim 1, characterized in that: The multiple independent differential input circuits are opto-isolated differential interfaces, and each channel is configured with a programmable amplifier with adjustable gain and a bandpass filter to simultaneously suppress low-frequency common-mode interference and high-frequency noise.

3. The FPGA-based B-code multi-channel consistency testing method according to claim 1, characterized in that: The FPGA's internal main clock frequency is 200 MHz, and frequency multiplication and phase compensation are performed through dual PLL circuits to ensure that the generated pulse timestamp resolution is better than 5 ns.

4. The FPGA-based B-code multi-channel consistency testing method according to claim 1, characterized in that: In the pulse width parsing step, the fixed pulse width of the frame header pulse is used as a reference to normalize the pulse width of subsequent pulses, and the pulse width is mapped to logic 0 or logic 1 through threshold decision.

5. The FPGA-based B-code multi-channel consistency testing method according to claim 1, characterized in that: The sliding window statistics use a sequence of continuous pulse timestamp differences with a window length of 10 frames. When the standard deviation within the window exceeds a preset threshold, a synchronization deviation anomaly alarm is triggered.

6. The FPGA-based B-code multi-channel consistency testing method according to claim 1, characterized in that: The multi-cycle synchronous sampling algorithm introduces an initial calibration clock offset in cross-device scenarios and dynamically compensates for this offset during testing, thereby achieving consistency verification of B-code signals across devices.

7. The FPGA-based B-code multi-channel consistency testing method according to claim 1, characterized in that: The wavelet transform employs a multi-scale decomposition method and calculates high-frequency energy in the third-level decomposition coefficients. When the energy value exceeds the threshold of 1000, it is determined to be a potential interference or deception signal.

8. The FPGA-based B-code multi-channel consistency testing method according to claim 1, characterized in that: The test report includes average synchronization deviation, maximum deviation, consistency ratio, and anomaly statistics between channels, and supports output in both structured text and binary data formats.

9. The FPGA-based B-code multi-channel consistency testing method according to claim 1, characterized in that: The offline analysis file can be imported into the accompanying analysis software, and the correlation between the timestamp sequences of the channels can be calculated using the Pearson correlation coefficient. When the correlation coefficient is less than 0.95, it is determined to be a synchronization anomaly.

10. An FPGA-based B-code multi-channel consistency testing device, used to implement the steps of the FPGA-based B-code multi-channel consistency testing method according to any one of claims 1-9, characterized in that, The device includes: The multi-channel signal acquisition module is used to acquire the B-code signal under test in parallel through multiple independent differential input circuits. Each channel is equipped with a programmable amplifier and filter to suppress common-mode interference and ensure the integrity of the input signal. The timestamp generation module, located inside the FPGA, uses the master clock and an independent timestamp register to capture the rising and falling edges of the B-code pulses of each channel and generate pulse timestamp data. The pulse width parsing module is used to identify the frame header pulse based on the B-code frame structure, and to perform pulse width parsing on the pulses in each frame, mapping the parsing results into the corresponding binary information bits. The consistency analysis module is used to calculate the difference between the timestamps of the same numbered pulses in multiple channels, and to quantify the synchronization deviation between channels and across devices through sliding window statistics and multi-cycle synchronous sampling algorithms. The interference detection module is used to perform wavelet transform or other frequency domain analysis on the acquired pulse sequence to extract high-frequency noise energy characteristics, and when the energy exceeds a preset threshold, it is determined to be an interference or deception signal and an alarm is output. The results output module is used to generate test reports containing pulse parameters, consistency deviations, and abnormal events based on the analysis results, and supports exporting raw data as offline analysis files.

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