Data transmission method and device

Abstract

The embodiment of the invention provides a data transmission method and device which are used for realizing full-path routing in a cluster during message transmission. The method is applied to a cluster, the cluster at least comprises a plurality of nodes which are directly connected, firstly, a first node obtains a first message, the first node is any node in the cluster, the first message carries information of a first target node, and the information of the first target node can comprise an identifier or an address of the first target node; then, the first node queries a forwarding port in a priority routing table based on the information of the first destination node, wherein the priority routing table comprises the relationship between the hop count of the first node and the first destination node and the port; and the first node forwards the first message through the forwarding port.

Description

[0001] This application is a divisional application of the original application with the application number 202510247488.6 and the original filing date of February 28, 2025, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of computers, and in particular to a data transmission method and device. BACKGROUND

[0003] The scheme of combining multiple computing nodes to form a large computing system through cluster networking is widely used in supercomputers and AI (artificial intelligence) computing scenarios. The interconnection topology of nodes in the cluster affects the communication performance and cost of the cluster. Existing schemes usually use FatTree or Torus structure networking for supercomputers and AI clusters to adapt to the characteristics of multi-neighbor communication of supercomputing and AI tasks.

[0004] However, with the development of computer technology, the requirements for system size in the computing field are gradually increasing. Cluster systems using shared memory can improve the resource utilization of computing and storage through resource pooling, thereby reducing the system usage cost. High-bandwidth interconnection using memory semantics can improve the communication efficiency between virtual machines and accelerate virtual machine migration, thereby realizing efficient scheduling and high reliability at the system level. Unlike supercomputers and AI computing tasks, the communication mode in general-purpose computing clusters has great randomness. Using Fat Tree topology networking can provide high bandwidth, but introduces additional switch cost and communication latency; using Torus networking provides high bandwidth and low latency links between neighbor nodes, but has high latency and a large amount of traffic conflicts in the global random traffic mode. Therefore, how to more efficiently implement data transmission within the cluster has become a problem to be solved. SUMMARY

[0005] The present application provides a data transmission method and device for realizing more diversified message routing within the cluster when transmitting messages.

[0006] Therefore, in a first aspect, the present application provides a data transmission method applied to a cluster, the cluster comprising at least a plurality of nodes connected directly, comprising: first, a first node acquires a first message, the first node being any node in the cluster, the first message carrying information of a first destination node, the information of the first destination node including an identifier or an address of the first destination node, etc.; then the first node queries a forwarding port in a priority routing table based on the information of the first destination node, the priority routing table comprising the relationship between the hop count and the port of the first node and the first destination node; and the first node forwards the first message through the forwarding port.

[0007] In the embodiments of the present application, for the direct connection of multiple nodes in the cluster, the priority routing table can be set, so that each node can query the hop count and the corresponding port from the priority routing table when forwarding the packet, so that the appropriate port can be selected for the packet based on the forwarding hop count. That is, a more flexible routing path can be achieved within the cluster without being affected by the node dimension.

[0008] In a possible implementation, the priority routing table described above includes a port corresponding to the Nth hop, and N is an integer. Therefore, in the embodiments of the present application, the port corresponding to the Nth hop of the first destination node can be directly written in the priority routing table, and the N can include the number of hops possibly forwarded between the first node and the first destination node, so that the corresponding port is selected as the forwarding port based on each hop count.

[0009] In a possible implementation, the first node queries the forwarding port in the priority routing table based on the information of the first destination node, including: the first node obtains at least one port corresponding to the hop count of the first destination node from the priority routing table, and then determines the forwarding port from the at least one port corresponding to the hop count of the first destination node in the order of increasing hop count, that is, the port corresponding to the smaller hop count is preferentially selected as the forwarding port, so as to preferentially use the shorter path to route the first packet and reduce the overall transmission delay of the first packet.

[0010] In a possible implementation, the first node forwards the first packet through the forwarding port, including: the first node determines the output queue through the input queue and the forwarding port, and forwards the first packet through the output queue, that is, the first node determines the output queue by excluding the channel between the previous hop node first, so as to avoid the case that the first packet falls into a live lock.

[0011] In a possible implementation, the first node determines the output queue through the input queue and the forwarding port, including: the first node determines the output queue range through the input sequence and the forwarding port, and the output queue range includes at least one queue; and the first node determines the output queue according to the congestion situation of the queue in the output queue range. In the embodiments of the present application, the first node can adaptively select the available output queue according to the congestion situation of the queue, such as selecting the queue with lower congestion degree as the congestion queue, so as to route the first packet with lower delay and improve the bandwidth utilization in the cluster.

[0012] In a possible implementation, the plurality of nodes are divided into a plurality of dimensions, nodes in the same dimension are directly connected, one node is divided into at least two dimensions, and the number of queues between a pair of nodes is greater than the number of dimensions. In the embodiment of the application, the number of queues set between the node pair is greater than the number of dimensions, to support the bidirectional transmission channel between the node pair, and improve the message transmission efficiency of the whole cluster.

[0013] In a second aspect, the application provides a node applied to a cluster, the cluster comprising at least a plurality of nodes directly connected, the node comprising:

[0014] a receiving module configured to obtain a first message, the first node being any one of the nodes in the cluster, and the first message carrying information of a first destination node;

[0015] a routing module configured to query a forwarding port in a priority routing table based on the information of the first destination node, the priority routing table comprising a relationship between a hop number and a port of the first node and the destination node;

[0016] a sending module configured to forward the first message through the forwarding port.

[0017] Effects achieved by the second aspect or any optional implementation of the second aspect can be referred to the description of the first aspect or any optional implementation of the first aspect, and will not be described here.

[0018] In a possible implementation, the priority routing table comprises a port corresponding to an Nth hop, N being an integer.

[0019] In a possible implementation, the routing module is specifically configured to: obtain, from the priority routing table, a port corresponding to at least one hop number corresponding to the first destination node; and determine the forwarding port from the ports corresponding to the at least one hop number corresponding to the first destination node in ascending order of the hop number.

[0020] In a possible implementation, the routing module is further configured to determine an output queue through the input queue and the forwarding port.

[0021] The sending module is specifically configured to forward the first message through the output queue.

[0022] In a possible implementation, the routing module is specifically configured to determine an output queue range through the input sequence and the forwarding port, the output queue range comprising at least one queue; and determine the output queue according to the congestion of the queues in the output queue range.

[0023] In a possible implementation, the plurality of nodes are divided into a plurality of dimensions, nodes in the same dimension are directly connected, one node is divided into at least two dimensions, and the number of queues between a pair of nodes is greater than the number of dimensions.

[0024] In a third aspect, the application provides a cluster, comprising at least a plurality of nodes directly connected, wherein the plurality of nodes comprise a node for executing the method of the first aspect or any of the optional implementation forms of the first aspect.

[0025] In a fourth aspect, the application provides a server, comprising a processor and a memory, wherein the processor and the memory are connected through a line, the processor invokes the program code in the memory for executing the functions related to processing in the method of any of the first aspects.

[0026] In a fifth aspect, the application provides a digital processing chip or a chip, comprising a processing unit and a communication interface, the processing unit obtains program instructions through the communication interface, the program instructions are executed by the processing unit, and the processing unit is used for executing the functions related to processing in the first aspect or any of the implementation forms of the first aspect.

[0027] In a sixth aspect, the application provides a computer readable storage medium, comprising instructions, when the instructions are executed on a computer, the computer executes the method in the first aspect or any of the implementation forms of the first aspect.

[0028] In a seventh aspect, the application provides a computer program product comprising computer programs / instructions, when the computer programs / instructions are executed by a processor, the processor executes the method in the first aspect or any of the implementation forms of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A cluster architecture schematic diagram provided by the embodiment of the application;

[0030] Figure 2 Another cluster architecture schematic diagram provided by the embodiment of the application;

[0031] Figure 3 A cluster architecture schematic diagram of an existing scheme;

[0032] Figure 4 A flowchart of a data transmission method provided by the embodiment of the application;

[0033] Figure 5 Another cluster architecture schematic diagram provided by the embodiment of the application;

[0034] Figure 6 A node structure schematic diagram provided by the embodiment of the application;

[0035] Figure 7 Another structure diagram of a node provided by an embodiment of the present application is provided.

[0036] Figure 8 Another structure diagram of a node provided by an embodiment of the present application is provided.

[0037] Figure 9 A virtual channel range determination manner provided by an embodiment of the present application is provided.

[0038] Figure 10 A forwarding path provided by an embodiment of the present application is provided.

[0039] Figure 11 Another structure diagram of a node provided by an embodiment of the present application is provided.

[0040] Figure 12 A structure diagram of a server provided by an embodiment of the present application is provided.

[0041] Figure 13 A structure diagram of a chip provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0043] The method provided by the embodiments of the present application can be applied to a cluster containing multiple nodes, and the cluster can specifically include multiple nodes. The nodes are connected to each other, and can transmit data to each other. Each node can be used to perform data processing, such as data storage, forwarding or calculation.

[0044] Further, the nodes in the cluster can be fully interconnected, that is, each node is directly connected to each other, that is, a full mesh architecture is implemented; or the multiple nodes in the cluster can be divided into multiple dimensions, and the nodes in each dimension are directly and fully connected to implement a full mesh architecture in multiple dimensions. In addition, in the multi-dimensional full mesh architecture, in order to realize the connectivity of all nodes in the cluster, the same nodes are included between different dimensions to realize data transmission between different dimensions.

[0045] For example, the cluster architecture provided by the embodiments of the present application can be as follows Figure 1As shown, exemplarily, the cluster may include node 1, node 2, node 3, node 4, node 5, node 6, node 7, node 8, and node 9, which are interconnected. This example uses nine nodes and is not intended to limit the number of nodes in the cluster. The number of nodes and connection structure can be adapted to suit the specific application scenario.

[0046] In one possible scenario, the nine nodes can be fully connected, meaning that each node is directly connected to the other eight nodes, and each node can communicate directly with the other eight nodes.

[0047] In one possible scenario, these 9 nodes can be divided into multiple dimensions, with shared nodes across different dimensions. For example, they could be divided into two dimensions, such as... Figure 1 As shown, nodes 1, 4, and 7 can be divided into dimension 2, while nodes 1, 2, and 3 can be divided into dimension 1.

[0048] Optionally, the aforementioned nodes can specifically be computing devices, such as a computer device or a server within a cluster. For example, multiple computer devices can be combined as nodes to form a cluster using high-bandwidth, low-latency interconnects. All nodes within a cluster typically use shared memory addresses or communicate using message passing interfaces.

[0049] Optionally, the aforementioned nodes may specifically be chips with computing capabilities, such as central processing units (CPUs), graphics processing units (GPUs), embedded neural network processing units (NPUs), or tensor processing units (TPUs) that have data processing capabilities.

[0050] For example, such as Figure 2 As shown, the cluster can include one or more computing devices, and each computing device can include multiple NPUs and CPUs, such as... Figure 2 The NPUs 1 to NPU 8 and CPU shown can be used as nodes to implement the method steps in the following embodiments of this application.

[0051] In addition, based on the aforementioned cluster architecture, the following will introduce some related terms or concepts that may be involved.

[0052] Fat Tree: A cluster networking topology in which nodes are connected to each other through one or more layers of switches.

[0053] Torus: A switchless cluster network topology in which nodes are connected to adjacent nodes through a ring of multiple dimensions.

[0054] Full mesh: A switchless cluster networking topology in which nodes are directly connected to each other.

[0055] Multidimensional Full mesh: refers to a cluster network topology in which nodes are directly connected to each other within a dimension.

[0056] Deadlock: A circular dependency on hardware resources during multiple packet routing processes prevents packets from continuing to advance in the network. For example, a deadlock occurs when the routing resources of some nodes become unavailable.

[0057] Livelock occurs when a packet is continuously forwarded during the routing process but fails to reach its destination node. For example, an algorithmic problem could create a routing loop, which is a case of livelock.

[0058] Lock-free: Routing and flow control algorithms in the network ensure that deadlocks and livelocks are avoided.

[0059] Virtual Channel: One or more virtual links or queues in a network that correspond to a physical link. Although different virtual channels share the same physical link, they have independent send and receive queues to avoid message waiting between virtual channels.

[0060] Furthermore, the aforementioned clusters can be specifically applied to high-performance computing or AI computing scenarios. For example, in neural network training or inference, especially when the neural network is a large model, the computational load is enormous. Using a cluster approach can achieve parallel computing of a large number of calculations, which can effectively improve the computational efficiency of the neural network. For instance, multiple modules in a neural network can be distributed to multiple nodes for computation, thereby improving the overall computational efficiency through parallel computing across multiple nodes.

[0061] For cluster topologies, existing solutions typically employ fat tree or torus networking topologies to suit the multi-neighbor communication characteristics of supercomputing and AI tasks. However, with the development of cloud computing and AI, the demands for system scale in general computing are gradually increasing. Therefore, cluster systems using shared memory are evolving to improve the utilization of computing and storage resources through resource pooling, thereby reducing system operating costs. High-bandwidth interconnects using memory semantics can improve communication efficiency between virtual machines, accelerate virtual machine migration, and thus achieve efficient system-level scheduling and high reliability.

[0062] Unlike supercomputing and AI computing tasks, communication patterns within general-purpose computing clusters exhibit significant randomness. While FatTree topology can provide high bandwidth, it introduces additional switching costs and communication latency. Torus networking, on the other hand, offers high-bandwidth, low-latency links between neighboring nodes, but suffers from high latency and numerous traffic conflicts under globally random traffic conditions. Therefore, the Full mesh architecture emerged as a solution.

[0063] Full mesh, as a switchless networking topology, offers advantages such as low latency, low cost, and low power consumption, making it suitable for general computing, AI computing, and other scenarios. However, because full mesh topologies have more physical links compared to Fat Trees or Toruses, they impose additional requirements on routing and flow control. Routing methods for full mesh topologies need to fully and rationally utilize existing paths in the topology while avoiding deadlocks or livelocks, in order to achieve high interconnect bandwidth and low transmission latency between any two nodes.

[0064] Existing cluster routing solutions are designed for Fat Tree or Torus architectures and cannot be directly applied to Full Mesh architectures. For example, Dimension Order Routing (DOR) is widely used in multi-dimensional Mesh or Torus networking to avoid locks during routing. DOR routes sort the N dimensions of an N-dimensional topology in any order. Packets sent from the source node to the destination node select relay nodes according to a pre-specified global dimensional order. Taking two dimensions X and Y as an example, ... Figure 3As shown, assuming DOR specifies an XY dimension order, a message sent from the source node (Xs, Ys) to the destination node (Xd, Yd) must first propagate along the X dimension, i.e., reach node (Xd, Ys) first, and then propagate along the Y dimension to reach the destination node (Xd, Yd). Since there is only forwarding from the X dimension to the Y dimension, and no forwarding from the Y dimension to the X dimension, DOR can avoid deadlock. However, DOR cannot fully utilize global paths for load balancing control, which can easily lead to unavoidable local traffic congestion and reduce the efficiency of communication within the cluster. Furthermore, the effective bandwidth between nodes is low. For example, since there is only one path between any two nodes that meets the DOR requirements, the effective bandwidth between nodes is only equal to the bandwidth of a single link. In a full mesh topology, each node and With direct connections between nodes, using the DOR scheme results in the maximum effective bandwidth between any two nodes being only the total bandwidth of the nodes. Furthermore, in the DOR scheme, a break in any link will inevitably cause one or more nodes to become unreachable, affecting the availability of the cluster as a whole.

[0065] Therefore, this application provides a data transmission method that can implement a full-path routing scheme for paths under a Full mesh or multi-dimensional Fullmesh architecture, enabling data transmission with diverse paths.

[0066] See Figure 4 The following is a flowchart illustrating a data transmission method provided in this application embodiment.

[0067] This application embodiment exemplifies the processing of one of the nodes as an example. For ease of distinction, this node is referred to as the first node, which can be any node in the cluster.

[0068] 401. The first node obtains the first message.

[0069] The first message can be a message received by the first node or a message generated by the first node. The first message carries information about the first destination node, including the unique identifier of the first destination node, such as the unique number and unique address of the first destination node in the cluster. The information of the first destination node can be used to indicate that the first message is transmitted to the first destination node.

[0070] Specifically, when the first message is generated by the first node, the first message may include data generated after the first node performs calculations. For example, if the cluster provided in this application embodiment is deployed during the training process of a neural network, each node can be used to perform some calculations during the training process, such as calculating activation values ​​or gradient values, and propagate them to other nodes in the cluster that need the activation values ​​or gradient values.

[0071] 402. The first node queries the priority routing table for the forwarding port based on the information of the first destination node. The priority routing table includes the relationship between the hop count and the port of the first node and the first destination node.

[0072] The priority routing table can be pre-configured in the first node, for example, when deploying a cluster, the corresponding priority routing table can be set in the storage space of each node in the cluster. Alternatively, the priority routing table can also be generated by the first node before transmitting the first packet, depending on the actual application scenario.

[0073] In one possible implementation, the priority routing table may include the port corresponding to the Nth hop, where N is a positive integer representing the possible number of hops from the first node to each destination node. Therefore, a priority routing table can be set up in each node to record the possible number of hops from each node to other nodes, allowing the selection of the appropriate port based on requirements.

[0074] Accordingly, in one possible implementation, the first node can obtain the port corresponding to at least one hop count of the first destination node from the priority routing table; the first node determines the forwarding port from the ports corresponding to at least one hop count of the first destination node in ascending order of hop count. Therefore, the first node can select available ports as forwarding ports in ascending order of hop count, that is, it can preferentially select ports with fewer hop counts as forwarding ports. The fewer the hop count, the fewer nodes are traversed, and the shorter the corresponding transmission path, so as to achieve a shorter path routing for the first packet.

[0075] Furthermore, it should be noted that the priority routing table mentioned in the embodiments of this application may also be called a forwarding table or routing table, etc., and the specific name can be determined according to the actual application scenario. The embodiments of this application are only introduced as examples.

[0076] 403. The first node forwards the first message through the forwarding port.

[0077] Once the forwarding port is determined, the first message can be sent from that port. Typically, the first node establishes connections with other nodes through this forwarding port, and the first node can send the first message to other nodes from this forwarding port.

[0078] Therefore, in this embodiment, a priority routing table can be set on each node within the cluster. The first node can determine the hop count and port to the first destination node by looking up the table, and thus select the port as the forwarding port based on the hop count. This enables various routing methods between nodes within the cluster, and even in a fully connected cluster, full-path routing can be achieved.

[0079] Furthermore, multiple virtual channels, i.e., multiple transmission queues, can be set up between directly connected node pairs. The first node can also determine the output queue through the input queue and the forwarding port, and then the first node forwards the first message through the output queue. Therefore, in this embodiment of the application, the first node can determine the output queue for sending the first message, i.e., the output virtual channel, based on the input queue and the forwarding port, thereby sending the first message from the available virtual channels.

[0080] Optionally, the first node can determine the output queue range by using the input sequence and the forwarding port. The output queue range includes at least one queue. Then, the output queue is determined based on the congestion status of the queues in the output queue range. For example, the output queue with a lower congestion level is selected first to transmit the first message as soon as possible.

[0081] Furthermore, multiple nodes are divided into multiple dimensions, with direct connections between nodes within the same dimension. Each node is divided into at least two dimensions. To support more diverse transmission paths within the cluster, the number of queues between a pair of nodes can be set to be greater than the number of dimensions to support bidirectional data transmission between node pairs. Therefore, in this embodiment, the number of virtual channels, i.e., queues, between node pairs can be set to be greater than the number of dimensions. For example, if the number of dimensions is 2, the number of queues can be set to be greater than 2, such as 3 or more.

[0082] The foregoing has described the method flow provided in the embodiments of this application. The following section will describe the method flow provided in the embodiments of this application in more detail, in conjunction with the specific system architecture and node structure.

[0083] First, taking a 2D 4x4 Full mesh topology cluster structure as an example, this architecture can be as follows: Figure 5 As shown, this includes 16 nodes, such as nodes 0 to 9 and nodes A to F. Each node can be a computing device or a chip, such as a CPU, NPU, or GPU. The 16 CPU nodes are connected through a 2D full mesh topology to form a switchless supernode.

[0084] Furthermore, these 16 nodes can be divided along multiple dimensions. For example, the 16 nodes can be divided into two dimensions: the X dimension (0 to 3) and the Y dimension (0 to C). Nodes along the X dimension are directly connected; for example, nodes 0, 1, 2, and 3 are directly connected, and nodes 0, 4, 8, and C are interconnected, and so on.

[0085] Typically, in a multidimensional full mesh topology, there may be multiple transmission paths between any two nodes: Figure 5 For example, a message might travel from node 0 to node 9 via paths such as 0-1-9, 0-8-9, and 0-2-A-9. The path with the fewest possible paths is called the shortest path. Typically, shortest path routing minimizes message transmission latency, but it doesn't fully utilize the bandwidth of the source and destination nodes. For instance, if the queue in the shortest path is congested, transmitting a message within that queue might cause the message to wait, while other available bandwidth resources remain underutilized.

[0086] The routing scheme provided in this application embodiment can achieve more efficient and better-suited packet transmission by taking into account both shorter transmission paths and effective utilization of available bandwidth resources.

[0087] Furthermore, considering the structure of each node within the cluster, the internal modules of each node can be divided into receiving modules, routing modules, arbitration modules, and sending modules, etc.

[0088] For example, a possible node structure could be as follows: Figure 6 As shown.

[0089] The message enters the routing module through the input port, and the receiving module can then include that input port.

[0090] The routing module obtains the destination node of the packet based on the parsed packet header, obtains one or more valid forwarding ports corresponding to the packet based on the routing priority table, and allocates available virtual channels.

[0091] When multiple messages are falsely sent to the same output port, the arbitration module assigns the port to a specific message according to its priority.

[0092] During the arbitration process, the message obtained from the outgoing port is serialized and sent by the sending module through the allocated port.

[0093] Furthermore, it should be noted that the steps executed by the aforementioned arbitration module can also be executed by the routing module, or in other words, the arbitration module can be deployed within the routing module, as shown in the embodiments of this application below. Figure 11In the corresponding structure, the steps that are executed by the arbitration module can also be executed by the routing module. The specific steps can be adjusted according to the actual application scenario, and this application does not limit them.

[0094] In combination with the above Figure 6 Regarding the node structure, this application provides a hardware-supported full-path routing mechanism under a 3D Full mesh topology. Specifically, at the source node of the packet injection network (i.e., the node that generates the packet), the packet is allowed to be routed to any non-local port. When local traffic is high, the packet can be forwarded outward using all ports of the source node. The routing mechanism proposed in this application symmetrically includes the full-port routing characteristic of the destination node: the destination node can be any node within the cluster, that is, the packet can carry the unique identifier of any destination node, and the packet can be routed to any destination node.

[0095] This application also provides a routing and forwarding mechanism for a full mesh topology. Specifically, it proposes a mechanism to control forwarding traffic by configuring a priority routing table on each node. In particular, the proposed priority routing table supports multi-path packet forwarding, meaning that packets can be forwarded to multiple outgoing ports during the forwarding process, maximizing the diversity of routing paths. Simultaneously, the packet forwarding process follows the shortest path principle, ensuring that each forwarding is progressive; that is, there is an upper limit to the number of forwardings any packet can undergo, thereby preventing loops in forwarding paths and avoiding livelock.

[0096] This application also provides a virtual channel allocation mechanism under a multi-dimensional Full mesh topology. Specifically, virtual channels are allocated according to the number of times a packet is forwarded, and the number of virtual channels is configurable. Each time a packet is forwarded at a node, it switches to an output virtual channel with a higher number than the input virtual channel. The virtual channel allocation strategy adopted in this application ensures that routing resources do not have circular dependencies, avoiding deadlock.

[0097] This application also provides a flow control mechanism under a multi-dimensional Full mesh topology. Specifically, by providing multiple legitimate port requests to the arbitration module, the arbitration module can decide which port to send packets to based on dynamic traffic. When network traffic pressure is low, the arbitration module prioritizes sending packets to the port with the shortest forwarding path; when network traffic pressure is high and the shortest path port encounters congestion, the arbitration module can forward packets to other legitimate paths.

[0098] Based on the aforementioned cluster architecture and node structure, the method provided in this application embodiment can be exemplarily divided into multiple parts, such as node configuration and message routing. Each part will be described below.

[0099] I. Node Configuration

[0100] Node configuration can be divided into port configuration, priority routing table configuration, and virtual channel configuration (or queue configuration).

[0101] 1. Port Configuration

[0102] For example, in conjunction with the foregoing Figure 5 The cluster architecture used can be configured in the following ways: Figure 7 As shown, a node can include 7 inbound ports and 7 outbound ports: 1 port connects to the computing module of this node, 3 ports connect to the routing modules of other nodes on the same X dimension, and 3 ports connect to other nodes on the same Y dimension. Figure 7 The example diagram uses node 0 to illustrate the connection relationships of the corresponding routing modules. There is a direct connection between two nodes in the same X or Y dimension, while message transmission between two nodes in different dimensions in both the X and Y directions requires passing through at least one forwarding node. For instance, port 0 connects to the internal modules of node 0, and ports 1, 2, and 3 directly connect to nodes 1, 2, and 3 in the X dimension, respectively. Ports 4, 5, and 6 connect to ports 4, 8, and C in the Y dimension, respectively.

[0103] Of course, this example only uses 7 ports as a case study. The specific number of ports can be determined based on the actual application scenario, and this application does not limit this.

[0104] Typically, the ports of a node and the nodes connected to those ports can be determined during node deployment. In subsequent message transmission, the output ports can be directly determined.

[0105] 2. Routing table configuration

[0106] The purpose of configuring the priority routing table is to establish a mapping between all destination nodes of the current node and the current node's outgoing port during each hop of route forwarding. This priority routing table can include...

[0107] The configuration of the priority routing table ensures that a packet reaches its destination node after a maximum of N forwards from any source node. In the routing strategy provided in this application embodiment, one priority routing table can be configured on each node to select the outgoing port for the packet during the first to Nth forwards.

[0108] In other words, when configuring priority routing tables for each node within a cluster, the following rules can typically be satisfied:

[0109] (1) Each entry in the priority routing table of each node can correspond to a node in the cluster. The number of entries in the priority routing table is usually the total number of nodes in the cluster minus one.

[0110] (2) Each priority routing table records one or more forwarding ports of the corresponding destination node, and the minimum remaining hop count to reach the destination node after forwarding through that port;

[0111] (3) The priority routing table is usually configured at the same time as the cluster initialization, and no adjustment is required during subsequent routing processes;

[0112] (4) When the node connection relationship in the cluster changes, the priority routing table can be adjusted. For example, when a link is broken or a node fails, the priority routing table entry can be modified to shield the faulty path.

[0113] The following example uses the priority routing table configuration of node 0 as an example for illustration.

[0114] Node 0 is represented as having coordinates (0, 0).

[0115] Consider destination node 1, with coordinates (1, 0). This node is directly connected to node 1 via port 1, so port 1 is configured as a 0-hop port. Nodes 2 and 3 are connected to ports 2 and 3, respectively. If a packet is forwarded through ports 2 and 3, it still requires at least one hop to reach destination node 1; therefore, ports 2 and 3 are configured as 1-hop ports. Nodes 4, 8, and C are connected to ports 4, 5, and 6, respectively. If a packet is forwarded to nodes 4, 8, and C first, it still requires at least two hops to reach destination node 1; therefore, ports 4, 5, and 6 are configured as 2-hop ports.

[0116] The configuration process for destination nodes 2, 3, 4, 8, and C is similar to that for destination node 1, and will not be repeated here.

[0117] For destination node 5, its coordinates are (1, 1). This node has no direct connection to destination node 5. After the packet is forwarded via ports 1 and 4, it still needs one hop to reach destination node 5, so these are configured as one-hop ports. After the packet is forwarded via ports 2, 3, 4, and 6, it still needs two hops to reach destination node 5, so these are configured as two-hop ports.

[0118] The configuration method for the remaining destination nodes is similar to that for node 5, and will not be repeated here.

[0119] For example, the priority routing configuration table can be configured as shown in Table 1.

[0120]

[0121] Table 1

[0122] The priority routing table configuration for the remaining nodes is similar to that for node 0, and will not be repeated here.

[0123] Therefore, in this embodiment, the control of forwarding traffic is achieved by configuring a priority routing table at each node. Specifically, the priority routing table proposed in this embodiment supports multi-path forwarding, meaning that during packet forwarding, packets can be forwarded to multiple outgoing ports, maximizing the diversity of routing paths. Simultaneously, the shortest path principle is followed during packet forwarding, ensuring that each forwarding is progressive; that is, there is an upper limit to the number of forwardings any packet can undergo, thereby preventing loops in forwarding paths and avoiding livelock.

[0124] 3. Virtual Channel Configuration

[0125] Specifically, for a D-dimensional full mesh network, N virtual channels, or N VCs, can be set between nodes. The number of virtual channels N must be greater than or equal to D+1.

[0126] For example, the configuration of a virtual channel can be as follows: Figure 8 As shown. Multiple virtual channels can be configured for each port. For example, taking a 2D Full mesh network architecture as an example, the number of virtual channels between a pair of nodes can be set to 3. For example, virtual channels VC0, VC1, and VC2 can be configured in the input port, and virtual channels VC3, VC4, and VC5 can be configured in the output port, and so on. This is only an example of two ports and is not intended to be a limitation.

[0127] For all virtual channels within the cluster, a unique number can be assigned to each virtual channel. Furthermore, in conjunction with the aforementioned... Figure 4 In the corresponding cluster architecture, for each node's virtual channel, a progressively increasing virtual channel number can be configured for the virtual channel in ascending order of hop count. This means that each virtual channel within the cluster has a unique identifier configured according to preset rules. This allows for the selection of virtual channels with shorter forwarding paths based on these preset rules when filtering available virtual channels later. Of course, besides increasing the virtual channel number according to hop count, other virtual channel numbering directions can be set. The specific direction can be adjusted according to the actual application scenario. This example only illustrates the method of increasing the virtual channel number while simultaneously increasing the hop count, and is not intended to be limiting.

[0128] II. Message Routing

[0129] After the cluster configuration is completed, during the cluster operation, the packets that need to be forwarded by each node can be routed based on the previously configured ports, priority routing tables, and virtual channels.

[0130] In combination with the above Figure 6The packet enters the routing module from the local port or input port. The routing module parses the packet header to obtain the destination node. Based on the destination node, the routing module looks up the priority routing table to obtain the valid forwarding ports and the minimum remaining forwarding hops H for each port. The routing module then determines the virtual channel VC used when the packet enters the node. IN Determine the range of output virtual channels that each legal port can use [VC] IN +1, VC N-H For example, a VC channel for a specific message can be like this: Figure 9 As shown, the message input VC is VC1, and the 0-hop VC range between the message input and the destination node is VC2-VC1. N The range of VC for jump 1 is VC2-VC. N-1 This allows the selection of virtual channels between nodes other than the previous hop node, and the combination of available ports and available virtual channels is output to the next stage, which is to perform a scrambling process to select the final virtual channel for forwarding the message.

[0131] For example, taking a message sent from node 0 to node 6 as an example, the routing process in this embodiment is as follows.

[0132] The process of packet routing at source node 0 is as follows:

[0133] (1) Node 0 is the source node. The packet enters the routing module through port 0. The routing module marks all 6 ports as valid forwarding ports (i.e., excludes port 0). For 1-hop ports 2 and 4, the corresponding available virtual channels are VC1 and VC2. For 2-hop ports 1, 3, 5, and 6, the corresponding available virtual channel is VC1.

[0134] (2) The arbitration module selects one of the six ports to send the packet based on the port traffic. During arbitration, ports 2 and 4 with the highest corresponding virtual channel number (VC2) are selected first for sending. If ports 2 and 4 are congested, ports 1, 3, 5, and 6 corresponding to VC1 are selected. If all of the above ports are congested, the packet will not be able to obtain port resources in this round of arbitration.

[0135] Since a message has multiple possible exit ports at the source node, message routing can be divided into the following two cases:

[0136] (1) Select port 2 or port 4 as the egress port for the message at source node 0. In this case, the message is sent to forwarding node 2 or node 4, and the input virtual channel used by the message is VC1 or VC2.

[0137] If a packet enters the forwarding node via VC2, the output virtual channel can only be VC3 (the output virtual channel must be at least the input virtual channel number + 1). In this case, only the 0-hop port can be used as a valid forwarding port, i.e., the output port directly connected to the destination node 6. The packet is directly delivered to the destination node 6 via the VC3 channel of this port. Figure 10 The left side shows an example path in this case (node ​​0-node 2-node 6).

[0138] If a packet enters the forwarding node via VC1, the output virtual channel can be selected from VC2 or VC3. In this case, the 0-hop port or 1-hop port in the priority routing table can be selected for forwarding.

[0139] (2) The packet selects ports 1, 3, 5, or 6 as the egress ports at source node 0. In this case, the packet is forwarded to forwarding nodes 1, 3, 8, or C as the first-hop forwarding node. In this case, the input virtual channel is VC1, and the routing module can select the 1-hop port corresponding to VC2 for secondary forwarding. After the packet reaches the second-hop forwarding node via VC2, it is forwarded to the destination node 6 for the last time via VC3 through the 0-hop port. Figure 10 The right side shows an example path in this case (node ​​0-node 3-node 7-node 6).

[0140] Considering both scenarios, a message sent from node 0 to node 6 may exist along multiple paths listed in Table 2.

[0141] For example, the combination of multiple routing paths can be shown in Table 2.

[0142]

[0143] Table 2

[0144] While minimum path routing typically reduces message transmission latency, it also significantly limits bandwidth utilization. In cases of uneven cluster communication traffic, a few nodes may generate the majority of the traffic. Taking the cluster networking method in Example 1 as an example, minimum path routing can only utilize one of the six external ports of both the source and destination nodes, resulting in substantial wasted network bandwidth under uneven traffic conditions.

[0145] In this embodiment, full-path routing allows for dynamic selection of the routing path based on real-time network traffic. When traffic pressure is low, the arbitration module in the routing module prioritizes the shortest path for packet forwarding, reducing transmission latency. When traffic pressure is high, the arbitration module can select any port at the source node for packet forwarding in the event of a port conflict on the shortest path. As shown in Table 2 above, the path combinations cover all outgoing ports of the source node (corresponding to first-hop nodes 1, 2, 3, 4, 8, C) and all incoming ports of the destination node (corresponding to last-hop nodes 2, A, E, 4, 5, 7).

[0146] In addition, In a full mesh topology, each node and With direct connections between nodes, using the DOR scheme results in the maximum effective bandwidth between any two nodes being only the total bandwidth of the nodes. The full-path scheme adopted in this application can effectively utilize the full bandwidth of the nodes. When the network generates unbalanced traffic, the maximum available bandwidth between any two nodes increases by (N-1)D times.

[0147] In this embodiment, virtual channels are allocated according to the number of times a packet is forwarded, and the number of virtual channels is configurable. Each time a packet is forwarded at a node, it switches to an output virtual channel with a higher number than the input virtual channel. Therefore, the virtual channel allocation strategy adopted in this embodiment ensures that routing resources do not have circular dependencies, avoiding deadlock. Global lock-free routing is guaranteed through virtual channel allocation. The allocation of VC resources according to the forwarding hop count ensures that routing queue resources do not cause circular dependencies. Furthermore, the limitation on the maximum number of hops in a route ensures that livelock does not occur during packet transmission.

[0148] The foregoing has described the method flow provided in the embodiments of this application. The following describes the structure of the apparatus for executing the foregoing method flow.

[0149] See Figure 11 This application provides a schematic diagram of a node structure, which includes:

[0150] The receiving module 1101 is used to obtain the first message, where the first node is any node in the cluster, and the first message carries information about the first destination node.

[0151] The routing module 1102 is used to query the forwarding port in the priority routing table based on the information of the first destination node. The priority routing table includes the relationship between the hop count and the port between the first node and the destination node.

[0152] The sending module 1103 is also used to forward the first message through the forwarding port.

[0153] In one possible implementation, the aforementioned priority routing table includes the port corresponding to the Nth hop, where N is an integer.

[0154] In one possible implementation, the aforementioned routing module 1102 is specifically used to: obtain a port corresponding to at least one hop count corresponding to the first destination node from the priority routing table; and determine a forwarding port from the ports corresponding to at least one hop count corresponding to the first destination node in ascending order of hop count.

[0155] In one possible implementation, the aforementioned routing module 1102 is further configured to determine the output queue by means of the input queue and the forwarding port;

[0156] The sending module is specifically used to forward the first message through the output queue.

[0157] In one possible implementation, the aforementioned routing module 1102 is specifically used to: determine the output queue range by means of the input sequence and the forwarding port, wherein the output queue range includes at least one queue; and determine the output queue based on the congestion status of the queues in the output queue range.

[0158] In one possible implementation, the aforementioned multiple nodes are divided into multiple dimensions, nodes within the same dimension are directly connected, a node is divided into at least two dimensions, and the number of queues between a pair of nodes is greater than the number of dimensions.

[0159] In this context, a node can be either a server or a chip. When the node is a server, the aforementioned cluster interface includes an architecture composed of multiple servers. When the node is a chip, the aforementioned cluster can include an architecture composed of multiple chips.

[0160] When the aforementioned node is a server, refer to Figure 12 This application provides a server for performing the steps executed by the node in the aforementioned method steps.

[0161] Figure 12 The server 120 shown may include a processor 1201, a memory 1202, a communication interface 1203, and a bus 1204. The processor 1201, the memory 1202, and the communication interface 1203 can be connected via the bus 1204.

[0162] Processor 1201 is the control center of server 120. It can be a general-purpose central processing unit (CPU) or other general-purpose processors. The general-purpose processor can be a microprocessor or any conventional processor, such as a GPU or NPU, and can be adapted to the actual application scenario.

[0163] As an example, processor 1201 may include one or more CPUs, and may also include other processors, such as... Figure 12 The CPU, NPU, or GPU shown are examples of such devices.

[0164] The memory 1202 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0165] In one possible implementation, the memory 1202 can exist independently of the processor 1201. The memory 1202 can be connected to the processor 1201 via a bus 1204 and is used to store data, instructions, or program code. When the processor 1201 calls and executes the instructions or program code stored in the memory 1202, it can implement the methods provided in the embodiments of this application. For example, the processor 1201 can call and execute the instructions or program code stored in the memory 1202 to perform the aforementioned... Figures 4 to 10 The corresponding method steps. For example, one of the servers can use the method steps provided in this application embodiment to route the received or generated messages to other servers through the communication interface 1203.

[0166] In another possible implementation, the memory 1202 can also be integrated with the processor 1201.

[0167] The communication interface 1203 is used for the server 120 to connect with other devices via a communication network, which may be Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. The communication interface 1203 may include a receiving module for receiving data and a transmitting module for sending data.

[0168] Bus 1204 can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, or an extended industry standard architecture (EISA) bus. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 12 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0169] It should be pointed out that, Figure 12 The structure shown does not constitute a limitation on server 120, except Figure 12 In addition to the components shown, server 120 may include more or fewer components than illustrated, or combine certain components, or have different component arrangements.

[0170] Alternatively, the aforementioned nodes can also be chips.

[0171] For example, please refer to Figure 13 , Figure 13 This is a schematic diagram of a chip provided in an embodiment of this application. The chip can be represented as a neural network processor (NPU) 130. The NPU 130 is mounted as a coprocessor on the host CPU, and tasks are assigned by the host CPU. The core part of the NPU is the arithmetic circuit 1303, which is controlled by the controller 1304 to extract matrix data from the memory and perform multiplication operations.

[0172] In some implementations, the arithmetic circuit 1303 internally includes multiple process engines (PEs). In some implementations, the arithmetic circuit 1303 is a two-dimensional pulsating array. The arithmetic circuit 1303 can also be a one-dimensional pulsating array or other electronic circuitry capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 1303 is a general-purpose matrix processor.

[0173] For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 1302 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 1301 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 1308.

[0174] Unified memory 1306 is used to store input and output data. Weight data is directly transferred to weight memory 1302 via direct memory access controller (DMAC) 1305. Input data is also transferred to unified memory 1306 via DMAC.

[0175] The bus interface unit (BIU) 1310 is used for interaction between the AXI bus and the DMAC and instruction fetch buffer (IFB) 1309.

[0176] The bus interface unit 1310 (BIU) is used by the instruction fetch memory 1309 to fetch instructions from external memory, and also by the memory access controller 1305 to fetch the original data of the input matrix A or the weight matrix B from external memory.

[0177] The DMAC is mainly used to move input data from external memory DDR to unified memory 1306, or to weight data to weight memory 1302, or to input data to input memory 1301.

[0178] The vector computation unit 1307 includes multiple arithmetic processing units that further process the output of the computation circuit as needed, such as vector multiplication, vector addition, exponential operations, logarithmic operations, size comparisons, etc. It is mainly used for computation in non-convolutional / fully connected layers of neural networks, such as batch normalization, pixel-level summation, and upsampling of feature planes.

[0179] In some implementations, the vector computation unit 1307 can store the processed output vector in the unified memory 1306. For example, the vector computation unit 1307 can apply linear and / or nonlinear functions to the output of the computation circuit 1303, such as performing linear interpolation on feature planes extracted by convolutional layers, or accumulating a vector of values ​​to generate activation values. In some implementations, the vector computation unit 1307 generates normalized values, pixel-level summed values, or both. In some implementations, the processed output vector can be used as activation input to the computation circuit 1303, for example, for use in subsequent layers of the neural network.

[0180] The instruction fetch buffer 1309 connected to the controller 1304 is used to store the instructions used by the controller 1304;

[0181] Unified memory 1306, input memory 1301, weighted memory 1302, and instruction fetch memory 1309 are all on-chip memories. External memory is proprietary to this NPU hardware architecture.

[0182] In the training or inference application scenarios of neural networks, the operations of each layer in the neural network can be performed by the operation circuit 1303 or the vector calculation unit 1307.

[0183] For example, in conjunction with the foregoing Figures 4 to 10 In the corresponding method flow, when the message is generated internally by a node, it can be calculated and generated using the aforementioned weight memory 1302, arithmetic circuit 1303, vector calculation unit 1307, or accumulator 1308, etc., and can be executed by the controller 1304. Figures 4 to 10 The method utilizes the bus interface unit 1310 to communicate with other nodes, thereby routing messages to other nodes. When a message is received by the controller 1304 through the bus interface unit 1310, the bus interface unit 1310 can execute the method provided in this application embodiment to route the message to other nodes through the bus interface unit 1310.

[0184] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more processors used to control the above. Figures 4 to 10 The method of program execution of integrated circuits.

[0185] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., including several instructions to cause a device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0186] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0187] This application also provides a computer-readable storage medium storing a program for training a model or performing inference tasks. When the program is run on a computer, it causes the computer to perform all or part of the steps of the decoding method provided in the foregoing embodiments of this application.

[0188] This application also provides a digital processing chip. This digital processing chip integrates circuitry for implementing the aforementioned processor or processor functions, and one or more interfaces. When the digital processing chip integrates a memory, it can perform the method steps of any one or more of the foregoing embodiments. When the digital processing chip does not integrate a memory, it can be connected to an external memory via a communication interface. The digital processing chip implements the method steps of any one or more of the foregoing embodiments based on the program code stored in the external memory.

[0189] This application also provides a computer program product comprising one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0190] The encoding or decoding device provided in this application embodiment can be a chip, which includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip in the server to execute the steps of the decoding method provided in the foregoing embodiments of this application. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. The storage unit can also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0191] Specifically, the aforementioned processing unit or processor can be a central processing unit (CPU), a neural-network processing unit (NPU), a graphics processing unit (GPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0192] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0193] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0194] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0195] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0196] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. The term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or devices. The naming or numbering of steps in this application does not imply that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effect can be achieved. The division of modules in this application is a logical division. In actual applications, there may be other division methods. For example, multiple modules may be combined into or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the modules shown or discussed may be through some ports, and the indirect coupling or communication connection between modules may be electrical or other similar forms, which are not limited in this application. Furthermore, the modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed in multiple circuit modules. Some or all of the modules can be selected to achieve the purpose of the solution in this application according to actual needs.

Claims

1. A data transmission method, characterized by, Applied to a cluster, the cluster comprising a plurality of nodes connected directly, comprising: A first node acquires a first message, the first node being any one node in the cluster, the first message carrying information of a first destination node; The first node queries a forwarding port in a priority routing table based on the information of the first destination node, the priority routing table comprising a relationship between a hop number and a port of the first node and the first destination node; The first node forwards the first message through the forwarding port.

2. The method of claim 1, wherein, The priority routing table comprises a port corresponding to an Nth hop, the N being an integer.

3. The method of claim 2, wherein, The first node queries a forwarding port in a priority routing table based on the information of the first destination node, comprising: The first node acquires at least one port corresponding to a hop number of the first destination node from the priority routing table; The first node determines the forwarding port from the at least one port corresponding to the hop number of the first destination node in an order of increasing hop number.

4. The method according to any one of claims 1-3, characterized in that, The first node forwards the first message through the forwarding port, comprising: The first node determines an output queue through an input queue and the forwarding port; The first node forwards the first message through the output queue.

5. The method of claim 4, wherein, The first node determines an output queue range through the input sequence and the forwarding port, the output queue range comprising at least one queue; The first node determines the output queue according to a congestion situation of the queue in the output queue range. The plurality of nodes are divided into a plurality of dimensions, nodes in a same dimension being connected directly, one node being divided into at least two dimensions, a number of queues between a pair of nodes being greater than a number of the dimensions.

6. The method according to claim 4 or 5, characterized in that, Applied to a cluster, the cluster comprising a plurality of nodes connected directly, comprising:

7. A node, characterized by A receiving module, configured to acquire a first message, the first node being any one node in the cluster, the first message carrying information of a first destination node; A routing module, configured to query a forwarding port in a priority routing table based on the information of the first destination node, the priority routing table comprising a relationship between a hop number and a port of the first node and the first destination node; A sending module, further configured to forward the first message through the forwarding port. The priority routing table comprises a port corresponding to an Nth hop, the N being an integer.

8. The node of claim 7, characterized in that, The routing module, specifically configured to:

9. The node of claim 8, characterized in that, Acquire at least one port corresponding to a hop number of the first destination node from the priority routing table; Determine the forwarding port from the at least one port corresponding to the hop number of the first destination node in an order of increasing hop number.

10. The node of any one of claims 7-9, wherein The routing module is further configured to determine an output queue through an input queue and the forwarding port; The sending module is specifically configured to forward the first message through the output queue. The routing module is specifically configured to:

11. The node of claim 10, characterized in that, ​ determining an output queue range according to the input sequence and the forwarding port, the output queue range including at least one queue; determining the output queue according to congestion of queues in the output queue range.

12. The node of claim 10 or 11, characterized by The plurality of nodes are divided into a plurality of dimensions, nodes in the same dimension are directly connected, one node is divided into at least two dimensions, and the number of queues between a pair of nodes is greater than the number of dimensions.

13. A cluster, characterized by At least including a plurality of nodes directly connected, the plurality of nodes including nodes for executing the method of any one of claims 1 to 6.

14. A server, characterized by comprising: a processor coupled to the memory, the memory storing a program, when the program instruction stored in the memory is executed by the processor, the steps of the method of any one of claims 1-6 are implemented.

15. A chip, characterized by comprising: a processing unit and a communication interface, the processing unit obtains program instructions through the communication interface, and the program instructions are executed by the processing unit to implement the steps of the method of any one of claims 1-6.

16. A computer program product comprising instructions, characterized in that, When the instructions are executed by the device, the device performs the operation steps of the method of any one of claims 1 to 6.

17. A computer readable storage medium characterized by comprising computer program instructions, when the computer program instructions are executed by the device, the device performs the operation steps of the method of any one of claims 1 to 6.

Images