Programmable SDI video signal generation system based on FPGA

Abstract

The invention provides an FPGA (Field Programmable Gate Array)-based programmable SDI (Serial Digital Interface) video signal generation system, which is integrated on a single FPGA chip and comprises an upper-layer control module, a gigabit Ethernet communication module, a target generation module and a video processing module, the PC end software issues a user configuration instruction, the instruction is analyzed by the communication module and then controls the target generation module to generate a dynamic target video stream, the video processing module synthesizes a background video and the target stream and performs SDI coding output, and programmable, multi-target and real-time SDI video test signal generation is realized. According to the invention, highly integrated and real-time programmable SDI video signal generation can be realized, various dynamic target video streams can be flexibly generated, complex scene synthesis and standard and non-standard SDI signal output are supported, the efficiency, coverage rate and repeatability of video detection and tracking algorithm test are improved, and the test cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of video testing equipment technology, and more specifically, to an FPGA-based programmable SDI video signal generation system. Background Technology

[0002] In the field of functional verification and performance evaluation of video detection and tracking algorithms, existing technologies have many shortcomings. Traditional video test signal generators can typically only produce simple signals such as color bars, grayscale images, and checkerboard patterns, and cannot generate complex, dynamic simulated targets or specific model targets, such as airplanes and tanks. When using pre-recorded real videos or CGI animations for algorithm testing, there are problems with poor flexibility and insufficient controllability. Target parameters are difficult to adjust, there is a lot of background interference, and it is difficult to accurately reproduce specific test scenarios, such as low contrast, high-speed motion, occlusion, and other complex situations. In addition, most existing commercial programmable graphics generators lack support for non-standard resolution SDI interfaces, and for the generation of model targets, existing solutions often rely on external rendering engines, resulting in low integration, high cost, and high power consumption.

[0003] In implementing the embodiments of the present invention, the prior art has at least the following problems or defects: it cannot meet the requirements of video detection and tracking algorithm testing for complex dynamic targets and controllable backgrounds, and it has obvious deficiencies in terms of integration, flexibility, and cost control. Summary of the Invention

[0004] This invention provides an FPGA-based programmable SDI video signal generation system, comprising:

[0005] The upper-level control module is used to run PC-side software to receive user configuration commands;

[0006] The communication module is connected to the upper-layer control module via Gigabit Ethernet and is used to receive and parse the user configuration commands;

[0007] A target generation module, connected to the communication module, is used to generate one or more dynamic target video streams based on the parameters parsed by the communication module.

[0008] The video processing module is connected to the communication module and the target generation module respectively, and is used to receive background video data and the dynamic target video stream, perform scene synthesis and SDI encoding processing, and output SDI video signal;

[0009] Each module of the system is integrated onto a single FPGA chip.

[0010] Furthermore, the communication module includes:

[0011] The gigabit network MAC module is used to implement the gigabit UDP network communication protocol and receive configuration information from the upper-layer control module;

[0012] The parameter parsing module, connected to the gigabit network MAC module, is used to parse the configuration information and store target parameters and scene parameters. The target parameters include target position, target size, target rotation angle, target movement speed, target color, target occlusion time, target scaling factor, and target movement trajectory. The scene parameters include video resolution, video frame rate, video contrast, and background type.

[0013] Furthermore, the target generation module includes:

[0014] The simulated target generation module is used to generate parameterized geometric targets in real time based on graphical calculation formulas;

[0015] The model target generation module is used to generate parameterized model targets based on pre-stored model bitmap matrix information;

[0016] A control interface module, connected to the communication module, is used to receive the target parameters and control the simulated target generation module and the model target generation module.

[0017] Furthermore, the simulated target generation module generates geometric shapes based on the current pixel coordinates (X,Y) and the target center point coordinates (X0,Y0), and the shape calculation formula includes:

[0018] The formula for determining a circle is: (X - X0) 2 +(Y-Y0) 2 ≤R 2 Where R is the radius of the circle, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point;

[0019] The formula for determining a ring shape is: R0 2 ≤(X-X0) 2 +(Y-Y0) 2 ≤R1 2 Where R0 is the inner ring radius, R1 is the outer ring radius, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point;

[0020] The formula for determining a square is: X0-W / 2≤X≤X0+W / 2 and Y0-H / 2≤Y≤Y0+H / 2, where W is the width, H is the height, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point.

[0021] The formula for determining a cross shape is: X = X0 and (Y0 - L / 2 ≤ Y ≤ Y0 + L / 2) or Y = Y0 and (X0 - L / 2 ≤ X ≤ X0 + L / 2), where L is the length of the cross line end, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point.

[0022] The formula for determining the ray is: (Y-Y0)×cosθ=(X-X0)×sinθ, where θ is the angle between the ray and the X-axis, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point.

[0023] Furthermore, the model target generation module includes:

[0024] The model memory, using the FPGA on-chip ROM, is used to store the bitmap matrix information of one or more model targets;

[0025] The scaling unit is used to scale the model using a bilinear interpolation algorithm based on the scaling factor in the target parameters; the bilinear interpolation algorithm is based on the gray values ​​I of the four adjacent pixels of the target point P(x0,y0). 11 ,I 12 ,I 21 ,I 22 Perform the calculation, where x0 is the X-axis coordinate of the target point, y0 is the Y-axis coordinate of the target point, and I 11 I represents the grayscale value of the pixel adjacent to the top left corner. 12 I represents the grayscale value of the pixel adjacent to the top right corner. 21 I represents the grayscale value of the pixel adjacent to the bottom left corner. 22 The grayscale value of the pixel adjacent to the bottom right corner;

[0026] A rotation unit is used to perform a rotation transformation on the model using a rotation matrix based on the rotation angle in the target parameters; the rotation matrix R is:

[0027]

[0028] The formula for calculating the coordinates pp after rotation is: pp=R×(pc)+c, where p is the original pixel coordinate, c is the coordinate of the rotation center point, pp is the pixel coordinate after rotation, and θ is the rotation angle;

[0029] A motion control unit is used to control the change of the target center coordinates (X0, Y0) according to the motion trajectory and motion speed in the target parameters; the motion trajectory includes linear motion and parabolic motion; the formula for calculating the linear motion is: X0 = X x +V x×T,Y0=Y y +V y ×T, where (X) x ,Y y V represents the target starting position. x The velocity is in the X-axis direction, and the velocity is in the Y-axis direction. y Let X be the velocity along the Y-axis, T be the time in frames, X0 be the real-time X-axis coordinate of the target center, and Y0 be the real-time Y-axis coordinate of the target center; the formula for calculating the parabolic motion is: X = X0 + V x ×T,Y=Y0+(1 / 2)×g×((X-X0) / V x ) 2 V x denoted as X, where X is the initial velocity along the X-axis, g is the gravitational acceleration, X is the target's real-time X-axis coordinate, Y is the target's real-time Y-axis coordinate, X0 is the target's initial X-axis coordinate, Y0 is the target's initial Y-axis coordinate, and T is the time in frames.

[0030] Furthermore, the video processing module includes:

[0031] The SDI video decoding module is used to receive external SDI input signals, deserialize them using the FPGA's internal primitives, and decode them into standard timing video data using the SDI-RXIP core.

[0032] A frame buffer processing module, connected to the SDI video decoding module and the communication module, is used to buffer video data using DDR3 memory; the frame buffer processing module adopts a triple buffering mechanism and a polling read / write arbitration strategy;

[0033] The scene compositing module, connected to both the frame buffer processing module and the target generation module, is used to perform alpha blending of the background video and the foreground dynamic target video stream; the alpha blending algorithm is as follows:

[0034] R(C)=[(256-Alpha)×R(B)+Alpha×R(A)]>>8

[0035] G(C)=[(256-Alpha)×G(B)+Alpha×G(A)]>>8

[0036] B(C)=[(256-Alpha)×B(B)+Alpha×B(A)]>>8

[0037] Where Alpha is an 8-bit transparency value, A is the background image pixel value, B is the foreground target image pixel value, C is the blended image pixel value, R is the red component, G is the green component, and B is the blue component.

[0038] The SDI video encoding module, connected to the scene synthesis module, is used to package the mixed video data according to the SDI protocol and convert it into a serial digital signal output through a GTX transceiver.

[0039] Furthermore, the sources of the background video include: real video output by the SDI video decoding module, images input from the host computer transmitted through the gigabit network MAC module, or test patterns generated internally by the FPGA.

[0040] Furthermore, the hardware circuitry of the system includes:

[0041] The minimum system circuit for an FPGA includes an FPGA chip, a QSPI FLASH configuration chip, and a crystal oscillator.

[0042] A DDR3 storage circuit, connected to the FPGA chip, is used to provide video frame buffer space;

[0043] A network PHY circuit, connected to the FPGA chip, is used to implement a Gigabit Ethernet physical layer interface;

[0044] The SDI input equalization circuit uses an LMH1219 chip, which is connected to the FPGA chip, and is used to equalize and restore the clock of the input SDI signal.

[0045] The SDI output driver circuit uses an LMH1218 chip, which is connected to the FPGA chip to drive the output SDI signal.

[0046] Furthermore, the upper-level control module is a PC-based software written in C++, providing a human-computer interaction interface, which includes a self-test module, a basic information module, a data export module, and a data erasure module.

[0047] Furthermore, the control interface module allows users to perform operations through the upper-level control module, including: selecting the target type, setting the target parameters, and setting the scene parameters.

[0048] The embodiments of the present invention have at least the following beneficial effects:

[0049] 1. This invention achieves a highly integrated design by integrating all key functional modules onto a single FPGA chip. This integration not only improves the system's real-time performance but also reduces power consumption and cost. Compared to traditional solutions that rely on external rendering engines or multiple independent devices, the system of this invention is more compact and efficient, capable of quickly responding to user commands and generating complex dynamic target video streams in real time, thus solving the problems of low integration, high power consumption, high cost, and slow response speed in existing technologies.

[0050] 2. This invention provides powerful programmability and flexibility, allowing users to dynamically program and control various parameters of the target through an upper-level control module, including the target's position, size, rotation angle, movement speed, color, occlusion time, scaling factor, and movement trajectory. This high degree of programmability enables users to quickly adjust test scenarios according to different test requirements and generate various complex dynamic targets, thereby solving the problems of poor test scenario flexibility and difficulty in accurately reproducing specific test scenarios in existing technologies, and greatly improving the efficiency and coverage of video detection and tracking algorithm testing.

[0051] 3. This invention supports the generation of both standard SDI and non-standard SDI video signals, enabling algorithm testing across a wider range of video processing systems. Simultaneously, the system provides controllable background options, including pre-loaded images, real camera footage, or test patterns generated internally by the FPGA, simulating complex real-world environments. This diverse support for backgrounds and video signals allows the invention to meet the needs of different testing environments, solving the problems of insufficient support for non-standard resolution SDI interfaces and excessive background interference in existing technologies, thus improving the accuracy and reliability of algorithm testing. Attached Figure Description

[0052] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein:

[0053] Figure 1 This is a schematic diagram of the structure of an FPGA-based programmable SDI video signal generation system according to an embodiment of the present invention;

[0054] Figure 2 This is a schematic diagram of an FPGA chip structure provided in an embodiment of the present invention;

[0055] Figure 3 This is a schematic diagram of coordinate rotation provided in an embodiment of the present invention;

[0056] Figure 4 This is a schematic diagram of video frame buffering provided in an embodiment of the present invention;

[0057] Figure 5 This is a schematic diagram of a DDR3 memory circuit provided in an embodiment of the present invention;

[0058] Figure 6 This is a schematic diagram of a network PHY circuit provided in an embodiment of the present invention;

[0059] Figure 7 This is a schematic diagram of an SDI input equalization circuit provided in an embodiment of the present invention;

[0060] Figure 8 This is a schematic diagram of an SDI output drive circuit provided in an embodiment of the present invention. Detailed Implementation

[0061] The principles and spirit of the invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided to make the invention more thorough and complete, and to fully convey the scope of the invention to those skilled in the art.

[0062] Those skilled in the art will understand that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, the present invention can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0063] It should be noted that the number of any elements in the accompanying drawings is for illustrative purposes only and not as a limitation, and any naming is for distinction only and has no limiting meaning.

[0064] The following is for reference. Figure 1 , Figure 1 This is a schematic diagram of the structure of an FPGA-based programmable SDI video signal generation system according to an embodiment of the present invention. Figure 1 As shown, an FPGA-based programmable SDI video signal generation system includes:

[0065] The upper-level control module is used to run PC-side software to receive user configuration commands;

[0066] The communication module is connected to the upper-layer control module via Gigabit Ethernet and is used to receive and parse the user configuration commands;

[0067] A target generation module, connected to the communication module, is used to generate one or more dynamic target video streams based on the parameters parsed by the communication module.

[0068] The video processing module is connected to the communication module and the target generation module respectively, and is used to receive background video data and the dynamic target video stream, perform scene synthesis and SDI encoding processing, and output SDI video signal;

[0069] Each module of the system is integrated onto a single FPGA chip.

[0070] It should be noted that the FPGA-based programmable SDI video signal generation system of this invention is a highly integrated video testing device. Its core lies in the real-time generation and processing of video signals through an FPGA chip. FPGA, or Field-Programmable Gate Array, is a programmable integrated circuit that can be programmed in the field to implement specific functions. This system receives user configuration commands through an upper-level control module. These commands are transmitted via Gigabit Ethernet to the communication module for parsing, thereby controlling the target generation module and video processing module to generate the dynamic target video stream and output the SDI video signal. SDI, or Serial Digital Interface, is a standard interface for transmitting digital video signals and is widely used in video production and transmission. Figure 2 As shown, all modules of the system are integrated on a single FPGA chip, achieving a high degree of hardware integration and improving the system's real-time performance and flexibility.

[0071] Specifically, the upper-layer control module is PC-based software written in C++, providing a human-computer interaction interface through which users can input various configuration commands, such as target type, target parameters, and scene parameters. The communication module includes a gigabit network MAC module and a parameter parsing module. The gigabit network MAC module is responsible for implementing the gigabit UDP network communication protocol and receiving configuration information from the upper-layer control module; the parameter parsing module parses this configuration information and stores the target and scene parameters. Target parameters include target position, target size, target rotation angle, target movement speed, target color, target occlusion time, target scaling factor, and target movement trajectory; scene parameters include video resolution, video frame rate, video contrast, and background type. The target generation module generates a dynamic target video stream based on the parsed parameters, including a simulated target generation module and a model target generation module. The simulated target generation module generates parameterized geometric targets in real time based on graphic calculation formulas, such as circles, rings, squares, and crosses; the model target generation module generates parameterized model targets, such as airplanes and tanks, based on pre-stored model bitmap raster information. The video processing module receives background video data and dynamic target video streams, performs scene compositing and SDI encoding, and outputs an SDI video signal. The background video can be an external SDI input signal, an image input from a host computer, or a test pattern generated internally by the FPGA.

[0072] Preferably, for the model target generation module, the model construction process is as follows: First, the bitmap information of the relevant model targets is pre-stored in the FPGA's on-chip ROM. These models can be complex contour models such as airplanes, tanks, and vehicles. The model library can be updated by receiving data transmitted from the host computer via the network port. When generating model targets, the model is transformed according to the received parameters, such as position, scaling, rotation, speed, and occlusion. For example, scaling uses a bilinear interpolation algorithm, which calculates based on the grayscale values ​​of the four adjacent pixels of the target point to achieve smooth scaling of the model. Rotation uses a rotation matrix for coordinate transformation. The calculation of the rotation matrix is ​​based on the original coordinates of the target point and the rotation angle, and the rotated coordinates are obtained through matrix operations. The motion control unit controls the change of the target center coordinates according to the motion trajectory and speed in the target parameters to achieve dynamic motion of the target. For example, linear motion updates the target center coordinates by calculating the target's initial position, speed, and time; parabolic motion calculates the target's real-time coordinates based on the initial velocity, gravitational acceleration, and time. These operations enable the model targets to undergo precise dynamic changes according to the user-defined parameters, meeting the needs of different testing scenarios.

[0073] In some embodiments, the communication module includes:

[0074] The gigabit network MAC module is used to implement the gigabit UDP network communication protocol and receive configuration information from the upper-layer control module;

[0075] The parameter parsing module, connected to the gigabit network MAC module, is used to parse the configuration information and store target parameters and scene parameters. The target parameters include target position, target size, target rotation angle, target movement speed, target color, target occlusion time, target scaling factor, and target movement trajectory. The scene parameters include video resolution, video frame rate, video contrast, and background type.

[0076] It should be noted that the communication module of this invention is a key component for command transmission and parsing within the system. It connects to the upper-layer control module via Gigabit Ethernet, receiving and parsing configuration commands sent by the user through the PC software. The Gigabit Ethernet MAC module is responsible for implementing the Gigabit UDP network communication protocol, ensuring high-speed data transmission and accurate reception. The parameter parsing module performs detailed parsing of this configuration information and stores the target parameters and scene parameters separately for subsequent module calls. Target parameters encompass various attributes of the target in the video scene, such as position, size, and rotation angle, while scene parameters define the overall characteristics of the video, such as resolution and frame rate. The accurate parsing and storage of these parameters provides the foundation for the accurate operation of the subsequent target generation module and video processing module.

[0077] Specifically, the gigabit network MAC module in the communication module is implemented based on the gigabit UDP network communication protocol. It can receive configuration information from the upper-layer control module, which contains various parameters required to generate dynamic target video streams. The parameter parsing module is connected to the gigabit network MAC module, and its main function is to parse the received configuration information and store the parsed parameters. Target parameters include target position, X and Y coordinates, target size, width W and height H, target rotation angle, target movement speed, speed in the X and Y axis directions, target color, target occlusion time, target scaling factor, and target movement trajectory, etc. Scene parameters include video resolution, such as 1920×1080, video frame rate, such as 30fps, video contrast, such as 50%, and background type, such as solid color background or specific pattern background, etc. The setting of these parameters allows users to accurately define the characteristics of each target and the entire video scene according to different testing requirements.

[0078] Preferably, after receiving the configuration information, the parameter parsing module parses this information according to a preset format. For example, for target position parameters, it parses the specific X and Y coordinates of the target in the video frame; for target size parameters, it parses the specific values ​​of the target's width W and height H. This precise parameter parsing process ensures that subsequent modules can accurately generate targets and process video based on these parameters. In terms of storage, the parameter parsing module stores the parsed parameters in the FPGA's internal storage unit so that the target generation module and video processing module can access them at any time. This precise parsing and storage mechanism guarantees that the system can accurately generate the required dynamic target video stream according to the user's configuration instructions and perform effective video processing.

[0079] In some embodiments, the target generation module includes:

[0080] The simulated target generation module is used to generate parameterized geometric targets in real time based on graphical calculation formulas;

[0081] The model target generation module is used to generate parameterized model targets based on pre-stored model bitmap matrix information;

[0082] A control interface module, connected to the communication module, is used to receive the target parameters and control the simulated target generation module and the model target generation module.

[0083] It should be noted that the target generation module of this invention is the core component of the system for generating dynamic target video streams. It includes a simulated target generation module, a model target generation module, and a control interface module. The simulated target generation module can generate parameterized geometric targets, such as circles and squares, in real time based on graphical calculation formulas. The model target generation module generates parameterized model targets, such as airplanes and tanks, based on pre-stored model bitmap information. The control interface module is connected to the communication module and is used to receive target parameters and control the simulated target generation module and the model target generation module. These modules work together to achieve flexible generation and precise control of dynamic targets, providing diverse testing scenarios for video testing.

[0084] Specifically, the simulated target generation module in the target generation module generates various geometric targets by calculating the relationship between pixel coordinates and target center point coordinates in real time using specific graphic calculation formulas. For example, the formula for determining whether a pixel belongs to a circle is based on whether the distance between the current pixel and the center point of the circle is less than or equal to the radius. The determination of a square is based on whether the pixel is located within a rectangular area centered on the target center point. The model target generation module is based on pre-stored model bitmap dot matrix information, which is stored in the FPGA's on-chip ROM. It maps the model data to the corresponding position on the screen using index information and transforms the model according to target parameters, such as scaling and rotation. The control interface module receives target parameters from the communication module. These parameters include the target's position, size, rotation angle, and movement speed, and are used to control the output of the simulated target generation module and the model target generation module. The setting of these parameters allows users to generate targets with specific attributes according to test requirements.

[0085] Preferably, when constructing a model, the model target generation module first needs to store the bitmap information of the model into the FPGA's on-chip ROM. These models can be common object outlines, such as airplanes, tanks, and vehicles. The storage process can be completed by receiving data transmitted from the host computer via the network port, allowing the model library to be updated as needed. When generating the model target, the model is transformed according to the target parameters. For example, scaling is implemented using a bilinear interpolation algorithm, which calculates based on the grayscale values ​​of the four adjacent pixels of the target point to smoothly change the size of the model. Rotation is implemented using a rotation matrix, which calculates new pixel coordinates based on the rotation angle, thereby changing the orientation of the model. The motion control unit controls the dynamic changes of the model based on the motion trajectory and velocity in the target parameters. For example, linear motion is achieved by calculating the new position of the target in each frame, while parabolic motion is achieved by calculating the trajectory of the target based on the initial velocity and gravitational acceleration. These detailed processing steps ensure that the model target can be accurately generated and moved according to the user-defined parameters, meeting various requirements for dynamic targets in video testing.

[0086] In some embodiments, the simulated target generation module generates a geometric shape based on the current pixel coordinates (X,Y) and the target center point coordinates (X0,Y0), and the shape calculation formula includes:

[0087] The formula for determining a circle is: (X - X0) 2 +(Y-Y0) 2 ≤R 2 Where R is the radius of the circle, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point;

[0088] The formula for determining a ring shape is: R0 2 ≤(X-X0) 2 +(Y-Y0) 2 ≤R1 2 Where R0 is the inner ring radius, R1 is the outer ring radius, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point;

[0089] The formula for determining a square is: X0-W / 2≤X≤X0+W / 2 and Y0-H / 2≤Y≤Y0+H / 2, where W is the width, H is the height, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point.

[0090] The formula for determining a cross shape is: X = X0 and (Y0 - L / 2 ≤ Y ≤ Y0 + L / 2) or Y = Y0 and (X0 - L / 2 ≤ X ≤ X0 + L / 2), where L is the length of the cross line end, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point.

[0091] The formula for determining the ray is: (Y-Y0)×cosθ=(X-X0)×sinθ, where θ is the angle between the ray and the X-axis, X is the X-axis coordinate of the current pixel, Y is the Y-axis coordinate of the current pixel, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point.

[0092] It should be noted that the simulated target generation module of this invention is an important component of the target generation module. Its function is to generate parameterized geometric targets in real time based on graphic calculation formulas. These geometric shapes include circles, toroidals, squares, crosses, and rays, etc., which can be defined by specific mathematical formulas. These formulas are based on the relationship between the current pixel coordinates and the target center point coordinates, and calculate whether each pixel belongs to a specific geometric shape. This real-time generation method enables the system to flexibly create various dynamic targets to meet the needs of different video testing scenarios.

[0093] Specifically, the circular determination formula in the simulated target generation module is based on the geometric definition of a circle, meaning all points whose distance from the center does not exceed the radius belong to that circle. The annular determination formula is based on the region between two concentric circles, judging by whether the distance from the pixel to the center is between the inner and outer radii. The square determination formula is based on the geometric properties of a rectangle, judging by whether the pixel is located within a rectangular area centered on the target's center point. The cross determination formula is based on two perpendicularly intersecting line segments, judging by whether the pixel lies on either line segment. The ray determination formula is based on the geometric definition of a ray, judging by calculating the angle between the pixel and the ray. The parameters in these formulas, such as the radius R of the circle, the width W and height H of the square, the length L of the line ends of the cross, and the angle θ between the ray and the X-axis, can all be set via user configuration commands, thus enabling flexible control over the target's shape and size.

[0094] Preferably, when generating geometric shapes, the simulated target generation module calculates the attributes of each pixel in real time based on the parameters input by the user through the upper-level control module. For example, when generating a circle, the system calculates the attributes of each pixel based on the user-defined center coordinates (X0, Y0) and radius R using the formula (X-X0). 2 +(Y-Y0) 2 ≤R 2The system determines whether each pixel belongs to the circle. For squares, it uses the user-defined width W and height H, along with the center coordinates (X0, Y0), to determine if a pixel belongs to the square area using the formulas X0-W / 2≤X≤X0+W / 2 and Y0-H / 2≤Y≤Y0+H / 2. These calculations are performed in real-time on the FPGA chip, ensuring efficient and real-time target generation. In this way, users can precisely define the shape and size of each target according to test requirements, thereby generating a dynamic target video stream that meets the test requirements.

[0095] In some embodiments, the model target generation module includes:

[0096] The model memory, using the FPGA on-chip ROM, is used to store the bitmap matrix information of one or more model targets;

[0097] The scaling unit is used to scale the model using a bilinear interpolation algorithm based on the scaling factor in the target parameters; the bilinear interpolation algorithm is based on the gray values ​​I of the four adjacent pixels of the target point P(x0,y0). 11 ,I 12 ,I 21 ,I 22 Perform the calculation, where x0 is the X-axis coordinate of the target point, y0 is the Y-axis coordinate of the target point, and I 11 I represents the grayscale value of the pixel adjacent to the top left corner. 12 I represents the grayscale value of the pixel adjacent to the top right corner. 21 I represents the grayscale value of the pixel adjacent to the bottom left corner. 22 The grayscale value of the pixel adjacent to the bottom right corner;

[0098] A rotation unit is used to perform a rotation transformation on the model using a rotation matrix based on the rotation angle in the target parameters; the rotation matrix R is:

[0099]

[0100] like Figure 3 As shown, the formula for calculating the coordinates pp after rotation is: pp=R×(pc)+c, where p is the original pixel coordinate, c is the coordinate of the rotation center point, pp is the pixel coordinate after rotation, and θ is the rotation angle;

[0101] A motion control unit is used to control the change of the target center coordinates (X0, Y0) according to the motion trajectory and motion speed in the target parameters; the motion trajectory includes linear motion and parabolic motion; the formula for calculating the linear motion is: X0 = X x +V x ×T,Y0=Y y +V y×T, where (X) x ,Y y V represents the target starting position. x The velocity is in the X-axis direction, and the velocity is in the Y-axis direction. y Let X be the velocity along the Y-axis, T be the time in frames, X0 be the real-time X-axis coordinate of the target center, and Y0 be the real-time Y-axis coordinate of the target center; the formula for calculating the parabolic motion is: X = X0 + V x ×T,Y=Y0+(1 / 2)×g×((X-X0) / V x ) 2 V x denoted as X, where X is the initial velocity along the X-axis, g is the gravitational acceleration, X is the target's real-time X-axis coordinate, Y is the target's real-time Y-axis coordinate, X0 is the target's initial X-axis coordinate, Y0 is the target's initial Y-axis coordinate, and T is the time in frames.

[0102] It should be noted that the model target generation module of this invention is a key component of the target generation module, used to generate parameterized model targets based on pre-stored model bitmap raster information. These model targets can be complex contour models, such as airplanes, tanks, and vehicles. The model target generation module includes a model memory, a scaling unit, a rotation unit, and a motion control unit. These units work together to realize the storage, scaling, rotation, and motion control of the model. Through these functions, the system can flexibly generate various dynamic model targets, meeting the needs of complex targets in video testing.

[0103] Specifically, the model memory uses on-chip ROM on the FPGA to store bitmap information of one or more model targets. These models can be updated by receiving data transmitted from the host computer via the network port, allowing the model library to be customized and expanded according to testing needs. The scaling unit uses a bilinear interpolation algorithm to scale the model, which calculates the scaling effect based on the grayscale values ​​of the four adjacent pixels of the target point. The rotation unit performs rotation transformation on the model using a rotation matrix, which calculates the new pixel coordinates based on the rotation angle. The motion control unit controls the change of the target's center coordinates based on the motion trajectory and velocity in the target parameters, realizing the dynamic movement of the target. These parameters include the target's starting position, velocity, rotation angle, scaling factor, etc., all of which can be set through user configuration commands, thereby achieving precise control of the model target.

[0104] Preferably, when constructing a model, the model target generation module first needs to store the bitmap information of the model into the FPGA's on-chip ROM. These models can be common object outlines, such as airplanes, tanks, and vehicles. The storage process can be completed by receiving data transmitted from the host computer via the network port, allowing the model library to be updated as needed. When generating the model target, the model is transformed according to the target parameters. For example, scaling is implemented using a bilinear interpolation algorithm, which calculates based on the grayscale values ​​of the four adjacent pixels of the target point to smoothly change the size of the model. Rotation is implemented using a rotation matrix, which calculates new pixel coordinates based on the rotation angle, thereby changing the orientation of the model. The motion control unit controls the dynamic changes of the model based on the motion trajectory and velocity in the target parameters. For example, linear motion is achieved by calculating the new position of the target in each frame, while parabolic motion is achieved by calculating the trajectory of the target based on the initial velocity and gravitational acceleration. These detailed processing steps ensure that the model target can be accurately generated and moved according to the user-defined parameters, meeting various requirements for dynamic targets in video testing.

[0105] In some embodiments, the video processing module includes:

[0106] The SDI video decoding module is used to receive external SDI input signals, deserialize them using the FPGA's internal primitives, and decode them into standard timing video data using the SDI-RXIP core.

[0107] A frame buffer processing module, connected to the SDI video decoding module and the communication module, is used to buffer video data using DDR3 memory; the frame buffer processing module adopts a triple buffering mechanism and a polling read / write arbitration strategy;

[0108] The scene compositing module, connected to both the frame buffer processing module and the target generation module, is used to perform alpha blending of the background video and the foreground dynamic target video stream; the alpha blending algorithm is as follows:

[0109] R(C)=[(256-Alpha)×R(B)+Alpha×R(A)]>>8

[0110] G(C)=[(256-Alpha)×G(B)+Alpha×G(A)]>>8

[0111] B(C)=[(256-Alpha)×B(B)+Alpha×B(A)]>>8

[0112] Where Alpha is an 8-bit transparency value, A is the background image pixel value, B is the foreground target image pixel value, C is the blended image pixel value, R is the red component, G is the green component, and B is the blue component.

[0113] The SDI video encoding module, connected to the scene synthesis module, is used to package the mixed video data according to the SDI protocol and convert it into a serial digital signal output through a GTX transceiver.

[0114] It should be noted that the video processing module of this invention is a key component of the system for processing background video and dynamic target video streams. Its function is to receive background video data and dynamic target video streams, perform scene compositing and SDI encoding, and output SDI video signals. The SDI video decoding module is responsible for decoding the external SDI input signal into standard time-series video data. The frame buffer processing module uses DDR3 memory to buffer the video data. The scene compositing module performs alpha mixing between the background video and the foreground dynamic target video stream. Finally, the SDI video encoding module packages and outputs the mixed video data according to the SDI protocol. This series of operations ensures efficient video signal processing and high-quality output.

[0115] Specifically, the video processing module includes the following key components: the SDI video decoding module uses internal FPGA primitives for deserialization and decodes external SDI input signals into standard timing video data via the SDI-RX IP core; the frame buffer processing module connects to the SDI video decoding module and the communication module, using DDR3 memory to buffer video data, employing a triple-buffering mechanism and a polling read-write arbitration strategy to prevent screen tearing; the scene compositing module performs alpha blending of the background video and the foreground dynamic target video stream, with the blending algorithm using a weighted average of the background and foreground pixel values ​​based on the transparency alpha value to generate the blended video pixel values; and the SDI video encoding module packages the blended video data according to the SDI protocol and converts it into a serial digital signal output via a GTX transceiver. The background video can originate from the real video output by the SDI video decoding module, images input from the host computer transmitted via the gigabit network MAC module, or test patterns generated internally by the FPGA. These functional modules work together to realize a complete processing flow from video input to output.

[0116] Preferably, when the frame buffer processing module uses DDR3 memory for video data buffering, it employs a triple-buffering mechanism, meaning it uses three buffers simultaneously for data read and write operations. This mechanism effectively avoids screen tearing during video processing, ensuring video smoothness and stability. When the scene compositing module performs alpha blending, the transparency value Alpha is an 8-bit grayscale channel ranging from 0 to 255, where 0 represents complete opacity and 255 represents complete transparency. The blending algorithm calculates the pixel values ​​of the blended image by weighted averaging of the background image pixel values ​​and the foreground target image pixel values. For example, for the red component R, the blended pixel value R(C) = [(256-Alpha)×R(B)+Alpha×R(A)]>>8, where A is the background image pixel value, B is the foreground target image pixel value, and C is the blended image pixel value. This blending method can be flexibly adjusted according to the transparency requirements of the target, achieving a natural blending of the background and foreground. When packaging the mixed video data according to the SDI protocol, the SDI video encoding module formats the data according to the requirements of the SDI protocol to ensure that the output video signal conforms to the standard specifications and is suitable for various video processing systems.

[0117] In some embodiments, the background video may be sourced from: a real video output by the SDI video decoding module, an image input from a host computer transmitted via the gigabit network MAC module, or a test pattern generated within the FPGA.

[0118] It should be noted that the background video sources of this invention are diverse, aiming to provide a rich and flexible selection of backgrounds for video testing. The background video can originate from real video output by the SDI video decoding module, images input to the host computer via the gigabit network MAC module, or test patterns generated internally by the FPGA. This diversity of background sources enables the system to simulate various real and virtual test scenarios, meeting the testing requirements of different video detection and tracking algorithms.

[0119] Specifically, there are three main sources of background video: First, real video output from the SDI video decoding module. This video originates from external SDI input signals, is deserialized using primitives within the FPGA, and decoded into standard timing video data using the SDI-RX IP core, providing a realistic video scene. Second, images input from the host computer are transmitted via the gigabit network MAC module. These images can be pre-prepared test images transmitted to the system over the network for specific test scenarios. Third, test patterns are generated internally by the FPGA. These patterns can be simple geometric shapes, such as colored bars, grayscale images, or checkerboard patterns, or complex test patterns used for basic video processing tests. This selection of background video sources provides users with great flexibility, allowing them to choose the appropriate background based on different testing needs.

[0120] Preferably, for test patterns generated internally by the FPGA, the system can generate different types of patterns according to user needs. For example, when generating a colored bar pattern, the system generates stripes of different colors row by row or column by column according to a preset color order and width ratio. For grayscale images, the system generates a gradient image from black to white based on the range and distribution of grayscale values. A checkerboard pattern is generated using alternating black and white squares and is used to test the resolution and contrast performance of the video processing system. The generation process of these test patterns is implemented through the logic circuits inside the FPGA. Users can set parameters such as the type, size, and color of the pattern through the upper-level control module to meet different test requirements. Furthermore, for externally input real video or images input from a host computer, the system receives and processes them through the corresponding interface module to ensure the integrity and real-time performance of the video data. This diverse range of background video sources and flexible processing methods enable the present invention to adapt to various complex test scenarios, improving the accuracy and reliability of video detection and tracking algorithm testing.

[0121] In some embodiments, the hardware circuitry of the system includes:

[0122] The minimum system circuit for an FPGA includes an FPGA chip, a QSPI FLASH configuration chip, and a crystal oscillator.

[0123] A DDR3 storage circuit, connected to the FPGA chip, is used to provide video frame buffer space;

[0124] A network PHY circuit, connected to the FPGA chip, is used to implement a Gigabit Ethernet physical layer interface;

[0125] The SDI input equalization circuit uses an LMH1219 chip, which is connected to the FPGA chip, and is used to equalize and restore the clock of the input SDI signal.

[0126] The SDI output driver circuit uses an LMH1218 chip, which is connected to the FPGA chip to drive the output SDI signal.

[0127] It should be noted that the hardware circuit design of this invention is the foundation of the system implementation, and its purpose is to provide the necessary hardware support for the entire FPGA-based programmable SDI video signal generation system. The hardware circuit includes an FPGA minimum system circuit, a DDR3 memory circuit, a network PHY circuit, an SDI input equalization circuit, and an SDI output driver circuit. These circuits work together to ensure that the system can efficiently process and generate SDI video signals, while guaranteeing the system's stability and reliability.

[0128] Specifically, the FPGA minimum system circuit is the core of the entire system, comprising the FPGA chip, QSPIFLASH configuration chip, and crystal oscillator. The FPGA chip is the key component for implementing system functions, responsible for running various logic algorithms and processing tasks. The QSPIFLASH configuration chip stores the FPGA's configuration file, ensuring correct loading and operation during system startup. The crystal oscillator provides a stable clock signal to the FPGA, guaranteeing the system's timing accuracy. The DDR3 memory circuit connects to the FPGA chip, providing video frame buffer space for storing and processing video data. The network PHY circuit implements the Gigabit Ethernet physical layer interface, enabling the system to receive and send data over the network. The SDI input equalization circuit uses the LMH1219 chip to equalize and clock the input SDI signal, ensuring signal quality and stability. The SDI output driver circuit uses the LMH1218 chip to drive the output SDI signal, ensuring accurate signal transmission to external devices. The design and selection of these hardware circuits are all aimed at meeting the system's requirements for high performance and high reliability.

[0129] Preferably, the selection of the FPGA chip in the FPGA minimum system circuit should consider factors such as its logic resources, number of I / O interfaces, and performance to meet the system's requirements for complex algorithms and large-scale data processing. The design of the DDR3 memory circuit needs to consider storage capacity and data transfer rate to ensure efficient caching and processing of video frame data. For example, a 1GB capacity, 32-bit DDR3 chip can be selected to meet the storage requirements of high-definition video data. The RTL8211 chip in the network PHY circuit provides a stable Gigabit Ethernet connection, supporting high-speed data transmission. The LMH1219 chip in the SDI input equalization circuit supports a rate range of 125Mbps to 11.88Gbps, is compatible with multiple SDI standards, and ensures the quality of the input signal. The LMH1218 chip in the SDI output driver circuit ensures the strength and stability of the output signal, supporting long-distance transmission. The detailed design and selection process of these hardware circuits is all aimed at ensuring the efficient and stable operation of the entire system, meeting the stringent requirements of video detection and tracking algorithm testing.

[0130] In some embodiments, the upper-level control module is PC-based software written in C++, providing a human-computer interaction interface, which includes a self-test module, a basic information module, a data export module, and a data erasure module.

[0131] It should be noted that the upper-level control module of this invention is PC-based software written in C++. Its main function is to provide a human-computer interface, enabling users to easily configure and control the entire SDI video signal generation system. Through this interface, users can set target type, target parameters, scene parameters, etc., and send these configuration commands to the FPGA chip via Gigabit Ethernet. This module is designed to improve the system's ease of use and flexibility, allowing users to quickly adjust the system configuration according to different testing needs.

[0132] Specifically, the human-machine interface of the upper-level control module includes a self-test module, a basic information module, a data export module, and a data erasure module. The self-test module checks the network connection status and the operating status of the recording device to ensure the system functions correctly upon startup. The basic information module displays basic information about the recording device, such as software version and stored data volume, helping users understand the current system status. The data export module parses and exports the collected data, including serial port data, analog data, CAN data, and video data, facilitating user analysis of test results. The data erasure module allows users to clear data stored in the system for new tests. This module design enables users to fully control and manage the entire testing process, from system checks to data processing, all within a single interface.

[0133] Preferably, during implementation, the upper-level control module optimizes each module according to different testing requirements. For example, in the self-test module, the system automatically checks the network connection and the FPGA chip's operating status to ensure all hardware devices are in good working order. In the basic information module, in addition to displaying basic information such as software version and stored data volume, the current test progress and system load can be displayed in real time. The data export module automatically identifies and parses the corresponding data format based on the user-selected data type, then exports it to the user-specified file format, such as CSV or Excel, facilitating subsequent data analysis. The data erasure module provides a secure data clearing mechanism to ensure that users do not accidentally lose important data during data clearing. Through these optimizations, the upper-level control module not only improves the system's usability but also enhances its stability and reliability, enabling the entire SDI video signal generation system to more efficiently serve the testing of video detection and tracking algorithms.

[0134] In some embodiments, the control interface module allows users to perform operations through the upper-level control module, including: selecting a target type, setting the target parameters, and setting the scene parameters.

[0135] It should be noted that the control interface module acts as a bridge between the upper-level control module and the target generation module. It allows users to perform a series of operations through the upper-level control module, including selecting the target type, setting target parameters, and setting scene parameters. These operations enable users to flexibly define and control dynamic targets and the overall scene in the video signal generation system to meet diverse testing needs.

[0136] Specifically, the control interface module's functions mainly include three aspects: First, users can select the target type through the upper-level control module. The target type can be a simulated target, such as geometric shapes like circles and squares, or a model target, such as a complex outline model like an airplane or tank. Second, users can set target parameters, including the target's position, X and Y coordinates, size (width W and height H), rotation angle, motion speed (speed along the X and Y axes), color, occlusion time, scaling factor, and motion trajectory. Finally, users can also set scene parameters, such as video resolution (e.g., 1920×1080), video frame rate (e.g., 30fps), video contrast (e.g., 50%), and background type (e.g., solid color background, specific pattern background, or realistic video background). These parameter settings are input through the upper-level control module and passed to the target generation module through the control interface module, thereby achieving precise control over the target and scene.

[0137] Preferably, the control interface module provides an intuitive user interface during implementation, enabling users to easily perform various settings. For example, when selecting a target type, users can choose the desired geometric shape or model target through a drop-down menu. When setting target parameters, users can precisely set the value of each parameter through input boxes or sliders. For model targets, users can also define the shape and appearance of the target by uploading a model file or selecting from a preset model library. When setting scene parameters, users can select different video resolutions, frame rates, and contrasts according to testing requirements, as well as choose a suitable background from various background types. These settings are all passed to the target generation module through the control interface module, thereby generating a dynamic target video stream that meets the user's needs in real time. This flexible control method enables the present invention to adapt to various complex testing scenarios, improving the efficiency and accuracy of video detection and tracking algorithm testing.

[0138] The above embodiments of the present invention have the following beneficial effects:

[0139] 1. This invention achieves a highly integrated design by integrating all key functional modules onto a single FPGA chip. This integration not only improves the system's real-time performance but also reduces power consumption and cost. Compared to traditional solutions that rely on external rendering engines or multiple independent devices, the system of this invention is more compact and efficient, capable of quickly responding to user commands and generating complex dynamic target video streams in real time, thus solving the problems of low integration, high power consumption, high cost, and slow response speed in existing technologies.

[0140] 2. This invention provides powerful programmability and flexibility, allowing users to dynamically program and control various parameters of the target through an upper-level control module, including the target's position, size, rotation angle, movement speed, color, occlusion time, scaling factor, and movement trajectory. This high degree of programmability enables users to quickly adjust test scenarios according to different test requirements and generate various complex dynamic targets, thereby solving the problems of poor test scenario flexibility and difficulty in accurately reproducing specific test scenarios in existing technologies, and greatly improving the efficiency and coverage of video detection and tracking algorithm testing.

[0141] 3. This invention supports the generation of both standard SDI and non-standard SDI video signals, enabling algorithm testing across a wider range of video processing systems. Simultaneously, the system provides controllable background options, including pre-loaded images, real camera footage, or test patterns generated internally by the FPGA, simulating complex real-world environments. This diverse support for backgrounds and video signals allows the invention to meet the needs of different testing environments, solving the problems of insufficient support for non-standard resolution SDI interfaces and excessive background interference in existing technologies, thus improving the accuracy and reliability of algorithm testing.

[0142] Furthermore, the storage medium in the embodiments of this application stores program instructions capable of implementing all the above methods. These program instructions can be stored in the storage medium in the form of a software product, including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0143] The above description is merely a selection of preferred embodiments of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention as described in the embodiments is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present invention.

Claims

1. A FPGA programmable SDI video signal generation system, characterized in that, The system comprises: an upper control module for running PC terminal software to receive user configuration instructions; a communication module connected with the upper control module through a gigabit Ethernet for receiving and analyzing the user configuration instructions; a target generation module connected with the communication module for generating one or more dynamic target video streams according to the parameters analyzed by the communication module; a video processing module connected with the communication module and the target generation module respectively for receiving background video data and the dynamic target video streams, performing scene synthesis and SDI encoding processing, and outputting an SDI video signal; wherein the modules of the system are integrated on a single FPGA chip.

2. The system of claim 1, wherein, The communication module comprises: a gigabit network MAC module for implementing a gigabit UDP network communication protocol to receive configuration information from the upper control module; a parameter analysis module connected with the gigabit network MAC module for analyzing the configuration information and storing target parameters and scene parameters; the target parameters include target position, target size, target rotation angle, target motion speed, target color, target occlusion time, target zoom factor and target motion trajectory; the scene parameters include video resolution, video frame rate, video contrast and background type.

3. The system of claim 1 or 2, wherein, The target generation module comprises: a simulated target generation module for generating parameterized geometric figure targets in real time according to a graphic calculation formula; a model target generation module for generating parameterized model targets according to pre-stored model bitmap dot array information; a control interface module connected with the communication module for receiving the target parameters and controlling the simulated target generation module and the model target generation module.

4. The system of claim 3, wherein, The simulated target generation module generates a geometric figure according to current pixel point coordinates (X, Y) and target center point coordinates (X0, Y0), and the graphic calculation formula comprises: The determination formula of the circle is: (X-X0) 2 +(Y-Y0) 2 ≤R 2 wherein R is the radius of the circle, X is the X-axis coordinate of the current pixel point, Y is the Y-axis coordinate of the current pixel point, X0 is the X-axis coordinate of the target center point, and Y0 is the Y-axis coordinate of the target center point. The annular determination formula is: R0 2 ≤ (X - X0) 2 + (Y - Y0) 2 ≤ R1 2 wherein R0 is an inner ring radius, R1 is an outer ring radius, X is an X-axis coordinate of a current pixel point, Y is a Y-axis coordinate of the current pixel point, X0 is an X-axis coordinate of a target center point, and Y0 is a Y-axis coordinate of the target center point. a judgment formula for a square: X0-W / 2≤X≤X0+W / 2 and Y0-H / 2≤Y≤Y0+H / 2, wherein W is width, H is height, X is current pixel point X-axis coordinate, Y is current pixel point Y-axis coordinate, X0 is target center point X-axis coordinate, and Y0 is target center point Y-axis coordinate; a judgment formula for a cross: X=X0 and (Y0-L / 2≤Y≤Y0+L / 2) or Y=Y0 and (X0-L / 2≤X≤X0+L / 2), wherein L is the length of a cross line end, X is current pixel point X-axis coordinate, Y is current pixel point Y-axis coordinate, X0 is target center point X-axis coordinate, and Y0 is target center point Y-axis coordinate; a judgment formula for a ray: (Y-Y0)×cosθ=(X-X0)×sinθ, wherein θ is the included angle between the ray and the X-axis, X is current pixel point X-axis coordinate, Y is current pixel point Y-axis coordinate, X0 is target center point X-axis coordinate, and Y0 is target center point Y-axis coordinate.

5. The system of claim 3, wherein, The model target generation module comprises: a model storage using an FPGA on-chip ROM for storing bitmap dot array information of one or more model targets; The scaling unit is configured to scale the model according to a scaling factor in the target parameter by using a bilinear interpolation algorithm; the bilinear interpolation algorithm is configured to calculate a gray value I 11 12 21 22 according to gray values of four adjacent pixel points of a target point P(x0, y0), wherein x0 is an X-axis coordinate of the target point, y0 is a Y-axis coordinate of the target point, I 11 is a gray value of an upper-left adjacent pixel point, I 12 is a gray value of an upper-right adjacent pixel point, I 21 is a gray value of a lower-left adjacent pixel point, and I 22 is a gray value of a lower-right adjacent pixel point.​​​ A rotation unit is configured to perform a rotation transformation on the model according to a rotation angle in the target parameter by using a rotation matrix; the rotation matrix R is: A calculation formula of the post-rotation coordinate pp is: pp = R x (p-c) + c, wherein p is an original image pixel coordinate, c is a rotation center point coordinate, pp is a post-rotation pixel coordinate, and θ is a rotation angle; A motion control unit is configured to control the change of the target center coordinates (X0, Y0) according to the motion trajectory and the motion speed in the target parameters; the motion trajectory includes linear motion and parabolic motion; the calculation formula of the linear motion is X0=X x +V x ×T,Y0=Y y +V y ×T, wherein (X x ,Y y ) is the starting position of the target, V x is the speed in the X-axis direction, Y y is the speed in the Y-axis direction, T is the time in frames, X0 is the real-time coordinate of the target center in the X-axis, and Y0 is the real-time coordinate of the target center in the Y-axis; the calculation formula of the parabolic motion is X=X0+V x ×T,Y=Y0+(1 / 2)×g×((X-X0) / V x )2, wherein V x is the initial speed in the X-axis, g is the acceleration of gravity, X is the real-time coordinate of the target in the X-axis, Y is the real-time coordinate of the target in the Y-axis, X0 is the initial coordinate of the target in the X-axis, Y0 is the initial coordinate of the target in the Y-axis, and T is the time in frames.

6. The system of claim 1, wherein, The video processing module comprises: An SDI video decoding module is configured to receive an external SDI input signal, decode the signal into standard timing video data by using an SDI-RXIP core and a FPGA internal primitive deserializing; A frame buffer processing module is connected with the SDI video decoding module and the communication module, and is configured to buffer the video data by using a DDR3 memory; the frame buffer processing module adopts a three-buffer mechanism and a polling read-write arbitration strategy; A scene synthesis module is connected with the frame buffer processing module and the target generation module, and is configured to perform Alpha blending on the background video and the foreground dynamic target video stream; the Alpha blending algorithm is: R(C) = [(256-Alpha) x R(B) + Alpha x R(A)] >> 8 G(C) = [(256-Alpha) x G(B) + Alpha x G(A)] >> 8 B(C) = [(256-Alpha) x B(B) + Alpha x B(A)] >> 8 wherein Alpha is an 8-bit transparency value, A is a background image pixel value, B is a foreground target image pixel value, C is a mixed image pixel value, R is a red component, G is a green component, and B is a blue component; An SDI video encoding module is connected with the scene synthesis module, and is configured to package the mixed video data according to an SDI protocol, and convert the data into a serial digital signal by using a GTX transceiver to output.

7. The system of claim 6, wherein, The background video sources include a real video output by the SDI video decoding module, an upper computer input picture transmitted by the gigabit network MAC module, or a test pattern generated by the FPGA internally.

8. The system of claim 1, wherein, The hardware circuit of the system comprises: An FPGA minimum system circuit comprises an FPGA chip, a QSPIFLASH configuration chip and a crystal oscillator; A DDR3 storage circuit is connected with the FPGA chip, and is configured to provide a video frame buffer space; A network PHY circuit is connected with the FPGA chip, and is configured to implement a gigabit Ethernet physical layer interface; An SDI input equalization circuit adopts an LMH1219 chip, and is connected with the FPGA chip, and is configured to equalize and recover a clock of an input SDI signal; An SDI output driving circuit adopts an LMH1218 chip, and is connected with the FPGA chip, and is configured to drive an output SDI signal.

9. The system of claim 1, wherein, The upper control module is a PC end software written based on a C++ language, and provides a man-machine interface; the interface comprises a self-checking module, a basic information module, a data exporting module and a data erasing module.

10. The system of claim 3, wherein, The control interface module allows a user to perform operations through the upper control module, including selecting a target type, setting the target parameter and setting the scene parameter.

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