A wireless communication system and method based on EtherCAT network

Abstract

This application discloses a wireless communication system and method based on an EtherCAT network. The system includes a wireless gateway and wireless slave stations. The wireless gateway includes an EtherCAT slave module, a wireless communication module, a control module, and an auxiliary function module. The control module encapsulates and converts EtherCAT frames received by the EtherCAT slave module with wireless frames from the wireless communication module through hardware-level protocol conversion. The wireless communication module uses either an FHSS module or a WiFi module. The auxiliary function module includes a timestamp module that records time information to assist the control module in using a multi-level distributed clock synchronization optimization algorithm for master-slave clock synchronization. The wireless slave station includes an EtherCAT slave module compatible with the wireless gateway that receives EtherCAT master station control commands, a wireless communication module of the same model that uploads wireless frames encapsulated with EtherCAT sub-messages, and a local control unit that parses EtherCAT master station control commands to collect local data and encapsulates it into EtherCAT sub-messages. This application can adapt to the requirements of industrial automation for high-precision and high-reliability wireless communication.

Description

Technical Field

[0001] This application relates to the field of industrial communication technology, specifically to a wireless communication system and method based on an EtherCAT network. Background Technology

[0002] The industrial automation field has developed rapidly in recent years, leading to a growing demand for wireless communication. In mobile device control, such as AGVs and welding robots, flexible wiring is needed to achieve more efficient operations; distributed sensor networks require reduced wiring costs and improved system scalability; and remote monitoring and maintenance require convenient management methods to ensure stable equipment operation. The application of wireless communication technology in industrial automation has greatly improved production flexibility and efficiency, driving the industry towards intelligence and automation.

[0003] In the past, to meet the wireless communication needs of industrial automation, wireless communication technologies such as WiFi, Bluetooth, and ISA100.11a were commonly used. WiFi technology, with its wide coverage and high transmission rate, has been applied in scenarios where real-time requirements are not high. Bluetooth technology, with its low power consumption and low cost, is suitable for short-range wireless communication. The ISA100.11a protocol is optimized for industrial applications, improving communication reliability to a certain extent. Furthermore, the EtherCAT protocol itself possesses advantages such as microsecond-level real-time performance, high bandwidth utilization, low-latency distributed clock synchronization accuracy, and flexible topology; however, its wireless implementation typically involves complex protocol conversion and synchronization calibration methods.

[0004] However, existing wireless communication technologies have many limitations. Technologies such as WiFi, Bluetooth, and ISA100.11a suffer from high latency, poor determinism, weak anti-interference capabilities, low bandwidth utilization, and poor synchronization accuracy, with synchronization accuracy only reaching the millisecond level, and device expansion is limited. The EtherCAT protocol faces challenges in ensuring real-time performance during wireless implementation. The uncertainty of the wireless channel leads to latency fluctuations; maintaining synchronization accuracy is difficult, as multipath effects and signal fluctuations affect the clock; protocol conversion is complex, making its "fly-read / fly-write" mechanism difficult to implement; and reliability is low, with wireless interference easily causing data loss. These problems make existing technologies unsuitable for the high real-time, high-precision, and high-reliability wireless communication requirements of industrial automation. Summary of the Invention

[0005] To meet the requirements of industrial automation for high-precision and high-reliability wireless communication, this application provides a wireless communication system and method based on EtherCAT network.

[0006] In a first aspect, this application provides a wireless communication system based on an EtherCAT network, comprising: a wireless gateway connected to an EtherCAT master station and a wireless slave station; the wireless gateway comprises: an EtherCAT slave station module, a wireless communication module, a control module, and an auxiliary function module; The control module encapsulates and converts the EtherCAT frames received by the EtherCAT slave module with the wireless frames of the wireless communication module through hardware-level protocol conversion. The wireless communication module selects at least one of the following communication modules: an FHSS module that supports pseudo-random frequency hopping or a WiFi module. The FHSS module uses a pseudo-random frequency hopping sequence aligned with the EtherCAT frame transmission period. The pseudo-random frequency hopping sequence is dynamically generated by the control module according to the communication period of the EtherCAT master station, and frequency switching is triggered when the control module detects that the EtherCAT frame transmission is complete. The auxiliary function module includes a timestamp module; the timestamp module is used to record the time information of EtherCAT frames arriving at each module in the wireless gateway and each module in the wireless slave station, so that the control module can perform master-slave clock synchronization based on the recorded time information using a multi-level distributed clock synchronization optimization algorithm; the multi-level distributed clock synchronization optimization algorithm includes hardware-level transmission delay compensation and master-slave clock offset calibration; The wireless slave station includes: an EtherCAT slave module compatible with the wireless gateway, a wireless communication module of the same model compatible with the wireless gateway, and a local control unit; the EtherCAT slave module compatible with the wireless gateway is used to receive EtherCAT master station control commands; the local control unit is used to parse the EtherCAT master station control commands and drive actuators or sensors to collect local data and encapsulate it into EtherCAT sub-messages; the wireless communication module of the same model is used to upload the wireless frames encapsulated with EtherCAT sub-messages to the wireless gateway.

[0007] By adopting the above scheme, hardware-level protocol conversion avoids interruption delays caused by software parsing, thus improving protocol conversion efficiency; a multi-level distributed clock synchronization optimization algorithm is used to compensate for wireless transmission delay fluctuations, improving clock synchronization accuracy; a pseudo-random frequency hopping sequence is used to align with the EtherCAT frame transmission period, reducing frame loss rate caused by frequency hopping switching; a timestamp module is set up to provide data support for delay compensation of distributed clock synchronization; based on the collaboration of various modules of the wireless slave station, the reception and parsing of EtherCAT master station control commands, and the collection and uploading of local data are realized, ensuring the normal operation of the wireless communication system; the overall real-time performance, determinism, synchronization accuracy, and reliability of wireless communication are improved, meeting the high-quality requirements of industrial automation for wireless communication.

[0008] Preferably, the control module in the wireless gateway adopts a heterogeneous architecture, including a microprocessor and a programmable logic device; the microprocessor is used to monitor link quality; the programmable logic device is used to implement hardware-level protocol conversion, dynamically generate frequency hopping sequences and control the frequency switching of the wireless communication module, manage the data buffer and output nanosecond-level timestamp signals; The wireless gateway uses a dual-port EtherCAT slave module as its EtherCAT slave module, and the wireless communication module in the wireless gateway is a dual wireless communication module including a primary wireless communication module and a backup wireless communication module. The dual-port EtherCAT slave module triggers port switching via hardware interrupt when the control module detects a primary link failure. The dual wireless communication module switches to the backup wireless communication module when the control module detects that the link quality of the primary communication module is lower than a preset quality.

[0009] By adopting the above scheme, the control modules of the heterogeneous architecture are set up to process tasks in parallel, reducing protocol conversion latency and retaining the real-time characteristics of EtherCAT fly-read and fly-write. The microprocessor is used to monitor link quality, and programmable logic devices are used to implement hardware-level protocol conversion, frequency hopping sequence generation and frequency switching control, thereby improving the real-time performance and synchronization accuracy of the system. In addition, a dual-port EtherCAT slave module and a dual wireless communication module backup unit are designed to automatically switch when the main link fails or its quality degrades, thereby improving the reliability and stability of the system.

[0010] Preferably, the auxiliary function module further includes a wide voltage input power supply module; the wide voltage input power supply module is used to output multiple sets of isolated power supplies to power the wireless communication module and the EtherCAT slave module.

[0011] By adopting the above scheme, a wide voltage input power supply module is designed to output multiple isolated power supplies to power the wireless communication module and the EtherCAT slave module, adapting to power fluctuation scenarios in industrial sites and providing power assurance for stable system operation.

[0012] Preferably, the control module is further configured to add a multi-level distributed clock synchronization optimization algorithm including dynamic drift compensation for master-slave clock synchronization; the dynamic drift compensation includes: collecting master-slave clock offsets once every preset time to construct an offset sequence; using a quadratic fitting algorithm to fit the sequence to obtain a drift trend function; predicting the offset of the next cycle; and using a PI closed-loop control algorithm to adjust the clock output frequency of the programmable logic device in the wireless gateway.

[0013] By adopting the above scheme, the dynamic drift of the master and slave clocks is compensated, and the clock synchronization accuracy is further improved.

[0014] Preferably, the control module is further configured to generate synchronization frames for EtherCAT frames, and control the synchronization frames to be transmitted in parallel through different wireless communication modules during the interval between the end of each EtherCAT frame transmission and the preparation for frequency hopping switching; it is also configured to receive the timestamps of the recorded EtherCAT frames and synchronization frames; for each EtherCAT frame period, it calculates the multipath synchronization frame delay characteristic values ​​based on the timestamps of the synchronization frames, including: multipath one-way delay, single-path delay mean, single-path delay variance, and multipath delay difference; based on the multipath synchronization frame delay characteristic values, it performs path delay calibration on each EtherCAT frame; and based on the calibrated EtherCAT frame path delay, it corrects the master-slave clock offset.

[0015] By adopting the above scheme, synchronization frames of EtherCAT frames are generated and sent in parallel during the intervals, avoiding conflicts between synchronization frames and EtherCAT frames and frequency hopping switching; by obtaining the timestamps of EtherCAT frames and synchronization frames, the delay characteristics of multi-path synchronization frames are calculated, and path delay calibration is performed on each EtherCAT frame, thereby correcting the master-slave clock offset and improving the clock synchronization accuracy and communication stability of the system.

[0016] Preferably, the control module is further configured to dynamically adjust the EtherCAT frame period to match the network load during the process of dynamically generating the frequency hopping sequence according to the communication period of the EtherCAT master station, and set the frequency hopping interval to be equal to the adjusted EtherCAT frame period; generate a pseudo-random frequency hopping sequence based on the random improved algorithm of chaotic mapping, and combine it with the designed multi-channel cooperative frequency hopping to obtain the reference frequency hopping sequence generated by the main channel and the offset frequency hopping sequence generated by the backup channel to adjust the sequence offset of the reference frequency hopping sequence, and load the reference frequency hopping sequence and the offset frequency hopping sequence into the sequence storage module of the programmable device; The control module is further configured to utilize a programmable logic device to generate a sequence index of the current cycle of the main channel and the backup channel during the frequency switching process triggered when the EtherCAT frame transmission is detected to be complete. When the EtherCAT frame transmission is detected to be complete, the index is updated to point to the frequency point of the next cycle, triggering the frequency switching to complete the frequency hopping of the main channel and the backup channel. Based on the real-time monitored signal quality of the main channel, when the signal quality of the main channel meets the preset channel switching standard, the frequency point is switched to the backup channel at the same time. When the signal quality of the main channel meets the preset channel recovery standard, the frequency point is switched back to the main channel at the same time.

[0017] By adopting the above scheme, dynamically adjusting the EtherCAT frame period to match the network load and setting the frequency modulation interval to be equal to it, the frequency hopping sequence can better adapt to the network conditions. A pseudo-random frequency hopping sequence is generated based on a randomized improved algorithm of chaotic mapping. Combined with multi-channel collaborative frequency hopping to obtain the reference and offset frequency hopping sequences, the randomness and anti-interference ability of frequency hopping are improved. Frequency switching is triggered when EtherCAT frame transmission is completed to avoid timing conflicts between frequency hopping switching and frame transmission. At the same time, channel switching is performed according to the signal quality of the main channel to improve the communication stability and reliability of the system in complex environments.

[0018] Preferably, the control module is further configured to determine that when the length of the encapsulated and converted EtherCAT frame exceeds the maximum load of the wireless frame, divide the encapsulated and converted EtherCAT frame into multiple fragments with fragment identifiers and transmit them sequentially through the wireless communication module, so that the wireless slave station can reassemble and verify the integrity according to the sequence number, and trigger a priority retransmission request when a fragment is lost; it is also configured to prioritize the retransmission of lost fragments after receiving the priority retransmission request.

[0019] By adopting the above scheme, when the length of the encapsulated and converted EtherCAT frame exceeds the maximum load of the wireless frame, it is divided into fragments with fragmentation identifiers and transmitted sequentially. This avoids discarding and retransmitting the entire frame, reduces the amount of retransmitted data, improves bandwidth utilization, and ensures that the wireless slave station reassembles and verifies data integrity in sequence.

[0020] Prior to this, the control module is also used to encrypt the EtherCAT master station control commands using the AES128 encryption algorithm. The encryption key is dynamically distributed by the EtherCAT master station, and a 16-bit CRC checksum is added to the wireless frame. It is also used to employ a request-response mechanism to send the EtherCAT master station control commands, wait for the wireless slave station to respond, and retransmit when the response times out.

[0021] By adopting the above scheme, the control commands of the EtherCAT master station are encrypted and the keys are dynamically distributed to avoid the security risks of fixed keys. Adding CRC check codes and using a request-response mechanism can ensure the integrity of data and the delivery of commands, and reduce the data eavesdropping rate and error rate.

[0022] Secondly, this application provides a wireless communication method based on the above system, comprising: The EtherCAT slave module in the wireless gateway receives EtherCAT frames sent by the EtherCAT master station. The EtherCAT frames received by the EtherCAT slave module are encapsulated and converted through hardware-level protocol conversion. The control module sends the converted wireless frames to the corresponding wireless slave stations, and a multi-level distributed clock synchronization algorithm is used to compensate for the wireless transmission delay.

[0023] By adopting the above scheme, the EtherCAT protocol and wireless communication are integrated, reducing protocol conversion delay, lowering wireless transmission delay fluctuations, improving the real-time performance and determinism of wireless communication, and ensuring industrial-grade clock synchronization accuracy.

[0024] Priority also includes: The wireless slave station parses the EtherCAT master station control commands, collects local data based on the parsed EtherCAT master station control commands, encapsulates it into EtherCAT sub-messages, and sends the wireless frames encapsulated with EtherCAT sub-messages to the wireless gateway through the wireless communication module. Using a wireless gateway, the wireless frames of the wireless communication module are encapsulated and converted through hardware-level protocol conversion. EtherCAT sub-messages are extracted from the wireless frames and written into the memory of the EtherCAT slave module. The EtherCAT sub-messages are then inserted into the corresponding sub-message field positions of the EtherCAT frame in an orderly manner according to the memory storage order to generate an EtherCAT frame. The generated EtherCAT frame is then sent back to the EtherCAT master station.

[0025] By adopting the above scheme, bidirectional data transmission and protocol conversion between the wireless slave station and the wireless gateway are realized, ensuring that the EtherCAT master station control commands can be accurately transmitted to the wireless slave station, and at the same time, the local data of the wireless slave station can be promptly transmitted back to the EtherCAT master station, thereby improving the real-time nature of communication and the reliability of data transmission.

[0026] In summary, this application has the following beneficial effects: 1. A hardware-level protocol conversion is implemented in the control module to avoid software store-and-forward delays and improve the real-time performance and determinism of wireless communication; a multi-level distributed clock synchronization optimization algorithm is used for master-slave clock synchronization to ensure industrial-grade clock synchronization accuracy; a pseudo-random frequency hopping sequence is aligned with the EtherCAT frame transmission period to reduce frame loss rate caused by frequency hopping switching and meet the requirements of high-reliability communication; and the collaboration of various modules in the wireless slave station enables bidirectional data transmission and protocol conversion between the wireless slave station and the wireless gateway, ensuring that local data can be accurately encapsulated and uploaded to the master station, thereby improving the information exchange efficiency and accuracy of the entire communication system. 2. The design incorporates a multi-level distributed clock synchronization optimization algorithm, including hardware-level transmission delay compensation and master-slave clock offset calibration, and adds dynamic drift compensation and path delay calibration to improve the synchronization accuracy of master and slave clocks and ensure the real-time performance and determinism of system communication. 3. Dynamically adjust the EtherCAT frame period to match the network load. Utilize the randomized improved algorithm of chaotic mapping and multi-channel collaborative frequency hopping to generate and load the reference and offset frequency hopping sequences. Trigger the primary and backup channel frequency hopping when the EtherCAT frame transmission is completed, and automatically switch channels when switching frequencies based on the primary channel signal quality. This improves the adaptability and flexibility of the frequency hopping sequence and enhances the system's anti-interference capability and communication stability. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the wireless communication system based on the EtherCAT network described in a specific embodiment; Figure 2 This is a flowchart of the wireless communication method based on the EtherCAT network described in a specific embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0029] Addressing the technical pain points of traditional wired EtherCAT networks in industrial automation, such as insufficient flexibility and poor real-time performance / low synchronization accuracy of traditional wireless communication technologies, Figure 1 As shown in the figure, this application discloses a wireless communication system based on an EtherCAT network, including modules such as a wireless gateway 1 and a wireless slave station 2. The wireless gateway 1 acts as a bridge between the EtherCAT master station and the wireless slave station, and includes an EtherCAT slave station module 11, a wireless communication module 12, a control module 13, and an auxiliary function module 14. The wireless slave station 2 includes an EtherCAT slave station module 21 compatible with the wireless gateway, a wireless communication module 22 of the same type, and a local control unit 23.

[0030] Specifically, from a hardware implementation perspective, the specific design of each module in the system includes: Firstly, the specific design of wireless gateway 1 is as follows.

[0031] The EtherCAT slave module 11 uses the Microchip LAN9252 chip. This chip, designed specifically for industrial real-time communication, is an EtherCAT slave controller that integrates dual Ethernet PHYs, supporting network transmission rates of 10 / 100Mbps. It has 4KiB of dual-port RAM (DPRAM) for data storage and exchange; three Fieldbus Memory Management Units (FMMUs) for managing data storage and access; and four SyncManagers, natively supporting distributed clock (DC) functionality. The chip communicates with the control module via an HBI (Host Bus Interface) or SPI interface. The HBI interface can reach a rate of 50MHz, meeting microsecond-level data transmission requirements. The SyncManagers output a synchronization interrupt signal via the SYNC pin to ensure timing alignment with the control module. Because the LAN9252 has its EtherCAT data link layer logic embedded in hardware, it can directly parse the EtherCAT frame header and extract sub-message data. It then uses FMMU mapping to determine the sub-message's ownership; sub-messages belonging to wired slave stations are directly forwarded through LAN9252 PORT1; sub-messages belonging to wireless slave stations are written to a specific address range in the DPRAM. Using the LAN9252 to parse EtherCAT frames sent by the EtherCAT master station avoids the interruption delays of software parsing, laying the foundation for hardware-level protocol conversion.

[0032] To adapt to the needs of different industrial scenarios, the wireless communication module 12 supports the selection of different wireless communication modules. In this embodiment, the wireless communication module 12 is selected from at least one of the following communication modules: the first is an FHSS module that supports pseudo-random frequency hopping, and the second is a WiFi module. The core parameters of the FHSS frequency hopping module are set as follows: operating frequency band is 2.4GHz ISM band, supporting more than 75 frequency hopping points, frequency hopping interval is configurable, with a maximum of 400ms, conforming to FCC Part 15.247 standard; it adopts GFSK modulation, with a data rate of up to 250kbps and a transmission delay ≤10μs. It communicates with the control module through an SPI interface with a clock rate of 10MHz, supporting hardware chip select (CS) and interrupt (IRQ) signals to achieve timing control of frame transmission. This FHSS frequency hopping module supports the customization of pseudo-random frequency hopping sequences, which can be dynamically generated by the control module according to the communication cycle of the EtherCAT master station, ensuring alignment with the EtherCAT frame transmission cycle. It triggers frequency switching when the control module detects the completion of EtherCAT frame transmission, solving the frame interruption problem caused by frequency hopping switching. The WiFi module is an 802.11b / g / n WiFi module, which supports 802.11b (11Mbps) / g (54Mbps) modes, uses MIMO technology, and has a transmission latency of ≤20μs. It also supports WPA2 Enterprise encryption to meet industrial data security requirements. It communicates with the control module via an RS485 interface, making it suitable for scenarios with high bandwidth requirements but low electromagnetic interference.

[0033] To adapt to the needs of different industrial scenarios and retain the real-time characteristics of EtherCAT's "fly-read and fly-write" capabilities, the control module 13 adopts a heterogeneous architecture, including a microprocessor and programmable logic devices, such as an ARM CortexA8 + FPGA heterogeneous architecture (e.g., TI AM3359 + Xilinx Spartan6), or a low-cost architecture of STM32H7 + FPGA (suitable for small to medium-scale scenarios). The microprocessor, taking the ARM CortexA8 (AM3359) as an example, is mainly responsible for system management (e.g., wireless network parameter configuration, link quality monitoring) and software-level data processing (e.g., AES encryption, CRC checksum), with a main frequency of 800MHz, and can run a Linux operating system (equipped with an IgH EtherCAT master protocol stack for debugging), etc.

[0034] The programmable logic device, taking an FPGA (Spartan6) as an example, utilizes an FPG in conjunction with a LAN9252 to achieve hardware-level protocol conversion (e.g., hardware-level encapsulation conversion between EtherCAT frames and wireless frames (GMII interface → wireless protocol frame header); specifically, based on the LAN9252 parsing the EtherCAT frame header, determining the sub-message's ownership, writing a specific address segment to the DPRAM, and triggering a SYNC interrupt on the LAN9252, the FPG reads the wireless sub-message from the DPRAM and encapsulates it into an FHSS / WiFi frame), dynamically generates frequency hopping sequences and controls the frequency switching of the wireless communication module, manages the data buffer (e.g., a 256KB DDR3 data buffer to store EtherCAT frames during frequency hopping), and outputs nanosecond-level timestamp signals (synchronized with the LAN9252's DC clock). By processing the core tasks in parallel using FPGA hardware, the protocol conversion delay can be reduced to less than 5μs.

[0035] To provide data support for delay compensation in distributed clock synchronization, the auxiliary function module 14 includes a timestamp module 141 and a wide voltage input power supply module 142. The timestamp module 141 is used to record the time information of EtherCAT frames arriving at the EtherCAT slave module and being sent to the wireless communication module. It is also used to receive and record the time information of the wireless communication module sending wireless frames to the wireless slave and the time of receiving the wireless slave's return response frame, so that the subsequent control module can use a multi-level distributed clock synchronization optimization algorithm to perform master-slave clock synchronization, including: synchronization between the EtherCAT master and the wireless gateway (the local clock of the EtherCAT master and the clock of the EtherCAT slave module of the wireless gateway), synchronization between the wireless gateway and the wireless slave (the clock of the wireless communication module of the wireless gateway and the clock of the wireless communication module of the wireless slave), and synchronization between the wireless slave and the local slave device (the local clock of the wireless slave and the clock of the local slave device connected to it).

[0036] The wide voltage input power module 142 adopts a wide voltage input (936V DC) switching power supply to output multiple isolated power supplies to power the wireless communication module and the EtherCAT slave module, such as outputting 3.3V (to power the LAN9252 and FPGA) and 5V (to power the wireless module), supporting overvoltage and overcurrent protection, and adapting to power fluctuation scenarios in industrial sites.

[0037] Secondly, the specific design of wireless slave station 2 is as follows.

[0038] Wireless slave 2 is an EtherCAT slave device that supports wireless communication (such as AGV controllers and distributed temperature sensors). Its hardware design is compatible with the wireless gateway to ensure communication consistency.

[0039] The EtherCAT slave module 21, which is compatible with the wireless gateway, uses the LAN9252 chip, and can receive master station control commands (such as AGV speed commands, which can be encapsulated in the corresponding fields of the frame) through SyncManager, and upload device status data (such as motor current and sensor sampling values).

[0040] The wireless communication module 22 of the same model uses the same FHSS / WiFi module as the wireless gateway to ensure compatibility of frequency hopping sequence / communication protocol; for example, the FHSS module on the AGV and the FHSS module of the gateway share the same frequency hopping sequence seed to avoid communication interruption caused by frequency mismatch.

[0041] The local control unit 23, using an STM32F407 MCU, is responsible for parsing the control commands output by the LAN9252 and driving actuators (such as the servo motors of the AGV) and sensors. It encapsulates local data (such as lidar obstacle information) into EtherCAT sub-messages, then encapsulates them into wireless frames, and uploads the wireless frames encapsulated with EtherCAT sub-messages to the wireless gateway through the same type of wireless communication module 22.

[0042] Furthermore, to address the issue of industrial wireless links being susceptible to interference and interruption, this embodiment primarily uses hardware redundancy design of the wireless gateway as an example. The EtherCAT slave module in the wireless gateway is a dual-port EtherCAT slave module, and the wireless communication module is a dual wireless communication module comprising a primary wireless communication module and a backup wireless communication module. The LAN9252 chip in the wireless gateway supports dual Ethernet ports (PORT0, PORT1). PORT0 connects to the EtherCAT master station, and PORT1 connects to the backup gateway (or backup master station). When the control module detects a link failure in PORT0, the LAN9252 triggers port switching via a hardware interrupt, with a switching time ≤1ms. The dual wireless communication module includes a primary wireless communication module and a backup wireless communication module. In some high-reliability scenarios (such as steelmaking workshops), the wireless gateway integrates two identical FHSS modules, implementing "hot backup" via an FPGA. When the control module detects link quality issues (signal strength <80dBm) in the primary wireless communication module, the FPGA automatically switches to the backup wireless communication module, avoiding the delay of software switching.

[0043] Specifically, algorithm optimization addresses the issues of "low clock synchronization accuracy" and "poor frame transmission reliability" in wireless environments, and works in conjunction with the hardware architecture to achieve "low latency, high synchronization, and strong anti-interference" wireless EtherCAT communication. From a software implementation perspective, the software architecture for the wireless gateway adopts a layered design, consisting of a driver layer, a protocol layer, and a task layer.

[0044] First, regarding the driver layer: The LAN9252 driver can be developed based on the TI Processor SDK Linux, implementing LAN9252 register configuration (such as FMMU mapping, SyncManager parameter settings), data read / write (reading EtherCAT sub-messages from DPRAM via the HBI interface), and interrupt handling (SYNC pin interrupt triggering synchronization calibration). The wireless communication module driver (for FHSS and WiFi selection) is configured. The FHSS module driver implements SPI interface data transmission and reception (such as sending frequency hopping sequence configuration command 0x01 and reading link quality register 0x05); the WiFi module driver implements RS485 interface frame parsing (extracting EtherCAT data segments from WiFi frames). The FPGA driver is configured via the SPI interface, configuring internal FPGA registers such as the frequency hopping sequence seed (0x1234), buffer address (0x00000x0FFF), and timestamp enable bit (bit 7), enabling software control of hardware functions.

[0045] Secondly, regarding the protocol layer: EtherCAT protocol parsing: Hardware-level parsing (performed by LAN9252): Extracting sub-messages from the EtherCAT frame (including command field, index field, and data length), filtering out sub-messages belonging to the wireless slave station (determined through FMMU address mapping); Software-level supplementary parsing (performed by ARM): Adding CRC checksums (16 bits) to key sub-messages (such as master synchronization frame 0x00) to ensure data integrity. Wireless protocol encapsulation: Encapsulating the filtered EtherCAT sub-messages into wireless frames, with the following frame structure (taking the FHSS frame as an example): Based on the standard Ethernet Type II frame (destination MAC + source MAC + type field + data + CRC), its core extension lies in the structured design of the "data segment". The EtherCAT frame type is 0x88A4, and the data segment contains multiple sub-messages. Each sub-message contains fields such as command, index, address area, and length, supporting dynamic data mapping. Compared to the existing technology that "encapsulates the complete EtherCAT frame into a wireless frame" (which results in excessively long wireless frames and easy packet loss), this embodiment only encapsulates "sub-messages specific to the wireless slave station", increasing bandwidth utilization to over 90%.

[0046] Finally, regarding the task layer, the FreeRTOS real-time operating system is used to create the following core tasks (priority from high to low): Synchronization calibration task (priority 10): period 100μs, calls the distributed clock synchronization algorithm to correct the local clock of the wireless slave station. Data forwarding task (priority 8): period 200μs, implements hardware-level conversion between EtherCAT frames and wireless frames (triggered by FPGA interrupt). Link monitoring task (priority 6): period 1ms, reads the link quality register of the wireless module (such as signal strength, bit error rate), and triggers redundancy switching. Parameter configuration task (priority 4): period 100ms, responds to parameter configuration commands from the master station (such as frequency hopping sequence adjustment, synchronization period modification).

[0047] Based on the software architecture, the algorithm functions include: First, the hardware-level protocol conversion process. This includes: implementing downlink data processing (master station - wireless slave station) through the control module. Specifically, the EtherCAT master station sends EtherCAT frames (containing sub-messages from the wired and wireless slave stations) to the LAN9252 of the wireless gateway. PORT0; The LAN9252 hardware parses the frame header and determines the sub-packet affiliation through FMMU mapping: sub-packets belonging to wired slaves are forwarded directly through PORT1; sub-packets belonging to wireless slaves are written to the 0x00000x07FF address segment of the DPRAM; the LAN9252 triggers a SYNC interrupt, the FPGA reads the wireless sub-packet from the DPRAM, encapsulates it into an FHSS / WiFi frame (adding a frame header, frequency hopping flag, and CRC); the FPGA controls the wireless module to send the frame to the corresponding wireless slave, with a transmission delay ≤15μs; uplink data processing (wireless slave to master) is implemented. The specific algorithm execution steps are as follows: the wireless slave encapsulates local data (such as sensor sampling values) into an EtherCAT sub-packet and sends it to the gateway through the wireless module; after the wireless module receives the frame, it triggers an FPGA interrupt, the FPGA extracts the sub-packet from the frame, and writes it into the LAN9252. The 0x08000x0FFF address range of DPRAM; LAN9252 inserts the uplink sub-messages in DPRAM into the corresponding positions of the EtherCAT frame to generate a complete EtherCAT frame; LAN9252 transmits the complete frame back to the EtherCAT master station through PORT0, with a total delay of ≤20μs.

[0048] Second, a distributed clock synchronization algorithm is implemented. The multi-level distributed clock synchronization optimization algorithm, executed by the control module, includes: hardware-level transmission delay compensation and master-slave clock offset calibration. Specifically, the hardware-level transmission delay compensation step includes: the EtherCAT master station sends a BWR (Write with Timestamp) command to the wireless gateway, and the LAN9252 records the command arrival time T1 (obtained via the timestamp module); the FPGA controls the wireless communication module to send the command to the wireless slave station, recording the transmission time T2; after receiving the command, the wireless slave station records the arrival time T3 via its own LAN9252 and immediately sends back a response frame; the FPGA records the response frame reception time T4, calculates the wireless transmission delay ΔT = [(T4-T1)-(T3-T2)] / 2, and writes it to the delay compensation register of the LAN9252 via the FMMU; this reduces the wireless transmission delay fluctuation from ±50μs to ±1μs after compensation. The master-slave clock offset calibration step includes: the EtherCAT master station periodically sending FRMW (ReadModifyWrite) instructions to read the local clock T_slave of the wireless slave station; the ARM calculates the offset ΔT_offset between the master station clock T_master and T_slave = T_master-T_slave; the ARM writes ΔT_offset into the system time register (address 0x0010) of the wireless slave station LAN9252 through ARMW (such as Atomic Write) instructions to correct the slave station's local clock.

[0049] Third, FHSS and EtherCAT frame synchronization is implemented. To resolve the timing conflict between FHSS frequency hopping and EtherCAT frame transmission, the control module performs the following steps to align the frequency hopping sequence with the frame period: The ARM reads the communication period T of the EtherCAT master station (e.g., 200μs) and calculates the frequency hopping interval T_hop=T (ensuring that the frequency point is switched only once within a frame period); The ARM generates a pseudo-random frequency hopping sequence S = {f1, f2, ..., f75} (based on seed 0x1234) and writes the sequence into the FPGA's frequency hopping control register; The FPGA monitors the transmission status of the EtherCAT frame (via the frame transmission completion interrupt of LAN9252) and triggers frequency hopping after the frame transmission ends to avoid frequency point changes during frame transmission; This achieves frequency point stability during frame transmission, reducing the frame loss rate caused by frequency hopping from 10% to below 0.1%.

[0050] By adopting the collaborative system design of hardware architecture reconstruction and software algorithm optimization disclosed in the embodiments, the deep integration of EtherCAT protocol and wireless communication is realized, solving the problems of latency fluctuation, synchronization accuracy loss and weak anti-interference capability in existing wireless transmission, while ensuring the compatibility and scalability of hardware architecture.

[0051] In a specific embodiment, to further optimize the accuracy of master-slave clock synchronization, by compensating for dynamic clock drift, the system further includes: The control module is further configured to incorporate a multi-level distributed clock synchronization optimization algorithm with dynamic drift compensation for master-slave clock synchronization, in order to avoid time deviations caused by clock drift during wireless communication.

[0052] The dynamic drift compensation step performed by the control module includes: the ARM sampled the master-slave clock offset ΔT_offset every 10ms, constructing an offset sequence {ΔT1, ΔT2, ..., ΔTn}; and a quadratic fitting algorithm was used to fit the sequence to obtain the drift trend function. (a, b, c are fitting coefficients), predict the offset ΔT_pred for the next cycle; use a PI closed-loop control algorithm to adjust the FPGA clock output frequency: PI output The input clock frequency of LAN9252 is dynamically adjusted through the PLL module of the FPGA, achieving a stable inter-station clock deviation within 70ns, which is superior to the millisecond-level synchronization accuracy of traditional wireless technologies.

[0053] Furthermore, considering potential path delays, to eliminate the uncertainty of path delays in wireless transmission, the delay characteristics of the service path are calibrated using the timestamp difference of multi-path synchronization frames. Simultaneously, it is compatible with EtherCAT's FMMU sub-message mapping mechanism to achieve microsecond-level synchronization between the master and slave stations, meeting the real-time communication requirements of EtherCAT. The system also includes: The control module is also used to generate synchronization frames for EtherCAT frames and control the parallel transmission of these synchronization frames through different wireless communication modules during the interval between the end of each EtherCAT frame transmission and the start of the frequency hopping preparation phase. Specifically, based on the EtherCAT frames received by the wireless gateway, the generated synchronization frames are extended EtherCAT application layer frames (non-process data frames), including: a master station transmission timestamp (Master_Tx, based on the master station's local clock); a cycle number (Cycle_Num, used to align with the service frame (i.e., the EtherCAT frame initiated by the master station) cycle); and a path identifier (Path_ID, such as 0x01=FHSS, 0x02=WIFI, marked separately for multi-path transmission). To avoid the transmission of synchronization frames affecting the transmission of EtherCAT frames, the synchronization frames are transmitted in parallel through all wireless modules during the service frame transmission interval of each EtherCAT cycle (i.e., after the EtherCAT frame transmission phase ends and before the frequency hopping preparation phase begins), ensuring that timestamps are collected simultaneously across multiple paths.

[0054] The control module is further configured to receive the timestamps of recorded EtherCAT frames and synchronization frames; for each EtherCAT frame period, calculate the multipath synchronization frame delay characteristic value based on the timestamp of the synchronization frame; perform path delay calibration on each EtherCAT frame based on the multipath synchronization frame delay characteristic value; and correct the master-slave clock offset based on the calibrated EtherCAT frame path delay.

[0055] The received EtherCAT frames and synchronization frames' related timestamps include: EtherCAT frames (in a single path, the timestamp Tx_Service_X sent by the wireless gateway and the timestamp Rx_Service_X received by the wireless slave), synchronization frames (path X (FHSS), the timestamp Tx_Sync_X sent by the wireless gateway and the timestamp Rx_Sync_X received by the wireless slave), and synchronization frames (path Y (WIFI), the timestamp Tx_Sync_Y sent by the wireless gateway and the timestamp Rx_Sync_Y received by the wireless slave); within the same cycle (Cycle_Num = N), the timestamps of the EtherCAT frames and synchronization frames must satisfy: Tx_Service_X Tx_Sync_X (which sets the transmission time of EtherCAT frames and synchronous frames on the same path to be close, with an error ≤10μs) ensures that both are affected by the same channel conditions.

[0056] Among them, the path delay characteristics calculated using the multipath timestamps of the synchronization frames include: multipath one-way delay, single-path delay mean, single-path delay variance, and multipath delay difference. The specific formulas are as follows: For each period N, calculate the one-way delay of path X and path Y based on the timestamp of the synchronization frame: D_Sync_X(N) = Rx_Sync_X(N)-Tx_Sync_X(N), D_Sync_Y(N)=Rx_Sync_Y(N)-Tx_Sync_Y(N); Calculate the statistical characteristics through a sliding window (e.g., window size K=10): mean delay of path X: μ_X(N) = avg(D_Sync_X(N-K+1..N)), delay fluctuation (variance) of path X: σ_X²(N) = var(D_Sync_X(N-K+1..N)), delay difference between path X and Y: ΔD(N)=μ_X(N)-μ_Y(N) (reflecting the inherent offset of the path).

[0057] The original delay of the EtherCAT frame on path X is: D_Service_X(N) = Rx_Service_X(N) - Tx_Service_X(N). However, due to wireless fluctuations, it needs to be corrected based on the characteristics of the synchronization frame: if |D_Service_X(N) - μ_X(N)| > 3σ_X(N), it is determined to be an abnormal delay and replaced with μ_X(N) (based on the smoothing result of the synchronization frame); path offset correction: if path Y is a stable reference (σ_Y²(N) < σ_th (preset threshold), then ΔD(N) is used to calibrate the long-term offset of path X: D_Service_Calib(N) = D_Service_X(N) - ΔD(N). Based on the calibrated service path delay D_Service_Calib(N), the clock deviation between the slave station and the master station is corrected, i.e., the clock deviation: ΔT_offset = Master_Time(N) + D_Service_Calib(N)-Slave_Time(N) is then used to perform dynamic drift compensation using the calculated clock offset.

[0058] In a specific embodiment, to make frequency hopping sequence generation and frequency switching methods more flexible and intelligent, The system further includes: for the control module, in the process of dynamically generating the frequency hopping sequence according to the communication cycle of the EtherCAT master station, dynamically adjusting the EtherCAT frame period to match the network load in order to improve bandwidth utilization, including: if the current load exceeds a first preset load (85%), then set the adjusted frame period = max(minimum period, current frame period * 0.7); if the current load is less than a second preset load (40%), then set the adjusted frame period = max(maximum period, current frame period * 1.5); otherwise, keep the frame period unchanged; and set the frequency modulation interval equal to the adjusted EtherCAT frame period.

[0059] The control module is further configured to generate a pseudo-random frequency hopping sequence based on a random improvement algorithm of chaotic mapping to increase the randomness and anti-interference capability of frequency hopping, and in conjunction with the designed multi-channel cooperative frequency hopping (different wireless transmission channels corresponding to different wireless communication modules), obtain the reference frequency hopping sequence generated by the main channel and the offset frequency hopping sequence generated by the backup channel that adjusts the sequence offset of the reference frequency hopping sequence, and load the reference frequency hopping sequence and the offset frequency hopping sequence into the sequence storage module of the programmable device.

[0060] Among them, the improved random algorithm based on chaotic mapping generates pseudo-random frequency hopping sequences, and the iterative formula includes:

[0061] In the formula, , For small perturbation terms, The chaotic sequence value for the nth iteration. The random numbers are uniformly distributed; based on the iteratively generated chaotic sequence, they are quantized and mapped to the set of available frequency points, as shown in the formula: ;in, For the number of frequency points, Frequency interval, That is, the frequency hopping point of the nth cycle; the embedded processor of the FPGA pre-generates a frequency hopping sequence of M cycles (M is the sequence period) and stores it in the on-chip RAM of the FPGA (main channel sequence RAM_A, spare channel sequence RAM_B). Among them, combined with the multi-channel coordinated frequency hopping design, the reference frequency hopping sequence generated by the main channel (as shown in the formula above) and the offset frequency hopping sequence are expressed as follows: , This is the frequency hopping point of the backup channel in the nth cycle. This is the offset, such as 32.

[0062] The control module is further configured to utilize a programmable logic device to generate sequence indices for the current cycle of the primary and backup channels during the frequency switching process triggered when the EtherCAT frame transmission is detected to be complete. Upon detection of the EtherCAT frame transmission completion, the indices are updated to point to the next cycle frequency, triggering the frequency switching to complete the frequency hopping of the primary and backup channels. Specifically, based on the periodic synchronization pulses provided by the EtherCAT distributed clock, the primary channel index is counted using the logic C_main n = (C_main + 1) % M (M=1024), with an initial value of 0, incrementing by 1 each cycle, pointing to the address of the current frequency point of the primary sequence. Similarly, the backup channel index count is calculated using the logic C_standby=(C_main+k) %M. The main channel and the backup channel read the current frequency from RAM_A and RAM_B respectively, and control the wireless communication module through the SPI interface to maintain the current frequency to complete the EtherCAT frame transmission. After the EtherCAT frame transmission is completed, the index is updated to point to the next cycle frequency, and the frequency switching is triggered to complete the frequency hopping of the main channel and the backup channel. That is, the main channel and the backup channel read the next cycle frequency from RAM_A and RAM_B respectively.

[0063] The design automatically switches to the backup channel when the main channel malfunctions, without affecting data transmission in the current cycle. Furthermore, the control module is used to monitor the link quality of the main channel in real time (in this embodiment, channel signal quality is used as the standard). The main channel signal quality meets preset channel switching criteria (e.g., the main channel receives a signal strength less than a preset received signal strength threshold or a bit error rate greater than a preset bit error rate threshold for three consecutive cycles, i.e., RSSI ≥ 80 dBm, BER ≤ 10⁻⁻⁴). 5 If the main channel link quality is poor, the frequency point will be switched to the backup channel (switched to the backup channel with the same index count according to the sequence index); when the main channel signal quality meets the preset channel recovery standard (such as the main channel meeting the received signal strength not less than the preset received signal strength threshold or the bit error rate not greater than the preset bit error rate threshold for 5 consecutive cycles), the frequency point will be switched back to the main channel automatically.

[0064] In a specific embodiment, to further reduce the amount of retransmitted data during wireless transmission, improve bandwidth utilization, and ensure data security and integrity, the system further includes: The control module is further configured to: determine if the length of the encapsulated EtherCAT frame exceeds the maximum load of the wireless frame; divide the encapsulated EtherCAT frame into multiple fragments with fragment identifiers and transmit them sequentially via the wireless communication module; allow the wireless slave to reassemble the fragments according to their sequence numbers and verify their integrity; trigger a priority retransmission request if a fragment is lost; and prioritize retransmission of lost fragments upon receiving a priority retransmission request. Specifically, the ARM processor determines the EtherCAT frame length L. If L > the maximum load of the wireless frame (e.g., 256 bytes), it divides the frame into n fragments (L1, L2, ..., Ln), adding a fragment identifier (1 byte) and a sequence number (1 byte) to each fragment. The FPGA transmits the fragments in sequence, and the wireless slave reassembles them according to their sequence numbers. If the wireless slave does not receive a fragment (timeout of 10μs), it sends a retransmission request (frame header 0xBB). Upon receiving the retransmission request, the wireless gateway prioritizes retransmitting lost fragments to ensure data integrity.

[0065] The control module is further configured to encrypt the EtherCAT master station control commands (control command information contained in the EtherCAT frame) sent by the master station using the AES128 encryption algorithm. The encryption key is dynamically distributed by the EtherCAT master station, and a 16-bit CRC checksum is added to the wireless frame. It also employs a request-response mechanism, waiting for a response from the wireless slave station after sending the control command and retransmitting if the response times out. Specifically, the ARM encrypts the EtherCAT master station control commands using the AES128 encryption algorithm, and the key is dynamically distributed by the EtherCAT master station to avoid the security risks of fixed keys. The FPGA adds a 16-bit CRC checksum to the wireless frame, and the receiving FPGA verifies the CRC; if the verification fails, a retransmission is triggered. For critical data such as (AGV) control commands, a request-response mechanism is used, where the wireless gateway sends the command and waits for a response from the slave station (retransmitting if the timeout is 5μs), ensuring command delivery. This achieves a data eavesdropping rate of 0 and a data error rate of <10⁻⁻⁻⁶. 6 The effect.

[0066] like Figure 2 As shown in the figure, this application discloses a wireless communication method based on an EtherCAT network. The method utilizes a wireless communication system based on an EtherCAT network to achieve wireless data communication transmission. The specific steps revolve around the wireless communication between the EtherCAT master station and the wireless slave station, including: The steps for an EtherCAT master station to send EtherCAT frames and transmit them to a wireless slave station are as follows: S11. Receive EtherCAT frames sent by the EtherCAT master station through the EtherCAT slave module in the wireless gateway.

[0067] S12. The EtherCAT frames received by the EtherCAT slave module are encapsulated and converted through hardware-level protocol conversion. This step is completed by the FPGA in the control module. It uses its own hardware parallel processing capabilities to convert the EtherCAT frames into wireless frames suitable for wireless communication, avoiding software store-and-forward latency.

[0068] S13. The control module sends the converted wireless frames to the corresponding wireless slave stations and compensates for wireless transmission delay using a multi-level distributed clock synchronization algorithm. The control module accurately sends the wireless frames to the corresponding wireless slave stations based on their address information.

[0069] The steps for a wireless slave station to collect data and upload it to the EtherCAT master station according to the data collection command are as follows: S21. Use the wireless slave station to parse the EtherCAT master station control commands, collect local data based on the parsed EtherCAT master station control commands and encapsulate them into EtherCAT sub-messages; send the wireless frames encapsulated with EtherCAT sub-messages to the wireless gateway through the wireless communication module.

[0070] Specifically, the EtherCAT slave module in the wireless slave station parses the EtherCAT master station control commands, such as sensor data acquisition commands; based on the parsed sensor data acquisition commands, the actuator or sensor is driven to collect local data and encapsulate it into EtherCAT sub-messages, and then the EtherCAT sub-messages are encapsulated into wireless frames to obtain the wireless frames encapsulated with EtherCAT sub-messages.

[0071] S22. Using a wireless gateway, the wireless frames of the wireless communication module are encapsulated and converted through hardware-level protocol conversion. The EtherCAT sub-messages in the wireless frames are extracted and written into the memory of the EtherCAT slave module. The EtherCAT sub-messages are inserted into the corresponding sub-message field positions of the EtherCAT frame in an orderly manner according to the memory storage order to generate an EtherCAT frame. The generated EtherCAT frame is then sent back to the EtherCAT master station.

[0072] This application also discloses a computer-readable storage medium.

[0073] Specifically, the computer-readable storage medium stores a computer program that can be loaded by a processor and executed, such as the wireless communication method based on the EtherCAT network described above. The computer-readable storage medium includes, for example, various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0074] This application also discloses a computer device.

[0075] Specifically, the computer device includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and executed using the aforementioned wireless communication method based on the EtherCAT network.

[0076] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.

Claims

1. A wireless communication system based on an EtherCAT network, characterized in that include: Wireless gateways and wireless slaves that establish connections with the EtherCAT master station; The wireless gateway includes: an EtherCAT slave module, a wireless communication module, a control module, and an auxiliary function module; The control module encapsulates and converts the EtherCAT frames received by the EtherCAT slave module with the wireless frames of the wireless communication module through hardware-level protocol conversion. The wireless communication module selects at least one communication module, either an FHSS module or a WiFi module that supports pseudo-random frequency hopping. The FHSS module uses a pseudo-random frequency hopping sequence aligned with the EtherCAT frame transmission period. The pseudo-random frequency hopping sequence is dynamically generated by the control module according to the communication period of the EtherCAT master station, and frequency switching is triggered when the control module detects that the EtherCAT frame transmission is complete. The auxiliary function module includes a timestamp module; the timestamp module is used to record the time information of EtherCAT frames arriving at each module in the wireless gateway and each module in the wireless slave station, so that the control module can perform master-slave clock synchronization based on the recorded time information using a multi-level distributed clock synchronization optimization algorithm; the multi-level distributed clock synchronization optimization algorithm includes hardware-level transmission delay compensation and master-slave clock offset calibration; The wireless slave station includes: an EtherCAT slave module compatible with the wireless gateway, a wireless communication module of the same model compatible with the wireless gateway, and a local control unit; the EtherCAT slave module compatible with the wireless gateway is used to receive EtherCAT master station control commands; the local control unit is used to parse the EtherCAT master station control commands and drive actuators or sensors to collect local data and encapsulate it into EtherCAT sub-messages; the wireless communication module of the same model is used to upload the wireless frames encapsulated with EtherCAT sub-messages to the wireless gateway; The control module in the wireless gateway adopts a heterogeneous architecture, including a microprocessor and a programmable logic device; the microprocessor is used to monitor link quality; the programmable logic device is used to implement hardware-level protocol conversion, dynamically generate frequency hopping sequences and control the frequency switching of the wireless communication module, manage the data buffer and output nanosecond-level timestamp signals. The wireless gateway uses a dual-port EtherCAT slave module as its EtherCAT slave module, and the wireless communication module in the wireless gateway uses a dual wireless communication module including a primary wireless communication module and a backup wireless communication module. The dual-port EtherCAT slave module triggers port switching via hardware interrupt when the control module detects a primary link failure. The dual wireless communication module switches to the backup wireless communication module when the control module detects that the link quality of the primary communication module is lower than a preset quality. The control module is also used to add a multi-level distributed clock synchronization optimization algorithm including dynamic drift compensation for master-slave clock synchronization; the dynamic drift compensation includes: collecting master-slave clock offsets once every preset time to construct an offset sequence; using a quadratic fitting algorithm to fit the sequence to obtain a drift trend function; predicting the offset of the next cycle; and using a PI closed-loop control algorithm to adjust the clock output frequency of the programmable logic device in the wireless gateway.

2. The wireless communication system based on an EtherCAT network according to claim 1, characterized in that, The auxiliary function module also includes a wide voltage input power supply module; the wide voltage input power supply module is used to output multiple sets of isolated power supplies to power the wireless communication module and the EtherCAT slave module.

3. The wireless communication system based on EtherCAT network according to claim 1, characterized in that, The control module is also used to generate synchronization frames for EtherCAT frames and control the synchronization frames to be transmitted in parallel through different wireless communication modules during the interval between the end of each EtherCAT frame transmission and the preparation for frequency hopping switching; it is also used to receive the timestamps of the recorded EtherCAT frames and synchronization frames; for each EtherCAT frame period, it calculates the multipath synchronization frame delay characteristic values ​​based on the timestamp of the synchronization frame, including: multipath one-way delay, single-path delay mean, single-path delay variance, and multipath delay difference; based on the multipath synchronization frame delay characteristic values, it performs path delay calibration on each EtherCAT frame; and based on the calibrated EtherCAT frame path delay, it corrects the master-slave clock offset.

4. The wireless communication system based on EtherCAT network according to claim 1, characterized in that, The control module is also used to dynamically adjust the EtherCAT frame period to match the network load during the process of dynamically generating the frequency hopping sequence according to the communication period of the EtherCAT master station, and set the frequency hopping interval to be equal to the adjusted EtherCAT frame period; generate pseudo-random frequency hopping sequences based on the random improved algorithm of chaotic mapping, and combine the designed multi-channel cooperative frequency hopping to obtain the reference frequency hopping sequence generated by the main channel and the offset frequency hopping sequence generated by the backup channel to adjust the sequence offset of the reference frequency hopping sequence, and load the reference frequency hopping sequence and the offset frequency hopping sequence into the sequence storage module of the programmable device; The control module is also used to generate a sequence index of the current cycle of the main channel and the backup channel during the frequency switching process triggered when the EtherCAT frame transmission is detected to be completed, and to update the index to point to the frequency point of the next cycle when the EtherCAT frame transmission is detected to be completed, thereby triggering the frequency switching to complete the frequency hopping of the main channel and the backup channel. Based on real-time monitoring of the main channel signal quality, when the main channel signal quality meets the preset channel switching standard, the frequency point is switched to the backup channel at the same time. When the main channel signal quality meets the preset channel recovery standard, the frequency point is switched back to the main channel automatically at the same time.

5. The wireless communication system based on EtherCAT network according to claim 1, characterized in that, The control module is also used to determine that when the length of the encapsulated and converted EtherCAT frame exceeds the maximum load of the wireless frame, it divides the encapsulated and converted EtherCAT frame into multiple fragments with fragment identifiers and transmits them sequentially through the wireless communication module so that the wireless slave station can reassemble them according to the sequence number and verify their integrity. If a fragment is lost, a priority retransmission request is triggered. It is also used to prioritize retransmission of lost fragments after receiving the priority retransmission request.

6. The wireless communication system based on EtherCAT network according to claim 1, characterized in that, The control module is also used to encrypt the EtherCAT master station control commands using the AES128 encryption algorithm. The encryption key is dynamically distributed by the EtherCAT master station, and a 16-bit CRC checksum is added to the wireless frame. It is also used to use a request-response mechanism to send EtherCAT master station control commands and wait for the wireless slave station to respond, and to retransmit when the response times out.

7. A wireless communication method based on the system of any of claims 1-6, characterized by, include: The EtherCAT slave module in the wireless gateway receives EtherCAT frames sent by the EtherCAT master station. The EtherCAT frames received by the EtherCAT slave module are encapsulated and converted through hardware-level protocol conversion. The control module sends the converted wireless frames to the corresponding wireless slave stations, and a multi-level distributed clock synchronization algorithm is used to compensate for the wireless transmission delay.

8. The wireless communication method according to claim 7, wherein, Also includes: The wireless slave station parses the EtherCAT master station control commands, collects local data based on the parsed EtherCAT master station control commands, encapsulates it into EtherCAT sub-messages, and sends the wireless frames encapsulated with EtherCAT sub-messages to the wireless gateway through the wireless communication module. Using a wireless gateway, the wireless frames of the wireless communication module are encapsulated and converted through hardware-level protocol conversion. EtherCAT sub-messages are extracted from the wireless frames and written into the memory of the EtherCAT slave module. The EtherCAT sub-messages are then inserted into the corresponding sub-message field positions of the EtherCAT frame in an orderly manner according to the memory storage order to generate an EtherCAT frame. The generated EtherCAT frame is then sent back to the EtherCAT master station.

Images