Semiconductor structure and manufacturing method thereof
By designing virtual patterns and virtual extensions in the semiconductor structure, the problems of active area bending and word line breakage are solved, improving the yield and mass production adaptability of the semiconductor structure, and reducing production costs and energy consumption.
Patent Information
- Application Number
- CN202411233386.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-13
- Filing Date
- 2024-09-04
- Publication Date
- 2026-02-13
AI Technical Summary
In the semiconductor manufacturing process, as devices are miniaturized, the aspect ratio of the active region increases, leading to problems such as bending of the active region and broken embedded word lines, which affect alignment and electrical connections.
By designing virtual patterns in the substrate and setting virtual extensions at the intersection of the virtual region and the array region, embedded word lines are formed. Virtual recesses are formed by etching a sacrificial material layer to avoid word line breaks, and a continuous word line structure is formed by stacking gate materials.
It improves the yield of semiconductor structures, solves the word line breakage problem, is suitable for mass production, reduces production costs and energy consumption, and increases the total number of chips on the wafer.
Smart Images
Figure CN121531707A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor structure and a method of fabricating the same, and more particularly to a method of fabricating a semiconductor structure and a semiconductor structure made thereby, which can avoid the breakage of word lines and improve the yield of the semiconductor structure. BACKGROUND
[0002] As the fabrication technology of devices continues to be scaled down, many challenges arise. In particular, as the size and pitch of active regions in a substrate are scaled down, the aspect ratio of the active regions is increased, and the problem of active region bowing at the edge of an array region is prone to occur. If this bowing problem occurs, it can affect the alignment of the active regions and the word lines, and even affect the electrical connection therebetween. To solve this bowing problem, a dummy pattern having a large size is traditionally designed at the edge of the array region in the substrate. However, when the area of the dummy pattern is increased, for example, in the process of fabricating a dynamic random access memory (DRAM) having embedded word lines, due to some manufacturing process factors, for example, in the manufacturing process of gate trenches, the substrate in the dummy region located at the edge of the array region and adjacent to the peripheral region can be relatively protruding due to the etching loading effect, and thus the word lines formed subsequently in the gate trenches can have the problem of breakage. SUMMARY
[0003] Some embodiments of the present application provide a semiconductor structure and a method of fabricating the same, which can improve the aforementioned problems of active region bowing and embedded word line breakage.
[0004] Some embodiments of the present application provide a semiconductor structure, which includes a substrate and a plurality of word lines. The substrate includes an array region, a peripheral region surrounding the array region, and a dummy region between the array region and the peripheral region. The array region has a plurality of active regions separated by isolation structures. The dummy region has a dummy pattern. The word lines are embedded in the substrate, each of the word lines extends along a first direction, and the word lines are arranged along a second direction, wherein each of the word lines has a dummy extension extending toward the interior of the substrate at the intersection with the dummy pattern, and the dummy extensions are arranged along the second direction.
[0005] Some embodiments of the present application provide a method of fabricating a semiconductor structure, which includes providing a substrate including an array region, a peripheral region surrounding the array region, and a dummy region between the array region and the peripheral region. The array region has a plurality of active regions separated by isolation structures. The dummy region has a dummy pattern. The method further includes forming a plurality of word lines embedded in the substrate, each of the word lines extends along a first direction, and the word lines are arranged along a second direction, wherein each of the word lines has a dummy extension extending toward the interior of the substrate at the intersection with the dummy pattern, and the dummy extensions are arranged along the second direction.
[0006] The semiconductor structure and the manufacturing method thereof can promote the alignment between the active region and the word line, form the word line continuously extending from the active region to the peripheral region, and improve the yield of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 is a partial top view of a semiconductor structure according to an embodiment of the present application.
[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H are cross-sectional schematic views of a semiconductor structure according to an embodiment of the present application at a plurality of intermediate manufacturing stages.
[0009] Figure 3A , Figure 3B are cross-sectional schematic views of a semiconductor structure according to another embodiment of the present application at a plurality of intermediate manufacturing stages.
[0010] REFERENCE NUMERALS
[0011] 100: substrate
[0012] A1: array region
[0013] AA: active region
[0014] A2: peripheral region
[0015] AD: dummy pattern
[0016] A3: dummy region
[0017] WL: word line
[0018] D1: first direction
[0019] D2: second direction
[0020] D3: third direction
[0021] D AA : arrangement direction of active region
[0022] 102: first protrusion portion
[0023] 104: second protrusion portion
[0024] 106: dummy protrusion portion
[0025] 111: gate trench
[0026] 111L: lower portion of gate trench
[0027] 111U: upper portion of gate trench
[0028] 112: isolation structure
[0029] 1200: sacrificial material layer
[0030] 120: remaining portion of sacrificial material layer
[0031] 122: sacrificial fill
[0032] 124: ring portion
[0033] 134: dummy via
[0034] 140: gate material stack
[0035] 141: gate dielectric layer
[0036] 143: gate blocking layer
[0037] 145, 145’: gate electrode layer
[0038] 146: fill of wordline material
[0039] 147, 149: dummy extension
[0040] 150: gate contact
[0041] 102a, 104a, 1200a, 120a: top surface
[0042] 112b, 122b, 134b, 146b, 147b: bottom surface
[0043] 147s: sidewall
[0044] C-C: cutline
[0045] L1, L2, L3: line
[0046] W1, W3, W4, W5: width
[0047] W2, W6: critical dimension DETAILED DESCRIPTION
[0048] The following provides many different embodiments for implementing relevant components of embodiments of the present invention. Of course, these are merely examples and are not intended to limit the invention. For example, unless specifically excluded, references to a first component being formed on or located on a second component may include both direct and indirect contact between the first and second components. Furthermore, the invention may repeat device symbols and / or letters in many embodiments. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed. Moreover, for the sake of brevity, not all known steps and structures are described in detail herein.
[0049] Furthermore, in some of the following embodiments, the semiconductor structure may be part of a DRAM, and other parts of the DRAM may be fabricated using known DRAM devices. Although the drawings only depict a portion of the array region and a portion of the peripheral region adjacent to the array region for illustrative purposes, the invention is not limited to the components shown.
[0050] like Figure 1 The partial top view of the semiconductor structure shown in this embodiment includes a substrate 100 and multiple word lines WL. The substrate 100 includes an array region A1, a virtual region A3, and a peripheral region A2. The virtual region A3 is located between the array region A1 and the peripheral region A2. The array region A1 has multiple active regions AA separated by an isolation structure 112. The virtual region A3 has a virtual pattern AD. In some embodiments, the semiconductor structure further includes multiple gate contacts 150 located in the peripheral region A2, and each gate contact 150 is electrically connected to a corresponding word line WL.
[0051] Each word line WL is located on the substrate 100 and extends along a first direction D1, and these word lines WL are spaced apart along a second direction D2, which is different from the first direction D1. In this example, the second direction D2 is perpendicular to the first direction D1, and each active region AA is approximately along direction D1. AA Extend, and in direction D AA Unlike the first direction D1 and the second direction D2, the virtual pattern AD extends, for example, along the second direction D2 and can be located on the left and right sides of the array region A1 (only one side is shown in the figure). Specifically, the virtual pattern AD can be located between the array region A1 and the side of the peripheral region A2 where the gate contact 150 is provided. The virtual pattern AD can be connected to some active regions AA located at the edge of the array region A1 to avoid peeling, collapse, or bending of these active regions AA, thereby promoting the alignment of the active regions AA with the subsequent word lines WL.
[0052] Furthermore, in this embodiment, the virtual pattern AD has a plurality of virtual recesses 134 extending toward the interior of the substrate 100 (i.e., in the third direction D3). Figure 2E), and the dummy recesses 134 are spaced apart in the second direction D2. Each word line WL has a dummy extension 147 filling in the dummy recess 134, i.e., the dummy extension 147 extends toward the interior of the substrate 100. Each dummy extension 147 is spaced apart from a corresponding electrically connected gate contact 150 in the first direction D1.
[0053] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H For example, is a cross-sectional view taken along the cross-sectional line C-C direction of Figure 1 Referring to Figure 2A , isolation structures 112 are formed in the substrate 100. The isolation structures 112 surround and define active areas AA and dummy areas AD. The substrate 100 can comprise a semiconductor material, such as silicon, gallium arsenide, gallium nitride, silicon germanium, or a combination thereof. In other embodiments, the substrate 100 is a silicon-on-insulator substrate. The isolation structures 112 can comprise silicon oxide, silicon nitride, other suitable insulating materials, or a combination thereof.
[0054] Thereafter, referring to Figure 1 and Figure 2B , the isolation structures 112 and the substrate 100 are formed with a plurality of gate trenches 111, each corresponding to one of the word lines WL. Due to etch selectivity, the isolation structures 112 are etched deeper than the substrate 100 during formation of the plurality of gate trenches 111. As a result, at the bottom of the gate trenches 111, the top surface of the substrate 100 is higher than the top surface of the isolation structures 112. In the present embodiment, in the gate trenches 111, the substrate 100 comprises a plurality of first protrusions 102 in the array area Al and a plurality of second protrusions 104 in the dummy area A3. Further, due to etch loading effects, the substrate 100 in the dummy area A3 and the peripheral area A2 is etched less than the array area Al during formation of the plurality of gate trenches 111. As a result, in the gate trenches 111, the top surface 104a of the substrate 100 (i.e., the second protrusions 104) in the dummy area A3 is higher than the top surface 102a of the substrate 100 (i.e., the first protrusions 102) in the array area Al.
[0055] Next, referring to Figure 2CA sacrificial material layer 1200 is filled in the gate trenches 111, such that the sacrificial material layer 1200 covers the first protrusions 102 and the second protrusions 104. In an embodiment, the sacrificial material layer 1200 fills the spaces between the first protrusions 102, and fills the spaces between the second protrusions 104 and the adjacent first protrusions 102. The sacrificial material layer 1200, for example, is over-deposited to extend over the top surface of the substrate 100 in the peripheral region A2 to cover the top surface of the substrate 100, in addition to filling the gate trenches 111. Accordingly, a top surface 1200a of the sacrificial material layer 1200 is a planar surface. In some embodiments, the material of the sacrificial material layer 1200 is different from the material of the isolation structures 112 and the material of the substrate 100. For example, the sacrificial material layer 1200 can include a material with high flowability, such as a spin-on carbon (SOC) layer.
[0056] According to some embodiments, referring to Figure 2D A portion of the sacrificial material layer 1200 is removed, such that a remaining portion 120 of the sacrificial material layer has a top surface 120a lower than the top surface 104a of the second protrusions 104. Accordingly, a portion of the second protrusions 104 protrude above the remaining portion 120 of the sacrificial material layer. The remaining portion 120 of the sacrificial material layer can have a continuous top surface 120a over the isolation structures 112 and the active region AA, and the top surface 120a is lower than the top surface 104a of the second protrusions 104.
[0057] In some embodiments, the portion of the sacrificial material layer 1200 can be removed by an etching manufacturing process, such as an etch-back. In some embodiments, the etching manufacturing process can be performed with a suitable etching selectivity, such as an etching selectivity of 3:1 between the sacrificial material layer 1200 and the substrate 100, to reduce the impact on the second protrusions 104. In more detail, in some embodiments, the remaining portion 120 of the sacrificial material layer covers the first protrusions 102, and is higher than the top surface 102a of the first protrusions 102. Further, in some embodiments, the remaining portion 120 of the sacrificial material layer can form sacrificial fillers 122 between the first protrusions 102 in the active region AA, and between the first protrusions 102 and the second protrusions 104.
[0058] Further, in some embodiments, the remaining portion 120 of the sacrificial material layer includes ring portions 124, which respectively surround the second protrusions 104 corresponding to the word lines WL in the dummy pattern AD, if viewed from above the substrate 100.
[0059] Furthermore, in some applications, the height of the remaining portion 120 of the sacrificial material layer and the height of the second protrusion 104 protruding above the remaining portion 120 can be controlled and adjusted according to the depth to which the second protrusion 104 is to be recessed later, and the present application does not limit the same.
[0060] Next, referring to Figure 2E In the gate trench 111, the second protrusion 104 is etched by an etching manufacturing process (e.g., a dry etching manufacturing process) using the remaining portion 120 of the sacrificial material layer as an etching mask, so as to recess the second protrusion 104 and form a virtual recess 134. The recessing depth of the virtual recess 134 is at least lower than the top surface 120a of the remaining portion 120 of the sacrificial material layer, so as to avoid the subsequent formed word line WL from being broken.
[0061] In some embodiments, the etching manufacturing process performed on the second protrusion 104 can have high selectivity, and almost does not affect the remaining portion 120 of the sacrificial material layer.
[0062] In some embodiments, the virtual recess 134 has a U-shaped cross section. However, the present application is not limited thereto, and the virtual recess 134 can also have other cross-sectional shapes.
[0063] According to some embodiments, the depth (e.g., line L2) of the virtual recess 134 can be at any level between the depth (e.g., line L1) of the top surface 120a of the remaining portion 120 of the sacrificial material layer and the depth of the isolation structure 112. In other words, the bottom surface 134b of the virtual recess 134 is not lower than the bottom surface 112b of the isolation structure 112, and is not higher than the top surface 120a of the remaining portion 120 of the sacrificial material layer. In preferred embodiments, the depth (e.g., line L2) of the virtual recess 134 can be substantially the same as, or higher than, the depth (e.g., line L3) of the sacrificial filling portion 122. In the present embodiment, the bottom surface 134b of the virtual recess 134 is lower than the bottom surface 122b of the sacrificial filling portion 122. In this way, the subsequent formed word line WL can be further prevented from being interfered, and the resistance of the word line WL can be reduced.
[0064] Furthermore, in some embodiments, the virtual protrusion portion 106 is formed in the substrate 100 at the same time when the virtual recess 134 is formed, so as to define the virtual recess 134. The top surface of the virtual protrusion portion 106 is not higher than the top surface 120a of the remaining portion 120 of the sacrificial material layer, and can be substantially coplanar with the top surface of the first protrusion 102, for example.
[0065] Afterwards, according to some embodiments, referring to Figure 2FIn some embodiments, the remaining portions 120 of the sacrificial material layers can be removed by one or more steps including a ashing manufacturing process, an etching manufacturing process, etc. to expose the first protrusions 102 in the array region Al and the dummy protrusions 106 in the dummy region A3 in the gate trenches 111.
[0066] According to some embodiments, referring to Figure 2G , a gate material stack 140 is formed in the gate trenches 111 and the dummy recesses 134. In this example, the gate material stack 140 includes a gate dielectric layer 141, a gate blocking layer 143, and a gate electrode layer 145.
[0067] According to some embodiments, the gate dielectric layer 141 conformally covers the sidewalls and top surfaces of the first protrusions 102, and the sidewalls and bottom surfaces of the dummy recesses 134. The gate dielectric layer 141 can include silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof. In one example, the gate dielectric layer 141 can be a multi-layer structure of silicon oxide / silicon nitride / silicon oxide (ONO), or a multi-layer structure of silicon nitride / silicon oxide / silicon nitride / silicon oxide / silicon nitride (NONON), but the application is not limited thereto.
[0068] According to some embodiments, the gate blocking layer 143 is conformally formed on the gate dielectric layer 141 above the first protrusions 102 and in the dummy recesses 134. The material of the gate blocking layer 143 can include a conductive metal, such as a metal, a metal alloy, a metal nitride, or a metal silicide, such as titanium nitride, titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten nitride (WN), tantalum (Ta), titanium (Ti), tungsten (W), ruthenium (Ru), or aluminum.
[0069] According to some embodiments, the gate electrode layer 145 is formed on the gate blocking layer 143. This gate electrode layer 145 is, for example, over-deposited to fill the remaining spaces of the gate trenches 111, and also extends onto the top surface of the substrate 100 in the peripheral region A2 to cover the top surface of the substrate 100. Accordingly, the top surface of the gate electrode layer 145 is a planar surface. The material of the gate electrode layer 145 can include a conductive metal, such as a metal, a metal alloy, a metal nitride, or a metal silicide, such as tungsten, tantalum, titanium, ruthenium, aluminum, tungsten nitride, titanium nitride, titanium silicon nitride, tantalum nitride, or other suitable conductive materials. The material of the gate electrode layer 145 is different from the material of the gate blocking layer 143. In some embodiments, the gate blocking layer 143 includes titanium nitride, and the gate electrode layer 145 includes tungsten.
[0070] After that, referring to Figure 2H , a portion of the gate material stack 140 is removed to recess the gate material stack 140 to form word lines WL. Each word line WL includes a dummy extension 147 filled in the dummy recess 134.
[0071] In some embodiments, the step of removing a portion of the gate material stack 140 can include a chemical mechanical polishing (CMP) fabrication process, an etch-back fabrication process, or other suitable fabrication process to remove the gate material stack 140 located outside the gate trench 111. Thereafter, the gate electrode layer 145 within the recessed gate trench 111 is formed, e.g., using a selective etching fabrication process, while leaving a portion of the gate electrode layer 145' at the lower portion 111L of the gate trench 111.
[0072] In this example, the word line WL includes the gate dielectric layer 141, the gate blocking layer 143, and the gate electrode layer 145' formed at the lower portion 111L of the gate trench 111. Each word line WL also includes the gate dielectric layer 141, the gate blocking layer 143, and the gate electrode layer 145' in the dummy extension 147 in the dummy recess 134.
[0073] Thereafter, an insulating layer (not shown) can be formed on the word line WL to fill the gate trench 111 to form an embedded word line WL. The material of the insulating layer is, for example, silicon nitride or other suitable insulating material. In some other embodiments, the word line WL can include the gate dielectric layer 141, the gate blocking layer 143, the gate electrode layer 145, and a work function layer formed sequentially. After the embedded word line WL is formed, subsequent fabrication processes can be performed to fabricate other components of the semiconductor structure. For example, bit lines (not shown) can be formed above the word lines WL, an interlayer dielectric layer (not shown) can be formed to cover the bit lines, gate contacts 150 can be formed, and known components such as capacitors (not shown), metal layers (not shown), etc. can be formed to complete the fabrication of a memory device (e.g., a DRAM). The bit lines, for example, extend in a second direction D2, which is perpendicular to the extension direction (first direction Dl) of the word lines WL. Further, as shown, the gate contacts 150 can be located in the peripheral region A2 and can be electrically connected to the underlying corresponding word lines WL through the above-mentioned interlayer dielectric layer. Figure 1
[0074] According to the semiconductor structure of the present application, as shown in FIG. 1, the substrate 100 has the first protruding portions 102 located in the active region AA and the dummy protruding portions 106 located in the dummy region A3, and the word lines WL include the fill portions 146 formed between the first protruding portions 102 and the dummy extensions 147 formed between the dummy protruding portions 106. In this embodiment, the width W3 of the first protruding portions 102 in the first direction Dl can be greater than the width W4 of the dummy protruding portions 106 in the first direction Dl. Each dummy extension 147 can have, but is not limited to, a U-shaped cross-section. Further, as shown in FIG. 1, the dummy extensions 147 can be formed in the dummy region A3 to extend in the second direction D2, which is perpendicular to the first direction Dl. Figure 2H Figure 1 As shown, each virtual extension 147 may have a circular top surface, but the present invention is not limited to this. The top surface of the virtual extension 147 may also be elliptical, quadrilateral, polygonal, or approximately the aforementioned shape. According to the above embodiment, the gate material stack 140 can continuously fill the gate trench 111, that is, extend continuously in the first direction D1, so that the word line WL does not have the problem of broken lines.
[0075] Furthermore, according to some embodiments, the depth of the virtual extension 147 (e.g., line L2) can fall at any horizontal height between the depth of the filler portion 146 (e.g., line L3) and the depth of the isolation structure 112 (e.g., line L1). In other words, the bottom surface 147b of the virtual extension 147 is not lower than the bottom surface 112b of the isolation structure 112, and not higher than the bottom surface 146b of the filler portion 146. In a preferred embodiment, the depth of the virtual extension 147 (e.g., line L2) can be approximately the same as or exceed the depth of the filler portion 146 (e.g., line L3). In this embodiment, the bottom surface 147b of the virtual extension 147 is lower than the bottom surface 146b of the filler portion 146. This further avoids interference from the word line WL and reduces the resistance of the word line WL.
[0076] like Figure 1 As shown, each character line WL has a width W1 in the second direction D2, the virtual pattern AD has a width W5 in the first direction D1, and the top surface of the virtual extension 147 has a critical dimension W2 in the second direction D2 that is less than or equal to the width W1, and a critical dimension W6 in the first direction D1 that is less than or equal to the width W5.
[0077] Furthermore, according to the semiconductor structure manufacturing method proposed in the first embodiment above, after removing the remaining portion 120 of the sacrificial material layer ( Figure 2F Then, the gate dielectric layer 141, the gate barrier layer 143, and the gate electrode layer 145 are deposited sequentially. Figure 2G However, the manufacturing method of the present invention is not limited to the above order. In the second embodiment of the present invention, as... Figure 3A As shown, gate trench 111 can be formed ( Figure 2B After that, a gate dielectric layer 141 is deposited first, followed by a sacrificial material layer 1200 deposited on top of the gate dielectric layer 141. Then, the following steps are performed: Figures 2D to 2F The steps shown are to form the virtual recess 134 and the remaining portion 120 after removing the sacrificial material layer.
[0078] Figure 3A , Figure 3B For example, it corresponds to Figure 1 The cross section taken along the CC direction. Figure 3A , Figure 3B Zhongyu Figure 1and Figure 2A 、 Figure 2B 、 Figure 2C 、 Figure 2D 、 Figure 2E 、 Figure 2F 、 Figure 2G 、 Figure 2H The same or similar components use the same or similar reference numbers, and the relevant details can be understood with reference to the above-described embodiments regarding the components, which are not repeated here.
[0079] Unlike the above-described embodiments as shown in Figure 2G , in this example, after forming the dummy recess 134, the gate blocking layer 143 and the gate electrode layer 145 are formed in the gate trench 111 and the dummy recess 134 without including the gate dielectric layer 141. Then, referring to Figure 3B , the gate electrode layer 145 in the recessed gate trench 111, leaving a portion of the gate electrode layer 145' in the lower portion 111L of the gate trench 111 to form an embedded word line WL. In each gate trench 111, each word line WL includes a dummy extension 149 filled in the dummy recess 134.
[0080] It is noted that in the second embodiment, in the step of recessing the second protrusion portion 104 to form the dummy recess 134, the gate dielectric layer 141 on the second protrusion portion 104 is removed together, and a remaining portion of the gate dielectric layer 141 covers the substrate 100 other than the second protrusion portion 104, such as covering the first protrusion portion 102 and the dummy protrusion portion 106 (as shown in Figure 3B ). In other words, the gate dielectric layer 141 does not exist in the dummy recess 134. That is, the dummy extension 149 includes the gate blocking layer 143 and the gate electrode layer 145', but does not include the gate dielectric layer 141.
[0081] In summary, according to the manufacturing method of the semiconductor structure proposed in some embodiments of the present application, the relatively protruding substrate portion (such as the second protrusion portion) in the dummy pattern is recessed before the gate material stack is deposited in the gate trench, so that after the gate material stack and the gate material stack of the recessed portion are filled in the gate trench, the word line can be continuously formed in the gate trench. Therefore, according to the semiconductor structure and the manufacturing method thereof, the problem of word line disconnection in the known technology is solved, and the yield of the semiconductor structure is improved. Furthermore, according to some embodiments of the present application, by forming a sacrificial material layer above the substrate and partially removing the sacrificial material layer, the remaining portion of the sacrificial material layer exposes the relatively protruding substrate portion (such as the second protrusion portion), and the remaining portion of the sacrificial material layer is used as an etching mask to recess the second protrusion portion. Therefore, according to the method proposed in the embodiments, the manufacturing process is simple, and is compatible with the existing semiconductor manufacturing process, which is suitable for mass production.
[0082] Furthermore, the present application is suitable for fabricating miniaturized semiconductor structures to increase the total number of dies on a wafer. Therefore, the present application can reduce the production cost and energy consumption of manufacturing individual ICs, and reduce the production energy consumption of subsequent packaging, thereby reducing the energy consumption in the semiconductor structure production process. In addition, since the yield of the semiconductor structure of the present application is improved, the present application provides a green semiconductor technology.
[0083] It should be understood by those skilled in the art to which this application pertains that they can readily apply the principles of the present application to other manufacturing processes and structures to produce the same results as the embodiments described herein, without departing from the spirit and scope of the present application. It should also be understood that such equivalent constructions are intended to fall within the spirit and scope of the present application, and that changes, substitutions, and alterations can be variously made by those skilled in the art without departing from the spirit and scope of the present application. Therefore, the scope of the present application is to be limited only by the scope of the claims.
Claims
1. A semiconductor structure, characterized in that, include: A substrate, comprising: An array region having multiple active regions, wherein the multiple active regions are separated by an isolation structure; A surrounding area, surrounding the array region; and A virtual region, located between the array region and the surrounding region, and having a virtual pattern; and Multiple character lines are embedded in the substrate, each character line extending along a first direction and arranged along a second direction, wherein each character line has a virtual extension extending toward the interior of the substrate at the intersection with the virtual pattern, and multiple virtual extensions are arranged along the second direction.
2. The semiconductor structure as described in claim 1, characterized in that, Each word line extends continuously from the array region to the peripheral region and is electrically connected to the gate contact located in the peripheral region. The virtual pattern has multiple virtual recesses, and each virtual extension is filled into one of the multiple virtual recesses.
3. The semiconductor structure as described in claim 2, characterized in that, The substrate has multiple protrusions located in the array region, and the virtual pattern includes virtual protrusion portions surrounding the multiple virtual extensions, with each word line covering the virtual protrusion portions and the multiple protrusions.
4. The semiconductor structure as described in claim 3, characterized in that, The width of one of the plurality of protrusions in the first direction is greater than the width of the virtual protrusion in the first direction.
5. The semiconductor structure as described in claim 1, characterized in that, The bottom surface of each virtual extension is not lower than the bottom surface of the isolation structure.
6. The semiconductor structure as described in claim 5, characterized in that, The substrate has multiple protrusions located in the array region, each word line has a filling portion between the multiple protrusions, and the bottom surface of each virtual extension is not higher than the bottom surface of the filling portion.
7. The semiconductor structure as described in claim 1, characterized in that, Each character line has a first width in the second direction, the virtual pattern has a second width in the first direction, the top surface of the virtual extension has a first critical dimension less than or equal to the first width in the second direction, and a second critical dimension less than or equal to the second width in the first direction.
8. The semiconductor structure as described in claim 1, characterized in that, Including: Multiple gate contacts are located in the peripheral area and electrically connected to the corresponding multiple word lines. Each virtual extension is spaced apart from the corresponding gate contact in the first direction by a distance.
9. The semiconductor structure as described in claim 8, characterized in that, The virtual pattern is connected to the plurality of active regions located at the edge of the array region.
10. The semiconductor structure as claimed in claim 1, characterized in that, This virtual extension does not have a gate dielectric layer.
11. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising: An array region having multiple active regions, wherein the multiple active regions are separated by an isolation structure; A surrounding area, surrounding the array region; and A virtual region, located between the array region and the surrounding region, and having a virtual pattern; and Multiple character lines are formed embedded in the substrate, each character line extending along a first direction and arranged along a second direction, wherein each character line has a virtual extension extending toward the interior of the substrate at the intersection with the virtual pattern, and multiple virtual extensions are arranged along the second direction.
12. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, Each word line extends continuously from the array region to the peripheral region and is electrically connected to the gate contact located in the peripheral region. The virtual pattern has multiple virtual recesses, and each virtual extension is filled into one of the multiple virtual recesses.
13. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The formation of the multiple word lines includes: Multiple gate trenches are formed in the isolation structure and the substrate, such that the substrate located at the bottom of the multiple gate trenches includes multiple first protrusions located in the array region and multiple second protrusions located in the virtual pattern, wherein the top surface of the multiple second protrusions is higher than the top surface of the multiple first protrusions; A sacrificial material layer is filled into the plurality of gate trenches to cover the plurality of first protrusions and the plurality of second protrusions; Remove a portion of the sacrificial material layer so that the top surface of the remaining portion of the sacrificial material layer is lower than the top surface of the plurality of second protrusions; Using the remaining portion of the sacrificial material layer as a mask, the plurality of second protrusions are recessed, thereby forming a plurality of virtual recesses in the virtual pattern; and Remove the remaining portion of the sacrificial material layer to expose the plurality of first protrusions and the plurality of dummy recesses in the plurality of gate trenches.
14. The method for manufacturing a semiconductor structure as described in claim 13, characterized in that, The top surface of the remaining portion of the sacrificial material layer is higher than the top surface of the plurality of first protrusions.
15. The method for manufacturing a semiconductor structure as described in claim 13, characterized in that, The remaining portion of the sacrificial material layer includes multiple rings, each ring surrounding one of the multiple second protrusions.
16. The method for manufacturing a semiconductor structure as described in claim 13, characterized in that, The bottom surface of the plurality of virtual recesses is not lower than the bottom surface of the isolation structure.
17. The method for manufacturing a semiconductor structure as described in claim 16, characterized in that, The remaining portion of the sacrificial material layer has a sacrificial filler between the plurality of first protrusions, wherein the bottom surface of the plurality of virtual recesses is not higher than the bottom surface of the sacrificial filler.
18. The method for manufacturing a semiconductor structure as described in claim 13, characterized in that, After forming the gate trench, it further includes: A gate dielectric layer is formed in the plurality of gate trenches. The sacrificial material layer is formed on the gate dielectric layer.
19. The method for manufacturing a semiconductor structure as described in claim 13, characterized in that, After removing the remaining portion of the sacrificial material layer, the formation of the plurality of letter lines further includes: A gate dielectric layer is deposited in the plurality of gate trenches and the plurality of virtual vias; Deposit a gate barrier layer on the gate dielectric layer; and A gate electrode layer is deposited on the gate barrier layer.
20. The method for manufacturing a semiconductor structure as described in claim 11, characterized in that, The virtual pattern is connected to the plurality of active regions located at the edge of the array region.