Memory device and manufacturing method thereof
By forming isolation structures and word line structures in DRAM memory cells and using specific etchant processes to form contact holes to increase the contact area between the active region and the bit line contacts, the problem of high resistance in DRAM memory cells is solved, memory performance is improved and the risk of current leakage is reduced.
Patent Information
- Application Number
- CN202411838590.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-08-13
- Filing Date
- 2024-12-13
- Publication Date
- 2026-02-13
AI Technical Summary
In existing DRAM memory cells, the resistance between different components of the memory cell is relatively high, which affects memory performance.
By forming an isolation structure in the substrate and forming a character line structure therebetween, and using a specific etchant process to form contact holes to expose the active area, the top surface of the active area is ensured to be raised and in contact with the character line contacts, thereby increasing the contact area and reducing resistance.
It effectively reduces the resistance of DRAM memory cells, improves memory performance, and avoids current leakage caused by component misalignment.
Smart Images
Figure CN121531708A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a memory device and a method of manufacturing the same. BACKGROUND
[0002] A typical DRAM memory cell incorporates a capacitor and a transistor, where the capacitor temporarily stores data according to a charge state of the capacitor. A bit line is electrically connected to a source / drain region of the transistor, and a word line is electrically connected to a gate region of the transistor. The capacitor is electrically connected to another source / drain region of the corresponding transistor. The resistance between different components of the memory cell should be reduced to enhance the performance of the memory cell. SUMMARY
[0003] It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory only and are intended to provide further explanation of the disclosure as claimed.
[0004] Some embodiments of the present disclosure provide a method of manufacturing a memory device, comprising the steps of: forming an isolation structure in a substrate to define an active region in the substrate; forming a word line structure between the isolation structure and the active region, wherein the word line structure comprises a word line layer and a gate dielectric layer extending along sidewalls and a bottom of the word line layer and along sidewalls of the active region; forming a cap layer covering the word line structure, the isolation structure, and the active region; forming a contact hole in the cap layer to expose the active region, wherein a top surface of the active region is raised; forming a bit line contact in the contact hole; and forming a bit line electrically connected to the bit line contact.
[0005] In some embodiments, the contact hole further exposes the gate dielectric layer along the sidewalls of the active region.
[0006] In some embodiments, the step of forming the contact hole comprises: forming a recess in the cap layer to expose the top surface of the active region and a top end of the gate dielectric layer conformally along the sidewalls of the active region; removing a portion of the gate dielectric layer conformally along the sidewalls of the active region through the recess; and after removing the portion of the gate dielectric layer, removing a portion of the active region such that the top surface of the active region is higher than the top end of the gate dielectric layer conformally along the sidewalls of the active region.
[0007] In some embodiments, the portion of the gate dielectric layer is removed using a first etchant, the portion of the active region is removed using a second etchant, and the first etchant is different from the second etchant.
[0008] In some embodiments, the portion of the cap layer adjacent to the gate dielectric layer is further removed using the first etchant.
[0009] In some embodiments, when the portion of the gate dielectric layer is removed, a top corner of the active region is etched such that the top surface of the active region is raised.
[0010] In some embodiments, a top surface of the active region is 3 nm to 10 nm higher than a top end of the gate dielectric layer conformally along sidewalls of the active region.
[0011] In some embodiments, a width of a bottom opening of the contact hole is not less than a width of a top portion of the active region.
[0012] In some embodiments, the bit line contact contacts a top end of the gate dielectric layer conformally along sidewalls of the active region.
[0013] In some embodiments, sidewalls of the bit line contact are raised toward the cap layer.
[0014] Some embodiments of the disclosure provide a memory device, comprising: a substrate comprising an active region protruding upward; an isolation structure in the substrate and adjacent to the active region of the substrate; a word line structure between the active region of the substrate and the isolation structure; a bit line contact over the active region of the substrate, wherein a top surface of the active region of the substrate is raised toward the bit line contact; and a bit line over the bit line contact.
[0015] In some embodiments, the word line structure comprises a word line layer and a gate dielectric layer extending along sidewalls and a bottom of the word line layer and along sidewalls of the active region of the substrate, wherein a top end of the gate dielectric layer along the sidewalls of the active region of the substrate is lower than the top surface of the active region of the substrate.
[0016] In some embodiments, the bit line contact contacts a top end of the gate dielectric layer along sidewalls of the active region of the substrate.
[0017] In some embodiments, a top surface of the active region of the substrate is 3 nm to 10 nm higher than a top end of the gate dielectric layer along sidewalls of the active region of the substrate.
[0018] In some embodiments, the memory device further comprises a cap layer over the word line structure and the isolation structure and adjacent to the bit line contact.
[0019] In some embodiments, sidewalls of the bit line contact are raised toward the cap layer.
[0020] In some embodiments, sidewalls of the cap layer are recessed toward the isolation structure.
[0021] In some embodiments, a bottom surface of the bit line contact is recessed toward the bit line.
[0022] In some embodiments, a width of a bottom of the bit line contact is not less than a width of a top portion of the active region of the substrate.
[0023] In some embodiments, a width of the bit line contact increases away from the active region of the substrate. BRIEF DESCRIPTION OF DRAWINGS
[0024] The present application can be more fully understood by reading the following detailed description together with the accompanying drawings, in which:
[0025] Figure 1 A circuit diagram of a memory device in some embodiments of the present application is illustrated.
[0026] Figure 2 A layout diagram of a memory device in some embodiments of the present application is illustrated.
[0027] Figures 3 to 6 A cross-sectional view of a memory device in some embodiments of the present application is illustrated along line A-A' in Figure 2
[0028] Figure 7 A layout diagram of a memory device in some embodiments of the present application is illustrated after forming contact holes in the cap layer.
[0029] Figure 8 Figure 9 A cross-sectional view of a memory device in some embodiments of the present application is illustrated along line A-A' in Figure 7 DETAILED DESCRIPTION
[0030] Figure 1 A circuit diagram of a memory device in some embodiments of the present application is illustrated. Referring to Figure 1 A memory device (e.g., a dynamic random access memory (DRAM)) can include a plurality of memory cells MC. A typical DRAM memory cell MC incorporates a capacitor CA and a transistor TR, where the capacitor CA temporarily stores data based on a charge state of the capacitor CA. A bit line 140 is electrically connected to a source / drain region of the transistor TR, and a word line structure 110 is electrically connected to a gate region of the transistor TR. The capacitor CA is electrically connected to another source / drain region of the corresponding transistor TR. The resistance of the DRAM memory cell can be reduced by increasing the contact area between two different components (e.g., the source / drain region of the transistor TR and a contact connected to the bit line 140).
[0031] Figure 2 A layout diagram of a memory device in some embodiments of the present application is illustrated. Figures 3 to 6 A cross-sectional view of a memory device in some embodiments of the present application is illustrated along line A-A' in Figure 2 Figure 2 Note that, for simplicity, Figure 2 Figure 3 A substrate 100 is provided, and an isolation structure 105 is formed in the substrate 100 to define an active area AA in the substrate 100. The active area AA is a protruding portion of the substrate 100. The active area AA and the substrate 100 outside the active area AA can have different types of conductors. In some embodiments, if the active area AA is an n-type region, the substrate 100 outside the active area AA is a p-type region. If the active area AA is an n-type region, the substrate 100 outside the active area AA is a p-type region. In some embodiments, the material of the isolation structure 105 is silicon oxide, silicon nitride, or the like.
[0032] Subsequently, word line structures 110 are formed between the isolation structure 105 and the active area AA. Each word line structure 110 includes a word line layer 112 and a gate dielectric layer 114 extending along the sidewalls and the bottom of the word line layer 112 and along the sidewalls of the active area AA and the isolation structure 105. Specifically, a hard mask HM can be formed over the substrate 100 and the isolation structure 105. A trench is formed in the substrate 100 by etching the substrate 100 through the hard mask HM. The gate dielectric layer 114 lines the surfaces of the trench. The word line layer 112 is then formed in the trench. In some embodiments, the word line layer 112 can include more than one conductive layer, such as a conductive layer 112A and a conductive layer 112B. The top surface of the word line layer 112 is lower than the top end of the gate dielectric layer 114, the top surface of the isolation structure 105, and the top surface of the active area AA. In some embodiments, the gate dielectric layer 114 can be formed of silicon oxide. The word line layer 112 can be formed of a conductive material, such as polysilicon, metal, or a combination thereof. For example, the conductive layer 112A can be made of metal, and the conductive layer 112B can be made of polysilicon.
[0033] Subsequently, a cap layer 120 is formed, which fills the remaining trench and covers the word line structures 110, the isolation structure 105, and the active area AA. In some embodiments, the cap layer 120 is made of a dielectric material, such as silicon oxide, silicon nitride, or the like.
[0034] Referring to Figure 4 A recess R is formed in the cap layer 120 to expose the top surface of the active area AA and the top end of the gate dielectric layer 114 conformally along the sidewalls of the active area AA. During the formation of the recess R, the hard mask HM located over the active area AA is also removed. The width of the bottom opening of the recess R is greater than the sum of the width of the top surface of the active area AA and the width of the gate dielectric layer 114 located on both sides of the active area AA. Thus, the bottom opening of the recess R also exposes a portion of the cap layer 120. The width of the bottom opening of the recess R can be determined to achieve a suitable profile of the contact hole to be formed subsequently.
[0035] Referring to Figure 5A portion of the gate dielectric layer 114, conformally along the sidewalls of the active region AA, is removed using a first etchant through a groove R. A portion of the capping layer 120 adjacent to the gate dielectric layer 114 is further removed using the first etchant. After removing the portion of the capping layer 120 adjacent to the gate dielectric layer 114, a contact hole H is formed in the capping layer 120 to expose the active region AA and the gate dielectric layer 114 along the sidewalls of the active region AA, and the contact hole H has recessed sidewalls. The first etchant has etching selectivity, such that the first etchant etches the gate dielectric layer 114 and the capping layer 120 faster than it etches the active region AA. Therefore, the active region AA in Figure 5 The core remains largely intact, and only the top corner of the active region AA is etched, causing the top surface of the active region AA to bulge.
[0036] See Figure 6 After removing a portion of the gate dielectric layer 114 along the sidewall of the active region AA, a second etchant is used to remove a portion of the active region AA, such that the top surface of the active region AA is higher than the top of the gate dielectric layer 114 conformally along the sidewall of the active region AA. After partially etching the active region AA, the width of the bottom opening of the contact hole H is not less than the width of the top portion of the active region AA. The second etchant is different from the first etchant. The second etchant has etching selectivity, such that the second etchant etches the active region AA faster than it etches the gate dielectric layer 114 and the capping layer 120. In some embodiments, the top of the active region AA is 3 to 10 nm higher than the top of the gate dielectric layer 114 conformally along the sidewall of the active region AA (i.e., the vertical distance D between the top of the active region AA and the top of the gate dielectric layer 114 conformally along the sidewall of the active region AA is 3 to 10 nm). Figure 5 The bottom opening of the recess R is wide enough that the etchant does not primarily etch the center of the active region AA. That is, the first etchant can easily etch a portion of the gate dielectric layer 114 along the sidewall of the active region AA and a portion of the capping layer 120 adjacent to the gate dielectric layer 114, while the second etchant can easily etch the peripheral portion of the active region AA. Therefore, the top surface of the gate dielectric layer 114 and the peripheral portion of the active region AA is not higher than the center of the active region AA, and the top surface of the active region AA is convex. If the top surface of the peripheral portion of the active region AA is higher than the top surface of the center of the active region AA, then the peripheral portion of the active region AA will become the tip of the active region AA. If components formed in subsequent processes (e.g., capacitor contacts) are not aligned with each other and contact the tip of the active region AA, the tip of the active region AA may cause leakage current. After forming the contact hole H, the remaining capping layer 120 still covers the word line structure 110 and the isolation structure 105, and the sidewall of the capping layer 120 is recessed towards the isolation structure 105.
[0037] Figure 7This diagram illustrates the layout of a memory device in some embodiments of the invention after the contact holes H are formed in the cover layer 120. In some embodiments, the cover layer 120 covers both ends of each active region AA. Capacitor contacts (not shown) may be electrically connected to both ends of each active region AA in a subsequent process (e.g., forming capacitor contacts through the cover layer 120). Therefore, if the capacitor contacts are misaligned, they may come into contact with the tips of the active regions AA, resulting in current leakage.
[0038] Figure 8 and Figure 9 Description of some embodiments of the present invention Figure 7 A cross-sectional view of the memory device taken along the center line A-A'. See also... Figure 8 The bit line contact 130 is formed in the contact hole H, and is connected to... Figure 7 The exposed portion of the active region AA in the active region AA is contacted, thus bit line contacts 130 are formed between the capping layers 120. Bit line contacts 130 conformally contact the top of the gate dielectric layer 114 along the sidewalls of the active region AA. The sidewalls of the bit line contacts 130 protrude towards the capping layer 120. The width of the bit line contacts 130 increases with distance from the active region AA of the substrate 100. The bottom of the bit line contacts 130 is recessed, and the contact area between the bit line contacts 130 and the active region AA is increased. Therefore, the resistance between the bit line contacts 130 and the active region AA is reduced. In some embodiments, the bit line contacts 130 may be made of a conductive material, such as a metal or a silicon-containing material.
[0039] See Figure 9 A bit line 140 is formed above the bit line contact 130 and the cover layer 120. The bottom surface of the bit line contact 130 is correspondingly recessed toward the bit line 140. The bit line 140 is electrically connected to the bit line contact 130. In some embodiments, the bit line 140 is formed of a conductive material, such as a metal.
[0040] Figure 9 The resulting memory device is also illustrated. The memory device includes a substrate 100, an isolation structure 105, a word line structure 110, bit line contacts 130, a cover layer 120, and bit lines 140. The substrate 100 includes an upwardly projecting active region AA (e.g., facing the bit line 140). The isolation structure 105 is located in the substrate 100 and adjacent to the active region AA of the substrate 100. The isolation structure 105 and the active region AA of the substrate 100 are arranged alternately in a specific direction, such as... Figure 9The word line structure 110 is located between the active area AA of the substrate 100 and the isolation structure 105. The bit line contact 130 is located above the active area AA of the substrate 100, and the top surface of the active area AA of the substrate 100 is convex toward the bit line contact 130. The cap layer 120 is located above the word line structure 110 and the isolation structure 105, and adjacent to the bit line contact 130. The bit line 140 is located above the bit line contact 130 and the cap layer 120.
[0041] Each word line structure 110 includes a word line layer 112 and a gate dielectric layer 114. The gate dielectric layer 114 is along the sidewall and the bottom of the word line layer 112, and extends along the sidewall of the active area AA of the substrate 100. The top end of the gate dielectric layer 114 along the sidewall of the active area AA of the substrate 100 is lower than the top surface of the active area AA of the substrate 100.
[0042] In the present disclosure, the top surface of the active area AA of the substrate 100 is convex toward the bit line contact 130. The convex top surface of the active area AA of the substrate 100 can provide advantages to the present disclosure. Specifically, when the interface is curved, the interface between the bit line contact 130 and the active area AA is larger. Therefore, the resistance between the bit line contact 130 and the active area AA is reduced. In addition, the convex top surface of the active area AA of the substrate 100 avoids the formation of a sharp tip of the active area AA. If the sharp tip contacts other components due to misalignment between the sharp tip and the other components (e.g., a capacitor contact), the sharp tip of the active area AA of the substrate 100 can increase the possibility of current leakage.
[0043] While the present disclosure has been described in detail with respect to certain embodiments thereof, other embodiments are possible. Accordingly, the spirit and scope of the claims appended hereto should not be limited to the description of the embodiments contained herein.
[0044] As various modifications could be made in the constructions without departing from the scope or spirit of the disclosure, it is intended that all cover within the scope and spirit of the disclosure, as defined by the appended claims.
[0045]
Symbol Description
[0046] 100: substrate
[0047] 105: isolation structure
[0048] 110: word line structure
[0049] 112: word line layer
[0050] 112A, 112B: conductive layer
[0051] 114: gate dielectric layer
[0052] 120: cover layer
[0053] 130: bit line contact
[0054] 140: bit line
[0055] AA: active area
[0056] A-A': line
[0057] CA: capacitor
[0058] D: vertical distance
[0059] H: contact hole
[0060] HM: hard mask
[0061] MC: memory cell
[0062] R: recess
[0063] TR: transistor
Claims
1. A method for manufacturing a memory device, characterized in that, Include: An isolation structure is formed in the substrate to define an active region in the substrate; A word line structure is formed between the isolation structure and the active region, wherein the word line structure includes a word line layer and a gate dielectric layer extending along the sidewalls and bottom of the word line layer and along the sidewalls of the active region. A cover layer is formed that covers the character line structure, the isolation structure, and the active area; Contact holes are formed in the cover layer to expose the active region, wherein the top surface of the active region is raised; A bit line contact is formed in the contact hole; and A bit line that is electrically connected to the contact of the bit line.
2. The manufacturing method according to claim 1, characterized in that, The contact hole further exposes the gate dielectric layer along the sidewall of the active region.
3. The manufacturing method according to claim 1, characterized in that, The contact hole includes: A groove is formed in the capping layer to expose the top surface of the active region and the top of the gate dielectric layer conformally along the sidewall of the active region; The groove removes a portion of the gate dielectric layer that conformally runs along the sidewall of the active region; and After removing that portion of the gate dielectric layer, a portion of the active region is removed such that the top surface of the active region is higher than the top of the gate dielectric layer, which conformally runs along the sidewall of the active region.
4. The manufacturing method according to claim 3, characterized in that, The first etchant is used to remove the portion of the gate dielectric layer, and the second etchant is used to remove the portion of the active region, wherein the first etchant and the second etchant are different.
5. The manufacturing method according to claim 4, characterized in that, The first etchant is used to further remove a portion of the cover layer adjacent to the gate dielectric layer.
6. The manufacturing method according to claim 3, characterized in that, When removing this portion of the gate dielectric layer, the top corner of the active region is etched, causing the top surface of the active region to bulge.
7. The manufacturing method according to claim 3, characterized in that, The top surface of the active region is 3 nm to 10 nm higher than the top of the gate dielectric layer that conformally runs along the sidewall of the active region.
8. The manufacturing method according to claim 1, characterized in that, The width of the bottom opening of the contact hole is not less than the width of the top portion of the active area.
9. The manufacturing method according to claim 1, characterized in that, The bit line contact is conformally connected to the top of the gate dielectric layer along the sidewall of the active region.
10. The manufacturing method according to claim 1, characterized in that, The sidewall of the bit line contact protrudes towards the cover layer.
11. A memory device, characterized in that, Include: The substrate includes an upwardly protruding active region; An isolation structure is located in the substrate and adjacent to the active region of the substrate; The character line structure is located between the active region and the isolation structure of the substrate; The bit line contact is located above the active area of the substrate, wherein the top surface of the active area of the substrate protrudes toward the bit line contact; and The bit line is located above the bit line contact point.
12. The memory device according to claim 11, characterized in that, This character line structure includes: Character line layer; and A gate dielectric layer extends along the sidewalls and bottom of the word line layer and along the sidewalls of the active region of the substrate, wherein the top of the gate dielectric layer along the sidewall of the active region of the substrate is lower than the top surface of the active region of the substrate.
13. The memory device according to claim 12, characterized in that, The bit line contact is in contact with the top of the gate dielectric layer along the sidewall of the active region of the substrate.
14. The memory device according to claim 12, characterized in that, The top surface of the active region of the substrate is 3 nm to 10 nm higher than the top of the gate dielectric layer along the sidewall of the active region of the substrate.
15. The memory device according to claim 11, characterized in that, Further includes: The overlay layer is located above the character line structure and the isolation structure and is adjacent to the character line contact.
16. The memory device according to claim 15, characterized in that, The sidewall of the bit line contact protrudes towards the cover layer.
17. The memory device according to claim 15, characterized in that, The sidewalls of the covering layer are recessed toward the isolation structure.
18. The memory device according to claim 11, characterized in that, The bottom surface of the bit line contact is recessed towards the bit line.
19. The memory device according to claim 11, characterized in that, The width of the bottom of the bit line contact is not less than the width of the top portion of the active area of the substrate.
20. The memory device according to claim 11, characterized in that, The width of the bit line contact increases as it moves further away from the active region of the substrate.