Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate; first and second semiconductor patterns extending in a first horizontal direction on the substrate and spaced apart from each other, the first semiconductor pattern including a channel region, a source region, and a drain region, the channel region, the source region, and the drain region being arranged in the first horizontal direction, and the channel region is between the source region and the drain region; a first word line and a second word line extending in a second horizontal direction on the first semiconductor pattern and spaced apart from each other in a vertical direction; a bit line connected to a source region of the first semiconductor pattern; the bit lines extend in the vertical direction; and a cell capacitor connected to the drain region of the first semiconductor pattern.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0108497, filed on August 13, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some exemplary embodiments of the present invention relate to a semiconductor memory device, and more specifically, to a three-dimensional semiconductor memory device. Background Technology

[0004] In the semiconductor manufacturing industry, there is a desire to achieve miniaturization, versatility, and higher performance in electronic products utilizing high-capacity semiconductor memory devices. To this end, increased integration is desired to provide semiconductor memory devices with higher capacity. Three-dimensional semiconductor memory devices have been proposed that increase memory capacity by stacking multiple memory cells vertically on a substrate. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a three-dimensional semiconductor memory device including a spacer layer located between a bit line and a source region and containing a high concentration of impurities.

[0006] The inventive concept is not limited to the aspects described above, and those skilled in the art will clearly understand from the following description other aspects not described herein.

[0007] According to some exemplary embodiments of the present invention, a semiconductor memory device is provided, the semiconductor memory device comprising: a first substrate; a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern and the second semiconductor pattern extending over the first substrate in a first horizontal direction and spaced apart from each other in a second horizontal direction and a vertical direction, the second horizontal direction and the vertical direction intersecting the first horizontal direction, the first semiconductor pattern including a channel region, a source region and a drain region, the channel region, the source region and the drain region being arranged in the first horizontal direction, and the channel region being between the source region and the drain region; a first word line and a second word line, the first word line and the second word line extending over the first semiconductor pattern in the second horizontal direction and spaced apart from each other in the vertical direction; a bit line connected to the source region of the first semiconductor pattern and extending in the vertical direction; a cell capacitor connected to the drain region of the first semiconductor pattern; and a spacer layer located between the first semiconductor pattern and the bit line, the spacer layer comprising a high concentration of impurities.

[0008] According to some example embodiments of the inventive concepts, there is provided a semiconductor memory device including: a first substrate; first and second semiconductor patterns extending in a first horizontal direction above the first substrate and spaced apart from each other in a second horizontal direction and a vertical direction, the second and vertical directions intersecting the first horizontal direction, the first semiconductor pattern including a channel region, a source region, and a drain region, the channel region, the source region, and the drain region being arranged in the first horizontal direction, and the channel region being interposed between the source region and the drain region; first and second word lines extending in the second horizontal direction above the first semiconductor pattern and spaced apart from each other in the vertical direction; a bit line connected to the source region of the first semiconductor pattern and extending in the vertical direction; a cell capacitor connected to the drain region of the first semiconductor pattern; a spacer layer on a first sidewall of the bit line and partially covering the source region of the first semiconductor pattern; and an isolation insulating layer on a second sidewall of the bit line opposite the first sidewall. The source region of the first semiconductor pattern includes the same impurity as an impurity of the spacer layer.

[0009] According to some example embodiments of the inventive concepts, there is provided a semiconductor memory device including: a first stack structure including a memory cell region including a plurality of memory cells and a plurality of cell capacitors arranged in three dimensions; and a second stack structure on the first stack structure, the second stack structure including a peripheral circuit region at a position vertically overlapping the plurality of memory cells, and the second stack structure being electrically connected to the plurality of memory cells. The first stack structure includes: a first substrate; first and second semiconductor patterns extending in a first horizontal direction above the first substrate and spaced apart from each other in a second horizontal direction and a vertical direction, the second and vertical directions intersecting the first horizontal direction, the first semiconductor pattern including a channel region, a source region, and a drain region, the channel region, the source region, and the drain region being arranged in the first horizontal direction, and the channel region being interposed between the source region and the drain region; a word line surrounding the first semiconductor pattern and extending in the second horizontal direction; a bit line connected to the source region of the first semiconductor pattern and extending in the vertical direction; the plurality of cell capacitors each connected to the drain region of the first semiconductor pattern; a spacer layer on a sidewall of the bit line and partially covering the source region of the first semiconductor pattern. The source region of the first semiconductor pattern includes the same impurity as an impurity of the spacer layer. BRIEF DESCRIPTION OF DRAWINGS

[0010] The example embodiments will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0011] BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram schematically showing a semiconductor memory device according to some example embodiments;

[0013] Figure 2 is a circuit diagram showing Figure 1 a memory cell region of the semiconductor memory device 1 shown in

[0014] Figure 3 is a schematic perspective view showing a memory cell region of the semiconductor memory device according to some example embodiments;

[0015] Figure 4 is a cross-sectional view of the semiconductor memory device taken along a line A1-A1' of Figure 3

[0016] Figure 5 Figure 3 is a cross-sectional view of the semiconductor memory device taken along a line B1-B1' of

[0017] Figure 6 is an enlarged view of a region CX1 of Figure 4

[0018] Figure 7 is a layout diagram schematically showing a semiconductor memory device according to some example embodiments;

[0019] Figure 8 is a schematic perspective view showing a memory cell region of the semiconductor memory device according to some example embodiments;

[0020] Figure 9 is a cross-sectional view of the semiconductor memory device taken along a line A2-A2' of Figure 8

[0021] Figures 10 to 16 is a schematic view showing a method of manufacturing a semiconductor memory device according to some example embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, some example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals are assigned to like elements throughout the drawings, and repeated description thereof will be omitted.

[0023] Figure 1 is a block diagram schematically showing a semiconductor memory device 10 according to some example embodiments.

[0024] Referring to Figure 1 , the semiconductor memory device 10 can include a memory cell region MCA and a peripheral circuit region PCA located at a higher vertical level than the memory cell region MCA. ​​​​

[0025] In some example embodiments, the memory cell area MCA can include a memory cell area of a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA can include a core area or a peripheral circuit area of the DRAM device. For example, the peripheral circuit area PCA can include peripheral circuit transistors for sending signals and / or power to a memory cell array of the memory cell area MCA. In some example embodiments, the peripheral circuit transistors can constitute various circuits such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0026] In Figure 1 In some example embodiments, the memory cell area MCA can include a memory cell area of a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA can include a core area or a peripheral circuit area of the DRAM device. For example, the peripheral circuit area PCA can include peripheral circuit transistors for sending signals and / or power to a memory cell array of the memory cell area MCA. In some example embodiments, the peripheral circuit transistors can constitute various circuits such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0027] In some example embodiments, the peripheral circuit area PCA and the memory cell area MCA are formed on separate wafers, and then the peripheral circuit area PCA and the memory cell area MCA can be attached to each other using a bonding pad. In some example embodiments, the peripheral circuit area PCA can be formed on a peripheral circuit wafer first, and then the memory cell area MCA can be formed on the peripheral circuit area PCA.

[0028] Figure 2 is a circuit diagram showing Figure 1 The circuit diagram of the memory cell area MCA is shown.

[0029] Referring to Figure 2 The memory cell area MCA can include a plurality of sub-cell arrays SCA. The plurality of sub-cell arrays SCA can be arranged in a second horizontal direction Y.

[0030] In some example embodiments, the sub-cell array SCA can include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC. Each of the plurality of memory cells MC can include one cell transistor TR and one cell capacitor CAP connected to the one cell transistor TR. Each of the plurality of memory cells MC can have a one-transistor-one-capacitor (1T1C) structure.

[0031] In some example embodiments, a plurality of word lines WL can each extend in the second horizontal direction Y, and can be spaced apart from each other in the first horizontal direction X and the vertical direction Z. A plurality of bit lines BL can each extend in the vertical direction Z, and can be spaced apart from each other in the first horizontal direction X and the second horizontal direction Y. One cell transistor TR can be located between one word line WL and one bit line BL.

[0032] In some example embodiments, a gate of the cell transistor TR can be connected to the word line WL, and a source of the cell transistor TR can be connected to the bit line BL via the first contact DC. The cell transistor TR can be connected to the cell capacitor CAP via the second contact BC. A drain of the cell transistor TR can be connected to a first electrode of the cell capacitor CAP via the second contact BC, and a second electrode of the cell capacitor CAP can be connected to the plate electrode PP.

[0033] In some example embodiments, in one sub-cell array SCA, a plurality of cell transistors TR can be arranged at positions overlapping each other in the vertical direction Z. In one sub-cell array SCA, a plurality of cell capacitors CAP can be arranged at positions overlapping each other in the vertical direction Z. One cell transistor TR and one cell capacitor CAP can be arranged side by side at the same vertical level, and a plurality of memory cells MC each including one cell transistor TR and one cell capacitor CAP can be stacked in the vertical direction Z. The storage capacity of the sub-cell array SCA can vary according to the number of memory cells MC stacked in the vertical direction Z or the number of layers thereof (e.g., the number of cell capacitors CAP or the number of layers thereof).

[0034] Figure 3 is a schematic perspective view illustrating a memory cell region of a semiconductor memory device according to some example embodiments.

[0035] Figure 4 is a cross-sectional view of the semiconductor memory device taken along Figure 3 line A1-A1' of

[0036] Figure 5 is a cross-sectional view of the semiconductor memory device taken along Figure 3 line B1-B1' of

[0037] Figure 6 is an enlarged view of a region CX1 of Figure 4

[0038] Referring to Figures 3 to 6 , the semiconductor memory device 10 can include a first stack structure SS1 and a second stack structure SS2, which can be bonded to the first stack structure SS1 by a first bonding pad BP1 and a second bonding pad BP2.​

[0039] In some example embodiments, the first stack structure SS1 can include a first substrate 110, a plurality of semiconductor patterns 120 arranged on the first substrate 110, a plurality of bit lines BL, a plurality of word lines WL, and a cell capacitor CAP.

[0040] In some example embodiments, the first substrate 110 can include Si, Ge, or SiGe. In some example embodiments, the first substrate 110 can include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. However, example embodiments are not limited thereto.

[0041] In some example embodiments, the plurality of semiconductor patterns 120 can extend in a first horizontal direction X on the first substrate 110 and be spaced apart from each other in a vertical direction Z.

[0042] In some example embodiments, the plurality of semiconductor patterns 120 can include, for example, an undoped semiconductor material or a doped semiconductor material. In some example embodiments, the plurality of semiconductor patterns 120 can include polysilicon. In some example embodiments, the plurality of semiconductor patterns 120 can include an amorphous metal oxide, a polycrystalline metal oxide, or a combination of an amorphous metal oxide and a polycrystalline metal oxide, and can include, for example, at least one of an In-Ga-based oxide (IGO), an In-Zn-based oxide (IZO), and an In-Ga-Zn-based oxide (IGZO). In some example embodiments, the plurality of semiconductor patterns 120 can include a 2D material semiconductor. For example, the 2D material semiconductor can include MoS2, WSe2, graphene, a carbon nanotube, or a combination thereof. However, example embodiments are not limited thereto.

[0043] In some example embodiments, each of the plurality of semiconductor patterns 120 can have a linear or bar shape extending in the first horizontal direction X. In some example embodiments, each of the semiconductor patterns 120 can include a channel region 120A and a source region 120S and a drain region 120D arranged in the first horizontal direction X with the channel region 120A therebetween. The source region 120S can be connected to the bit line BL, and the drain region 120D can be connected to the cell capacitor CAP. An ohmic metal layer including a metal silicide or the like can be further formed between the source region 120S and the bit line BL and between the drain region 120D and the cell capacitor CAP. However, example embodiments are not limited thereto.

[0044] In some example embodiments, the plurality of bit lines BL can each extend in a vertical direction Z on the first substrate 110 and can be spaced apart from each other in a second horizontal direction Y. In this case, the bit lines BL can include a metal. For example, the bit lines BL can include a metal such as Ti, Ta, Mo, Ru, W, Co, Al, and Ni, a conductive metal nitride such as TiN, TaN, WN, RuTiN, TiSiN, WSiN, and TaSiN, a metal silicide such as TiSi, WSi, TaSi, CoSi, and NiSi, or a combination thereof, but example embodiments are not limited thereto.

[0045] In some example embodiments, the source region 120S and the drain region 120D of the semiconductor pattern 120 can be doped with a first impurity. The channel region 120A can be doped with a second impurity different from the first impurity. For example, the source region 120S and the drain region 120D can each be of a first conductivity type due to the first impurity, and the channel region 120A can be of a second conductivity type different from the first conductivity type due to the second impurity.

[0046] In some example embodiments, the first conductivity type can represent an n-type, and the second conductivity type can represent a p-type, but example embodiments are not limited thereto. For example, the first conductivity type can represent a p-type, and the second conductivity type can represent an n-type. When the first conductivity type represents an n-type, the first impurity can include phosphorus (P), arsenic (As), or antimony (Sb). Also, when the second conductivity type represents a p-type, the second impurity can include boron (B), aluminum (Al), gallium (Ga), or indium (In). For example, the source region 120S and the drain region 120D of the semiconductor pattern 120 can be doped with phosphorus (P). However, example embodiments are not limited thereto.

[0047] In some example embodiments, the spacer layer 141 can be located between the bit line BL and the semiconductor pattern 120. Specifically, the spacer layer 141 can be located between the bit line BL and the source region 120S. The spacer layer 141 can extend in the vertical direction Z on the sidewall BLS of the bit line BL. The spacer layer 141 can cover the sidewall BLS of the bit line BL and can partially cover the source region 120S. For example, the spacer layer 141 can cover a portion of the upper surface and a portion of the lower surface of the source region 120S. In some example embodiments, the spacer layer 141 can enclose one end of the source region 120S. The spacer layer 141 can at least partially surround the source region 120S. For example, the spacer layer 141 can cover a portion of the upper surface, a portion of the lower surface, and a portion of the sidewall of the source region 120S. That is, the source region 120S can pass through the spacer layer 141, and one end thereof can be connected to the bit line BL.

[0048] In some example embodiments, a pair of spacer layers 141 can be spaced apart from each other in the first horizontal direction X, and a bit line BL is interposed between the pair of spacer layers 141. Also, the plurality of spacer layers 141 can each extend in the vertical direction Z on the first substrate 110 and can be spaced apart from each other in the second horizontal direction Y.

[0049] In some example embodiments, the spacer layer 141 can include an insulating material including a high concentration of impurities. The impurities in the spacer layer 141 can be the same as the impurities in the source region 120S. For example, the spacer layer 141 can include a first impurity.

[0050] In some example embodiments, the spacer layer 141 can include a high concentration of phosphorus (P). For example, the spacer layer 141 can include a phosphosilicate glass (PSG). However, example embodiments are not limited thereto. When the spacer layer 141 includes the PSG, the source region 120S can be n-type as the first conductive type.

[0051] In some example embodiments, the spacer layer 141 can include a high concentration of boron (B). For example, the spacer layer 141 can include a borosilicate glass (BSG). However, example embodiments are not limited thereto. When the spacer layer 141 includes the BSG, the source region 120S can be p-type as the first conductive type.

[0052] In some example embodiments, the concentration of the impurities in the spacer layer 141 can be higher than the concentration of the impurities in the source region 120S. For example, a first concentration, which is the concentration of phosphorus (P) in the spacer layer 141, can be higher than a second concentration, which is the concentration of phosphorus (P) in the source region 120S. Also, a third concentration, which is the concentration of boron (B) in the spacer layer 141, can be higher than a fourth concentration, which is the concentration of boron (B) in the source region 120S. Since the concentration of the impurities in the spacer layer 141 is higher than the concentration of the impurities in the source region 120S, the impurities (e.g., phosphorus or boron) can diffuse from the spacer layer 141 to the source region 120S.

[0053] In some example embodiments, the semiconductor memory device 10 according to the inventive concept can include the spacer layer 141 including a high concentration of impurities, and the spacer layer 141 is adjacent to the source region 120S. Accordingly, the source region 120S can be doped with the impurities through the spacer layer 141. In the semiconductor memory device according to the comparative example, the source region is formed only by gas phase doping (GPD). Accordingly, the reliability of the semiconductor memory device is deteriorated due to loss of the impurities during a process (e.g., heat treatment). In the semiconductor memory device 10 according to the inventive concept, the impurities are continuously supplied to the source region 120S by the spacer layer 141 including a high concentration of impurities. Accordingly, the reliability of the semiconductor memory device 10 can be improved.

[0054] In addition, the source region 120S is doped with impurities by using the spacer layer 141, and the resistance of the bit line BL can be reduced by using the bit line BL including a metal.

[0055] In some example embodiments, the plurality of word lines WL each can extend in the second horizontal direction Y on the semiconductor pattern 120 and can be spaced apart from each other in the vertical direction Z. The plurality of word lines WL each can have a gate all around (GAA) structure that surrounds each of the plurality of semiconductor patterns 120 and extends in the second horizontal direction Y.

[0056] In some example embodiments, the plurality of word lines WL each can have a dual word line structure in which a pair of word lines are spaced apart from each other in the vertical direction Z and the semiconductor pattern 120 is interposed therebetween. In some example embodiments, the plurality of word lines WL each can have a single word line structure including only one word line WL disposed on the semiconductor pattern 120.

[0057] In some example embodiments, the plurality of word lines WL can include at least one of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). However, example embodiments are not limited thereto.

[0058] In some example embodiments, the gate insulating layer 130 can be located between the word line WL and the semiconductor pattern 120. The gate insulating layer 130 can include at least one selected from a group consisting of a ferroelectric material and a high-k dielectric material having a higher dielectric constant than silicon oxide. In some example embodiments, the gate insulating layer 130 includes at least one selected from a group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalum (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). However, example embodiments are not limited thereto.

[0059] In some example embodiments, the unit capacitor CAP can include the first electrodes EL1, the capacitor dielectric layer DL, and the second electrodes EL2. The first electrodes EL1 can each extend in the first horizontal direction X and can be spaced apart from each other in the vertical direction Z. The first electrodes EL1 can have inner spaces (not shown) extending in the first horizontal direction X, and the inner spaces thereof can be filled with the capacitor dielectric layer DL and the second electrodes EL2. For example, the first electrodes EL1 can have a cup shape rotated by 90 degrees.

[0060] In some example embodiments, the capacitor dielectric layer DL can include at least one selected from a group consisting of a ferroelectric material and a high-k dielectric material having a higher dielectric constant than silicon oxide. In some example embodiments, the capacitor dielectric layer DL includes at least one selected from a group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalum (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). However, example embodiments are not limited thereto.

[0061] In some example embodiments, the second electrodes EL2 can fill the inner spaces of the first electrodes EL1, and the capacitor dielectric layer DL can be located between the second electrodes EL2 and the inner spaces of the first electrodes EL1.

[0062] In some example embodiments, the first electrodes EL1 and the second electrodes EL2 can include a doped semiconductor material, a conductive metal nitride such as titanium nitride, tantalum nitride, niobium nitride, and tungsten nitride, a metal such as ruthenium, iridium, titanium, and tantalum, and a conductive metal oxide such as iridium oxide and niobium oxide. However, example embodiments are not limited thereto.

[0063] In some example embodiments, the plate electrode PP can extend in the vertical direction Z and the second horizontal direction Y on one side of the unit capacitor CAP. The second electrodes EL2 of the unit capacitor CAP can be electrically connected to the plate electrode PP. For example, a plurality of second electrodes EL2 spaced apart from each other in the vertical direction Z and a plurality of second electrodes EL2 spaced apart from each other in the second horizontal direction Y can be commonly connected to the plate electrode PP.

[0064] In some example embodiments, the molded insulating layer 122 can be located between two adjacent semiconductor patterns 120 spaced apart from each other in the vertical direction Z, between two adjacent word lines WL spaced apart from each other in the vertical direction Z, and between two adjacent first electrodes EL1 spaced apart from each other in the vertical direction Z. In addition, the molded insulating layer 122 can also be located between two bit lines BL spaced apart from each other in the second horizontal direction Y. In addition, the molded insulating layer 122 can also be located between two spacer layers 141 spaced apart from each other in the second horizontal direction Y.

[0065] In some example embodiments, the molded insulating layer 122 can include silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, or a combination thereof. However, example embodiments are not limited thereto. In some example embodiments, the molded insulating layer 122 can include a plurality of insulating layers. Here, the insulating material layers formed between a plurality of bit lines BL, a plurality of spacer layers 141, a plurality of word lines WL, a plurality of semiconductor patterns 120, and a plurality of unit capacitors CAP can be collectively referred to as the molded insulating layer 122, according to a manufacturing process used to form the three-dimensional structure.

[0066] In some example embodiments, the first stack structure SS1 can include an upper wiring structure 150. The upper wiring structure 150 can include a wiring layer 152, a through-portion 154, and an insulating layer 156. The upper wiring structure 150 can also include a contact 158 electrically connected to a bit line BL, a word line WL, and a plate electrode PP. In addition, a first bonding pad BP1 can be formed on the upper wiring structure 150 and can be located on the same plane as an uppermost surface of the insulating layer 156.

[0067] In some example embodiments, the second stack structure SS2 can include a second substrate 310, peripheral circuit transistors 320 disposed on the second substrate 310, a front wiring structure 330 covering the peripheral circuit transistors 320 on an upper surface of the second substrate 310, and a rear wiring structure 340 disposed on a bottom surface of the second substrate 310. The front wiring structure 330 can include a wiring layer 332, a through-portion 334, and an insulating layer 336, and the rear wiring structure 340 can include a wiring layer 342, a through-portion 344, and an insulating layer 346.

[0068] In some example embodiments, the back wiring structure 340 can include a second bonding pad BP2 located on the same plane as a bottom surface of the insulating layer 346, and as the first bonding pad BP1 and the second bonding pad BP2 are connected to each other, the first stack structure SS1 and the second stack structure SS2 can be bonded to each other. In some example embodiments, the first stack structure SS1 and the second stack structure SS2 can be attached to each other by a copper oxide hybrid bonding method. In some example embodiments, the first bonding pad BP1 and the second bonding pad BP2 can include copper or a copper alloy. An interface between the insulating layer 156 of the upper wiring structure 150 and the insulating layer 346 of the back wiring structure 340 can extend in a flat shape, and the interface can be located on the same plane as an interface between the first bonding pad BP1 and the second bonding pad BP2.

[0069] In some example embodiments, the peripheral circuit transistor 320 can include a gate electrode 322 and a gate insulating layer 324 disposed on an active region of the second substrate 310. In some example embodiments, the peripheral circuit transistor 320 can include a sense amplifier, and the sense amplifier can be electrically connected to a bit line BL of the first stack structure SS1. In addition, the peripheral circuit transistor 320 can include a sub word line driver, and the sub word line driver can be electrically connected to a word line WL of the first stack structure SS1.

[0070] In some example embodiments, the second stack structure SS2 can further include a through-connection 350 passing through the second substrate 310. A wiring layer 332 in the front wiring structure 330 can be electrically connected to a wiring layer 342 in the back wiring structure 340 through the through-connection 350. In addition, the wiring layer 342 in the back wiring structure 340 can be electrically connected to a wiring layer 152 in the upper wiring structure 150 via the second bonding pad BP2 and the first bonding pad BP1.

[0071] Figure 7 is a layout diagram schematically illustrating a semiconductor memory device according to some example embodiments.

[0072] Referring to Figure 7 and Figure 5 together, a word line WL can extend in a second horizontal direction Y to cross a first horizontal direction X, i.e., a direction in which the semiconductor pattern 120 extends. A word line pad WLP can be located at an end of the word line WL. As shown in Figure 7 , a plurality of word line pads WLP can be sequentially arranged in the second horizontal direction Y. In addition, as shown in Figure 5 , a plurality of word line pads WLP can be arranged in a stepped shape in the second horizontal direction Y.

[0073] In some example embodiments, a word line pad WLP1 connected to a word line WL located at the top, a second word line pad WLP2 connected to a word line WL located below the top word line WL, and a third word line pad WLP3 connected to a word line WL located below both of the top two word lines WL can be arranged in this order in the second horizontal direction Y. In this way, a word line pad WLPn connected to an nth word line WL from the top can be arranged in the second horizontal direction Y.

[0074] A word line contact WCT can be disposed on an upper surface of each of the word line pads WLP, and the word line WL can be electrically connected to the upper wiring structure 150 via the word line contact WCT.

[0075] Figure 8 FIG. 1 is a schematic perspective view illustrating a memory cell region of a semiconductor memory device 20 according to some example embodiments.

[0076] Figure 9 FIG. 2 is a cross-sectional view of the semiconductor memory device 20 taken along a line A2-A2' of FIG. 1. Figure 8

[0077] In describing the semiconductor memory device 20 of Figure 8 and Figure 9 , the same reference numerals as those described with reference to the semiconductor memory device 10 basically represent the same components, and a repeated description thereof is omitted. Figures 1 to 7

[0078] Referring to Figure 8 and Figure 9 , a plurality of bit lines BL can each extend in the vertical direction Z over the first substrate 110 and can be spaced apart from each other in the second horizontal direction Y. In this case, the bit lines BL can include a metal.

[0079] In some example embodiments, an isolation insulating layer 243 can pass through the bit lines BL in the vertical direction Z. The bit lines BL can include a first bit line BL1 and a second bit line BL2 spaced apart from each other with the isolation insulating layer 243 interposed therebetween. The isolation insulating layer 243 can electrically isolate the first bit line BL1 from the second bit line BL2. Here, the isolation insulating layer 243 can include silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, or a combination thereof. However, example embodiments are not limited thereto.

[0080] ​​In some example embodiments, each of the bit lines BL can include a first sidewall BLS1 and a second sidewall BLS2 opposite to the first sidewall BLS1 in the first horizontal direction X. The spacer layer 141 can extend in the vertical direction Z on the first sidewall BLS1 of the bit line BL. The isolation insulating layer 243 can extend in the vertical direction Z on the second sidewall BLS2 of the bit line BL. The isolation insulating layer 243 can be spaced apart from the spacer layer 141 in the first horizontal direction X, and the bit line BL is interposed between the isolation insulating layer 243 and the spacer layer 141.

[0081] In some example embodiments, the spacer layer 141 can be located between the bit line BL and the semiconductor pattern 120. Specifically, the spacer layer 141 can be located between the bit line BL and the source region 120S. The spacer layer 141 can cover the first sidewall BLS1 of the bit line BL, and can partially cover the source region 120S. For example, the spacer layer 141 can cover a portion of the upper surface and a portion of the lower surface of the source region 120S. In some example embodiments, the spacer layer 141 can enclose one end of the source region 120S. The spacer layer 141 can at least partially surround the source region 120S. For example, the spacer layer 141 can cover a portion of the upper surface, a portion of the lower surface, and a portion of the sidewall of the source region 120S. That is, the source region 120S can pass through the spacer layer 141, and one end thereof can be connected to the bit line BL.

[0082] In some example embodiments, the source region 120S and the drain region 120D of the semiconductor pattern 120 can be doped with a first impurity. The channel region 120A can be doped with a second impurity different from the first impurity. For example, the source region 120S and the drain region 120D can each be of a first conductivity type due to the first impurity, and the channel region 120A can be of a second conductivity type different from the first conductivity type due to the second impurity.

[0083] In some example embodiments, the first conductivity type can represent an n-type and the second conductivity type can represent a p-type, but example embodiments are not limited thereto. For example, the first conductivity type can represent a p-type and the second conductivity type can represent an n-type. When the first conductivity type represents an n-type, the first impurity can include phosphorus (P), arsenic (As), or antimony (Sb). Also, when the second conductivity type represents a p-type, the second impurity can include boron (B), aluminum (Al), gallium (Ga), or indium (In). For example, the source region 120S and the drain region 120D of the semiconductor pattern 120 can be doped with phosphorus (P). However, example embodiments are not limited thereto.

[0084] In some example embodiments, the spacer layer 141 can include an insulating material including a high concentration of impurities. The impurities in the spacer layer 141 can be the same as the impurities in the source region 120S. For example, the spacer layer 141 can include the first impurity.

[0085] In some example embodiments, the spacer layer 141 can include a high concentration of phosphorus (P). For example, the spacer layer 141 can include PSG. When the spacer layer 141 includes PSG, the source region 120S can be n-type as the first conductivity type.

[0086] In some example embodiments, the spacer layer 141 can include a high concentration of boron (B). For example, the spacer layer 141 can include BSG. When the spacer layer 141 includes BSG, the source region 120S can be p-type as the first conductivity type.

[0087] In some example embodiments, the concentration of impurities in the spacer layer 141 can be higher than the concentration of impurities in the source region 120S. For example, a first concentration, which is the concentration of phosphorus (P) in the spacer layer 141, can be higher than a second concentration, which is the concentration of phosphorus (P) in the source region 120S. In addition, a third concentration, which is the concentration of boron (B) in the spacer layer 141, can be higher than a fourth concentration, which is the concentration of boron (B) in the source region 120S. Since the concentration of impurities in the spacer layer 141 is higher than the concentration of impurities in the source region 120S, the impurities (e.g., phosphorus or boron) can diffuse from the spacer layer 141 to the source region 120S.

[0088] In some example embodiments, the semiconductor memory device 20 according to the inventive concept can include the spacer layer 141 including a high concentration of impurities, and the spacer layer 141 is adjacent to the source region 120S. Accordingly, the source region 120S can be doped with the impurities through the spacer layer 141. In the semiconductor memory device according to the comparative example, the source region is formed only by using the GPD. Accordingly, the reliability of the semiconductor memory device is deteriorated due to the loss of impurities in the process (e.g., heat treatment). In the semiconductor memory device 20 according to some example embodiments of the inventive concept, the impurities are continuously supplied to the source region 120S by utilizing the spacer layer 141 including a high concentration of impurities. Accordingly, the reliability of the semiconductor memory device 20 can be improved.

[0089] In addition, the source region 120S is doped with the impurities by utilizing the spacer layer 141, and the resistance of the bit line BL can be reduced by utilizing the bit line BL including the metal.

[0090] Figures 10 to 16 FIG. 1 is a schematic diagram illustrating a semiconductor memory device according to some example embodiments.

[0091] Referring to Figure 10 The sacrificial mold layer SFL and the semiconductor layer 120L can be alternately and sequentially formed on the first substrate 110, thereby forming a mold stack MS.

[0092] In some example embodiments, the sacrificial mold layer SFL and the semiconductor layer 120L can include materials having etching selectivity with respect to each other. For example, the sacrificial mold layer SFL and the semiconductor layer 120L can each include a single-crystal layer of a Group IV semiconductor, a Group II-VI compound semiconductor, or a Group III-V compound semiconductor, and the sacrificial mold layer SFL and the semiconductor layer 120L can include different materials. In some example embodiments, the sacrificial mold layer SFL can include SiGe, and the semiconductor layer 120L can include single-crystal silicon. The sacrificial mold layer SFL and the semiconductor layer 120L can each have a thickness of several tens of nm.

[0093] In some example embodiments, the sacrificial mold layer SFL and the semiconductor layer 120L can be formed by an epitaxial process. For example, the epitaxial process can include a vapor phase epitaxy (VPE), a CVD process such as an ultra-high vacuum (UHV) chemical vapor deposition (CVD), a molecular beam epitaxy, or a combination thereof. During the epitaxial process, a liquid or gaseous precursor can be used as a precursor for forming the sacrificial mold layer SFL and the semiconductor layer 120L.

[0094] Referring to Figure 11 A mask pattern (not shown) can be formed on the mold stack MS, and the mold stack MS can be partially removed by using the mask pattern as an etching mask to form a first opening OP1. Next, a first insulating layer 410 can be formed inside the first opening OP1.

[0095] In some example embodiments, a plurality of semiconductor patterns 120 can be formed from the semiconductor layer 120L by forming the first opening OP1. Here, the plurality of semiconductor patterns 120 can be formed by patterning a portion of the semiconductor layer 120L.

[0096] Referring to Figure 12 The sacrificial mold layer SFL can be removed to form a second opening OP2 between the plurality of semiconductor patterns 120.

[0097] In some example embodiments, a mask pattern M10 can be formed on the mold stack MS, a portion of the sacrificial mold layer SFL not covered by the mask pattern M10 can be removed, and a portion of the sacrificial mold layer SFL located at a position vertically overlapping the mask pattern M10 can not be removed but remain. Here, the portion of the semiconductor pattern 120 covered by the sacrificial mold layer SFL is referred to as a residual pattern 120R. The mask pattern M10 can be disposed on a structure in which the residual pattern 120R and the sacrificial mold layer SFL are alternately stacked with each other.

[0098] In some example embodiments, the process of removing the sacrificial molding layer SFL can include a wet etching process or a retreat process. For example, the process of removing the sacrificial molding layer SFL can include an etching process that is selective between the sacrificial molding layer SFL and the semiconductor layer 120L. For example, in the wet etching process or the retreat process, the etching speed on the plurality of semiconductor patterns 120 can be relatively low, while the etching speed on the sacrificial molding layer SFL can be relatively high.

[0099] Referring to Figure 13 The gate insulating layer 130 and the word line WL can be sequentially formed on the upper surface, the side surface, and the bottom surface of each of the plurality of semiconductor patterns 120 inside the second opening OP2.

[0100] For example, the gate insulating layer 130 can conformally surround each of the plurality of semiconductor patterns 120, and the word line WL can surround each of the plurality of semiconductor patterns 120 and extend on the gate insulating layer 130 in the second horizontal direction Y.

[0101] In some example embodiments, the gate insulating layer 130 and the word line WL at both ends (e.g., both ends in the first horizontal direction X) of each of the plurality of semiconductor patterns 120 inside the second opening OP2 can be partially removed. In some example embodiments, a protective layer (not shown) covering both ends of the plurality of semiconductor patterns 120 inside the second opening OP2 can be formed first, the gate insulating layer 130 and the word line WL around a central portion of the plurality of semiconductor patterns 120 can be formed, and then the protective layer can be removed. Accordingly, both ends of the plurality of semiconductor patterns 120 can be exposed again without being covered by the gate insulating layer 130 and the word line WL.

[0102] Next, a spacer layer 141 can be formed to partially cover the semiconductor pattern 120. The spacer layer 141 can extend in the vertical direction Z while surrounding each end portion of the plurality of semiconductor patterns 120 spaced apart from each other in the vertical direction Z. For example, the spacer layer 141 can cover a portion of the upper surface and a portion of the lower surface of the semiconductor pattern 120. In some example embodiments, the spacer layer 141 can surround one end of the semiconductor pattern 120. The spacer layer 141 can at least partially encircle the semiconductor pattern 120. For example, the spacer layer 141 can cover a portion of the upper surface, a portion of the lower surface, and a portion of the sidewall of the semiconductor pattern 120. That is, the semiconductor pattern 120 can pass through the spacer layer 141.

[0103] Next, a source region 120S and a drain region 120D can be formed. The source region 120S and the drain region 120D can be formed at both ends of the semiconductor pattern 120 exposed by partially removing the gate insulating layer 130 and the word line WL, respectively.

[0104] In some example embodiments, the spacer layer 141 can include an insulating material including a high concentration of impurities. For example, the spacer layer 141 can include a first impurity.

[0105] In some example embodiments, the spacer layer 141 can include a high concentration of phosphorus (P). For example, the spacer layer 141 can include PSG. In some example embodiments, the spacer layer 141 can include a high concentration of boron (B). For example, the spacer layer 141 can include BSG.

[0106] Next, the first impurity can be diffused from the spacer layer 141 into the semiconductor pattern 120. Here, a process of diffusing the first impurity can include a heat treatment process. As the first impurity is diffused into the semiconductor pattern 120, a source region 120S can be formed in a portion of the semiconductor pattern 120 adjacent to the spacer layer 141. Here, the impurity in the spacer layer 141 can be the same as the impurity in the source region 120S.

[0107] For example, when the spacer layer 141 includes PSG, the source region 120S can be doped with phosphorus (P), and thus, the source region 120S can be n-type as a conductivity type. When the spacer layer 141 includes BSG, the source region 120S can be doped with boron (B), and thus, the source region 120S can be p-type as a conductivity type.

[0108] In some example embodiments, after diffusing the impurity into the source region 120S using the spacer layer 141, a gas phase doping process can be further performed.

[0109] In some example embodiments, the source region 120S and the drain region 120D can be formed by doping the impurity to both ends of the semiconductor pattern 120 through a gas phase doping. For example, when n-type impurities are doped to the source region 120S using PSG, the source region 120S and the drain region 120D can be additionally doped with n-type impurities through a gas phase process. For example, when p-type impurities are doped to the source region 120S using BSG, the source region 120S and the drain region 120D can be additionally doped with p-type impurities through a gas phase process. A process of doping the source region 120S through a gas phase process can be omitted.

[0110] In some example embodiments, the semiconductor memory device 10 according to the inventive concept each includes a spacer layer 141 including a high concentration of impurities, and the spacer layer 141 is adjacent to the source region 120S. Thus, the source region 120S can be doped with the impurities through the spacer layer 141. The impurities are continuously supplied to the source region 120S using the spacer layer 141 including a high concentration of impurities. Thus, the reliability of the semiconductor memory device 10 can be improved.

[0111] In addition, the source region 120S is doped with impurities by the spacer layer 141, and the resistance of the bit line BL can be reduced by using the bit line BL including metal.

[0112] Next, a molding insulating layer 122 can be formed to fill the inside of the second opening OP2. In some example embodiments, the molding insulating layer 122 can be located between two adjacent word lines WL in the vertical direction Z and between the end portions of two adjacent semiconductor patterns 120 in the vertical direction Z.

[0113] In some example embodiments, the word line WL can be removed to form a word line pad WLP (see Figure 5 ). The word line pad WLP can be arranged in a stepped shape. For example, the word line pad WLP connected to one word line WL can be spaced apart from another word line pad WLP connected to another word line WL below the one word line WL in the second horizontal direction Y.

[0114] Referring to Figure 14 , the first insulating layer 410 can be partially removed to form a bit line opening BLH, and a bit line BL can be formed inside the bit line opening BLH.

[0115] In some example embodiments, two semiconductor patterns 120 can be spaced apart from each other in the first horizontal direction X with a bit line BL interposed therebetween. One sidewall of one bit line BL can contact a source region 120S of one semiconductor pattern 120, and the other sidewall of the one bit line BL can contact a source region 120S of another semiconductor pattern 120. That is, two semiconductor patterns 120 arranged at the same vertical level in the vertical direction can be electrically connected to one bit line BL, but the inventive concept is not limited thereto. For example, an isolation insulating layer 243 (see Figure 9 ) can be formed to pass through the bit line BL in the vertical direction Z, and thus, a first bit line BL1 (see Figure 9 ) and a second bit line BL2 (see Figure 9 ) spaced apart from each other with the isolation insulating layer 243 interposed therebetween can be electrically separated from each other.

[0116] Referring to Figure 15 , the sacrificial molding layer SFL and the remaining pattern 120R can be removed, and a unit capacitor CAP can be formed at a position where the sacrificial molding layer SFL and the remaining pattern 120R have been removed.

[0117] In some example embodiments, the unit capacitor CAP can include a first electrode EL1, a capacitor dielectric layer DL, and a second electrode EL2. The first electrode EL1 can be electrically connected to the drain region 120D of the semiconductor pattern 120, and can have an inner space EL1H extending in the first horizontal direction X. The capacitor dielectric layer DL can be conformally disposed within the inner space EL1H, and the inner space EL1H can be filled with the second electrode EL2.

[0118] Next, a plate electrode PP can be formed, which is electrically connected to the second electrode EL2 and extends in the second horizontal direction Y.

[0119] Referring to Figure 16 The upper wiring structure 150 can be formed. The upper wiring structure 150 can include a wiring layer 152, a through-connection 154, an insulating layer 156, and a contact 158. For example, the contact 158 can be electrically connected to the bit line BL, the word line WL, and the plate electrode PP. Next, a first bonding pad BP1 can be formed on the upper wiring structure 150, and the first bonding pad BP1 can be located on the same plane as an uppermost surface of the insulating layer 156.

[0120] Referring back to Figure 4 and Figure 5 The second stack structure SS2 can be prepared.

[0121] In some example embodiments, the second stack structure SS2 can include a second substrate 310, peripheral circuit transistors 320 disposed on the second substrate 310, a front wiring structure 330 covering the peripheral circuit transistors 320 on an upper surface of the second substrate 310, and a back wiring structure 340 disposed on a bottom surface of the second substrate 310.

[0122] In some example embodiments, the peripheral circuit transistors 320 are formed on a first surface (or an upper surface) of the second substrate 310, the front wiring structure 330 is formed on the first surface of the second substrate 310, and a carrier substrate is attached to the front wiring structure 330. Next, a second surface (or a bottom surface) of the second substrate 310 can be ground to thin the second substrate 310. Next, the second stack structure SS2 can be completed by forming the back wiring structure 340 and a second bonding pad BP2 on the second surface of the second substrate 310.

[0123] Next, the second stack structure SS2 and the first stack structure SS1 can be bonded to each other. In this case, the first bonding pad BP1 of the first stack structure SS1 can be bonded to the second bonding pad BP2 of the second stack structure SS2, and an upper surface of the upper insulating layer 156 can be bonded to a bottom surface of the insulating layer 346.

[0124] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device comprising: a first substrate; a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern and the second semiconductor pattern extending in a first horizontal direction above the first substrate and spaced apart from each other in a second horizontal direction and a vertical direction, the second horizontal direction and the vertical direction crossing the first horizontal direction, the first semiconductor pattern including a channel region, a source region, and a drain region, the channel region, the source region, and the drain region being arranged in the first horizontal direction, and the channel region being interposed between the source region and the drain region; a first word line and a second word line, the first word line and the second word line extending in the second horizontal direction above the first semiconductor pattern and spaced apart from each other in the vertical direction; a bit line connected to the source region of the first semiconductor pattern, and the bit line extending in the vertical direction; a cell capacitor connected to the drain region of the first semiconductor pattern; and a spacer layer between the first semiconductor pattern and the bit line, and the spacer layer including a high concentration of impurities. The spacer layer is on a sidewall of the bit line and partially covers the source region of the first semiconductor pattern.

2. The semiconductor memory device according to claim 1, wherein, The source region of the first semiconductor pattern passes through the spacer layer and is connected to the bit line.

3. The semiconductor memory device according to claim 1, wherein, The source region of the first semiconductor pattern includes the same impurities as the impurities of the spacer layer.

4. The semiconductor memory device of claim 1, wherein, 5. The semiconductor memory device of claim 4, wherein: a concentration of the impurities in the spacer layer is a first concentration, a concentration of the impurities in the source region of the first semiconductor pattern is a second concentration, and the first concentration is higher than the second concentration. The impurities include phosphorus (P).

6. The semiconductor memory device of claim 1, wherein, The bit line includes a metal.

7. The semiconductor memory device of claim 1, wherein, 8. The semiconductor memory device of claim 6, further comprising: an isolation insulating layer passing through the bit line in the vertical direction. The first word line encloses the first semiconductor pattern and extends in the second horizontal direction.

9. The semiconductor memory device of claim 1, wherein, 10. The semiconductor memory device of claim 1, further comprising: a gate insulating layer between the first semiconductor pattern and the first word line, wherein the gate insulating layer conformally covers the channel region of the first semiconductor pattern.

11. A semiconductor memory device comprising: a first substrate; a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern and the second semiconductor pattern extending in a first horizontal direction above the first substrate and spaced apart from each other in a second horizontal direction and a vertical direction, the second horizontal direction and the vertical direction crossing the first horizontal direction, the first semiconductor pattern including a channel region, a source region, and a drain region, the channel region, the source region, and the drain region being arranged in the first horizontal direction, and the channel region being interposed between the source region and the drain region; ​ a first word line and a second word line, the first word line and the second word line extending in the second horizontal direction above the first semiconductor pattern and spaced apart from each other in the vertical direction; a bit line connected to a source region of the first semiconductor pattern and extending in the vertical direction; a cell capacitor connected to a drain region of the first semiconductor pattern; a spacer layer on a first sidewall of the bit line and partially covering the source region of the first semiconductor pattern; and a separation insulating layer on a second sidewall of the bit line opposite to the first sidewall, wherein the source region of the first semiconductor pattern includes the same impurity as that of the spacer layer.

12. The semiconductor memory device according to claim 11, wherein the spacer layer is on the first sidewall of the bit line and surrounds one end of the source region of the first semiconductor pattern, and the source region of the first semiconductor pattern passes through the spacer layer and is connected to the bit line.

13. The semiconductor memory device according to claim 11, wherein the spacer layer includes phosphorus silicate glass, and the source region of the first semiconductor pattern has n-type conductivity.

14. The semiconductor memory device according to claim 11, wherein the spacer layer includes borosilicate glass (BSG), and the source region of the first semiconductor pattern has p-type conductivity. the bit line includes metal.

15. The semiconductor memory device of claim 11, wherein, 16. A semiconductor memory device, comprising: a first stack structure including a memory cell region including a plurality of memory cells and a plurality of cell capacitors arranged in three dimensions; and a second stack structure on the first stack structure, the second stack structure including a peripheral circuit region at a position vertically overlapping the plurality of memory cells and electrically connected to the plurality of memory cells, wherein the first stack structure includes: a first substrate, a first semiconductor pattern and a second semiconductor pattern extending in a first horizontal direction above the first substrate and spaced apart from each other in a second horizontal direction and a vertical direction, the second horizontal direction and the vertical direction intersecting the first horizontal direction, the first semiconductor pattern including a channel region, a source region, and a drain region, the channel region, the source region, and the drain region being arranged in the first horizontal direction and the channel region being interposed between the source region and the drain region, a word line surrounding the first semiconductor pattern and extending in the second horizontal direction, a bit line connected to the source region of the first semiconductor pattern and extending in the vertical direction, the plurality of cell capacitors each connected to the drain region of the first semiconductor pattern, a spacer layer on a sidewall of the bit line and partially covering the source region of the first semiconductor pattern, and wherein the source region of the first semiconductor pattern includes the same impurity as that of the spacer layer. ​ 17. The semiconductor memory device according to claim 16, wherein the impurity in the spacer layer and the source region of the first semiconductor pattern includes phosphorus (P), and the source region of the first semiconductor pattern has n-type conductivity.

18. The semiconductor memory device according to claim 16, wherein the impurity in the spacer layer and the source region of the first semiconductor pattern includes boron (B), and the source region of the first semiconductor pattern has p-type conductivity.

19. The semiconductor memory device according to claim 16, wherein the concentration of the impurity in the spacer layer is a first concentration, the concentration of the impurity in the source region of the first semiconductor pattern is a second concentration, and the first concentration is higher than the second concentration.

20. The semiconductor memory device according to claim 16, further comprising: an isolation insulating layer that passes through the bit line in the vertical direction.

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