Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device may include preparing a substrate, adsorbing a Si-based growth inhibitor, and selectively forming a metal oxide layer. The substrate may include a growing region including TiN and a non-growing region including Si. The surfaces of the growth region and the non-growth region may be exposed. The Si-based growth inhibitor may be adsorbed on the exposed surface of the non-growth region by supplying the Si-based growth inhibitor to the substrate. A metal oxide layer may be selectively formed on the growth region relative to the non-growth region by supplying a metal precursor and an oxidizing reactant gas to the substrate. Selectively forming the metal oxide layer on the growth region may include forming a SiTiON layer between a surface of the growth region and the metal oxide layer.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application 10-2024-0107882, filed with the Korean Intellectual Property Office on August 12, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device including a capacitor. Background Technology

[0004] With the development of electronic technology, the miniaturization of semiconductor devices is rapidly advancing. Therefore, the area occupied by patterns in semiconductor devices can become extremely small, and the spacing between patterns can become extremely narrow. In particular, as the patterns of the lower electrode of capacitors in semiconductor memory devices become more intricate, semiconductor devices incorporating supports for the lower electrode patterns have been developed to limit and / or prevent the collapse of the lower electrode. For such semiconductor devices, methods for efficiently forming a dielectric layer on the lower electrode using simple processes may be required. Summary of the Invention

[0005] This invention provides a method for manufacturing semiconductor devices using a simple process.

[0006] The present invention provides a method for manufacturing a semiconductor device including a capacitor using a simple process and / or a semiconductor device manufactured using the method.

[0007] According to one embodiment of the present invention, a method for manufacturing a semiconductor device may include: preparing a substrate comprising a TiN-containing growth region and a Si-containing non-growth region, wherein the surfaces of the growth region and the non-growth region are exposed; adsorbing a Si-based growth inhibitor onto the surface of the non-growth region by supplying a Si-based growth inhibitor to the substrate; and selectively forming a metal oxide layer on the growth region relative to the non-growth region by supplying a metal precursor and an oxidation reactant gas to the substrate. Selectively forming the metal oxide layer on the growth region may include forming a SiTiON layer between the surface of the growth region and the metal oxide layer.

[0008] According to one embodiment of the present invention, a method of manufacturing a semiconductor device may include: providing a structure on a substrate in a reaction chamber, the structure including a plurality of lower electrodes and a plurality of supports between the plurality of lower electrodes, the plurality of lower electrodes comprising TiN, the plurality of supports supporting the plurality of lower electrodes, and the plurality of supports comprising SiO. xSiN x The reaction chamber contains SiON, SiCN, or SiOCN; Si-based growth inhibitors are supplied to the reaction chamber to provide the structure on the substrate with the Si-based growth inhibitors, which are adsorbed onto the surfaces of the plurality of supports. The Si-based growth inhibitors include SiPhCl3, Si(CH3)3(NMe2), (CH3)3SiN(CH3)2, SiMe3(NMe2), SiMe3OEt, or SiMe3OMe; Hydrogenation of the structure on the substrate is performed simultaneously with the adsorption of the Si-based growth inhibitors onto the structure by supplying hydrogen-containing gas to the reaction chamber; Selective formation of an interface layer, comprising a molybdenum oxide layer, is performed on the region of the plurality of lower electrodes not covered by the plurality of supports. The selective formation of the interface layer includes the sequential supply of a molybdenum precursor and an oxidation reactant gas to the reaction chamber while the structure on the substrate is located in the reaction chamber, and the selective formation of the interface layer includes the formation of a SiTiON layer between the plurality of lower electrodes and the molybdenum oxide layer; A dielectric layer is formed on the interface layer; and an upper electrode is formed on the dielectric layer. Attached Figure Description

[0009] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figures 1A to 1C It is a schematic cross-sectional view conceptually illustrating a method for manufacturing a semiconductor device according to some embodiments;

[0011] Figure 1D This is a schematic cross-sectional view conceptually illustrating one aspect of a method for manufacturing a semiconductor device according to some embodiments;

[0012] Figure 2 It is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some implementation schemes;

[0013] Figure 3 This is a graph comparing the adsorption selectivity of growth inhibitors according to some other implementation schemes;

[0014] Figure 4 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some other embodiments;

[0015] Figures 5A to 5C This is a conceptual diagram illustrating the surface state changes of non-growth regions due to hydrogenation during a method of manufacturing a semiconductor device according to some embodiments;

[0016] Figure 6This is a diagram illustrating the growth selectivity when using a method for manufacturing semiconductor devices according to some embodiments;

[0017] Figure 7 It is a cross-sectional view of a semiconductor device formed according to a method for manufacturing semiconductor devices according to some implementation schemes;

[0018] Figure 8 It is a cross-sectional view of a semiconductor device formed according to a method for manufacturing a semiconductor device according to some other embodiments; and

[0019] Figures 9 to 17 This is a sequential cross-sectional view illustrating a method for manufacturing a semiconductor device according to some implementation schemes. Detailed Implementation

[0020] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0021] Figures 1A to 1C It is a schematic cross-sectional view conceptually illustrating a method for manufacturing a semiconductor device according to some embodiments. Figure 1D This is a schematic cross-sectional view conceptually illustrating one aspect of a method for manufacturing a semiconductor device according to some implementation schemes.

[0022] Reference Figure 1A A substrate 1 is provided, comprising a growth region 10 in which the growth of a specific material layer is required and a non-growth region 12 in which the growth of a specific material layer is not required. A method for manufacturing a semiconductor device according to some embodiments involves growing a specific thin film by atomic layer deposition (ALD). ALD is a technique in which a chemical substance, referred to as a precursor (which is the raw material for the thin film), and a reactive substance that reacts with the precursor are alternately and sequentially supplied to a reaction space to grow an ultrathin film on the order of atomic layers with thicknesses on the order of angstroms on a substrate. ALD has the advantages of finely controlling the thickness of the grown film and the ability to uniformly apply high-quality films across the entire exposed surface. However, to form a film only in selected areas chosen from the entire exposed surface of the substrate using ALD, the following disadvantage exists: after growing the film on the entire exposed surface of the substrate by ALD, additional photolithography and etching processes must then be performed to remove the film formed in the unselected areas. Therefore, some implementations involve forming specific films only in specific regions using a region-selective deposition method or a region-selective atomic layer deposition (AS-ALD) method, wherein the AS-ALD method grows the film in the specific region in a bottom-up manner while using an ALD method.

[0023] Refer again Figure 1AThe growth region 10 of the substrate 1 is the area in which a specific film can be grown according to subsequent processes. There are no limitations on the geometry and material properties of the growth region 10, as long as a specific film can be grown therein according to subsequent processes. In some embodiments, the growth region 10 may include a conductive region, which may contain, for example, a metal or a metal nitride. In some embodiments, the growth region 10 may contain a transition metal or a transition metal nitride belonging to periods 4-7 and groups 3-12 of the periodic table. In some embodiments, the growth region 10 may contain a metal such as Cu, Al, or W. In some embodiments, the growth region 10 may contain a nitride such as TiN or Si3N4.

[0024] On the other hand, the non-growth region 12 adjacent to the growth region 10 is a region in which the growth of a specific film is not required in subsequent processes. There are no limitations on the geometry and material properties of the non-growth region 12 unless a specific film is grown therein according to subsequent processes. In some embodiments, the non-growth region 12 may include an insulating region. In some embodiments, the non-growth region 12 may contain SiO₂. x For example, SiO2. In some other embodiments, the non-growth region 12 may contain SiN. x SiON, SiCN, or SiOCN.

[0025] Reference Figure 1B Growth inhibitor 13 can be adsorbed onto the non-growth region 12 to passivate the exposed surface of the non-growth region 12. Relative to the surface of the growth region 10, growth inhibitor 13 can be selectively adsorbed onto the surface of the non-growth region 12. Growth inhibitor 13 can modify the surface of the non-growth region 12 to delay the adsorption of a specific precursor onto the non-growth region 12, wherein the specific precursor can be adsorbed onto the growth region 10 during subsequent atomic layer deposition. Alternatively, this selective passivation can be achieved using self-assembled monolayer (SAM) or small molecule inhibitor (SMI) precursor compounds. Compared to SAM, SMI precursor compounds have the advantages of rapid deposition from the vapor phase and ease of deposition in ALD or chemical vapor deposition (CVD) equipment.

[0026] Therefore, in some embodiments, growth inhibitor 13 can be adsorbed using an SMI precursor. In some embodiments, a Si-based growth inhibitor precursor can be used for growth inhibitor 13. In some embodiments, the Si-based growth inhibitor precursor may include, for example, SiPhCl3, Si(CH3)3(NMe2), (CH3)3SiN(CH3)2, SiMe3(NMe2), SiMe3OEt, or SiMe3OMe.

[0027] In some implementations, the Si-based growth inhibitor precursor may include SiA x By C z D m SiA x B y C z D m It may include one or more leaving groups from ligands A, B, C, and D, and one or more inert ligands. Leaving groups may include -Cl, -Br, -I, -OR, -N-R2, -OH, and -NH. 2、 -SH, etc. Inert ligands may include -R, cyclopentadienyl, phenyl, benzyl, benzoyl, etc. On the other hand, in some embodiments, the growth inhibitor precursor may include acetylacetone, alcohol, etc.

[0028] On the other hand, the adsorption process of the SMI precursor can be performed a sufficient number of cycles (e.g., M cycles, where M is a natural number greater than 1) to ensure that the growth inhibitor 13 is sufficiently adsorbed onto the surface of the non-growth region 12. Unadsorbed SMI precursor can be removed from the reaction space while a purge gas (e.g., argon) is supplied. Therefore, the supply and removal of the SMI precursor from the reaction space can be repeated multiple times to form the growth inhibitor 13 of the desired thickness.

[0029] Furthermore, after the growth inhibitor 13 is adsorbed onto the surface of the non-growth region 12, the growth inhibitor 13 or reactive groups on the surface of the non-growth region 12 can be hydrogenated. In some embodiments, hydrogenation can be performed before the growth inhibitor 13 is adsorbed onto it. In some embodiments, hydrogenation can be performed both before and after the growth inhibitor 13 is adsorbed onto it. The hydrogenation can be performed by supplying a reducing gas into the reaction space in which the substrate 1 is disposed. In some embodiments, the hydrogenation can be performed using H2 gas, CCP H2 plasma, ICPH2 plasma, remote H2 plasma, etc. Details of the hydrogenation process will be described later.

[0030] Reference Figure 1C A growth material layer, such as a metal oxide layer 14, can be grown on growth region 10. The growth of the metal oxide layer 14 can be delayed by growth inhibitor 13, thus allowing selective growth of the metal oxide layer 14 on growth region 10 relative to non-growth region 12. The metal oxide layer 14 can be formed by the ALD method, in which a metal precursor and an oxidation reactant gas are alternately and sequentially supplied to a reaction space where the substrate 1 is disposed. The steps of supplying the metal precursor and the supplying the oxidation reactant gas can be performed in multiple cycles (e.g., N cycles, where N is a natural number greater than 1).

[0031] The metal oxide layer 14 may include, but is not limited to, oxide layers of various metals, such as molybdenum oxide layer, niobium oxide layer, titanium oxide layer, tantalum oxide layer, vanadium oxide layer, manganese oxide layer or yttrium oxide layer.

[0032] In some embodiments, when the metal oxide layer 14 is a molybdenum oxide layer, the metal precursor may include a molybdenum precursor, and the molybdenum precursor may include a tetravalent, pentavalent, or hexavalent precursor. In some embodiments, the tetravalent molybdenum precursor may include MoA x B y C z D m (2≤x+y+z+m≤4, 0≤x, y, z, m≤4), MoA x B y C z D m E n (2≤x+y+z+m+n≤5, 0≤x, y, z, m, n≤5) or MoA x B y C z D m E n F i (2≤x+y+z+m+n+i≤6, 0≤x、y、z+m+n、i≤6), but not limited to this.

[0033] The oxidizing reaction gas may include, but is not limited to, O3, O2, O2 plasma, H2O, NO2, NO2 plasma, N2O, N2O plasma, dry air, or alcohol.

[0034] On the other hand, during the step of forming the metal oxide layer 14 on the growth region 10, trace amounts of Si components derived from the Si-based growth inhibitor may remain between the surface of the growth region 10 and the metal oxide layer 14 within the growth region 10. In some embodiments, when the growth inhibitor 13 is formed using a Si-based growth inhibitor precursor, the content of Si components remaining between the surface of the growth region 10 and the metal oxide layer 14 within the growth region 10 can be increased compared to when the growth inhibitor 13 is formed without using a Si-based growth inhibitor precursor. In some embodiments, when the growth region 10 contains TiN, a SiTiON layer can be formed between the surface of the growth region 10 and the metal oxide layer 14. For example, as... Figure 1D As shown, a SiTiON layer 15 can be formed between the surface of the growth region 10 and the metal oxide layer 14.

[0035] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some implementation schemes. (Refer to...) Figure 2 Together Figures 1A to 1C The following describes in detail a method for manufacturing a semiconductor device according to some implementation schemes.

[0036] A substrate 1, with the surfaces of the growth region 10 and the non-growth region 12 exposed, can be provided in a reaction space (not shown), such as a reaction chamber. As described above, the growth region 10 may comprise a metal or a metal nitride, and a specific material layer may be grown on the metal or metal nitride by a subsequent process. In this embodiment, the growth region 10 comprises TiN, but is not limited thereto. On the other hand, the non-growth region 12 may comprise an insulating region that does not require the growth of a specific material layer by a subsequent process. In this embodiment, the non-growth region 12 comprises SiO2, but is not limited thereto.

[0037] Next, the step of adsorbing growth inhibitors (S10) can be performed on substrate 1 in the reaction space. The adsorption of growth inhibitors can be performed by supplying a growth inhibitor precursor into the reaction space. An SMI precursor can be used as the growth inhibitor precursor. In this embodiment, the growth inhibitor precursor may include a Si-based growth inhibitor precursor, and SiPhCl3 (trichlorophenylsilane; TCPS) can be used as a Si-based growth inhibitor precursor, but is not limited thereto. TCPS has the chemical formula C6H5Cl3Si, and can be a compound having the chemical formula SiCl3. TCPS can selectively adsorb only on the surface of SiO2, which is the non-growth region 12, and can hardly adsorb on the surface of TiN, which is the growth region 10.

[0038] Next, a purging step (S20) can be performed, in which a purge gas (e.g., argon) can be supplied to the reaction space to remove any remaining unadsorbed TCPS. On the other hand, since the growth inhibitor 13 can be adsorbed on the surface of the non-growth region 12 of the substrate 1 in atomic layer units, the adsorption step (S10) and the purging step (S20) can be performed in multiple cycles (e.g., M cycles, where M is a natural number) so that the growth inhibitor 13 can be adsorbed on the surface of the non-growth region 12 with sufficient thickness.

[0039] Figure 3 The results show the measurement of contact angles (e.g., water contact angles (WCA)) on the surfaces of SiO2 and TiN after multiple cycles of the adsorption growth inhibitor step (S10) and the scavenging step (S20) using TCPS as an SMI precursor. (See reference...) Figure 3Without TCPS treatment (i.e., when the number of SMI cycles is zero), the water contact angle on the surface of SiO2 is approximately 44.5 degrees. However, the contact angle on the surface of SiO2 can increase with the number of SMI cycles. For example, when the number of SMI cycles exceeds approximately 100, the water contact angle can become greater than approximately 60 degrees. Generally, the larger the contact angle on the surface of any material, the lower the wettability, and therefore the surface can be hydrophobic. On the other hand, the smaller the contact angle, the higher the wettability, and therefore the surface can be hydrophilic.

[0040] On the other hand, it can be observed that the water contact angle on the TiN surface does not increase with the number of SMI cycles, but rather decreases slightly. Therefore, it can be seen that TCPS can selectively adsorb onto the SiO2 surface relative to the TiN surface. Furthermore, trace amounts of TCPS can adsorb onto the TiN surface, which serves as growth region 10. Therefore, trace amounts of Si components derived from Si-based growth inhibitors can remain on the TiN surface.

[0041] Refer again Figure 2 After repeating the steps of adsorbing growth inhibitors (S10) and removing growth inhibitors (S20) M times, a step of supplying a metal precursor to the reaction space is performed (S30). The metal precursor can be a raw material precursor for the metal oxide layer 14 to be grown on the growth region 10, and can include, for example, molybdenum precursors, niobium precursors, titanium precursors, tantalum precursors, vanadium precursors, manganese precursors, or yttrium precursors, but is not limited thereto. In this embodiment, a molybdenum precursor can be used, but is not limited thereto. The molybdenum precursor can include a tetravalent precursor, a pentavalent precursor, or a hexavalent precursor. In some embodiments, the tetravalent molybdenum precursor can include MoA x B y C z D m (2≤x+y+z+m≤4, 0≤x, y, z, m≤4), MoA x B y C z D m E n (2≤x+y+z+m+n≤5, 0≤x, y, z, m, n≤5) or MoA x B y C z D m E n F i (2≤x+y+z+m+n+i≤6, 0≤x、y、z+m+n、i≤6), but not limited to this.

[0042] The molybdenum precursor can be adsorbed on the growth region 10 of the substrate 1 at atomic layer units, and any unadsorbed residual molybdenum precursor can be removed with a purge gas (e.g., argon) (S40).

[0043] Next, the step of supplying reactants into the reaction space can be performed (S50). The reactants may include reactant gases, such as oxidizing reactant gases. Oxidizing reactant gases may include, but are not limited to, O3, O2, O2 plasma, H2O, NO2, NO2 plasma, N2O, N2O plasma, dry air, or alcohols. In this embodiment, O2 may be used as the oxidizing reactant gas.

[0044] Next, residual oxidant gases that have not reacted with the metal precursor can be removed (S60).

[0045] By sequentially performing the steps of supplying the metal precursor (S30), cleaning (S40), supplying the reactant (S50), and cleaning (S60), a metal oxide layer 14 (e.g., a molybdenum oxide layer) can be formed on the growth region 10 in atomic layer units, relative to the non-growth region 12. The steps of supplying the metal precursor (S30) and supplying the reactant (S50) can be performed alternately. In order to form a metal oxide layer 14 of the desired thickness on the growth region 10, the steps of supplying the metal precursor (S30), cleaning (S40), supplying the reactant (S50), and cleaning (S60) can be performed multiple times, for example, N cycles (N is a natural number).

[0046] In addition, such as Figure 2 As shown, the steps of adsorbing growth inhibitors (S10) and clearing (S20) can be repeated for M cycles as a sub-cycle. Then, the steps of supplying metal precursors (S30), clearing (S40), supplying reactants (S50), and clearing (S60) can be repeated for N cycles as another sub-cycle. Then, the M cycles and N cycles can be combined into P cycles as a super-cycle.

[0047] On the other hand, during the step of forming the metal oxide layer 14 on the growth region 10, trace amounts of Si components derived from the Si-based growth inhibitor precursor may remain on the surface of the growth region 10. In some embodiments, when the growth inhibitor 13 is formed using the Si-based growth inhibitor precursor, the content of Si components remaining between the surface of the growth region 10 and the metal oxide layer 14 in the growth region 10 can be increased compared to forming the growth inhibitor 13 without using the Si-based growth inhibitor precursor. In some embodiments, when the growth region 10 contains TiN, a SiTiON layer can be formed between the surface of the growth region 10 and the metal oxide layer 14.

[0048] Figure 4 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some other embodiments. Figure 4 The methods for manufacturing semiconductor devices can differ from those based on Figure 2 The method for manufacturing semiconductor devices differs in that, after the step of adsorbing growth inhibitors, a further hydrogenation treatment step can be performed on the adsorbed growth inhibitors and the surface reactor. In the following text, details regarding... Figure 2 The description is a repetitive description.

[0049] Reference Figure 4 Together Figures 1A to 1C After providing substrate 1 within the reaction space (not shown), TCPS (C6H5Cl3Si) can be used as a Si-based growth inhibitor precursor to selectively adsorb growth inhibitor 13 onto the non-growth region 12 containing SiO2 relative to the TiN-containing growth region 10. The SiO2 surface can have hydrophilic properties with -OH groups at the end. When TCPS adsorbs onto the SiO2 surface, the two Si-Cl bonds can break and bond to the SiO2 surface, and this chemical state allows Cl atoms to remain even after the reaction. At this time, because Cl atoms have a higher electronegativity than Si, Cl atoms can have a partially negative charge, which may result in a low water contact angle and can serve as adsorption sites where metal precursors, such as molybdenum precursors, subsequently supplied to the reaction space can be adsorbed. That is, the molybdenum precursor may adsorb onto the non-growth region 12, which may reduce the deposition selectivity of the metal oxide layer (e.g., the molybdenum oxide layer).

[0050] In some embodiments, to improve the deposition selectivity of the metal oxide layer, after the step of adsorbing growth inhibitors (S10), the adsorbed growth inhibitors 13 and the surface reactor may be further subjected to a hydrogenation treatment step (S22). As mentioned above... Figure 1B As shown, in some embodiments, hydrogenation can be performed before the adsorption of growth inhibitor 13. In some embodiments, hydrogenation can be performed both before and after the adsorption of growth inhibitor 13. Specifically, after the step of adsorbing the growth inhibitor (S10), unadsorbed residual Si-based growth inhibitor precursor in the reaction space can be removed with a purge gas (S20), and then hydrogenation can be performed while a reducing gas is supplied in the reaction space. In some embodiments, hydrogenation can be performed using H2 gas, CCP H2 plasma, ICP H2 plasma, remote H2 plasma, etc.

[0051] In some embodiments, the hydrogenation step (S22) can be performed by exposing the substrate 1, on which the growth inhibitor 13 is adsorbed, to approximately 1000 sccm of approximately 99.999% hydrogen (H2) at a pressure of approximately 10 Torr in a reaction space for approximately 10 minutes. Next, the scavenging step (S24) can be performed by supplying 1000 sccm of argon to the reaction space for approximately 1 minute. In some embodiments, the hydrogenation step (S22) can be performed at a temperature range of approximately 100°C to approximately 400°C. In some embodiments, the hydrogenation step (S22) can be performed at approximately 120°C, the same temperature as the deposition temperature of the metal oxide layer 14 to be formed in subsequent processes. The steps of adsorbing the growth inhibitor (S10) and performing the hydrogenation step (S22) can be performed alternately and sequentially, and can be performed M cycles. In this embodiment, the two steps are repeated 10 times.

[0052] After the step of adsorbing the growth inhibitor (S10), a hydrogenation treatment step (S22) is performed, in which hydrogen gas, as a reducing gas, reduces the -OH groups on the SiO2 surface on which TCPS has not been adsorbed to -H groups. The molybdenum precursor supplied in subsequent processes may not adsorb onto the -H groups. At this time, the Cl atoms remaining on the SiO2 surface after TCPS adsorption can also be removed. Therefore, -OH groups that can serve as adsorption sites (at which metal precursors (e.g., molybdenum precursors) can be adsorbed onto the SiO2 surface in subsequent processes) can be reduced to -H groups, and Cl atoms can be removed, so that almost no adsorption of the molybdenum precursor occurs on the SiO2 surface. As a result, the metal oxide layer 14 can be selectively grown on the growth region 10 relative to the non-growth region 12 where the growth inhibitor 13 has been adsorbed, thus significantly improving growth selectivity.

[0053] Figures 5A to 5C This is a conceptual diagram illustrating the surface state changes of a substrate due to hydrogenation during a method for manufacturing a semiconductor device according to some embodiments.

[0054] Reference Figures 5A to 5C , Figure 5A This demonstrates that the SiO2 surface possesses hydrophilic properties capped with -OH groups prior to the adsorption of growth inhibitors. Figure 5B The adsorption state of the growth inhibitor TCPS on the SiO2 surface is shown. TCPS is a SiCl3 compound containing a benzene ring, which can delay the adsorption of the molybdenum precursor on the SiO2 surface due to its own steric hindrance. On the other hand, the WCA value after TCPS adsorption was measured to be approximately 62.0 degrees. Figure 5CThe surface state after additional hydrogenation treatment of the SiO2 surface adsorbed with TCPS is shown. On the other hand, the WCA value after hydrogenation treatment was measured to be approximately 75.4 degrees. Additional hydrogenation can reduce the adsorption sites of molybdenum precursors on the SiO2 surface by replacing the -OH groups on the SiO2 surface with Si-H, thus limiting, delaying, or preventing the adsorption of molybdenum precursors on the SiO2 surface in subsequent processes. Furthermore, during hydrogenation treatment, residual Cl atoms that could serve as adsorption sites for molybdenum precursors in subsequent processes can also be removed, thereby reducing the adsorption sites and limiting, delaying, or preventing the adsorption of molybdenum precursors on the SiO2 surface in subsequent processes.

[0055] Refer again Figure 4 After repeating the steps of adsorbing the growth inhibitor (S10) and hydrogenation (S22) M times, the steps of supplying the metal precursor (S30) and cleaning (S40), and supplying the reactants (S50) and cleaning (S60) can be repeated N times. Furthermore, after performing M and N cycles respectively, by repeating a P cycle as a supercycle including the M and N cycles as sub-cycles multiple times, the metal oxide layer 14 can be selectively grown to the desired thickness on the growth region 10. On the other hand, as described above, in the step of forming the metal oxide layer 14 on the growth region 10, trace amounts of Si components derived from the Si-based growth inhibitor precursor may remain on the surface of the growth region 10. In some embodiments, compared to forming the growth inhibitor 13 without using the Si-based growth inhibitor precursor, when the growth inhibitor 13 is formed using the Si-based growth inhibitor precursor, the content of Si components remaining between the surface of the growth region 10 and the metal oxide layer 14 in the growth region 10 can be increased. In some implementations, when the growth region 10 contains TiN, a SiTiON layer can be formed between the growth region 10 and the metal oxide layer 14.

[0056] In the following text, refer to Figure 4 Various implementation schemes will be described, in which a molybdenum oxide layer 14 can be selectively grown on the TiN surface of the growth region 10 compared to the SiO2 surface of the non-growth region 12.

[0057] In some embodiments, as a first step, SiPhCl3, serving as a growth inhibitor precursor, is supplied to the reaction space for 1 second, the reaction proceeds for 300 seconds, and then purges for 300 seconds. This first step can be performed once or multiple times to selectively adsorb the growth inhibitor onto the SiO2 surface. Next, as a second step, for example, a Mo(NMeEt)4 molybdenum precursor can be supplied to the reaction space for 0.5 seconds and purged for 40 seconds. Next, as a third step, O2 can be supplied to the reaction space for 1 second and purged for 20 seconds. The second and third steps can be repeated 30 times to selectively grow a molybdenum oxide layer with a thickness of less than 10 angstroms on the TiN surface.

[0058] In some embodiments, as a first step, (CH3)3SiN(CH3)2, serving as a growth inhibitor precursor, is supplied to the reaction space for 0.2 seconds, reacted for 60 seconds, and then purged for 60 seconds. This first step can be performed once or multiple times to selectively adsorb the growth inhibitor onto the SiO2 surface. Next, as a second step, a Mo(NMeEt)4 molybdenum precursor is supplied to the reaction space for 0.5 seconds and purged for 40 seconds. Next, as a third step, O2 is supplied to the reaction space for 1 second and purged for 20 seconds. The second and third steps can be repeated 30 times to selectively grow a molybdenum oxide layer with a thickness of less than 10 angstroms on the TiN surface.

[0059] In some embodiments, as a first step, SiPhCl3, serving as a growth inhibitor precursor, is supplied to the reaction space for 1 second, reacted for 300 seconds, and then purged for 300 seconds. This first step can be performed once or multiple times to selectively adsorb the growth inhibitor onto the SiO2 surface. Next, as a second step, H2 gas is supplied to the reaction space for 600 seconds and purged for 60 seconds. Next, as a third step, Mo(NMeEt)4, a molybdenum precursor, is supplied to the reaction space for 0.5 seconds and purged for 40 seconds. Next, as a fourth step, O2 is supplied to the reaction space for 1 second and purged for 20 seconds. The third and fourth steps can be repeated 30 times to selectively grow a molybdenum oxide layer with a thickness of less than 10 angstroms on the TiN surface.

[0060] In some embodiments, as a first step, (CH3)3SiN(CH3)2, serving as a growth inhibitor precursor compound, is supplied to the reaction space for 0.2 seconds, reacted for 60 seconds, and then purged for 60 seconds. This first step can be performed once or multiple times to selectively adsorb the growth inhibitor onto the SiO2 surface. Next, as a second step, H2 gas is supplied to the reaction space for 600 seconds, and then purged for 60 seconds. Next, as a third step, Mo(NMeEt)4, a molybdenum precursor, is supplied to the reaction space for 0.5 seconds, and then purged for 40 seconds. Next, as a fourth step, O2 is supplied to the reaction space for 1 second, and then purged for 20 seconds. Steps three through four can be repeated 30 times to selectively grow a molybdenum oxide layer with a thickness of less than 10 angstroms on the TiN surface.

[0061] In some embodiments, as a first step, SiPhCl3, serving as a growth inhibitor precursor compound, is supplied to the reaction space for 1 second, reacted for 300 seconds, and then purged for 300 seconds. This first step can be performed once or multiple times to selectively adsorb the growth inhibitor onto the SiO2 surface. Next, as a second step, H2 gas is supplied to the reaction space for 600 seconds and purged for 60 seconds. Next, as a third step, Mo(NMeEt)4, a molybdenum precursor, is supplied to the reaction space for 1 second and purged for 40 seconds. Next, as a fourth step, O2 is supplied to the reaction space for 1 second and purged for 20 seconds. Steps three through four can be repeated 30 times to selectively grow a molybdenum oxide layer with a thickness of less than 10 angstroms on the TiN surface.

[0062] In some embodiments, as a first step, (CH3)3SiN(CH3)2, serving as a growth inhibitor precursor compound, is supplied to the reaction space for 1 second, reacted for 300 seconds, and then purged for 300 seconds. This first step can be performed once or multiple times to selectively adsorb the growth inhibitor onto the SiO2 surface. Next, as a second step, H2 gas is supplied to the reaction space for 600 seconds and purged for 60 seconds. Next, as a third step, Mo(NMeEt)4, a molybdenum precursor, is supplied to the reaction space for 1 second and purged for 40 seconds. Next, as a fourth step, O2 is supplied to the reaction space for 1 second and purged for 20 seconds. The third and fourth steps can be repeated 30 times to selectively grow a molybdenum oxide layer with a thickness of less than 10 angstroms on the TiN surface.

[0063] Figure 6 This is a graph showing the growth selectivity as a result of a method for manufacturing semiconductor devices according to some embodiments.

[0064] Reference Figure 6Atomic layer deposition was performed multiple times on substrates where the TiN and SiO2 surfaces were exposed, and it was shown that molybdenum oxide (MoO2) was selectively grown on the TiN surface relative to the SiO2 surface. x ) layer. In Figure 6 In the middle, the hollow square mark (□) indicates that it is based on Figure 2 The process involved 25, 50, 75, and 100 cycles of TCPS adsorption and removal on the SiO2 surface (where TCPS was used as a growth inhibitor), respectively, to determine the growth selectivity of the molybdenum oxide layer on the TiN surface relative to the SiO2 surface. Figure 6 In the diagram, a hollow circle (○) indicates that the shape is based on... Figure 4 The process involved 25, 50, 75, and 100 cycles of TCPS adsorption, removal, hydrogenation, and removal on the SiO2 surface, respectively, to determine the growth selectivity of the molybdenum oxide layer on the TiN surface relative to the SiO2 surface.

[0065] exist Figure 6 In the diagram, the horizontal axis represents the molybdenum oxide layer (MoO) grown on the TiN surface. x The thicknesses of the molybdenum oxide layers are 0.5 nm, 1.0 nm, 1.5 nm, and 2.0 nm, respectively, corresponding to the results of performing the aforementioned 25 cycles, 50 cycles, 75 cycles, and 100 cycles. For example, when based on... Figure 2 When performing 50 cycles of atomic layer deposition (ALD) on the process, the growth selectivity of molybdenum oxide layers on TiN surfaces was 61% compared to SiO2 surfaces, while when based on... Figure 4 When the atomic layer deposition process is performed for 50 cycles, the growth selectivity of the molybdenum oxide layer on the TiN surface is 96% compared with that on the SiO2 surface, showing a significant improvement of about 35% in growth selectivity.

[0066] Figure 7 This is a cross-sectional view of a semiconductor device 100 formed according to a method for manufacturing a semiconductor device according to some implementation schemes. Figure 7 This is a cross-sectional view of a metal-insulator-metal (MIM) capacitor structure for a dynamic random access memory (DRAM) device, which is used in a method for manufacturing semiconductor devices according to some implementation schemes.

[0067] Reference Figure 7The semiconductor device 100 may include a capacitor 100C formed on a substrate 110. The capacitor 100C may include a lower electrode 120, an upper electrode 130, and a dielectric layer 124 between the lower electrode 120 and the upper electrode 130. Additionally, the capacitor 100C may also include an interface layer 122 between the lower electrode 120 and the dielectric layer 124. The lower electrode 120 may be electrically connected to a conductive portion (not shown) within the substrate 110 via a contact plug 114 passing through an interlayer insulating layer 112.

[0068] Furthermore, as the integration density of the semiconductor device 100 increases, the aspect ratio of the pattern of the lower electrode 120 becomes very large, thus raising concerns about the possibility of the lower electrode 120 collapsing. Therefore, to prevent the lower electrode 120 from collapsing, a first support 118a and a second support 118b that can support the lower electrode 120 to each other can be formed.

[0069] On the other hand, an upper electrode 130 is formed on the sidewall and upper part of the lower electrode 120, with an interface layer 122 and a dielectric layer 124 between them. A silicon-containing intermediate layer 126 may be formed between the lower electrode 120 and the interface layer 122. In addition, an etch stop layer 116 may be formed around the lower electrode 120 near the lower part of the lower electrode 120.

[0070] Substrate 110 may contain materials suitable for semiconductor processes. For example, substrate 110 may include a semiconductor substrate, and the semiconductor substrate may include a silicon-containing material. The semiconductor substrate may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The semiconductor substrate may also include other semiconductor materials, such as germanium. The semiconductor substrate may also include group III / V semiconductor substrates, such as compound semiconductor substrates, such as GaAs. The semiconductor substrate may also include silicon-on-insulator (SOI) substrates.

[0071] exist Figure 7 In the diagram, the lower electrode 120 is shown as having a columnar shape, but the lower electrode 120 may include a cylindrical shape or a combination of cylindrical and columnar shapes. The bottom of the lower electrode 120 may be electrically connected to the contact plug 114 via an etch stop layer 116. The outer wall of the lower electrode 120 may be supported by a first support 118a and a second support 118b. The first support 118a and the second support 118b may include plate-like structures that extend horizontally to support adjacent lower electrodes 120. The support may include one or more supports. For example, the support may include a multilayer insulating support. Figure 7A two-tiered (two-layered) first support 118a and second support 118b are shown, with the first support 118a located at the lower portion and the second support 118b located at the upper portion. The first support 118a and second support 118b may be vertically spaced apart from each other to support the outer wall of the lower electrode 120. The first support 118a and second support 118b may contain the same material or different materials. The first support 118a and second support 118b may contain nitride-based materials. In some embodiments, the first support 118a and second support 118b may contain oxide-based materials. For example, the first support 118a and second support 118b may contain silicon nitride, silicon carbon nitride, or silicon boron nitride, but are not limited thereto.

[0072] The lower electrode 120 may comprise polycrystalline silicon or a metal-based material. Metal-based materials may include metals, metal nitrides, metal silicon nitrides, conductive metal oxides, metal silicides, noble metals, or combinations thereof. The lower electrode 120 may comprise at least one of the following: transition metals or transition metal nitrides, such as Ti, TiN, TiSiN, Ta, TaN, TiAlN, W, WN, Ru, RuO2, Ir, IrO2, Pt, Mo, or combinations thereof.

[0073] The upper electrode 130 may comprise polycrystalline silicon, silicon germanium, metal, metal nitride, metal silicon oxide, conductive metal oxide, metal silicide, noble metal, or combinations thereof. The upper electrode 130 may comprise at least one of the following: Ti, TiN, TiSiN, Ta, TaN, TiAlN, W, WN, Ru, RuO2, Ir, IrO2, Pt, Mo, or combinations thereof. For example, the upper electrode 130 may be formed by sequentially stacking TiN, SiGe, and WN.

[0074] The dielectric layer 124 may comprise a high-k material having a higher dielectric constant than silicon oxide. High-k materials may include, but are not limited to, HfO2, ZrO2, Al2O3, TiO2, Ta2O5, Nb2O5, or SrTiO3. In some embodiments, the dielectric layer 124 may comprise a composite layer comprising two or more high-k material layers.

[0075] In some embodiments, dielectric layer 124 may comprise a zirconium oxide-based material that exhibits good leakage current characteristics while sufficiently reducing the equivalent oxide thickness (EOT). In some embodiments, dielectric layer 124 may comprise hafnium oxide having a tetragonal crystalline phase. In some embodiments, dielectric layer 124 may comprise a ferroelectric material, an antiferroelectric material, or a combination thereof. In some embodiments, dielectric layer 124 may comprise HfZrO, Hf-rich HfZrO, Zr-rich HfZrO, or a combination thereof. In some embodiments, dielectric layer 124 may comprise a high-bandgap material with high bandgap energy to improve leakage current characteristics. High-bandgap materials may include aluminum oxide, silicon oxide, or beryllium oxide.

[0076] An interface layer 122 can be formed between the lower electrode 120 and the dielectric layer 124, thereby increasing the dielectric constant of the dielectric layer 124 and reducing the leakage current of the capacitor 100C. Furthermore, by introducing an interface layer 122 with a high work function, the dielectric relaxation (D / R) characteristics and leakage current characteristics of the capacitor can be improved. Additionally, when the interface layer 122 is in direct contact with the dielectric layer 124, it can generate a high dielectric constant due to a phase transition, thereby increasing the capacitance of the capacitor.

[0077] Interface layer 122 may contain an insulating material. Interface layer 122 may be a single material layer or a multilayer material layer comprising different material layers. The region between the lower electrode 120 and the first support 118a and the second support 118b may have an interface-free structure in which interface layer 122 is not disposed. Interface layer 122 may serve to increase the dielectric constant of dielectric layer 124. Dielectric layer 124 may have an increased dielectric constant due to interface layer 122. For example, when dielectric layer 124 is used alone, the dielectric constant of dielectric layer 124 is about 60, but when dielectric layer 124 is in contact with interface layer 122, the dielectric constant of dielectric layer 124 may be greater than 60. Interface layer 122 may serve as a polarization enhancement layer to enhance the polarization of dielectric layer 124, and the dielectric constant of dielectric layer 124 may be increased by enhanced polarization. Interface layer 122 may contain an insulating material, thus interface layer 122 may serve to reduce leakage current.

[0078] Interface layer 122 and dielectric layer 124 may comprise different materials from each other. Interface layer 122 may comprise a first high-k dielectric material, and dielectric layer 124 may comprise a second high-k dielectric material, wherein the first high-k dielectric material may be different from the second high-k dielectric material. Dielectric layer 124 may comprise a first metal, and interface layer 122 may comprise a second metal. The first metal may be different from the second metal. The first metal may comprise at least one selected from hafnium, zirconium, aluminum, and titanium. The second metal may comprise niobium (Nb), tantalum (Ta), titanium (Ti), yttrium (Y), vanadium (V), manganese (Mn), or molybdenum (Mo). Dielectric layer 124 may comprise a first metal oxide, and interface layer 122 may comprise a second metal oxide. In another embodiment, dielectric layer 124 may comprise a first metal oxide, and interface layer 122 may comprise a second metal oxynitride. Dielectric layer 124 may comprise hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or combinations thereof. Interface layer 122 may comprise a niobium-based material. Interface layer 122 may comprise niobium oxide (Nb₂O₅), niobium nitride (NbN), or niobium oxynitride (NbON). The niobium nitride (NbN) as interface layer 122 may be insulating, and insulating niobium nitrides may include nitrogen-rich niobium nitrides. In some embodiments, interface layer 122 may comprise a high-k material, such as tantalum oxide, titanium oxide, yttrium oxide, or molybdenum oxide.

[0079] Figure 8 This is a cross-sectional view of semiconductor device 100A formed according to a method for manufacturing semiconductor devices according to other embodiments. The difference is: Figure 7 The semiconductor device 100 may include a two-layer support structure in which a first support 118a is located at the lower layer and a second support 118b is located at the upper layer, but Figure 8 The semiconductor device 100A may include a single-layer support 118b located only in the upper layer. In the following text, references to... Figure 7 The description is a repetitive description.

[0080] Reference Figure 8 There is no lower level Figure 7 As shown in the first support 118a, the upper electrode 130 can extend vertically corresponding to the sidewall of the lower electrode 120. This embodiment can be adopted when the vertical height of the lower electrode 120 is relatively small.

[0081] Figures 9 to 17 These are cross-sectional views illustrating methods for manufacturing semiconductor devices according to some embodiments, shown in sequence. Specifically, Figures 9 to 17 It is used to explain the manufacturing process, such as Figure 7 A cross-sectional view of a method for a semiconductor device 100 including a MIM capacitor is shown.

[0082] Reference Figure 9 An interlayer insulating layer 112 can be formed on substrate 110. Substrate 110 may include a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (Si-Ge) substrate. The substrate may include specific circuit patterns, such as patterns for forming transistors. In some embodiments, multiple word lines and bit lines may be formed on and / or within substrate 110. In this case, interlayer insulating layer 112 may be formed to cover the word lines and bit lines. In a DRAM device, source / drain regions (not shown) may be formed on both sides of each word line, and contact plugs 114 passing through interlayer insulating layer 112 may be connected to one of the source / drain regions.

[0083] The interlayer insulating layer 112 may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. The contact plug 114 may comprise a semiconductor material, a metal, a metal nitride, a metal silicide, or a combination thereof. For example, the contact plug 114 may comprise polysilicon, tungsten, tungsten nitride, titanium nitride, titanium silicon nitride, titanium silicide, cobalt silicide, or a combination thereof. In some embodiments, the contact plug 114 may be formed by sequentially stacking a semiconductor material, a metal silicide, a metal nitride, and a metal.

[0084] An etch stop layer 116 can be formed on the interlayer insulating layer 112, and a mold structure ML can be formed on the etch stop layer 116. The etch stop layer 116 may contain silicon oxide, silicon nitride, silicon oxynitride, or silicon carbon nitride. The mold structure ML may be a stacked structure containing different insulating materials. For example, the mold structure ML can be formed on the etch stop layer 116 by sequentially stacking a first mold layer 117a, a first support forming material layer 118a', a second mold layer 117b, and a second support forming material layer 118b'. On the other hand, in manufacturing... Figure 8 When the semiconductor device 100A shown is used, the mold structure ML may include a mold layer and a support forming material layer (i.e., a second support forming material layer 118b') on the etch stop layer 116.

[0085] The first support forming material layer 118a' and the second support forming material layer 118b' may contain materials that are etch-selective relative to the first mold layer 117a and the second mold layer 117b. Additionally, the first support forming material layer 118a' and the second support forming material layer 118b' may contain materials that are etch-selective relative to the etch stop layer 116. The first support forming material layer 118a' and the second support forming material layer 118b' may contain silicon nitride-based materials. For example, the first mold layer 117a and the second mold layer 117b may contain silicon oxide, and the first support forming material layer 118a' and the second support forming material layer 118b' may contain silicon nitride (SiN). x In some embodiments, the first support forming material layer 118a' and the second support forming material layer 118b' may comprise silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or silicon boron nitride (SiBN). In some embodiments, the first support forming material layer 118a' and the second support forming material layer 118b' may comprise a laminate of silicon nitride and silicon carbon nitride, or a laminate of silicon nitride and silicon boron nitride. The first support forming material layer 118a' and the second support forming material layer 118b' may comprise the same material, but in some embodiments, the first support forming material layer 118a' and the second support forming material layer 118b' may comprise different materials.

[0086] Reference Figure 10 Multiple first openings 120H can be formed within the mold structure ML. The openings 120H can be formed using a mask (not shown) formed by photolithography. To form the first openings 120H, the mask can be used as an etching mask to sequentially etch the second support forming material layer 118b', the second mold layer 117b, the first support forming material layer 118a', and the first mold layer 117a. The etching process for forming the first openings 120H can be stopped at the etching stop layer 116. The etching process for forming the first openings 120H can be performed using a dry etching process, a wet etching process, or a combination thereof. The first openings 120H can be a location where a lower electrode can be formed in a subsequent process. Therefore, the first support forming material layer 118a' and the second support forming material layer 118b' can become the first support 118a and the second support 118b, respectively, supporting the lower electrode formed within the first openings 120H in a subsequent process.

[0087] Next, the etch stop layer 116 exposed at the bottom of the first opening 120H can be removed under separate etch conditions to expose the upper surface of the contact plug 114. Depending on the size of the horizontal width of the first opening 120H, the entire upper surface of the contact plug 114 can be exposed, or only a portion of the upper surface can be exposed.

[0088] Reference Figure 11 A lower electrode 120 can be formed within each of the first openings 120H. The lower electrode 120 can have a columnar shape. In some embodiments, the lower electrode 120 can have a cylindrical shape. In some embodiments, the lower electrode 120 can have a combination of columnar and cylindrical shapes. To form a lower electrode 120 with a columnar shape, a conductive metal can be deposited to fill the first openings 120H, followed by a planarization process. The lower electrode 120 can comprise polycrystalline silicon or a metal-based material. The metal-based material can include metals, metal nitrides, metal silicon nitrides, conductive metal oxides, metal silicides, noble metals, or combinations thereof. The lower electrode 120 can comprise at least one of the following: Ti, TiN, TiSiN, Ta, TaN, TiAlN, W, WN, Ru, RuO2, Ir, IrO2, Pt, Mo, or combinations thereof.

[0089] Reference Figure 12 A portion of the second support 118b can be etched to form the second opening 130H. A portion of the upper surface of the second mold layer 117b can be exposed through the second opening 130H. Additionally, the remainder of the second support 118b, except for the etched portion used to form the second opening 130H, can partially surround the outer wall of the lower electrode 120 and can restrict and / or prevent the lower electrode 120 from collapsing. One second support 118b can contact the outer walls of at least two adjacent lower electrodes 120.

[0090] Reference Figure 13 The second mold layer 117b exposed through the second opening 130H can be removed by an etching process (e.g., a wet etching process). The etching process for the second mold layer 117b can be performed using an etching solution that has etching selectivity relative to the second support 118b. In some embodiments, when the second mold layer 117b comprises silicon oxide, the second mold layer 117b can be removed by a wet etching process using, for example, hydrofluoric acid (HF). In this case, not only the second mold layer 117b directly exposed below the second opening 130H can be removed, but also the second mold layer 117b between adjacent lower electrodes 120 can be removed.

[0091] After removing the second mold layer 117b, the portion of the first support 118a exposed vertically below the second opening 130H can be etched and removed. Etching this portion of the first support 118a exposes the upper surface of the first mold layer 117a. Additionally, the remaining unetched portion of the first support 118a, together with the second support 118b, can partially surround the outer wall of the lower electrode 120, limiting and / or preventing the lower electrode 120 from collapsing. One first support 118a may also contact the outer walls of at least two adjacent lower electrodes 120.

[0092] Subsequently, the first mold layer 117a exposed beneath the first support 118a can be completely removed by an etching process (e.g., a wet etching process). The etching process for the first mold layer 117a can be performed using an etching solution that has etching selectivity relative to the first support 118a and the second support 118b. In some embodiments, when the first mold layer 117a comprises silicon oxide, the first mold layer 117a can be removed by a wet etching process using, for example, hydrofluoric acid. The etching process for the first mold layer 117a can continue until the etch stop layer 116 is exposed.

[0093] Meanwhile, the etch stop layer 116 can remain between adjacent lower electrodes 120. In some embodiments, the etch stop layer 116 can be removed by a separate etch process.

[0094] As a result, Figure 13 As shown, a structure including a plurality of lower electrodes 120 and a plurality of first supports 118a and second supports 118b supporting the lower electrodes 120 can be formed on the substrate 110. Figure 13 In the structure shown, including the lower electrode 120, portions of the surfaces of the lower electrode 120, the first support 118a and the second support 118b, and the etch stop layer 116 may be exposed. In some embodiments, the surface of the interlayer insulating layer 112 may be exposed when the etch stop layer 116 is removed.

[0095] Reference Figure 14 Provided within the reaction space Figure 13 Following the structure, a growth inhibitor precursor can be supplied to selectively adsorb the growth inhibitor 121 onto the exposed surfaces of the first support 118a and the second support 118b relative to the exposed surface of the lower electrode 120. The step of selectively adsorbing the growth inhibitor 121 can correspond to... Figure 2 and 4 The steps shown are the adsorption of growth inhibitors (S10) and the removal of growth inhibitors (S20).

[0096] As mentioned above Figures 1A to 1CAs described in points 2 and 4, the lower electrode 120 may correspond to the growth region 10, and the first support 118a and the second support 118b may correspond to the non-growth region 12. Additionally, the etch stop layer 116 may also correspond to the non-growth region 12. When the etch stop layer 116 is removed, the interlayer insulating layer 112 may also correspond to the non-growth region 12. The growth region may be a region in which an interface layer and a dielectric layer can be grown in the MIM capacitor structure according to subsequent processes. The non-growth region may include a region in which an interface layer and a dielectric layer are not grown according to subsequent processes.

[0097] The SMI precursor can be supplied within the reaction space to selectively adsorb the growth inhibitor 121 onto the exposed surfaces of the first support 118a and the second support 118b, as well as the exposed surface of the etch stop layer 116. In some embodiments, the growth inhibitor precursor may include a Si-based growth inhibitor precursor, such as SiPhCl3, but is not limited thereto.

[0098] In some embodiments, in addition to SiPhCl3, the Si-based growth inhibitor precursor may also include Si(CH3)3(NMe2), (CH3)3SiN(CH3)2, SiMe3(NMe2), SiMe3OEt, or SiMe3OMe. In some embodiments, the Si-based growth inhibitor precursor may include SiA x B y C z D m SiA x B y C z D m It may include one or more leaving groups from ligands A, B, C, and D, and one or more inert ligands. Leaving groups may include -Cl, -Br, -I, -OR, -N-R2, -OH, and -NH. 2、 -SH, etc. Inert ligands may include -R, cyclopentadienyl, phenyl, benzyl, benzoyl, etc. On the other hand, in some embodiments, the growth inhibitor precursor may include acetylacetone, alcohol, etc.

[0099] Si-based growth inhibitor precursors may hardly adsorb onto the exposed surface of the lower electrode 120, which serves as the growth region. However, trace amounts of the Si-based growth inhibitor precursors may adsorb onto the exposed surface of the lower electrode 120, thus leaving trace amounts of Si components. Next, a purge gas (e.g., argon) can be supplied to the reaction space to remove any unadsorbed Si-based growth inhibitor precursors remaining in the reaction space.

[0100] On the other hand, the adsorption of growth inhibitors and the removal of unadsorbed growth inhibitor precursors can be performed by atomic layer deposition. Therefore, growth inhibitor 121 can be adsorbed at atomic layer levels, and thus the supply of growth inhibitors and the removal of unadsorbed growth inhibitor precursors can be repeated multiple times, for example, M cycles. In some embodiments, after M cycles of supplying and removing growth inhibitor precursors, a metal precursor and reactants can be supplied to the reaction space to form a layer on the exposed surface of the lower electrode 120 where the unadsorbed growth inhibitor 121 has been deposited. Figure 15 Interface layer 122 in the middle.

[0101] On the other hand, such as Figure 4 As shown, after M cycles of supplying and removing the growth inhibitor precursor, the subsequently adsorbed growth inhibitor 121 or the structure on the first support 118a and the second support 118b adsorbed by the growth inhibitor 121 can be further hydrogenated.

[0102] As mentioned above Figure 1B and 4 As shown, in some embodiments, hydrogenation can be performed before the adsorption of growth inhibitor 121. In some embodiments, hydrogenation can be performed both before and after the adsorption of growth inhibitor 121. Additionally, after the step of adsorbing the growth inhibitor (S10), unadsorbed Si-based growth inhibitor precursors in the reaction space can be removed with a purge gas (e.g., argon). Hydrogenation can be performed simultaneously with the supply of reducing gas to the reaction space where the structure is located. In some embodiments, hydrogenation can be performed using H2 gas, CCP H2 plasma, ICP H2 plasma, remote H2 plasma, etc.

[0103] In some embodiments, the hydrogenation process can be performed by exposing the structure with growth inhibitor 121 to approximately 1000 sccm of approximately 99.999% hydrogen (H2) at a pressure of approximately 10 Torr in the reaction space for approximately 10 minutes. The reaction space can then be purged by supplying 1000 sccm of argon for approximately 1 minute. In some embodiments, the hydrogenation process can be performed at a temperature range of approximately 100°C to approximately 400°C. In some embodiments, the hydrogenation process can be performed at approximately 120°C, the same temperature as the deposition temperature of the interface layer to be formed in subsequent processes. The steps of adsorbing the growth inhibitor and the hydrogenation process can be performed alternately and sequentially, and can be repeated M cycles, for example, 10 times.

[0104] By performing a hydrogenation step after the adsorption of growth inhibitor, the -OH groups on the surfaces of the first support 118a, the second support 118b, and / or the etch stop layer 116 on which the Si-based growth inhibitor precursor has not been adsorbed can be reduced to -H groups by hydrogen gas, which is used as a reducing gas. The adsorption of the metal precursor supplied in subsequent processes can be restricted on the -H groups. Additionally, the hydrogenation step can also remove Cl atoms remaining on the surfaces of the first support 118a, the second support 118b, and / or the etch stop layer 116 after the adsorption of the Si-based growth inhibitor 121. Therefore, the -OH groups (which can serve as adsorption sites for the metal precursor adsorbed in subsequent processes to form the interface layer 122) can be reduced to -H groups, and Cl atoms can also be removed, so that almost no adsorption of the metal precursor occurs on the surfaces of the first support 118a, the second support 118b, and / or the etch stop layer 116, except for the exposed surface of the lower electrode 120. As a result, a relatively small amount of interface layer 122 can be formed on the surfaces of the first support 118a, the second support 118b, and / or the etch stop layer 116, compared to the exposed surface of the lower electrode 120.

[0105] On the other hand, the adsorption of growth inhibitors and the removal of growth inhibitor precursors, as well as the hydrogenation treatment and its removal, can be performed by atomic layer deposition. Therefore, growth inhibitor 121 can be adsorbed at atomic layer units, and thus the supply and hydrogenation treatment of growth inhibitors can be repeated multiple times, for example, M cycles.

[0106] Further reference Figure 15 An interface layer 122 can be formed on the exposed surface of the lower electrode 120 where the growth inhibitor 121 has not been adsorbed. The interface layer 122 may include a metal oxide layer. The interface layer 122 can be formed using atomic layer deposition. Figure 2 and 4 As shown, the steps of forming interface layer 122 may include a series of alternating and sequential steps of supplying a metal precursor, a scavenging step, a reactant supply step, and a scavenging step in the reaction space. When interface layer 122 is a metal oxide layer, the metal precursor may be a raw material precursor for the metal oxide layer to be grown on the lower electrode 120, and may include, for example, molybdenum precursor, niobium precursor, titanium precursor, tantalum precursor, vanadium precursor, manganese precursor, or yttrium precursor, but is not limited thereto. In this embodiment, a molybdenum precursor may be used, but is not limited thereto. The molybdenum precursor may include a tetravalent precursor, a pentavalent precursor, or a hexavalent precursor. In some embodiments, the tetravalent molybdenum precursor may include MoA x B y C z D m (2≤x+y+z+m≤4, 0≤x, y, z, m≤4), MoAx B y C z D m E n (2≤x+y+z+m+n≤5, 0≤x, y, z, m, n≤5) or MoA x B y C z D m E n F i (2≤x+y+z+m+n+i≤6, 0≤x、y、z+m+n、i≤6), but not limited to this.

[0107] The reactants supplied to the reaction space may include, for example, oxidizing reactant gases. Oxidizing reactant gases may include, but are not limited to, O3, O2, O2 plasma, H2O, NO2, NO2 plasma, N2O, N2O plasma, dry air, or alcohols.

[0108] To form an interface layer 122 of the desired thickness (e.g., a metal oxide layer) on the lower electrode 120, the supply and removal of the metal precursor, and the supply and removal of the reactants, can be performed multiple times, for example, N cycles. Alternatively, the steps of adsorbing growth inhibitors and hydrogenation treatment can be repeated M cycles as a sub-cycle, and then the steps of supplying the metal precursor and supplying the reactants can be repeated N cycles as another sub-cycle. Then, the M cycles and N cycles can be combined into P cycles as a super-cycle, thereby forming an interface layer 122 of the desired thickness on the lower electrode 120.

[0109] On the other hand, during the step of forming the interface layer 122 on the lower electrode 120, trace amounts of the Si-based growth inhibitor precursor can be adsorbed onto the surface of the lower electrode 120. Therefore, a Si-containing intermediate layer 126 containing trace amounts of Si derived from the Si-based growth inhibitor precursor can be formed. Furthermore, due to the Si-containing intermediate layer 126, the Si content on the surface of the lower electrode 120 can be increased compared to the case where Si-based growth inhibitor adsorption and hydrogenation are not performed. In some embodiments, when the lower electrode 120 is TiN, the Si-containing intermediate layer 126 may include a SiTiON layer. The Si composition of the Si-containing intermediate layer 126 can limit and / or prevent oxidation of the surface of the lower electrode 120, thereby minimizing the loss of the lower electrode 120.

[0110] Reference Figure 16 The growth inhibitor 121 remaining on the exposed surfaces of the first support 118a, the second support 118b, and the etch stop layer 116 can be removed or oxidized. For example, ozone (O3) can be supplied to the reaction space to oxidize the growth inhibitor 121, thereby eliminating leakage current factors in the capacitor.

[0111] Reference Figure 17 , can Figure 16 As a result, a dielectric layer 124 is formed. The dielectric layer 124 can be formed not only on the exposed surface of the interface layer 122, but also on the exposed surfaces of the first support 118a, the second support 118b, and the etch stop layer 116. The dielectric layer 124 and the lower electrode 120 do not need to be in direct contact with each other because of the interface layer 122. The outer wall of the lower electrode 120 can be surrounded by the interface layer 122, and the outer surface of the interface layer 122 can be surrounded by the dielectric layer 124.

[0112] The dielectric layer 124 may comprise a high-k material having a higher dielectric constant than silicon oxide. High-k materials may include, but are not limited to, HfO2, ZrO2, Al2O3, TiO2, Ta2O5, Nb2O5, or SrTiO3. In some embodiments, the dielectric layer 124 may comprise a composite layer comprising two or more of the aforementioned high-k material layers.

[0113] Next, refer to again Figure 7 An upper electrode 130 can be formed on the dielectric layer 124. Therefore, a semiconductor device 100 including a MIM capacitor can be obtained using the lower electrode 120, the interface layer 122, the dielectric layer 124, and the upper electrode 130. The upper electrode 130 can fill the space between adjacent lower electrodes 120 and extend to cover the upper portion of the lower electrodes 120. The upper electrode 130 can comprise polysilicon, silicon germanium, metal, metal nitride, metal silicon oxide, conductive metal oxide, metal silicide, noble metal, or combinations thereof. The upper electrode 130 can comprise at least one of the following: Ti, TiN, TiSiN, Ta, TaN, TiAlN, W, WN, Ru, RuO2, Ir, IrO2, Pt, Mo, or combinations thereof. In some embodiments, the upper electrode 130 can be formed by sequentially stacking TiN, SiGe, and WN.

[0114] Although the inventive concept has been specifically shown and described with reference to its embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A substrate is prepared, the substrate comprising a growth region containing TiN and a non-growth region containing Si, wherein the surface of the growth region is exposed and the surface of the non-growth region is exposed; By supplying the substrate with a Si-based growth inhibitor, the Si-based growth inhibitor is adsorbed onto the surface of the non-growth region; and By supplying the substrate with metal precursor and oxidation reactant gases, a metal oxide layer is selectively formed on the growth region relative to the non-growth region. Selectively forming a metal oxide layer on the growth region includes forming a SiTiON layer between the surface of the growth region and the metal oxide layer.

2. The method according to claim 1, further comprising: After the Si-based growth inhibitor is adsorbed onto the surface of the non-growth region, the substrate is hydrogenated while the growth inhibitor is adsorbed onto the surface of the non-growth region.

3. The method according to claim 1, wherein the non-growth region comprises SiO x SiN x SiON, SiCN, or SiOCN.

4. The method according to claim 1, wherein the Si-based growth inhibitor comprises SiPhCl3, Si(CH3)3(NMe2), (CH3)3SiN(CH3)2, SiMe3(NMe2), SiMe3OEt or SiMe3OMe.

5. The method according to claim 1, wherein The metal oxide layer includes a molybdenum oxide layer, a niobium oxide layer, a titanium oxide layer, a tantalum oxide layer, a vanadium oxide layer, a manganese oxide layer, or a yttrium oxide layer.

6. A method for manufacturing a semiconductor device, the method comprising: A structure comprising a plurality of lower electrodes and a plurality of supports is formed on a substrate, wherein the plurality of supports support the plurality of lower electrodes and are located between the plurality of lower electrodes on the substrate; Si-based growth inhibitors are selectively adsorbed onto the exposed surfaces of the plurality of supports relative to the exposed surfaces of the plurality of lower electrodes. While the Si-based growth inhibitor is selectively adsorbed onto the exposed surfaces of the plurality of supports, the structure is subjected to hydrogenation treatment. An interface layer is selectively formed on the regions of the plurality of lower electrodes that are not covered by the plurality of supports, the interface layer comprising a metal oxide layer; A dielectric layer is formed on the interface layer; as well as An upper electrode is formed on the dielectric layer.

7. The method of claim 6, wherein The selective adsorption of the Si-based growth inhibitor and the hydrogenation treatment of the structure are repeated.

8. The method of claim 6, wherein Forming the interface layer includes repeating the following steps multiple times: supplying a metal precursor to a reaction space in which the structure is disposed and supplying an oxidation reactant gas to the reaction space.

9. The method of claim 6, wherein The plurality of lower electrodes contain TiN, and During the formation of the interface layer, a SiTiON layer is formed between the lower electrode and the metal oxide layer.

10. The method of claim 6, wherein The metal oxide layer includes a molybdenum oxide layer, a niobium oxide layer, a titanium oxide layer, a tantalum oxide layer, a vanadium oxide layer, a manganese oxide layer, or a yttrium oxide layer.

11. The method according to claim 6, further comprising: After the interface layer is formed, the Si-based growth inhibitor adsorbed on the support is oxidized.

12. The method of claim 6, wherein each of the plurality of lower electrodes comprises a transition metal or a transition metal nitride.

13. The method of claim 6, wherein When the Si-based growth inhibitor is adsorbed onto the exposed surfaces of the plurality of supports, the Si-based growth inhibitor is also adsorbed onto the exposed surfaces of the substrate excluding the plurality of lower electrodes.

14. The method of claim 13, wherein The surfaces of the plurality of supports or the substrates on which the Si-based growth inhibitor is adsorbed contain SiO₂. x SiN x SiON, SiCN, or SiOCN.

15. The method of claim 6, wherein The Si-based growth inhibitors include SiPhCl3, Si(CH3)3(NMe2), (CH3)3SiN(CH3)2, SiMe3(NMe2), SiMe3OEt, or SiMe3OMe.

16. The method of claim 6, wherein The Si-based growth inhibitor includes SiA x B y C z D m ,in In SiA x B y C z D m In the equation, A, B, C, and D are ligands, x + y + z + m = 4, and 0 ≤ x, y, z, and m ≤ 4. SiA x B y C z D m It includes at least one leaving group from A, B, C and D and at least one inert ligand.

17. The method of claim 8, wherein The metal precursor includes a molybdenum precursor, and The molybdenum precursor includes MoA x B y C z D m Where 2≤x+y+z+m≤4, 0≤x, y, z and m≤4, The molybdenum precursor includes MoA x B y C z D m E n Where 2≤x+y+z+m+n≤5, 0≤x, y, z, m and n≤5, or The molybdenum precursor includes MoA x B y C z D m E n F i , where 2≤x+y+z+m+n+i≤6, 0≤x, y, z, m, n and i≤6.

18. The method of claim 8, wherein The oxidation reaction gases include O3, O2, O2 plasma, H2O, NO2, NO2 plasma, N2O, N2O plasma, dry air, or alcohol.

19. A method for manufacturing a semiconductor device, the method comprising: Provide structures on a substrate in the reaction chamber. The structure includes multiple lower electrodes and multiple supports between the multiple lower electrodes. The plurality of lower electrodes contain TiN. The plurality of supports support the plurality of lower electrodes, and the plurality of supports contain SiO2. x SiN x SiON, SiCN, or SiOCN; The Si-based growth inhibitor is supplied to the reaction chamber to provide the structure on the substrate, and the Si-based growth inhibitor is adsorbed onto the surface of the plurality of supports. The Si-based growth inhibitors include SiPhCl3, Si(CH3)3(NMe2), (CH3)3SiN(CH3)2, SiMe3(NMe2), SiMe3OEt, or SiMe3OMe; The structure is hydrogenated while the Si-based growth inhibitor is adsorbed onto the structure on the substrate by supplying hydrogen-containing gas into the reaction chamber. An interface layer is selectively formed on the regions of the plurality of lower electrodes that are not covered by the plurality of supports. The interface layer includes a molybdenum oxide layer. The selective formation of the interface layer includes the sequential supplying of molybdenum precursor and oxidation reactant gases into the reaction chamber while the structure on the substrate is located in the reaction chamber, and... The selectively formed interface layer includes forming a SiTiON layer between the plurality of lower electrodes and the molybdenum oxide layer; A dielectric layer is formed on the interface layer; and An upper electrode is formed on the dielectric layer.

20. The method of claim 19, further comprising: After selectively forming the interface layer, the Si-based growth inhibitor adsorbed on the plurality of supports is oxidized.

Images