Semiconductor structure, forming method, memory, operating method and memory system

Abstract

The invention provides a semiconductor structure, a semiconductor structure forming method, a memory, a memory operation method and a memory system, and relates to the technical field of semiconductors. The semiconductor structure comprises a storage unit array comprising a stacking structure and a connecting structure, the stacking structure comprises stacked conductive layers, the storage unit array comprises at least one storage block group, the storage block group comprises at least one storage block, the conductive layers, located on the same layer, of the storage blocks in the storage block group are connected, and the storage blocks in the storage block group are connected. The conductive layers, located on the same layer, of the storage blocks in the storage block group are connected with the same connecting structure. According to the semiconductor structure, the number of required connection structures is reduced, so that the chip area occupied by the connection structures is reduced, and the storage density increasing speed is increased.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor structures, and more particularly, to a semiconductor structure, a semiconductor structure forming method, a memory, a memory operating method and a storage system. BACKGROUND

[0002] With the development of semiconductor technology, the feature size of semiconductor devices is increasingly reduced, and the integration level is also increasingly high. The process and manufacturing technology of planar storage units become challenging and costly, and three-dimensional semiconductor structures emerge as the times require. Three-dimensional semiconductor structures stack storage units in a three-dimensional manner, which can multiply the integration level on a unit area of wafer and reduce the cost.

[0003] Three-dimensional semiconductor structures can include volatile memory, non-volatile memory, and the like. Flash memory is a widely used non-volatile memory that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. The threshold voltage of the storage unit in the flash memory can be changed to a desired level to perform read, program and erase operations. For NAND flash memory, the erase operation can be performed at the block level, and the program operation or read operation can be performed at the page level.

[0004] The above information disclosed in the background section is only for the purpose of enhancing the understanding of the background of the present disclosure, and therefore it can include information that does not constitute the prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide a semiconductor structure, a semiconductor structure forming method, a memory, a memory operating method and a storage system.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to an aspect of the present disclosure, a semiconductor structure is provided, comprising: a storage unit array, the storage unit array comprising a stack structure and a connection structure, the stack structure comprising stacked conductive layers, wherein: the storage unit array comprises at least one storage block group, the storage block group comprising at least one storage block, the conductive layers at the same layer of the storage blocks in the storage block group are connected, and the conductive layers at the same layer of the storage blocks in the storage block group are connected to the same connection structure.

[0008] According to an embodiment of the present disclosure, the memory cell array further comprises a first gate line slit structure at least partially penetrating the stack structure, wherein: the first gate line slit structure comprises a plurality of mutually isolated sub-gate line slit structures, a gate line slit partition region is formed between adjacent sub-gate line slit structures, and conductive layers at a same layer of memory blocks in the memory block group are connected through the gate line slit partition region.

[0009] According to an embodiment of the present disclosure, the number of memory blocks in the memory block group is related to the number of stacked conductive layers in the stack structure.

[0010] According to an embodiment of the present disclosure, the memory block group comprises at least two memory blocks.

[0011] According to an embodiment of the present disclosure, the stack structure comprises a first stack structure and a second stack structure, the first stack structure comprises the conductive layers and first dielectric layers stacked alternately, and the second stack structure comprises the second dielectric layers and the first dielectric layers stacked alternately; and the connection structure at least partially penetrates the second stack structure.

[0012] According to an embodiment of the present disclosure, the conductive layers and the first dielectric layers of the first stack structure are stacked along a first direction, and the second dielectric layers and the first dielectric layers of the second stack structure are stacked along the first direction; the connection structure comprises a first part and a second part connected to each other, the first part of the connection structure at least partially penetrates the second stack structure to the corresponding second dielectric layer along the first direction, and the second part of the connection structure extends along a second direction to be connected to the corresponding conductive layer in the first stack structure, the first direction being perpendicular to the second direction.

[0013] According to an embodiment of the present disclosure, the memory cell array further comprises an array common source, and the array common sources of different memory blocks in the memory block group are mutually isolated.

[0014] According to an embodiment of the present disclosure, there is a slit between the array common sources of adjacent memory blocks in the memory block group to isolate the array common sources of adjacent memory blocks.

[0015] According to an embodiment of the present disclosure, the semiconductor structure further comprises a peripheral circuit, and the peripheral circuit comprises an array common source control circuit configured to distinguishably control voltages applied to the array common sources of different memory blocks.

[0016] According to an embodiment of the present disclosure, the memory cell array comprises a plurality of memory block groups; and the memory cell array further comprises a second gate line slit structure at least partially penetrating the stack structure to separate adjacent memory block groups in the plurality of memory block groups.

[0017] According to yet another aspect of the present disclosure, a memory operation method is provided. The memory includes at least one memory block group, the memory block group includes at least two memory blocks, conductive layers of the at least two memory blocks at a same layer are connected, array common sources of the at least two memory blocks are isolated from each other, the at least two memory blocks include an operating memory block and a non-operating memory block; the method includes: providing a first voltage to the array common source of the operating memory block in an erase phase; and providing a second voltage to the array common source of the non-operating memory block in the erase phase, the second voltage is less than the first voltage.

[0018] According to an embodiment of the present disclosure, the method further includes: providing a third voltage to word lines of the at least two memory blocks in the erase phase, the third voltage is less than the first voltage.

[0019] According to an embodiment of the present disclosure, the method further includes: providing the second voltage to the array common source of the at least two memory blocks in a pre-erase phase before the erase phase.

[0020] According to an embodiment of the present disclosure, the method further includes: providing a third voltage to word lines of the at least two memory blocks in a pre-erase phase before the erase phase.

[0021] According to an embodiment of the present disclosure, the method further includes: setting bit lines, top select lines and bottom select lines of the at least two memory blocks to a floating state in the erase phase.

[0022] According to an embodiment of the present disclosure, the method further includes: setting bit lines, top select lines and bottom select lines of the at least two memory blocks to a floating state in a pre-erase phase before the erase phase.

[0023] According to an embodiment of the present disclosure, the second voltage is a ground voltage.

[0024] According to an embodiment of the present disclosure, the third voltage is a ground voltage.

[0025] According to yet another aspect of the present disclosure, a method for forming a semiconductor structure is provided. The method includes: forming a stack structure on a substrate, the stack structure includes conductive layers stacked along a first direction, the stack structure includes at least one memory block group, the memory block group includes at least two memory blocks, conductive layers of the at least two memory blocks at a same layer are connected; removing the substrate to expose a bottom layer of the stack structure along the first direction; forming an array common source layer on the exposed bottom layer of the stack structure along the first direction; and segmenting the array common source layer to isolate array common sources of adjacent memory blocks in the memory block group from each other.

[0026] According to an embodiment of the present disclosure, the splitting the array common source layer to isolate the array common sources of the adjacent memory blocks in the memory block group from each other comprises: splitting the array common source layer along a second direction to form a gap extending along the second direction between the array common sources of the adjacent memory blocks in the memory block group, the second direction being perpendicular to the first direction.

[0027] According to an embodiment of the present disclosure, the method further comprises: forming a plurality of first contact holes arranged along a second direction between the adjacent memory blocks at least partially through the stack structure along the first direction; removing the stack structure between the adjacent first contact holes of the portion between the adjacent memory blocks in the memory block group to form a first gate line gap; and forming a first gate line gap structure in the first gate line gap.

[0028] According to an embodiment of the present disclosure, the stack structure comprises at least two memory block groups; and the method further comprises: removing the stack structure between the adjacent first contact holes of the portion between the adjacent memory block groups in the memory block group to form a second gate line gap; and forming a second gate line gap structure in the second gate line gap.

[0029] According to an embodiment of the present disclosure, the stack structure comprises a first stack structure and a second stack structure; and the forming a stack structure on a substrate comprises: alternately stacking a sacrificial layer and a first dielectric layer along the first direction on the substrate; replacing the portion of the sacrificial layer in a first region with the conductive layer to form the first stack structure; and replacing the portion of the sacrificial layer in a second region with the conductive layer to form the second stack structure.

[0030] According to an embodiment of the present disclosure, the method further comprises: forming a first portion of a second contact hole by at least partially penetrating the second stack structure along the first direction to the corresponding sacrificial layer; forming a second portion of the second contact hole by removing the sacrificial layer from the first portion of the second contact hole to expose the corresponding conductive layer; and forming a connection structure in the first portion of the second contact hole and the second portion of the second contact hole.

[0031] According to an embodiment of the present disclosure, the method further comprises: reforming a substrate on the array common source layer.

[0032] According to still another aspect of the present disclosure, there is provided a memory, comprising any of the semiconductor structures described above.

[0033] According to still another aspect of the present disclosure, there is provided a memory system, comprising any of the memories described above and a controller coupled to the memory.

[0034] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0035] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

[0036] Figure 1 A block diagram of an exemplary system having a memory in accordance with an embodiment of the present disclosure is shown.

[0037] Figure 2A A block diagram of an exemplary memory system is shown.

[0038] Figure 2B A block diagram of another exemplary memory system is shown.

[0039] Figure 3 A schematic circuit diagram of a memory 300 including a peripheral circuit provided in accordance with an embodiment of the present disclosure is shown.

[0040] Figure 4 A schematic diagram of a peripheral circuit provided in accordance with an embodiment of the present disclosure is shown.

[0041] Figure 5 A design layout of a semiconductor structure in accordance with an exemplary embodiment is shown.

[0042] Figure 6 A mark-up diagram of a semiconductor structure in Figure 5 in some embodiments is shown.

[0043] Figure 7 A structure diagram of a memory block in Figure 5 in accordance with an exemplary embodiment is shown.

[0044] Figure 8 A cross-sectional diagram of a semiconductor structure in Figure 5 in accordance with an exemplary embodiment is shown.

[0045] Figure 9 A flowchart of a semiconductor structure formation method in accordance with an exemplary embodiment is shown.

[0046] Figure 10 A process flow diagram of the step S902 shown in Figure 9 in an embodiment is shown.

[0047] Figure 11 A flowchart of a semiconductor structure formation method in accordance with Figure 10 is shown.

[0048] Figure 12 A flowchart of a semiconductor structure formation method in accordance with Figure 9A flowchart of another semiconductor structure formation method is shown.

[0049] Figure 13 is a flowchart of another semiconductor structure formation method according to an example embodiment. Figure 9 A flowchart of another semiconductor structure formation method is shown.

[0050] Figure 14 is a flowchart of another semiconductor structure formation method according to an example embodiment.

[0051] Figure 15 is a flowchart of a memory operation method according to an example embodiment.

[0052] Figure 16 is a flowchart of another memory operation method according to an example embodiment. Figure 15 A flowchart of another memory operation method is shown.

[0053] Figure 17 is a flowchart of another memory operation method according to an example embodiment. Figure 15 to Figure 16 is a waveform diagram of a memory in an erase phase.

[0054] Figure 18 is a waveform diagram of a memory in a program phase according to an example embodiment.

[0055] Figure 19 is a waveform diagram of a memory in a read phase according to an example embodiment. DETAILED DESCRIPTION

[0056] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views. Like components are identified with like reference numerals, and thus description of such components can be omitted from repeated descriptions.

[0057] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0058] In addition, the terms "first", "second", and the like are used only for descriptive purposes, and do not denote or imply relative importance or an ordered ranking of the indicated technical features. Thus, features defined with "first", "second" can include, explicitly or implicitly, one or more of such features. In the description of the disclosure, the meaning of "a plurality of" is at least two, for example, two, three, and the like, unless otherwise explicitly and specifically limited. The symbol " / " generally represents an "or" relationship between the objects before and after it.

[0059] In the present disclosure, unless otherwise explicitly and specifically defined, the terms "connected", "coupled", and the like should be interpreted broadly, for example, can be electrically connected or can communicate with each other; can be directly connected, or can be indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0060] Figure 1 A block diagram of an exemplary system having a memory in embodiments of the present disclosure is shown. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, or any other suitable electronic device having a memory therein.

[0061] As shown in Figure 1 The system 100 can include a host 108 and a memory system 102 having one or more memories 104 and a memory controller 106, as shown. The host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor) of an electronic device. The host 108 can be configured to send data to or receive data from the memory 104.

[0062] The memory 104 can be any memory in the present disclosure, for example, a non-volatile memory. The non-volatile memory can be a NAND flash memory (e.g., a three-dimensional (3D) NAND flash memory).

[0063] In some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108, and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104, and communicate with the host 108.

[0064] In some embodiments, the memory controller 106 is configured to send a command to the memory 104 to cause the memory 104 to perform a memory operation method provided by embodiments of the present disclosure.

[0065] In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

[0066] In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which can be used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, and the like, as well as enterprise storage arrays. The memory controller 106 can be configured to send commands to the memory 104 to cause the memory 104 to perform operations, such as read, erase, and program operations.

[0067] The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like.

[0068] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) with respect to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., the host 108) in accordance with a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, and the like.

[0069] The memory controller 106 and the one or more memories 104 can be integrated into various types of storage devices, such as included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0070] Figure 2A An exemplary block diagram of a memory system is shown. As Figure 2AAs shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, MMCmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a connector for connecting the memory card 202 to a host computer (e.g., ...). Figure 1 The memory card connector 204 is coupled to the host 108.

[0071] Figure 2B A block diagram of another memory system is shown as an example. Figure 2B As shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0072] Figure 3 A schematic circuit diagram of a memory 300 including peripheral circuitry provided for embodiments of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of memory strings 308 of NAND flash memory, each memory string 308 extending vertically above a substrate (not shown).

[0073] In some embodiments, the peripheral circuit 302 is configured to perform the operation methods provided in the embodiments of this disclosure. It is understood that the peripheral circuit 302 may be configured to perform the operation methods provided in the embodiments of this disclosure according to instructions received from the memory controller 106.

[0074] In some embodiments, each memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0075] In some embodiments, each storage cell 306 can store 1-bit data or 2-bit data or more, i.e., can be of Single-Level Cell (SLC) type, Multi-Level Cell (MLC) type, Triple-Level Cell (TLC) type, Quad-Level Cell (QLC) type, or higher.

[0076] As shown in Figure 3 each storage string 308 can include a Source Select Gate (SSG) 310 at its source end and a Drain Select Gate (DSG) 312 at its drain end. The SSG 310 and the DSG 312 can be configured to activate a selected storage string 308 during read and program operations.

[0077] In some embodiments, the sources of the storage strings 308 in the same block 304 are coupled through the same Source Line (SL) 314 (e.g., a common SL). For example, all storage strings 308 in the same block 304 have an Array Common Source (ACS). As shown in Figure 3 the storage strings 308 can be organized into a plurality of blocks 304. In some embodiments, each of the plurality of blocks 304 can have a common source line 314 (e.g., coupled to ground); in other embodiments, the plurality of blocks 304 can be divided into storage block groups, the array common sources of different storage blocks in each storage block group being isolated from each other, see Figure 8 In some embodiments, each block 304 is a basic unit of data for erase operations, i.e., all storage cells 306 on the same block 304 are erased at the same time.

[0078] In some embodiments, the transistors of the DSG 312 of each storage string 308 are coupled to a respective Bit Line (BL) 316, from which data can be read or written via an output bus (not shown). Each storage string 308 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the DSG 312) or a deselection voltage (e.g., 0V) to the respective DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the SSG 310) or a deselection voltage (e.g., 0V) to the respective SSG 310 via one or more SSG lines 315.

[0079] AsFigure 3 As shown, the memory cells 306 of the memory string 308 can be coupled by a word line (WL) 318, which selects which row of memory cells 306 is affected by read and program operations. The peripheral circuitry 302 can be coupled to the memory cell array 301 by bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory cell array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each memory cell 306 that becomes an operation target via the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using Metal-Oxide-Semiconductor (MOS) technology.

[0080] Figure 4 A schematic diagram of a peripheral circuit provided for embodiments of the present disclosure. As shown, the peripheral circuitry 302 can include page buffer circuitry / sense amplifiers 404, column decoders / BL drivers 406, row decoders / WL drivers 408, voltage generators 410, control logic 412, registers 414, input / output (I / O) circuitry 416, and data bus 418. It should be understood that additional peripheral circuitry not shown in FIG. 4 can also be included in some examples. Figure 4 Figure 4

[0081] In some embodiments, the page buffer circuitry / sense amplifiers 404 can be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic 412. For example, the page buffer circuitry / sense amplifiers 404 can store a page of program data (write data) to be programmed into the memory cell array 301. As another example, the page buffer circuitry / sense amplifiers 404 can also sense low-power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to identifiable logic levels in read operations. The column decoders / BL drivers 406 can be configured to be controlled by the control logic 412 and select one or more memory strings 308 by applying bit line voltages generated from the voltage generators 410.

[0082] ​​Row decoders / WL drivers 408 can be configured to be controlled by control logic 412 and select / deselect blocks 304 of memory cell array 301 and select / deselect word lines 318 of blocks 304. Row decoders / WL drivers 408 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 410. In some embodiments, row decoders / WL drivers 408 can also select / deselect and drive SSG lines 314 and DSG lines 313. Voltage generator 410 can be configured to be controlled by control logic 412 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages, etc. to be supplied to memory cell array 301.

[0083] Control logic 412 can be coupled to each portion of peripheral circuit 302 and configured to control the operation of each portion. In some embodiments, array common source of different memory blocks in the same memory block group are isolated from each other, control logic 412 can include array common source control circuit configured to distinguish control voltages applied to array common sources of different memory blocks to perform erase operation, etc. on the memory blocks.

[0084] Register 414 can be coupled to control logic 412 and can include status register, command register, and address register to store status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. Input / output circuit 416 can be coupled to control logic 412 and act as control buffer to buffer control commands received from host (not shown) and relay them to control logic 412, and buffer status information received from control logic 412 and relay them to the host. Input / output circuit 416 can also be coupled to column decoder / bit line driver 406 via data bus 418 and act as data I / O interface and data buffer to buffer data and relay them to or from memory cell array 301. Figure 4

[0085] The semiconductor structure in the memory device employs a stack structure to provide the gate conductive layers of the transistors (including the select gates and the word lines), employs a channel structure through the stack structure to provide the channel layer of the transistors, and employs a connection structure through the stack structure to implement a conductive path for connecting the gate conductive layers through which the channel structure passes to the external circuit. Figure 5 A design layout of a semiconductor structure is shown according to an exemplary embodiment. Figure 5 ​The illustrated semiconductor structure can include a memory cell array 301, which can include a stack structure 502 and a connection structure 504, the stack structure 502 can include stacked conductive layers 5022.

[0086] As shown, the stack structure 502 can be stacked by conductive layers 5022 parallel to the plane (XY plane) of the X direction and the Y direction along the Z direction perpendicular to the XY plane, and the conductive layers 5022 can be word lines 318 of the memory cell array 301. The connection structure 504 can pass through the stack structure 502 along the Z direction and be connected with the corresponding conductive layer 5022. Figure 5

[0087] The memory cell array 301 can include at least one memory block group 3012, and the memory block group 3012 can include at least one memory block 304. The conductive layers 3012 of the memory blocks 304 in the memory block group 3012 at the same layer are connected, and the conductive layers 3012 of the memory blocks 304 in the memory block group 3012 at the same layer are connected with the same connection structure.

[0088] In some embodiments, the number of memory blocks of a memory block group can be related to the number of stacked conductive layers in the stack structure. Different conductive layers are connected with different connection structures, so the more the number of stacked conductive layers in the stack structure, the more the number of required connection structures; the medium layers are also included between the stacked conductive layers in the stack structure, the more the number of stacked conductive layers in the stack structure, the more the total number of layers stacked in the stack structure, and the larger the inner diameter of the connection structure passing through the stack structure. The number of memory blocks in the memory block group can be increased accordingly to reduce the total number of connection structures, to reduce the impact of the increase in the number of connection structures and the increase in the inner diameter of all connection structures on the area of the chip occupied by the connection structures. For example, the memory block group includes at least two memory blocks.

[0089] According to the semiconductor structure provided by the embodiments of the present disclosure, by dividing the memory cell array into at least one memory block group, and connecting the conductive layers at the same layer of the memory blocks in the memory block group with the same connection structure, compared with connecting the conductive layers at the same layer of different memory blocks with different connection structures, the total number of required connection structures is reduced, and the limitation of the increase in the number of layers of the stack structure caused by the increase in the area of the chip occupied by the connection structures can be avoided as much as possible, thereby improving the speed of increasing the storage density.

[0090] In some embodiments, a partition region can be provided on a gate line slot (GLS) structure for isolating the (gate) conductive layers of adjacent memory blocks, to communicate the conductive layers of adjacent memory blocks. Figure 6 The illustrated semiconductor structure in some embodiments is shown in the diagram in Figure 5 As shown, the stack structure 502 can be stacked by conductive layers 5022 parallel to the plane (XY plane) of the X direction and the Y direction along the Z direction perpendicular to the XY plane, and the conductive layers 5022 can be word lines 318 of the memory cell array 301. The connection structure 504 can pass through the stack structure 502 along the Z direction and be connected with the corresponding conductive layer 5022.​Figure 6 As shown, the memory cell array 301 can further include a first gate line slit structure 602 at least partially penetrating the stack structure along the Z direction, the first gate line slit structure 602 can include a plurality of mutually isolated sub-gate line slit structures 6022, a gate line slit partition region 604 is formed between adjacent sub-gate line slit structures 6022, and the conductive layers at the same layer of the memory blocks in the memory block group 3012 are connected through the gate line slit partition region 604.

[0091] The memory cell array 301 can further include a second gate line slit structure 606 at least partially penetrating the stack structure along the Z direction, to separate adjacent memory block groups in the plurality of memory block groups.

[0092] In some embodiments, the connection structure can be connected with the gate conductive layer penetrating the channel structure. Figure 7 According to an exemplary embodiment, a structure diagram of one memory block in the memory block group is shown. Figure 5 According to an exemplary embodiment, a structure diagram of one memory block in the memory block group is shown. Figure 7 According to an exemplary embodiment, a structure diagram of one memory block in the memory block group is shown. Figure 5 The difference between the two is that, Figure 7 A view of a cross section perpendicular to the Z direction is shown, which is different from Figure 5 As shown, the stack structure 502 can include a first stack structure 702 and a second stack structure 704, the first stack structure 702 can include conductive layers 5022 Figure 7 (not shown in the figure, which is in other planes perpendicular to the Z direction) and first dielectric layers 5024 alternately stacked along a first direction (for example, the Z direction in the figure), and the second stack structure 704 includes second dielectric layers 5026 Figure 7 (not shown in the figure, which is in other planes perpendicular to the Z direction) and first dielectric layers 5024 alternately stacked along the first direction, and the first dielectric layers 5024 are in the plane (X'Y' plane) where the X' direction and the Y' direction in the figure are located. The channel structure 7062 can be located in the first stack structure 702, and the channel structure 7062 can penetrate at least part of the first stack structure 702 along the Z direction. Figure 7 Figure 7 Figure 7

[0093] ​​​The connection structure 504 can be located in the second stack structure 704 and extend through at least a portion of the second stack structure 704 in the Z direction. The connection structure 504 can include a first portion 5042 and a second portion 5044 connected to each other. The first portion 5042 of the connection structure extends through at least a portion of the second stack structure 704 in the Z direction to a corresponding second medium layer. The second portion 5044 of the connection structure extends in a second direction (e.g., the Y' direction in the figure) to a corresponding conductive layer in the second stack structure 704 through which the dummy channel structure 7064 extends in the Z direction. The conductive layer in the second stack structure 704 through which the dummy channel structure 7064 extends at least partially connects to a corresponding conductive layer in the first stack structure 702, so that the connection structure 504 is connected to the corresponding conductive layer in the first stack structure 702 through which the channel structure 7062 extends at least partially. The second portion 5044 of the connection structure can form a disc shape parallel to the X'Y' plane after formation, and the position of the disc shape can be as shown by the dashed circular structure in the view of Figure 7

[0094] In some embodiments, the semiconductor structure in the memory block in Figure 3 may further include a top select gate (TSG) (e.g., which can be the DSG 312) partition region 708. The channel structure 7062 corresponds to the memory string 308 in the memory block in Figure 8 The TSG partition region 708 divides the memory strings 308 in one memory block 304 into a plurality of string columns 3042, and the memory strings 308 at different string columns in one memory block 304 can be connected to the same BL, so as to reduce the number of BLs arranged.

[0095] For the semiconductor structure in which the conductive layers at the same layer in the memory blocks in the memory block group are in communication, in some embodiments, the differentiating operation on the different memory blocks in the memory block group can be implemented by separating the ACSs of the different memory blocks in the memory block group. Figure 5 A cross-sectional view of the semiconductor structure in Figure 8 is shown according to an example embodiment. Figure 5 A view of another cross section perpendicular to the Z direction different from Figure 8 is shown. As shown in Figure 9 , the memory cell array 302 further includes an array common source 802, and the array common sources of the different memory blocks in the memory block group 3012 are isolated from each other.

[0096] In some embodiments, there is a gap 804 between the array common sources of the adjacent memory blocks in the memory block group, so as to isolate the array common sources of the adjacent memory blocks.

[0097] ​According to the semiconductor structure provided by the embodiments of the present disclosure, the conductive layers of the memory blocks in the same layer in the memory block group are connected with the same connection structure, and the array common sources of different memory blocks in the memory block group are isolated from each other, so that the distinguishing operation of different memory blocks in the memory block group is realized.

[0098] Figure 9 is a flowchart of a semiconductor structure forming method according to an exemplary embodiment. As shown in the method 90, for example, the overall steps of forming the semiconductor structure shown in Figure 5 to Figure 8 Figure 9 The method 90 provided by the embodiments of the present disclosure can include the following steps S902 to S908 with reference to Figure 7

[0099] In step S902, the stack structure 502 is formed on the substrate.

[0100] In some embodiments, the initial stack structure can be formed by alternately stacking the silicon oxide layer (for example, the first dielectric layer) and the silicon nitride layer (for example, the second dielectric layer) by using a multi-layer thin film deposition technology. The silicon oxide layer serves as an isolation layer, and the silicon nitride layer serves as a sacrificial layer of the gate conductive structure such as a word line, which can be partially replaced by a conductive metal (for example, tungsten (W) material) to form a conductive layer in a subsequent process to form the final stack structure. The process of replacing the silicon nitride layer can use phosphoric acid to etch the silicon nitride layer, and then fill the conductive metal material in the gap layer.

[0101] In another embodiment, the silicon oxide layer and the polysilicon layer can be alternately stacked by using a multi-layer thin film deposition technology.

[0102] In the embodiments of the present disclosure, the silicon oxide layer and the silicon nitride layer are alternately stacked as an example, but are not limited thereto.

[0103] With reference to Figure 10 In some embodiments, the stack structure 502 can include the first stack structure 702 and the second stack structure 704. The first stack structure 702 can be formed by alternately stacking the sacrificial layer and the first dielectric layer on the substrate, and replacing part of the sacrificial layer in the first region with the conductive layer. The second stack structure 704 can be formed by replacing part of the sacrificial layer in the second region with the conductive layer. The implementation in some embodiments can refer to Figure 11 .

[0104] In some embodiments, the connection structure 504 can be formed at least partially through the second stack structure 704 after the stack structure 502 is formed. The exemplary implementation of forming the connection structure can refer to Figure 8 .

[0105] With reference to Figure 12 ​​The formed stack structure 502 can include conductive layers 5022 stacked along the first direction. The stack structure 502 can include at least one memory block group 3012 including at least two memory blocks 304, and the conductive layers of the at least two memory blocks 304 at the same layer are connected. In some embodiments, the memory blocks can be divided by a gate line slit structure, for example, the memory blocks adjacent to one memory block group can be separated by a first gate line slit structure, and an example embodiment of the first gate line slit structure can refer to Figure 13 .

[0106] In some embodiments, the stack structure can include at least two memory block groups, and the memory blocks adjacent to each other between the memory block groups can be separated by a second gate line slit structure, and an example embodiment of the second gate line slit structure can refer to Figure 14 .

[0107] In step S904, the substrate is removed to expose the bottom layer of the stack structure along the first direction.

[0108] In some embodiments, after the stack structure, the connection structure, and the like are formed, the chip can be flipped to have the substrate upward, and then the substrate is removed to expose the bottom layer of the stack structure close to the original substrate along the Z direction.

[0109] In step S906, an array common source layer is formed on the exposed bottom layer of the stack structure along the first direction.

[0110] In some embodiments, the array common source layer can be deposited on the bottom layer of the stack structure exposed after the substrate is removed (for example, which can be the first dielectric layer).

[0111] In step S908, the array common source layer is segmented to isolate the array common sources of the memory blocks adjacent to each other in the memory block group.

[0112] In some embodiments, the array common source layer can be segmented at the positions corresponding to the gate line slit structure in the Z direction to isolate the array common sources of the memory blocks adjacent to each other in the memory block group. For a specific embodiment, refer to Figure 10 .

[0113] According to the method for forming a semiconductor structure provided by the embodiments of the present disclosure, by removing the substrate after the stack structure and the connection structure are formed, then forming an array common source layer on the exposed dielectric layer, and corresponding segmenting the array common source layer to isolate the array common sources of the memory blocks adjacent to each other in the memory block group, the differentiating operation on different memory blocks in the memory block group is realized in the case that the conductive layers of the memory blocks in the memory block group at the same layer are connected to the same connection structure.

[0114] Figure 9 It is shown that Figure 10The step S902 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 12 As shown in the present embodiment, step S902 may further include the following steps.

[0115] Step S1002: Alternately stack a sacrificial layer and a first dielectric layer on the substrate along a first direction.

[0116] In some embodiments, a multilayer thin film deposition technique can be used to alternately stack silicon oxide layers and silicon nitride (e.g., Si3N4) layers along the Z-direction to form an initial stacked structure.

[0117] Step S1004: Replace part of the sacrificial layer in the first region with a conductive layer to form a first stacked structure.

[0118] In some embodiments, the first region may include a core region. A channel hole can be formed in the core region by patterning and etching the upper surface layer of the initial stacked structure (along the Z-direction or the opposite direction of the Z-direction) and the underlying silicon oxide-silicon nitride layer, etc., using photolithography and etching processes. For example, a photolithography process can be performed to pattern the opening of the channel hole using an etching mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes (e.g., reactive ion etching (RIE)) can be performed to penetrate the silicon oxide-silicon nitride layer. After forming the channel hole, a channel structure is formed in the channel hole, and then from the gate line gap (e.g., which may be...) Figure 13 The first gate line gap and Figure 12 The sacrificial layer (silicon nitride layer) is etched in the second gate line gap, and a conductive layer is deposited on the surface of the first dielectric layer exposed after the sacrificial layer is removed to form a first stacked structure.

[0119] Step S1006: Replace part of the sacrificial layer in the second region with a conductive layer to form a second stacked structure.

[0120] In some embodiments, the second region may include a stepped region. In some embodiments, a virtual channel via may also be formed inside the edge of a memory block extending along the X (or X') direction in the stepped region of the initial stacked structure, for example, by patterning and etching the upper surface layer and the underlying silicon oxide-silicon nitride layer of the initial stacked structure sequentially using photolithography and etching processes. After forming the virtual channel via, a virtual channel structure is formed in the virtual channel via, and then from the gate line gap (e.g., which may be...) Figure 13 The first gate line gap and Figure 11The sacrificial layer is then replaced by a conductive layer from the virtual channel hole to connect the conductive layer around the virtual channel hole with the conductive layer around the channel hole.

[0121] Figure 10 According to Figure 11 A flowchart of a method of forming a semiconductor structure is shown. As Figure 11 The method shown provides an exemplary embodiment of forming a connection structure.

[0122] Referring to Figure 12 The method 110 provided by the embodiments of the present disclosure can include the following steps.

[0123] In step S1102, a first portion of a second contact hole is formed by at least partially penetrating a second stack structure in a first direction to a corresponding sacrificial layer.

[0124] In some embodiments, the second contact hole for forming a connection structure can be formed by sequentially etching the upper layer of the second stack structure (in the Z direction or the opposite direction of the Z direction) and the silicon oxide-silicon nitride layer thereunder using a lithography, etching process pattern. For example, a lithography process can be performed to pattern the opening of the contact hole using an etching mask (e.g., a photoresist mask), and one or more dry etching and / or wet etching processes can be performed to pass through the silicon oxide-silicon nitride layer to stop at the designated silicon nitride layer (sacrificial layer) corresponding to the conductive layer of the first stack structure 702 and the second stack structure 704.

[0125] In step S1104, the sacrificial layer is removed from the first portion of the second contact hole to expose the corresponding conductive layer to form a second portion of the second contact hole.

[0126] In some embodiments, after forming the first portion of the second contact hole penetrating at least part of the second stack structure in the Z direction, the corresponding sacrificial layer can be removed from the bottom of the first portion of the second contact hole in the Y (or Y' direction) to expose the conductive layer penetrated by the virtual channel structure to form the second portion of the second contact hole.

[0127] In step S1106, a connection structure is formed in the first portion of the second contact hole and the second portion of the second contact hole.

[0128] In some embodiments, a first conductive layer, a second conductive layer, and a third conductive layer may be sequentially deposited within the formed second contact hole, and then an insulating core may be filled. The first and third conductive layers may be, for example, titanium nitride films, the second conductive layer may be, for example, a tungsten layer, and the insulating core may be, for example, an oxide (OX, typically including silicon dioxide (SiO2)).

[0129] According to the connection structure formation method provided in the embodiments of this disclosure, a second contact hole is formed by an SCT (Use Stair Step (SS) Etch Process to accurately place Contact Hole on each WL) process, and then a connection structure is formed in the second contact hole to achieve the extraction of the gate conductive layer.

[0130] Figure 9 It is based on Figure 12 A flowchart illustrating another method for forming a semiconductor structure is shown. (See attached flowchart.) Figure 12 The method shown can be, for example, an exemplary implementation of forming a first gate line gap structure for distinguishing memory blocks in a group of memory blocks.

[0131] refer to Figure 13 The method 120 provided in this embodiment may include the following steps.

[0132] In step S1202, at least partially penetrating the stacked structure along the first direction, a plurality of first contact holes arranged along the second direction are formed between adjacent storage blocks.

[0133] In some embodiments, multiple first contact holes can be formed along the X (or X') direction at predetermined division positions between adjacent memory blocks on the stacked structure. When forming each first contact hole, for example, photolithography and etching processes can be used to pattern and etch the upper surface layer of the stacked structure and the underlying silicon oxide layer-silicon nitride layer until the substrate.

[0134] In step S1204, the stacked structure between adjacent first contact holes in the portion between adjacent memory blocks in the memory block group is removed to form a first gate line gap.

[0135] In some embodiments, a plurality of first contact holes arranged along the X (or X') direction can be divided into several groups, each group including the same number of adjacent first contact holes, for example, each group includes 3, 4, or 5 adjacent first contact holes. For each group, the stacking structure between the first contact holes can be removed, that is, the first contact holes in each group are brought together to form a sub-gate line gap.

[0136] In step S1206, a first gate line gap structure is formed in the first gate line gap.

[0137] In some embodiments, polysilicon can be deposited in each sub-gate line slit to form a sub-gate line slit structure 6022, and a plurality of sub-gate line slit structures 6022 form the first gate line slit structure 602. The stack structure between adjacent sub-gate line slit structures 6022 can form a gate line slit partition region 604 to enable the conductive layers in the same layer of the memory cells in the memory cell group 3012 to be connected to each other when the sacrificial layer is replaced by the conductive layer in the gate line slit.

[0138] According to the method for forming a semiconductor structure provided by the embodiments of the present disclosure, by removing the stack structure between the adjacent first contact holes in the portion between adjacent memory cells in the memory cell group, and retaining the stack structure between the adjacent first contact holes in the portion, the first gate line slit structure with the gate line slit partition region is formed, and the conductive layers in the same layer of the memory cells in the memory cell group are connected to the same connection structure, which reduces the total number of required connection structures compared to the connection of the conductive layers in the same layer of different memory cells to different connection structures, and can avoid the limitation of the increase of the number of stack layers caused by the increase of the area of the chip occupied by the connection structure, thereby improving the speed of increasing the storage density.

[0139] Figure 9 is according to Figure 13 is a flowchart of another method for forming a semiconductor structure. As The method shown in Figure 12 may be an example embodiment of forming a second gate line slit structure for separating a memory cell group.

[0140] In step S1302, the stack structure between the adjacent first contact holes in the portion between adjacent memory cells in the memory cell group is removed to form a second gate line slit.

[0141] Figure 14 The division position between adjacent memory cells described in the foregoing embodiments can include a division position between adjacent memory cells in a memory cell group, and can also include a division position between adjacent memory cell groups. The stack structure between the first contact holes in the portion between adjacent memory cell groups can be removed, i.e., the first contact holes in the portion between adjacent memory cell groups are converged together to form a second gate line slit.

[0142] In step S1304, a second gate line slit structure is formed in the second gate line slit.

[0143] In some embodiments, polysilicon can be deposited in the second gate line slit to form a second gate line slit structure 606.

[0144] Figure 14 is a flowchart of another method for forming a semiconductor structure according to an example embodiment. As Figure 9 The method shown inFigure 14 The step S908 in some example embodiments is further illustrated based on the step S906.

[0145] With reference to Figure 11 The method 140 provided by the embodiments of the present disclosure can include the following steps S1402 to S1412.

[0146] In step S1402, a stack structure is formed on a substrate, the stack structure including conductive layers stacked along a first direction, the stack structure including at least one memory block group, the memory block group including at least two memory blocks, and the conductive layers at the same layer of the at least two memory blocks being connected.

[0147] The implementation of the step S1402 in some example embodiments can refer to the step S902.

[0148] In step S1404, a connection structure is formed through the stack structure.

[0149] The implementation of the step S1404 in some example embodiments can refer to Figure 15 .

[0150] In step S1406, the substrate is removed to expose a bottom layer of the stack structure along the first direction.

[0151] In step S1408, an array common source layer is formed on the exposed bottom layer of the stack structure along the first direction.

[0152] The implementation of the step S1406 and the step S1408 in some example embodiments can refer to the step S904 and the step S906.

[0153] In step S1410, the array common source layer is segmented along a second direction, and a gap extending along the second direction is formed between the array common sources of adjacent memory blocks in the memory block group, the second direction being perpendicular to the first direction.

[0154] In some embodiments, the array common source layer can be segmented along the X (or X') direction at the position corresponding to the gate line gap structure in the Z direction, and a gap extending along the X (or X') direction is formed between the array common sources of adjacent memory blocks in the memory block group, so as to isolate the array common sources of adjacent memory blocks in the memory block group from each other.

[0155] In step S1412, the substrate is reformed on the array common source layer.

[0156] According to the method for forming a semiconductor structure provided by the embodiments of the present disclosure, by removing the substrate after the formation of the stack structure and the connection structure, then forming an array common source layer on the exposed dielectric layer, and corresponding segmenting the array common source layer to form a gap extending along a second direction perpendicular to the first direction between the array common sources of adjacent memory blocks in a memory block group, the array common sources of adjacent memory blocks in the memory block group are isolated from each other, so that the differentiating operation on different memory blocks in the memory block group is realized in the case that the conductive layers at the same layer of the memory blocks in the memory block group are connected to the same connection structure.

[0157] Figure 15 is a flowchart of a memory operation method according to an exemplary embodiment. As shown in the method Figure 5 to Figure 8 shown in the semiconductor structure Figure 15 shown in the semiconductor structure, the method shows the operation of the same memory block group in the erase phase, the memory block group at least includes an operating memory block and a non-operating memory block, the operating memory block may, for example, be a memory block to be erased, and the non-operating memory block may, for example, be a memory block not to be erased.

[0158] With reference to Figure 17 , the method 150 provided by the embodiments of the present disclosure can include the following steps S1502 to S1508.

[0159] In step S1502, in the erase phase, a first voltage is provided to the array common source of the operating memory block.

[0160] In some embodiments, the first voltage can be an erase operation voltage, which can be a high positive voltage, for example, can be 20V or higher, which can be represented as Verase in Figure 17 .

[0161] In step S1504, in the erase phase, a second voltage is provided to the array common source of the non-operating memory block, and the second voltage is less than the first voltage.

[0162] In some embodiments, the second voltage can be an erase inhibit voltage, which can be a low voltage, for example, can be a ground voltage, which can be represented as GND in Figure 17 to Figure 19 .

[0163] In step S1506, in the erase phase, a third voltage is provided to the word line of the at least two memory blocks, and the third voltage is less than the first voltage.

[0164] In some embodiments, the third voltage can be a low voltage, for example, can be a ground voltage.

[0165] In step S1508, in the erase phase, the bit line and the top select line (also referred to as TSG line, which can be represented as TSG in Figure 17 to Figure 19The bottom select line (also known as the top select gate (BSG)) is represented as TSG, and the bottom select line (e.g., SSG 310) is also represented as BSG. Figure 16 The value (represented as BSG) is set to a floating state.

[0166] In some embodiments, during the erase phase, the bit lines, top select line, and bottom select line of both the operating memory block and the non-operating memory block can be set to a floating state.

[0167] According to the memory operation method provided in the embodiments of this disclosure, by applying voltages separately to the array common source of the operating memory block and the array common source of the non-operating memory block, it is possible to perform an erase operation on the operating memory block while not performing an erase operation on the non-operating memory block when the conductive layer of the operating memory block and the non-operating memory block are on the same layer and connected to the same connection structure.

[0168] Figure 15 It is based on Figure 16 A flowchart illustrating another memory operation method is shown. (See attached flowchart.) Figure 5 to Figure 8 The method shown illustrates the process of applying the eraser before the erasure phase. Figure 16 The process of operating the semiconductor structure shown.

[0169] refer to Figure 17 The method 160 provided in this embodiment may include the following steps S1602 to S1606.

[0170] In step S1602, during the pre-erase phase prior to the erase phase, a third voltage is provided to the word lines of at least two memory blocks.

[0171] In step S1604, during the pre-erasure phase, a second voltage is provided to the array common source of at least two memory blocks.

[0172] In some embodiments, prior to the erase phase, a low voltage, such as ground voltage, may be provided to the array common source for both operational and non-operational memory blocks.

[0173] In step S1606, during the pre-erasure phase, the bit lines, top select line, and bottom select line of at least two memory blocks are set to a floating state.

[0174] Figure 15 to Figure 16 It is based on Figure 17 The diagram shows a waveform of a memory during the erase phase. (Refer to...) Figure 18In some embodiments, prior to the Terase erasure phase, for both operational and non-operational memory blocks, ACS and WL are grounded, and BL, TSG, and BSG are floated. During the Terase erasure phase, for operational memory blocks, Verase is applied to ACS, WL remains grounded, and BL, TSG, and BSG remain floated; for non-operational memory blocks, ACS and WL remain grounded, and BL, TSG, and BSG remain floated.

[0175] Figure 18 This is a waveform diagram illustrating a memory during the programming phase according to an exemplary embodiment. (Refer to...) Figure 19 In some embodiments, during the pre-charge phase Tpre prior to the programming phase Tpgm, for operational memory blocks, a circuit supply voltage Vcc is provided to the selected BL, unselected BL, selected TSG, unselected TSG, and ACS, while the selected WL, unselected WL, and BSG are grounded. For non-operational memory blocks, a circuit supply voltage Vcc is provided to the selected BL, unselected BL, all TSGs (all unselected), and ACS, while the selected WL, unselected WL, and BSG are grounded. During the programming phase Tpgm, for operational memory blocks, a programming operating voltage Vpgm is applied to the selected WL, a programming pass voltage Vpass is applied to the unselected WL, Verase is applied to the selected BL, unselected TSG, BSG, and ACS, and the circuit supply voltage Vcc is maintained for the unselected BL and selected TSG. For non-operational memory blocks, the operation except for the TSG is the same as for operational memory blocks, but all TSGs of non-operational memory blocks are unselected, meaning all TSGs of non-operational memory blocks are grounded.

[0176] Figure 19 This is a waveform diagram illustrating a memory during the read phase according to an exemplary embodiment. (Refer to...) Figure 19 In some embodiments, during the read phase Tread, T r1 T r2 T r3 Three consecutive time periods with three gradually increasing reading voltages V R1 V R2 V R3 Perform the reading.

[0177] like ​ As shown, during the read phase Tread, for the operating memory block, a bit line bias voltage V is applied to the selected BL. BL For the selected WL in T r1 T r2 T r3 Three consecutive time periods provide a gradually increasing read voltage V. R1 V R2 V R3The unselected BL, the unselected TSG and the ACS are grounded, the selected TSG and the BSG are provided with a circuit power supply voltage Vcc, and the unselected WL is provided with a read-through voltage Vpass; for the non-operating memory block, the operation is the same as that of the operating memory block except that the TSG is unselected, i.e. all the TSGs of the non-operating memory block are grounded.

[0178] The exemplary embodiments of this disclosure are specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structure, arrangement or implementation method described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements within the spirit and scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A memory cell array, the memory cell array comprising a stacked structure and a connection structure, the stacked structure comprising stacked conductive layers, wherein: The storage cell array includes at least one storage block group, the storage block group includes at least one storage block, the conductive layers of the storage blocks in the storage block group that are on the same layer are connected, and the conductive layers of the storage blocks in the storage block group that are on the same layer are connected to the same connection structure.

2. The semiconductor structure according to claim 1, characterized in that, The memory cell array further includes a first gate line slot structure that at least partially extends through the stacked structure, wherein: The first gate line gap structure includes multiple mutually isolated sub-gate line gap structures, and a gate line gap isolation region is formed between adjacent sub-gate line gap structures. The conductive layers of the memory blocks in the memory block group that are on the same layer are connected through the gate line gap isolation region.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The number of storage blocks in the storage block group is related to the number of conductive layers stacked in the stacked structure.

4. The semiconductor structure according to claim 1 or 2, characterized in that, The storage block group comprises at least two storage blocks.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The stacked structure includes a first stacked structure and a second stacked structure. The first stacked structure includes the conductive layer and the first dielectric layer stacked alternately, and the second stacked structure includes the second dielectric layer and the first dielectric layer stacked alternately. The connection structure extends at least through a portion of the second stacked structure.

6. The semiconductor structure according to claim 5, characterized in that, The conductive layer and the first dielectric layer of the first stacked structure are stacked along a first direction, and the second dielectric layer and the first dielectric layer of the second stacked structure are stacked along the first direction; The connection structure includes a first part and a second part that are connected to each other. The first part of the connection structure extends at least through a portion of the second stacked structure to a corresponding second dielectric layer along the first direction. The second part of the connection structure extends along the second direction to connect with a corresponding conductive layer in the first stacked structure. The first direction is perpendicular to the second direction.

7. The semiconductor structure according to claim 4, characterized in that, The storage cell array also includes an array common source, and the array common sources of different storage blocks in the storage block group are isolated from each other.

8. The semiconductor structure according to claim 7, characterized in that, There are gaps between the array common sources of adjacent memory blocks in the memory block group to isolate the array common sources of adjacent memory blocks.

9. The semiconductor structure according to claim 7, characterized in that, It also includes peripheral circuitry, which includes an array common source control circuit configured to differentiate the voltage applied to the array common source of different memory blocks.

10. The semiconductor structure according to any one of claims 1 to 9, characterized in that, The storage unit array includes multiple storage block groups; The memory cell array further includes a second gate line slot structure that at least partially extends through the stacked structure to separate adjacent memory block groups among the plurality of memory block groups.

11. A memory operation method, characterized in that, The memory includes at least one group of memory blocks, the group of memory blocks includes at least two memory blocks, the conductive layers of the at least two memory blocks on the same layer are connected, the array common source of the at least two memory blocks is isolated from each other, and the at least two memory blocks include operational memory blocks and non-operational memory blocks; The method includes: During the erase phase, a first voltage is provided to the array common source of the operational memory blocks; During the erasure phase, a second voltage is provided to the array common source of the non-operating memory block, the second voltage being less than the first voltage.

12. The method according to claim 11, characterized in that, Also includes: During the erase phase, a third voltage is provided to the word lines of the at least two memory blocks, the third voltage being less than the first voltage.

13. The method according to claim 11 or 12, characterized in that, Also includes: In the pre-erasure phase preceding the erasure phase, the second voltage is provided to the array common source of the at least two memory blocks.

14. The method according to any one of claims 11 to 13, characterized in that, Also includes: In the pre-erasure phase preceding the erasure phase, a third voltage is provided to the word lines of the at least two memory blocks.

15. The method according to any one of claims 11 to 14, characterized in that, Also includes: During the erasure phase, the bit lines, top select line, and bottom select line of the at least two memory blocks are set to a floating state.

16. The method according to any one of claims 11 to 15, characterized in that, Also includes: In the pre-erasure phase preceding the erasure phase, the bit lines, top select line, and bottom select line of the at least two memory blocks are set to a floating state.

17. The method according to any one of claims 11 to 16, characterized in that, The second voltage is the ground voltage.

18. The method according to claim 12 or 14, characterized in that, The third voltage is the ground voltage.

19. A method for forming a semiconductor structure, characterized in that, include: A stacked structure is formed on a substrate, the stacked structure including conductive layers stacked along a first direction, the stacked structure including at least one group of memory blocks, the group of memory blocks including at least two memory blocks, and the conductive layers of the at least two memory blocks in the same layer being connected. Remove the substrate to expose the bottom layer of the stacked structure along the first direction; An array common source layer is formed on the bottom layer of the exposed stacked structure along the first direction; The array common source layer is segmented to isolate the array common sources of adjacent memory blocks in the memory block group from each other.

20. The method according to claim 19, characterized in that, The array common source layer is segmented to isolate the array common sources of adjacent memory blocks in the memory block group from each other, including: The array common source layer is divided along a second direction, forming a gap extending along the second direction between the array common sources of adjacent memory blocks in the memory block group, the second direction being perpendicular to the first direction.

21. The method according to claim 19 or 20, characterized in that, Also includes: A plurality of first contact holes arranged in a second direction are formed between adjacent storage blocks, at least partially penetrating the stacked structure along the first direction; Remove the stacked structure between adjacent first contact holes in the portion between adjacent memory blocks in the memory block group to form a first gate line gap; A first gate line gap structure is formed in the first gate line gap.

22. The method according to claim 21, characterized in that, The stacked structure includes at least two groups of storage blocks; The method further includes: Remove the stacked structure between adjacent first contact holes between adjacent memory block groups in the memory block group to form a second gate line gap; A second gate line gap structure is formed in the second gate line gap.

23. The method according to any one of claims 19 to 22, characterized in that, The stacking structure includes a first stacking structure and a second stacking structure; Forming a stacked structure on a substrate includes: A sacrificial layer and a first dielectric layer are alternately stacked on a substrate along the first direction; The first stacked structure is formed by replacing a portion of the sacrificial layer in the first region with the conductive layer. The second stacked structure is formed by replacing a portion of the sacrificial layer in the second region with the conductive layer.

24. The method according to claim 23, characterized in that, Also includes: The second contact hole is formed by penetrating at least partially through the second stacked structure to the corresponding sacrificial layer along the first direction; Remove the sacrificial layer from the first portion of the second contact hole to expose the corresponding conductive layer, forming the second portion of the second contact hole; A connection structure is formed in the first portion and the second portion of the second contact hole.

25. The method according to any one of claims 19 to 24, characterized in that, Also includes: A substrate is reformed on the array common source layer.

26. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 1 to 10.

27. A storage system, characterized in that, It includes the memory as described in claim 26 and a controller coupled to the semiconductor device.

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