Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device capable of reducing a chip area and a method for manufacturing the semiconductor device. According to one embodiment, a semiconductor device includes: a first chip having a first substrate on which a first transistor is formed; and a second chip disposed above the first chip and having a second substrate on which a second transistor is formed. The second substrate includes a first insulating film region and a second insulating film region respectively penetrating through the second substrate. The first chip and the second chip are electrically connected via a first through-hole group and a second through-hole group, the first through-hole group includes at least a first through-hole and a second through-hole respectively penetrating through the first insulating film region, and the second through-hole group includes at least a third through-hole and a fourth through-hole respectively penetrating through the second insulating film region. The first through-hole group is arranged at a different pitch from the second through-hole group.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device and a manufacturing method of a semiconductor device. BACKGROUND

[0002] As a semiconductor device, a NAND type flash memory is known. SUMMARY

[0003] Provided is a semiconductor device and a manufacturing method of a semiconductor device capable of reducing a chip area.

[0004] The semiconductor device of the embodiment includes a first chip having a first substrate in which a first transistor is formed, and a second chip disposed above the first chip and having a second substrate in which a second transistor is formed. The second substrate includes a first insulating film region and a second insulating film region each of which penetrates the second substrate. The first chip and the second chip are electrically connected via a first through-hole group and a second through-hole group, the first through-hole group including at least a first through-hole and a second through-hole each of which penetrates the first insulating film region, and the second through-hole group including at least a third through-hole and a fourth through-hole each of which penetrates the second insulating film region. The first through-hole group is arranged at a different pitch from the second through-hole group. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a block diagram showing an example of the overall configuration of a memory system including the semiconductor device of the embodiment.

[0006] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor device of the embodiment.

[0007] Figure 3 is a circuit diagram showing an example of the circuit configuration of a row decoder module included in the semiconductor device of the embodiment.

[0008] Figure 4 is a circuit diagram showing an example of the circuit configuration of a sense amplifier module included in the semiconductor device of the embodiment.

[0009] Figure 5 is a perspective view showing an example of the appearance of the semiconductor device of the embodiment.

[0010] Figure 6 is a plan view showing an example of the planar layout of the semiconductor device of the embodiment.

[0011] Figure 7 is a plan view showing an example of the planar layout of a memory cell array in a core region of the semiconductor device of the embodiment.

[0012] Figure 8is a plan view showing an example of a planar layout in a memory region of a memory cell array included in the semiconductor device of the embodiment.

[0013] Figure 9 is a sectional view showing an example of a cross-sectional structure in a memory region of a memory cell array included in the semiconductor device of the embodiment.

[0014] Figure 10 is a sectional view showing an example of a cross-sectional structure of a memory pillar included in the semiconductor device of the embodiment.

[0015] Figure 11 is a plan view showing an example of a planar layout in a contact region of a memory cell array included in the semiconductor device of the embodiment.

[0016] Figure 12 is a sectional view showing an example of a cross-sectional structure in a contact region of a memory cell array included in the semiconductor device of the embodiment.

[0017] Figure 13 is a sectional view showing an example of a cross-sectional structure of a core region of the semiconductor device of the embodiment.

[0018] Figure 14 is a plan view showing an example of a planar layout of a through-hole in a memory region of the semiconductor device of the embodiment.

[0019] Figure 15 is a plan view showing another example of a planar layout of a through-hole in a memory region of the semiconductor device of the embodiment.

[0020] Figure 16 is a plan view showing an example of a planar layout of a through-hole in a contact region of the semiconductor device of the embodiment.

[0021] Figure 17 is a sectional view showing an example of a cross-sectional structure of a peripheral region of the semiconductor device of the embodiment.

[0022] Figure 18 is a plan view showing an example of a planar layout of a through-hole in a peripheral region of the semiconductor device of the embodiment.

[0023] Figure 19 is a plan view showing an example of a planar layout of a bonding pad in a peripheral region of the semiconductor device of the embodiment.

[0024] Figure 20 is a plan view showing another example of a planar layout of a through-hole in a peripheral region of the semiconductor device of the embodiment.

[0025] Figure 21FIG. 1 is a plan view showing another example of a plan layout of a bonding pad in a peripheral region of a semiconductor device according to an embodiment.

[0026] Figure 22 FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure of a wall region of a semiconductor device according to an embodiment.

[0027] Figure 23 FIG. 3 is a plan view showing an example of a plan layout of a through-hole in a wall region of a semiconductor device according to an embodiment.

[0028] Figure 24 FIG. 4 is a flowchart showing an example of a manufacturing method of a semiconductor device according to an embodiment.

[0029] Figure 25 FIG. 5 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0030] Figure 26 FIG. 6 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0031] Figure 27 FIG. 7 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0032] Figure 28 FIG. 8 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0033] Figure 29 FIG. 9 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0034] Figure 30 FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0035] Figure 31 FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0036] Figure 32 FIG. 12 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0037] Figure 33 FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0038] Figure 34 FIG. 14 is a cross-sectional view showing an example of a cross-sectional structure at a manufacturing intermediate stage of a semiconductor device according to an embodiment.

[0039] Figure 35FIG. 1 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0040] Figure 36 FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0041] Figure 37 FIG. 3 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0042] Figure 38 FIG. 4 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0043] Figure 39 FIG. 5 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0044] Figure 40 FIG. 6 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0045] Figure 41 FIG. 7 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0046] Figure 42 FIG. 8 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0047] Figure 43 FIG. 9 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the embodiment.

[0048] Figure 44 FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a core region of a semiconductor device according to the first modification.

[0049] Figure 45 FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a peripheral region of a semiconductor device according to the first modification.

[0050] Figure 46 FIG. 12 is a cross-sectional view showing an example of a cross-sectional structure of a wall region of a semiconductor device according to the first modification.

[0051] Figure 47 FIG. 13 is a flowchart showing an example of a manufacturing method of a semiconductor device according to the first modification.

[0052] Figure 48 FIG. 14 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device in the middle of manufacturing according to the first modification.

[0053] Figure 49is a cross-sectional view showing an example of a cross-sectional structure of a manufacturing intermediate of a semiconductor device of a first modification example.

[0054] Figure 50 is a cross-sectional view showing an example of a cross-sectional structure of a peripheral region of a semiconductor device of a second modification example.

[0055] Figure 51 is a cross-sectional view showing an example of a cross-sectional structure when a plurality of semiconductor devices of the second modification example are stacked.

[0056] Figure 52 is a cross-sectional view of an XZ plane showing an example of a configuration of another transistor applicable to the semiconductor device of the embodiment, the first modification example, and the second modification example.

[0057] Figure 53 is a cross-sectional view of a YZ plane of the transistor of Figure 52

[0058] Figure 54 is a cross-sectional view of an XZ plane showing an example of a configuration of another transistor applicable to the semiconductor device of the embodiment, the first modification example, and the second modification example.

[0059] Figure 55 is a cross-sectional view of a YZ plane of the transistor of Figure 54 DETAILED DESCRIPTION

[0060] Hereinafter, the embodiment will be described with reference to the drawings.

[0061] The embodiment illustrates a device, a method for embodying the technical idea of the present application. The drawings are schematic or conceptual. The dimensions, ratios, and the like of the respective drawings are not necessarily the same as those in reality. The illustration of the configuration is appropriately omitted. The hatching of the plan view is not necessarily related to the raw material or the characteristics of the constituent element.

[0062] In the present specification, the same reference numerals are attached to constituent elements having substantially the same functions and configurations. The numbers, characters, and the like attached in the reference numerals are referred to by the same reference numerals, and are used to distinguish similar elements from each other.

[0063] <1> Embodiment

[0064] The configuration of the semiconductor device of the embodiment will be described. The semiconductor device of the embodiment includes a memory cell and a CMOS circuit for accessing the memory cell, and has a configuration in which the CMOS circuit is arranged on a plurality of substrates stacked.

[0065] <1-1> Overall configuration of semiconductor device

[0066] Figure 1 ​​is a block diagram showing an example of the overall configuration of a memory system including a semiconductor device according to an embodiment. As shown in Figure 1 The semiconductor device 1 is controlled by an external memory controller 2. The semiconductor device 1 is, for example, a NAND-type flash memory capable of nonvolatile storage of data. The semiconductor device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0067] The memory cell array 10 includes a plurality of data blocks BLK0 to BLKn ("n" is an integer of one or more). A data block BLK is a collection of a plurality of memory cells. The data block BLK corresponds to, for example, a unit of erasing of data. The data block BLK includes a plurality of pages. A page corresponds to a unit of performing readout and writing of data. Although not shown in the drawing, a plurality of bit lines BL0 to BLm ("m" is an integer of one or more) and a plurality of word lines WL are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line BL and one word line WL.

[0068] The input / output circuit 11 is an interface circuit responsible for the transmission and reception of input / output signals between the memory controller 2. The input / output signals include, for example, data DAT, status information, address information, instructions, and the like. The input / output circuit 11 can input and output data DAT between the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 can output status information transmitted from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and instructions transmitted from the memory controller 2 to the register circuit 13, respectively.

[0069] The logic controller 12 controls the input / output circuit 11 and the sequencer 14 based on a control signal input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to activate the semiconductor device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal received by the input / output circuit 11 is an instruction, address information, or the like. The logic controller 12 instructs the input / output circuit 11 to input or output the input / output signal.

[0070] The register circuit 13 temporarily stores status information, address information, and instructions. The status information is updated based on the control of the sequencer 14 and is transmitted to the input / output circuit 11. The address information includes a data block address, a page address, a column address, and the like. The instructions include commands related to various actions of the semiconductor device 1.

[0071] The sequencer 14 controls the overall actions of the semiconductor device 1. The sequencer 14 performs a readout action, a write action, an erase action, and the like based on the instructions and the address information stored in the register circuit 13.

[0072] The driver circuit 15 generates voltages used in a readout operation, a write operation, an erase operation, and the like. Further, the driver circuit 15 supplies the generated voltages to the row decoder module 16, the sense amplifier module 17, and the like.

[0073] The row decoder module 16 is a circuit for selecting a data block BLK as an operation target and transferring a voltage to a wiring such as a word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are respectively associated with the data blocks BLK0 to BLKn for selection of the data blocks BLK. Each row decoder RD transfers a voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0074] The sense amplifier module 17 is a circuit for transferring a voltage to each bit line BL and reading out data. The sense amplifier module 17 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are respectively associated with a plurality of bit lines BL0 to BLm. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on a voltage of the associated bit line BL, a latch circuit that temporarily holds data, and the like.

[0075] Further, a combination of the semiconductor device 1 and the memory controller 2 can also constitute one semiconductor device. As such a semiconductor device, for example, a memory card like an SD card, an SSD (solid state drive), and the like can be cited. TM

[0076] <1-2> Circuit configuration of semiconductor device

[0077] The circuit configuration of the semiconductor device 1 will be described.

[0078] <1-2-1> Circuit configuration of memory cell array

[0079] Figure 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10 included in the semiconductor device 1 according to the embodiment. Figure 2 One of a plurality of data blocks BLK included in the memory cell array 10 is shown. As shown in Figure 2 The data block BLK includes, for example, five string units SU0 to SU4. Select gate lines SGD0 to SGD4 and SGS, and word lines WL0 to WL7 are provided per data block BLK. Bit lines BL0 to BLm and source lines SL are shared among a plurality of data blocks BLK.

[0080] ​Each string unit SU includes a plurality of NAND strings NS. The plurality of NAND strings NS are respectively associated with bit lines BL0 to BLm. That is, each bit line BL is shared by the NAND strings NS to which the same column address is assigned among a plurality of data blocks BLK. Each NAND string NS is connected between an associated bit line BL and a source line SL. Each NAND string NS includes, for example, storage element transistors MT0 to MT7 and selection transistors ST1 and ST2. Each storage element transistor MT is a storage element having a control gate and a charge accumulation layer, and nonvolatilely holds (stores) data. The selection transistors ST1 and ST2 are respectively used for selection of the string unit SU.

[0081] In each NAND string NS, the selection transistor ST1, the storage element transistors MT7 to MT0, and the selection transistor ST2 are connected in series. Specifically, the drain and the source of the selection transistor ST1 are respectively connected to the associated bit line BL and the drain of the storage element transistor MT7. The drain and the source of the selection transistor ST2 are respectively connected to the source of the storage element transistor MT0 and the source line SL. The storage element transistors MT0 to MT7 are connected in series between the selection transistors ST1 and ST2.

[0082] The selection gate lines SGD0 to SGD4 are respectively associated with the string units SU0 to SU4. Each selection gate line SGD is connected to the gate of each of the plurality of selection transistors ST1 included in the associated string unit SU. The selection gate line SGS is connected to the gate of each of the plurality of selection transistors ST2 included in the associated data block BLK. The word lines WL0 to WL7 are respectively connected to the control gates of the storage element transistors MT0 to MT7.

[0083] A set of the plurality of storage element transistors MT connected to a common word line WL within the same string unit SU is referred to as a "cell group CU", for example. The storage capacity of the cell group CU is defined as "1 page of data" in the case where each storage element transistor MT stores 1 bit of data, for example. The cell group CU can have a storage capacity of 2 pages of data or more depending on the number of bits of data stored by each storage element transistor MT.

[0084] Furthermore, the circuit configuration of the storage element array 10 included in the semiconductor device 1 of the embodiment can be other configurations. For example, the number of string units SU included in each data block BLK, and the number of storage element transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0085] <1-2-2> Circuit configuration of row decoder module

[0086] Figure 3is a circuit diagram showing an example of a circuit configuration of a row decoder module 16 included in the semiconductor device 1 according to the embodiment. Figure 3 The connection relationship of the row decoder module 16 with the driver circuit 15 and the memory cell array 10, and the detailed circuit configuration of the row decoder RD0 are shown. As shown in Figure 3 The row decoders RD and the driver circuit 15 are connected via signal lines CG0 to CG7, SGDD0 to SGDD4, SGSD, USGD, and USGS. The row decoders RD and the associated data block BLK are connected via word lines WL0 to WL7, and selection gate lines SGS and SGD0 to SGD4.

[0087] Hereinafter, the connection relationship of each element of the row decoder RD0 with the driver circuit 15 and the data block BLK0 will be described. The other row decoders RD have the same configuration as the row decoder RD0 except for the associated data block BLK. The row decoder RD0 includes, for example, transistors TR0 to TR19, transfer gate lines TG and bTG, and a data block decoder BD.

[0088] The transistors TR0 to TR19 are each a high-voltage N-type MOS transistor (hereinafter, also referred to as "HV (High-Voltage) transistor"). The drain and source of the transistor TR0 are connected to the signal line SGSD and the selection gate line SGS, respectively. The drains of the transistors TR1 to TR8 are connected to the signal lines CG0 to CG7, respectively. The sources of the transistors TR1 to TR8 are connected to the word lines WL0 to WL7, respectively. The drains of the transistors TR9 to TR13 are connected to the signal lines SGDD0 to SGDD4, respectively. The sources of the transistors TR9 to TR13 are connected to the selection gate lines SGD0 to SGD4, respectively. The drain and source of the transistor TR14 are connected to the signal line USGS and the selection gate line SGS, respectively. The drains of the transistors TR15 to TR19 are connected to the signal line USGD. The sources of the transistors TR15 to TR19 are connected to the selection gate lines SGD0 to SGD4, respectively. The gates of the transistors TR0 to TR13 are connected to the transfer gate line TG. The gates of the transistors TR14 to TR19 are connected to the transfer gate line bTG.

[0089] The data block decoder BD is a circuit having a function of decoding a data block address. The data block decoder BD applies prescribed voltages to the transfer gate lines TG and bTG, respectively, on the basis of the decoding result of the data block address. Specifically, the data block decoder BD corresponding to the selected data block BLK applies voltages of "H" level and "L" level to the transfer gate lines TG and bTG, respectively. The data block decoder BD corresponding to the non-selected data block BLK applies voltages of "L" level and "H" level to the transfer gate lines TG and bTG, respectively. Thus, the voltages of the signal lines CGO to CG7 are transferred to the word lines WLO to WL7 of the selected data block BLK, respectively, the voltages of the signal lines SGDDO to SGDD4 and SGSD are transferred to the select gate lines SGD0 to SGD4 and SGS of the selected data block BLK, respectively, and the voltages of the signal lines USGD and USGS are transferred to the select gate lines SGD and SGS of the non-selected data block BLK, respectively.

[0090] Further, the row decoder module 16 can be constituted of other circuits. For example, the number of the transistors TR included in the row decoder module 16 can be changed according to the number of the wirings provided in each data block BLK. Since the signal lines CG are shared among a plurality of data blocks BLK, they can also be called "global word lines". Since the word lines WL are provided for each data block BLK, they can also be called "local word lines". Since the signal lines SGDD and SGSD are shared among a plurality of data blocks BLK, respectively, they can also be called "global transfer gate lines". Since the select gate lines SGD and SGS are provided for each data block BLK, respectively, they can also be called "local transfer gate lines".

[0091] <1-2-3> Circuit configuration of sense amplifier module

[0092] Figure 4 is a circuit diagram showing an example of the circuit configuration of the sense amplifier module 17 included in the semiconductor device 1 according to the embodiment. Figure 4 An extraction shows the circuit configuration of one sense amplifier unit SAU. As shown in Figure 4 The sense amplifier unit SAU includes, for example, a sense amplifier section SA, a bit line connection section BLHU, a latch circuit SDL, ADL, BDL, CDL, and XDL, and a bus LBUS. The sense amplifier section SA and the latch circuit SDL, ADL, BDL, CDL, and XDL are configured to be able to transmit and receive data via the bus LBUS, for example.

[0093] The sense amplifier section SA is a circuit for determining data based on the voltage of the bit line BL, and applying a voltage to the bit line BL. If the control signal STB is set to active at the time of the read operation, the sense amplifier section SA determines whether the data read from the selected memory cell transistor MT is "0" or "1" based on the voltage of the associated bit line BL. The latch circuits SDL, ADL, BDL, CDL, and XDL are circuits each capable of temporarily holding data. The latch circuit XDL is used for input and output of data DAT between the sense amplifier unit SAU and the input and output circuit 11. The latch circuit XDL can also be used as a buffer memory.

[0094] The sense amplifier section SA includes transistors TR30 to TR37, a capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection section BLHU is a switching circuit for preventing a high voltage applied to the channel of the NAND string NS in the erase operation from being applied to the circuit in the sense amplifier section SA. The bit line connection section BLHU includes a transistor TR38. The latch circuit SDL includes inverters IV0 and IV1, transistors TR40 and TR41, and nodes SINV and SLAT. The transistor TR30 is a P-type MOS transistor. The transistors TR31 to TR38, TR40, and TR41 are N-type MOS transistors, respectively. The transistor TR38 is an N-type MOS transistor (HV transistor) having a higher withstand voltage than the N-type transistors in the sense amplifier section SA. Hereinafter, a transistor having a lower withstand voltage than the HV transistor will be referred to as an "LV (Low-Voltage) transistor".

[0095] The gate of the transistor TR30 is connected to the node SINV. The source of the transistor TR30 is connected to a power supply line. The drain of the transistor TR30 is connected to the node ND1. The node ND1 is connected to the drains of the transistors TR31 and TR32, respectively. The sources of the transistors TR31 and TR32 are connected to the node ND2 and the SEN, respectively. The node ND2 and the SEN are connected to the source and the drain of the transistor TR33, respectively. The node ND2 is connected to the drains of the transistors TR34 and TR35, respectively. The source of the transistor TR35 is connected to the node SRC. The gate of the transistor TR35 is connected to the node SINV. The node SEN is connected to the gate of the transistor TR36 and one electrode of the capacitor CP. The source of the transistor TR36 is grounded. The drain and the source of the transistor TR37 are connected to the bus line LBUS and the drain of the transistor TR36, respectively. The drain of the transistor TR38 is connected to the source of the transistor TR34. The source of the transistor TR38 is connected to the bit line BL associated with the sense amplifier unit SAU.

[0096] A power supply voltage VDD is applied to the source of the transistor TR30, for example. A ground voltage VSS is applied to the node SRC, for example. The control signals BLX, HLL, XXL, BLC, and STB are input to the gates of the transistors TR31, TR32, TR33, TR34, and TR37, respectively. The control signal BLS is input to the gate of the transistor TR38. The other electrode of the capacitor CP is input with the clock signal CLK.

[0097] The input node and the output node of the inverter IV0 are connected to the nodes SLAT and SINV, respectively. The input node and the output of the inverter IV1 are connected to the nodes SINV and SLAT, respectively. One end and the other end of the transistor TR40 are connected to the node SINV and the bus LBUS, respectively. The gate of the transistor TR40 is input with the control signal STI. One end and the other end of the transistor TR41 are connected to the node SLAT and the bus LBUS, respectively. The gate of the transistor TR41 is input with the control signal STL. The latch circuit SDL holds data at the node SLAT and holds inverted data of the data held at the node SLAT at the node SINV.

[0098] The circuit configuration of the latch circuits ADL, BDL, CDL, and XDL is similar to that of the latch circuit SDL. For example, the latch circuit ADL holds data at the node ALAT and holds inverted data thereof at the node AINV. Also, the gate of the transistor TR40 of the latch circuit ADL is input with the control signal ATI, and the gate of the transistor TR41 of the latch circuit ADL is input with the control signal ATL. The latch circuit BDL holds data at the node BLAT and holds inverted data thereof at the node BINV. Also, the gate of the transistor TR40 of the latch circuit BDL is input with the control signal BTI, and the gate of the transistor TR41 of the latch circuit BDL is input with the control signal BTL. The same applies to the latch circuits CDL and XDL, and thus the description thereof is omitted.

[0099] Further, the control signals BLX, HLL, XXL, BLC, STB, BLS, STI, and STL, and the clock signal CLK are generated by the sequencer 14, for example, respectively. The sense amplifier module 17 can also have other circuit configurations. For example, the number of latch circuits included in each sense amplifier unit SAU can be changed according to the number of bits stored in the memory cell transistor MT, or the like. The sense amplifier unit SAU can also have an operation circuit capable of performing a simple logical operation. The sense amplifier module 17 can determine (decide) the data stored in the memory cell transistor MT by appropriately performing an operation process using the latch circuit in the readout operation of each page.

[0100] <1-3> Configuration of semiconductor device

[0101] The configuration of the semiconductor device 1 will be described. In the following drawings referred to, a three-dimensional orthogonal coordinate system is used. The X direction corresponds to the extending direction of the word line WL. The Y direction corresponds to the extending direction of the bit line BL. The Z direction corresponds to the vertical direction with respect to the surface of the substrate taken as a reference. In this specification, "up and down" is defined based on the direction along the Z direction, and the direction away from the substrate taken as a reference is taken as the positive direction (up). As the substrate taken as a reference, for example, the substrate disposed at the lowermost portion in the drawing is used. The surface of the substrate corresponds to the side face on which the transistor (CMOS circuit) is formed. The back surface of the substrate corresponds to the side face opposite to the surface.

[0102] <1-3-1> Appearance of Semiconductor Device

[0103] The appearance of the semiconductor device 1 of the embodiment will be described. The semiconductor device 1 of the embodiment is formed by joining three semiconductor circuit substrates each of which is formed with a semiconductor circuit, and separating the joined semiconductor circuit substrates by each chip. That is, the semiconductor device 1 of the embodiment has a joining surface formed by joining the semiconductor substrates W1 and W2, and a joining surface formed by joining the semiconductor substrates W2 and W3. Hereinafter, a case where the semiconductor substrate W3 is removed during the manufacturing process of the semiconductor device 1 will be described. According to the configuration of the memory cell array 10, a part of the semiconductor substrate W3 can also remain after the semiconductor substrates W2 and W3 are joined.

[0104] Figure 5 is a perspective view showing an example of the appearance of the semiconductor device 1 of the embodiment. As shown in Figure 5 , the semiconductor device 1 has, for example, a configuration in which the semiconductor substrate W1, the first CMOS layer 100, the semiconductor substrate W2, the second CMOS layer 200, the memory layer 300, and the wiring layer 400 are stacked in this order from the lower side.

[0105] The first CMOS layer 100 includes CMOS circuits formed using the semiconductor substrate Wl. The second CMOS layer 200 includes CMOS circuits formed using the semiconductor substrate W2. The group of the first CMOS layer 100 and the second CMOS layer 200 includes, for example, the input / output circuit 11, the logic controller 12, the register circuit 13, the sequencer 14, the driver circuit 15, the row decoder module 16, and the sense amplifier module 17. The memory layer 300 includes the memory cell array 10 formed using the semiconductor substrate W3 (not shown). The wiring layer 400 includes, for example, a plurality of pads PD used for connection of the semiconductor device 1 and the memory controller 2. The pads PD are connected to the input / output circuit 11 and are exposed on the surface of the semiconductor device 1. Hereinafter, the semiconductor substrate Wl and the first CMOS layer 100 will be collectively referred to as "the first CMOS chip CCP1". The semiconductor substrate W2 and the second CMOS layer 200 will be collectively referred to as "the second CMOS chip CCP2". The memory layer 300 and the wiring layer 400 will be collectively referred to as "the array chip ACP".

[0106] The semiconductor substrate Wl, the semiconductor substrate W2, and the semiconductor substrate W3 are, for example, silicon substrates. The semiconductor substrate Wl and the semiconductor substrate W2 each have an impurity diffusion region corresponding to the circuit design of the semiconductor device 1. The thickness of the semiconductor substrate W2 is, for example, thinner than the thickness of the semiconductor substrate Wl. The semiconductor device 1 has a bonding surface between the adjacent substrates. In an embodiment, the contact (boundary) portion of the first CMOS layer 100 and the semiconductor substrate W2 and the contact (boundary) portion of the second CMOS layer 200 and the memory layer 300 each correspond to the bonding surface. The bonding surface is a surface formed by bonding two wafers (substrates) and corresponds to the boundary portion of the two substrates to be bonded. A layer in which circuits such as the first CMOS layer 100 are formed can be interposed between the two substrates to be bonded. In this specification, the process of bonding two substrates will be referred to as "bonding process".

[0107] <1-3-2> Planar layout of semiconductor device

[0108] Figure 6 is a plan view showing an example of the planar layout of the semiconductor device 1 according to the embodiment. As shown in Figure 6 , the semiconductor device 1 includes, for example, a core region CR, a peripheral region PR, a wall region WR, and a cutout region KR.

[0109] The core region CR is, for example, a rectangular region provided near the center of the semiconductor substrate Wl. In the core region CR, for example, the memory cell array 10, the register circuit 13, the sequencer 14, the driver circuit 15, the row decoder module 16, and the sense amplifier module 17 are arranged.

[0110] The peripheral region PR is a quadrangular ring-shaped region provided in a manner of surrounding the outer periphery of the core region CR. In the peripheral region PR, for example, an input / output circuit 11, a logic controller 12, and the like are arranged. In the peripheral region PR, for example, a contact and the like that connects a wiring provided in the wiring layer 400 to a circuit provided in the first CMOS layer 100, the second CMOS layer 200, and the memory layer 300 are arranged.

[0111] The wall region WR is a quadrangular ring-shaped region provided in a manner of surrounding the outer periphery of the peripheral region PR. In the wall region WR, at least one sealing portion ES (not shown) provided in a manner of surrounding the outer periphery of the peripheral region PR is arranged. Details of the sealing portion ES will be described later.

[0112] The cutout region KR is a quadrangular ring-shaped region provided in a manner of surrounding the outer periphery of the wall region WR. The cutout region KR is in contact with the outermost periphery of the semiconductor device 1. In the cutout region KR, for example, an alignment mark and the like used at the time of manufacturing the semiconductor device 1 are arranged.

[0113] <1-3-3> Planar layout of memory cell array

[0114] Figure 7 is a plan view showing an example of a planar layout of the memory cell array 10 in the core region CR of the semiconductor device 1 according to the embodiment. Figure 7 Regions corresponding to the four data blocks BLK0 to BLK3 included in the memory cell array 10 are shown. As shown in Figure 7 the memory cell array 10 includes, for example, a plurality of slits SLT and a plurality of slits SHE. In addition, the memory cell array 10 includes, for example, a memory region MA arranged in the X direction and a contact region CA.

[0115] Each slit SLT has a portion extending in the X direction and crosses the contact region CA and the memory region MA in the X direction. A plurality of slits SLT are arranged in the Y direction. Each slit SLT disconnects wirings (for example, the word lines WL0 to WL7 and the selection gate lines SGD and SGS) adjacent via the slit SLT. In each slit SLT, a conductor of a spacer having an insulator provided on a side wall can be arranged to be insulated from the wirings, or can be embedded with an insulator. In the memory cell array 10, regions divided by the slits SLT each correspond to one data block BLK.

[0116] Each of the slits SHE has a portion extending along the X direction and crosses the memory area MA along the X direction. The plurality of slits SHE are arranged in the Y direction. In this example, four slits SHE are respectively arranged between two slits SLT adjacent in the Y direction. Each of the slits SHE has, for example, a configuration in which an insulator is buried. Each of the slits SHE disconnects a wiring (at least, the selection gate line SGD) adjacent via the slit SHE. In the memory cell array 10, the regions divided by the slits SLT and SHE respectively correspond to one string unit SU.

[0117] Further, the planar layout of the memory cell array 10 included in the semiconductor device 1 of the embodiment can also be other layouts. For example, the number of the slits SHE arranged between two slits SLT adjacent can be designed to be any number. The number of the string units SU included in each data block BLK can be changed based on the number of the slits SHE arranged between two slits SLT adjacent.

[0118] <1-3-4> Planar layout of memory area

[0119] Figure 8 is a plan view showing an example of the planar layout in the memory area MA of the memory cell array 10 included in the semiconductor device 1 of the embodiment. Figure 8 A region including one data block BLK (string units SU0 to SU4) is shown. As shown in Figure 8 The semiconductor device 1 includes, for example, a plurality of memory pillars MP, a plurality of contact pieces CV, and a plurality of bit lines BL in the memory area MA.

[0120] Each of the memory pillars MP functions as one NAND string NS. The plurality of memory pillars MP are arranged, for example, in a staggered shape of 24 columns in the region between two slits SLT adjacent. For example, a slit SHE is arranged in an overlapping manner with the memory pillar MP of the 5th column, the memory pillar MP of the 10th column, the memory pillar MP of the 15th column, and the memory pillar MP of the 20th column, respectively, counted from the upper side of the paper.

[0121] Each of the bit lines BL has a portion extending along the Y direction. The plurality of bit lines are arranged in the X direction. Each of the bit lines BL is arranged in an overlapping manner with at least one memory pillar MP per string unit SU. In this example, two bit lines BL are arranged in an overlapping manner with one memory pillar MP. The memory pillar MP and one of the plurality of bit lines BL arranged in an overlapping manner are electrically connected via the contact piece CV. In addition, the contact piece CV between the memory pillar MP and the bit line BL connected to different two selection gate lines SGD can be omitted.

[0122] Furthermore, the planar layout in the memory area MA of the memory cell array 10 included in the semiconductor device 1 of the embodiment can also be other layouts. For example, the number of the memory pillars MP, the slits SHE, and the like arranged between the two adjacent slits SLT can be appropriately changed. The number of the bit lines BL overlapping with each memory pillar MP can be designed to be any number.

[0123] <1-3-5> Cross-sectional configuration of memory area

[0124] Figure 9 is a cross-sectional view along the IX-IX line of Figure 8 of the semiconductor device 1 of the embodiment. The cross-sectional view along the IX-IX line of Figure 9 represents an example of the configuration of the memory cell array 10 formed in the semiconductor substrate W3 before being bonded to the semiconductor substrate W2, and represents the coordinate axes based on the semiconductor substrate W3. As shown in Figure 9 indicated, the memory cell array 10 includes, for example, the conductive layers 21 to 25, the insulator layers 31 to 35, the insulating member 36, and the contact pieces CV, V1, and V2 in the memory area MA.

[0125] The conductive layer 21 is provided on the semiconductor substrate W3. On the conductive layer 21, the insulator layer 31 is provided. On the insulator layer 31, the conductive layer 22 and the insulator layer 32 are alternately provided. That is, a plurality of conductive layers 22 are arranged in the Z direction. The number of layers of the conductive layers 22 corresponds to, for example, the number of layers of the stacked wiring (the selection gate line SGS, the word line WL, and the selection gate line SGD). On the uppermost conductive layer 22, the insulator layer 33, the conductive layer 23, the insulator layer 34, and the insulator layer 35 are sequentially provided. The conductive layers 21 and 22 are each formed into a plate shape extending along the XY plane, for example. The conductive layer 23 has, for example, a portion formed into a line shape extending in the Y direction. The conductive layer 21 functions as the source line SL. In this example, the 10 layers of the conductive layers 22 arranged in the Z direction function as the selection gate line SGS, the word lines WL0 to WL7, and the selection gate line SGD from the side of the source line SL. The conductive layer 23 functions as the bit line BL. The conductive layer 21 includes, for example, polysilicon (Si). The conductive layer 22 includes, for example, tungsten (W). The conductive layer 23 includes, for example, copper (Cu). The conductive layer 23 is included in the wiring layer M0.

[0126] A conductive layer 24 is provided above the conductive layer 23. The conductive layer 24 is a wiring that relays connection of the bit line BL and the read amplifier module 17. The conductive layer 23 and the conductive layer 24 are connected via a contact V1. A conductive layer 25 is provided above the conductive layer 24. The conductive layer 25 corresponds to a bonding pad BP for bonding of the semiconductor substrate W2 and the semiconductor substrate W3. The conductive layer 24 and the conductive layer 25 are connected via a contact V2. The side surface of the conductive layer 24 and the contacts V1 and V2 are covered with an insulating layer 34. The insulating layer 34 can be composed of a plurality of insulating films. The side surface of the conductive layer 25 is covered with an insulating layer 35. The memory cell array 10 can include a plurality of conductive layers 24 and a plurality of conductive layers 25. The conductive layer 24 includes, for example, copper. The conductive layer 24 is included in the wiring layer M1. The conductive layer 25 includes, for example, copper. The insulating layer 35 and the conductive layer 25 are included in the bonding layer B1.

[0127] The insulating member 36 has a portion formed in a plate shape extending along the XZ plane. The insulating member 36 disconnects the insulating layer 31 and the conductive layer 22 and the insulating layer 32 alternately provided. In the present example, the insulating member 36 is embedded in the slit SLT. In the slit SLT, the conductive body with the spacer having the insulating body provided to the side wall can be disposed separately from the conductive layers 21 and 22.

[0128] Each memory pillar MP is provided extending along the Z direction, penetrates the insulating layer 31 and the conductive layer 22 and the insulating layer 32 alternately provided, and is connected to the conductive layer 21. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a laminated film 42. The core member 40 is an insulating body provided extending along the Z direction. The semiconductor layer 41 covers the core member 40. A part of the side surface of the semiconductor layer 41 is in contact with the conductive layer 21. That is, the semiconductor layer 41 in the memory pillar MP and the conductive layer 21 (the source line SL) are connected via the side surface of the memory pillar MP. The laminated film 42 covers the side surface and the bottom surface of the semiconductor layer 41 except for the contact portion of the semiconductor layer 41 and the conductive layer 21. Connection is established between the corresponding semiconductor layer 41 (the memory pillar MP) and the conductive layer 23 (the bit line BL) via the contact CV.

[0129] The portion of the conductive layer 22 that crosses the memory pillar MP as the selection gate line SGS functions as the selection transistor ST2. The portion of the conductive layer 22 that crosses the memory pillar MP as the word line WL functions as the memory cell transistor MT. The portion of the conductive layer 22 that crosses the memory pillar MP as the selection gate line SGD functions as the selection transistor ST1. In each memory pillar MP, the semiconductor layer 41 functions as the channel (current path) of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2 included in the NAND string NS.

[0130] <1-3-6> Cross-sectional configuration of memory pillar

[0131] Figure 10 is a cross-sectional view along the X-X line of an example of a cross-sectional configuration of a memory pillar MP included in the semiconductor device 1 of the embodiment. Figure 9 Figure 10 represents a cross section including the memory pillar MP and the conductor layer 22 and parallel to the surface of the semiconductor substrate W3. As shown in Figure 10 The laminated film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a barrier insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The barrier insulating film 45 surrounds the side surface of the insulating film 44. The conductor layer 22 surrounds the side surface of the barrier insulating film 45. The tunnel insulating film 43 and the barrier insulating film 45 each include, for example, silicon oxide (SiO2). The insulating film 44 serves as a charge accumulation layer of the memory cell transistor MT. The insulating film 44 includes, for example, silicon nitride (SiN).

[0132] <1-3-7> Planar layout of contact region

[0133] Figure 11 is a plan view representing an example of a planar layout in the contact region CA of the memory cell array 10 included in the semiconductor device 1 of the embodiment. Figure 11 Also shown is the memory region MA in the vicinity of the contact region CA. As shown in Figure 11 In the contact region CA, for example, the end portions of each of the selection gate line SGS, the word lines WL0 to WL7, and the selection gate line SGD have platform portions.

[0134] The platform portions correspond to portions in the laminated wiring that do not overlap with the upper wiring layer (conductor layer). The configuration formed by the plurality of platform portions is similar to a step, a terrace, a rimstone, or the like. In this example, a step configuration having a step difference in the X direction is formed by the end portion of the selection gate line SGS, the end portion of each of the word lines WL0 to WL7, and the end portion of the selection gate line SGD. In other words, the step difference is formed between the selection gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, between the word line WL6 and the word line WL7, and between the word line WL7 and the selection gate line SGD, respectively.

[0135] ​Additionally, the semiconductor device 1 includes multiple contacts CC in the data block BLK of the contact area CA. The contacts CC are components used for the connection between the line decoder module 16 and the stacked wiring. Each contact CC is connected to any one of the platform portions of the stacked wiring in the memory cell array 10, i.e., the multiple conductive layers 22 (select gate line SGS, word lines WL0 to WL7, and select gate line SGD), which are disposed in the data block BLK.

[0136] Furthermore, an example is shown where the contact element CC is connected to the platform portion formed in the contact area CA, but this is not a limitation. Even if the contact area CA does not have a platform portion, the semiconductor device 1 can still be configured such that a certain contact element CC and the associated wiring group are not short-circuited to ground with other wiring.

[0137] <1-3-8> Cross-sectional structure of the contact area

[0138] Figure 12 This is an example of the cross-sectional structure of the contact region CA of the memory cell array 10 included in the semiconductor device 1 of the embodiment, along... Figure 11 A sectional view of line XII-XII. Figure 12 This indicates the structure formed in the contact region CA of the memory cell array 10 on the semiconductor substrate W3 before the bonding process, and the memory region MA near the contact region CA. For example... Figure 12 As shown, the ends of each of the plurality of conductive layers 22 are stepped and covered by an insulating layer 33. In the contact region CA, insulating layers 34 and 35 are stacked on the insulating layer 33. In addition, the semiconductor device 1 includes, for example, a plurality of contacts CC, a plurality of contacts V1 and V2, and a plurality of conductive layers 26, 27 and 28 in the contact region CA.

[0139] Multiple contacts CC are respectively disposed on the platform portions of the select gate line SGS, word lines WL0 to WL7, and select gate line SGD. Each contact CC penetrates the insulating layer 33. A conductive layer 26 is disposed above each of the multiple contacts CC. A contact V1 is disposed on each conductive layer 26. Figure 12Only the contact V1 corresponding to the selection gate line SGS among the plurality of contacts V1 is shown. On the contact V1, the conductive layer 27 is provided. On the conductive layer 27, the contact V2 is provided. The conductive layers 26 and 27 and the plurality of contacts V2 and V1 are covered with the insulator layer 34. On the contact V2, the conductive layer 28 is provided through the insulator layer 35. The conductive layer 28 corresponds to the bonding pad BP for the bonding of the semiconductor substrate W2 and the semiconductor substrate W3. The conductive layer 26 contains, for example, copper. The conductive layer 26 is contained in the wiring layer M0. The conductive layer 27 contains, for example, copper. The conductive layer 27 is contained in the wiring layer M1. The conductive layer 28 contains, for example, copper. The conductive layer 28 is contained in the bonding layer B1.

[0140] The group of the conductive layers 26, 27, and 28 and the contacts CC, V1, and V2 described above corresponds to the wiring and the contacts for connecting any one of the plurality of conductive layers 22 and the row decoder module 16. Although the illustration is omitted, the plurality of conductive layers 22 other than the selection gate line SGS are also connected to the row decoder module 16 via the group of the conductive layers 26, 27, and 28 and the contacts CC, V1, and V2, respectively, in the same manner.

[0141] <1-3-9> Cross-sectional configuration of semiconductor device

[0142] Figure 13 is a sectional view showing an example of a cross-sectional configuration of the core region CR of the semiconductor device 1 according to the embodiment. Figure 13 shows a cross section in the core region CR of the semiconductor device 1 including the memory region MA and the contact region CA, and shows the coordinate axes with the semiconductor substrate W1 as a reference. Further, Figure 13 shows a state after the semiconductor substrate W3 is removed. As Figure 13 indicated, the semiconductor device 1 has a configuration in which the memory region MA shown in Figure 9 is inverted upside down and a configuration in which the contact region CA shown in Figure 12 is inverted upside down, corresponding to the memory layer 300. The semiconductor device 1 includes the insulator layers 50 and 51, the conductive layers GC1 and 52 to 54, and the contacts 55 to 59 corresponding to the first CMOS layer 100. The semiconductor device 1 includes the insulator layers 70 and 71, the conductive layers GC2 and 72 to 75, and the contacts 59 and 76 to 80 corresponding to the second CMOS layer 200. The semiconductor device 1 includes the insulator layer 91, the insulator layer 92, the conductive layer 93, the insulator layer 94, the insulator layer 95, and the insulator layer 96 corresponding to the wiring layer 400.

[0143] Hereinafter, a region corresponding to the memory region MA of the first CMOS chip CCP1 is referred to as "region Alm". A region corresponding to the contact region CA of the first CMOS chip CCP1 is referred to as "region Alc". A region corresponding to the memory region MA of the second CMOS chip CCP2 is referred to as "region A2m". A region corresponding to the contact region CA of the second CMOS chip CCP2 is referred to as "region A2c".

[0144] The insulator layer 50 is provided on the semiconductor substrate Wl. The insulator layer 50 covers the circuit (e.g., the conductive layers GC1 and 52 to 54, and the contact 55 to 59) provided on the semiconductor substrate Wl. The insulator layer 50 can be composed of a plurality of insulator layers. Further, the insulator layer 50 successively includes the wiring layers DO, Dl, and D2 from the side of the semiconductor substrate Wl. The wiring of the first CMOS layer 100 is provided in the wiring layers DO, Dl, and D2. The insulator layer 51 is provided on the insulator layer 50. The insulator layer 51 is in contact with the back surface of the semiconductor substrate W2. The boundary portion of the insulator layer 51 and the semiconductor substrate W2 corresponds to the bonding surface between the semiconductor substrate Wl and the semiconductor substrate W2 (the first CMOS chip CCP1 and the second CMOS chip CCP2). The insulator layer 51 contains, for example, silicon oxide. Hereinafter, the layer including the insulator layer 51 is referred to as "bonding layer B2".

[0145] The insulator layer 70 is provided on the semiconductor substrate W2. The insulator layer 70 covers the circuit (e.g., the conductive layers GC2 and 72 to 74, and the contacts 59 and 76 to 80) provided on the semiconductor substrate W2. The insulator layer 70 can be composed of a plurality of insulator layers. Further, the insulator layer 70 successively includes the wiring layers D3, D4, and D5 from the side of the semiconductor substrate Wl. The wiring of the second CMOS layer 200 is provided in the wiring layers D3, D4, and D5. Further, the number of the wiring layers of the second CMOS layer 200 can be different from the number of the wiring layers of the first CMOS layer 100. The insulator layer 71 is provided on the insulator layer 70. The insulator layer 71 is in contact with the insulator layer 35 included in the memory layer 300. The boundary of the insulator layer 71 and the insulator layer 35 corresponds to the bonding surface between the semiconductor substrate W2 and the semiconductor substrate W3 (the second CMOS chip CCP2 and the array chip ACP). The insulator layer 71 contains, for example, silicon oxide. Hereinafter, the layer including the insulator layer 71 is referred to as "bonding layer B3".

[0146] The conductive layer GC1 is provided on the gate insulating film provided on the semiconductor substrate W1. The contact 55 is provided on the conductive layer GC1. The two contacts 56 included in the region Alm are connected to two impurity diffusion regions provided on the semiconductor substrate W1. For example, the two impurity diffusion regions correspond to the source and the drain of the transistor TRa, respectively. Similarly, the two contacts 56 included in the region Alc are connected to two impurity diffusion regions provided on the semiconductor substrate W1. For example, the two impurity diffusion regions correspond to the source and the drain of the transistor TRc, respectively. In the semiconductor substrate W1, an STI (Shallow Trench Isolation) is provided as appropriate in accordance with the layout of the transistors. The STI is provided to electrically separate the transistors from other elements. The STI (hereinafter, also referred to as an "insulating film region STI") surrounds an active region AA of the transistor. The active region AA is a region where the transistor is provided. The active region AA includes, for example, the gate insulating film, the conductive layer GC1, and the two impurity diffusion regions. The insulating film region STI is in contact with the impurity diffusion regions. The transistor TRa is included in, for example, the sense amplifier module 17. The transistor TRa is, for example, an HV transistor (transistor TR38) in the sense amplifier unit SAU. The transistor TRc is included in, for example, the row decoder module 16. The transistor TRc is, for example, an HV transistor (transistor TR0) in the row decoder RD. The row decoder RD is included in the first CMOS chip CCP1.

[0147] The semiconductor substrate W1 and the transistors provided on the semiconductor substrate W1 receive heat of about 1000 °C in the activation anneal process described later at the time of manufacturing the semiconductor device 1. Thus, the thickness of the semiconductor substrate W1 is set to be thicker than that of the semiconductor substrate W2 in consideration of heat resistance. In addition, the HV transistor is provided in the semiconductor substrate W1 in consideration of heat resistance. The thickness of the semiconductor substrate W1 where the HV transistor is provided is relatively thick because the depletion layer of the HV transistor is relatively likely to expand. Note that the transistors provided on the semiconductor substrate W1 can be LV transistors that withstand heat in the activation anneal process.

[0148] The conductive layer 52 is provided on each of the contact 55 and the contact 56. The conductive layer 52 is included in the wiring layer DO. The conductive layer 53 is provided on the conductive layer 52 via the contact 57. The conductive layer 53 is included in the wiring layer Dl. On the conductive layer 53, the conductive layer 54 is provided via the contact 58. The conductive layer 54 is included in the wiring layer D2. The conductive layers 52 to 54 receive heat of about 1000°C at the time of manufacture by an activation annealing process. Therefore, as the material of the conductive layers 52 to 54, a conductive material having a relatively high melting point is used. The conductive layers 52 to 54 include, for example, tungsten. The contact 59 is provided on the conductive layer 54. The contact 59 is provided through the semiconductor substrate W2 and the insulator layer 51. The contact 59 and the semiconductor substrate W2 are insulated by the insulating film region INS. That is, the semiconductor substrate W2 includes the insulating film region INS that penetrates the semiconductor substrate W2. The semiconductor substrate W2 includes a plurality of insulating film regions INS. Further, the thickness of the insulating film region STI is thinner than the thickness of the insulating film region INS. The contact 59 corresponds to a via. A plurality of contacts 59 penetrate the insulating film region INS. That is, a plurality of contacts 59 penetrate the insulating film region INS provided in the semiconductor substrate W2. The contact 59 includes, for example, tungsten or copper. The insulating film region INS includes, for example, silicon oxide or silicon nitride. Hereinafter, the contact 59 is referred to as a "via 59". A plurality of vias 59 that penetrate one insulating film region INS are referred to as a "via group Gv". A plurality of wirings that are respectively provided in the same layer and contact the via group Gv are referred to as a "wiring group Gi".

[0149] The conductive layer GC2 is provided on the gate insulating film provided on the semiconductor substrate W2. The contact 76 is provided on the conductive layer GC2. The two contacts 77 included in the region A2m are connected to two impurity diffusion regions provided in the semiconductor substrate W2. The two impurity diffusion regions correspond to, for example, the source and the drain of the transistor TRb, respectively. In the semiconductor substrate W2, the STI is appropriately provided in accordance with the layout of the transistor. The transistor TRb is included, for example, in the sense amplifier module 17. The transistor TRb is, for example, an LV transistor (transistor TR34) in the sense amplifier unit SAU. The LV transistor operates faster than the HV transistor. The sense amplifier unit SAU is included in the first CMOS chip CCP1 and the second CMOS chip CCP2.

[0150] For thinning of the semiconductor device 1, the thickness of the semiconductor substrate W2 is set to be thinner than the thickness of the semiconductor substrate W1. Therefore, for example, an LV transistor is provided in the semiconductor substrate W2. Further, the transistor provided in the semiconductor substrate W2 can be, for example, an MOS transistor (hereinafter, also referred to as "VLV (Very-Low-Voltage) transistor") of a lower voltage resistance than the LV transistor, or can be an MOS transistor (hereinafter, also referred to as "HVN (High-Voltage-Negative) transistor") of a high voltage resistance that can operate even if the thickness of the semiconductor substrate W2 is relatively thin. The HVN transistor is an N-type HV transistor.

[0151] The gate length of the transistors TRa and TRc, which are HV transistors, is longer than the gate length of the transistor TRb, which is an LV transistor. The size relationship of the gate lengths of the VLV transistor, the LV transistor, and the HV transistor is, for example, VLV transistor < LV transistor < HV transistor. Further, the film thickness of the gate insulating films of the transistors TRa and TRc is thicker than the film thickness of the gate insulating film of the transistor TRb. The size relationship of the film thicknesses of the gate insulating films of the VLV transistor, the LV transistor, and the HV transistor is VLV transistor < LV transistor < HV transistor.

[0152] The conductive layer 72 is provided on each of the contact 76 and 77 and the through-hole 59. The conductive layer 72 is included in the wiring layer D3. The position of the upper surface of each of the plurality of through-holes 59 included in the insulating film region INS is the same as the position of the upper surface of the contact 76 and 77. The conductive layer 73 is provided on the conductive layer 72 via the contact 78. The conductive layer 73 is included in the wiring layer D4. The conductive layer 73 can be provided in a current path between the contact 77 and the through-hole 59, or can be provided in a current path between the through-hole 59 and the bonding pad BP. In the example of FIG. 6, the conductive layer 73 is provided in a current path between the contact 76 and the through-hole 59. Figure 13 In the example of FIG. 6, the source or drain of the transistor TRa is electrically connected to the source or drain of the transistor TRb via the contacts 56 to 58, the through-hole 59, the contacts 78 and 77, and the conductive layers 52 to 54, 72, and 73. The conductive layer 74 is provided on the conductive layer 73 via the contact 79. The conductive layer 74 is included in the wiring layer D5. The conductive layers 72 to 74 include, for example, copper. The conductive layer 75 is provided on the conductive layer 74 via the contact 80. The conductive layer 75 is included in the bonding layer B3. The conductive layer 75 corresponds to the bonding pad BP for bonding of the semiconductor substrate W2 and the semiconductor substrate W3. The conductive layer 75 includes, for example, copper.

[0153] With the above configuration, in the storage region MA and the contact region CA, the first CMOS chip CCP1 and the second CMOS chip CCP2 are electrically connected via the group Gv of through-holes included in the insulating film region INS.

[0154] In the storage region MA, the via group Gv including the plurality of vias 59 of the via insulating film region INS is connected to the wiring group Gi including the plurality of conductive layers 54 (wirings) provided in the wiring layer D2. One of the plurality of conductive layers 54 included in the wiring group Gi of the wiring layer D2 is electrically connected to the conductive layer 52 (wiring) electrically connected to one of the source or drain of the transistor TRa. Another of the plurality of conductive layers 54 included in the wiring group Gi of the wiring layer D2 is electrically connected to the conductive layer 52 (wiring) electrically connected to the other of the source or drain of the transistor TRa. Further, the via group Gv including the plurality of vias 59 of the via insulating film region INS is connected to the wiring group Gi including the plurality of conductive layers 72 provided in the wiring layer D3. Of the plurality of conductive layers 72 included in the wiring group Gi of the wiring layer D3, the conductive layer 72 electrically connected to the other of the source or drain of the transistor TRa via the conductive layers 52 and 54 and the via 59 is electrically connected to the conductive layer 72 (wiring) electrically connected to one of the source or drain of the transistor TRb.

[0155] In the contact region CA, the via group Gv including the plurality of vias 59 of the via insulating film region INS is connected to the wiring group Gi including the plurality of conductive layers 54 (wirings) provided in the wiring layer D2. One of the plurality of conductive layers 54 included in the wiring group Gi of the wiring layer D2 is electrically connected to the conductive layer 52 (wiring) electrically connected to one of the source or drain of the transistor TRc. Further, the via group Gv including the plurality of vias 59 of the via insulating film region INS is connected to the wiring group Gi including the plurality of conductive layers 72 provided in the wiring layer D3.

[0156] In the storage region MA, the conductive layer 25 disposed opposite to the conductive layer 75 is connected. The conductive layer 25 is connected to the conductive layer 23 (bit line BL) with which the association is established via the contacts VI and V2 and the conductive layer 24. Thus, the conductive layer 23 (bit line BL) is connected to the transistor TRa provided on the semiconductor substrate Wl via the contacts VI, V2, 78 to 80 and 56 to 58, the via 59, and the conductive layers 24, 25, 72 to 75 and 52 to 54. The other conductive layers 23 are also connected to the other transistors provided on the semiconductor substrate Wl, respectively, in the same manner.

[0157] In the contact region CA, the oppositely arranged conductor layer 28 is in contact with the conductor layer 75. The conductor layer 28 is connected to the associated conductor layer 22 (e.g., select gate line SGS) via the contacts V1, V2, and CC and the conductor layers 26 and 27. Thus, the conductor layer 22 (e.g., select gate line SGS) is connected to the transistor TRc provided on the semiconductor substrate W1 via the contacts CC, V1, V2, 78 to 80, and 56 to 58, the via hole 59, and the conductor layers 26 to 28, 72 to 75, and 52 to 54. The other conductor layers 22 are also similarly connected to the other transistors provided on the semiconductor substrate W1, respectively.

[0158] On the conductor layer 21, the insulator layer 91, the insulator layer 92, the conductor layer 93, the insulator layer 94, the insulator layer 95, and the insulator layer 96 are provided in this order. A part of the conductor layer 93 penetrates the insulator layers 91 and 92. The conductor layer 93 can have a part in contact with the conductor layer 21. The insulator layers 91, 92, and 94, for example, each include silicon oxide. The insulator layer 95, for example, includes silicon nitride. The insulator layer 96, for example, includes polyimide.

[0159] Figure 14 is a plan view showing an example of a plan layout of the via holes 59 in the memory area MA of the semiconductor device 1. In Figure 14 , an example in which 14 via holes 59 penetrate the insulating film region INS is shown, and the conductor layers 54 connected to the via holes 59 are shown by broken lines. As shown in Figure 14 , the via holes 59, for example, have a circular cross-sectional shape in the XY plane (a cross section parallel to the surface of the semiconductor substrate W1). If the diameter of the via hole 59 is set to "diameter Dv1" and the pitch (distance) between adjacent two via holes 59 is set to "pitch Pv1", the plurality of via holes 59 having the diameter Dv1 are arranged in a 60° staggered manner (60° staggered arrangement) at the pitch Pv1. In other words, the plurality of via holes 59 are arranged at each vertex of an equilateral triangle, respectively. This arrangement is an arrangement corresponding to a honeycomb structure. Further, the plurality of via holes 59 can be arranged in a square arrangement or in a 45° staggered manner, for example.

[0160] Figure 15 is a plan view showing another example of a plan layout of the via holes 59 in the memory area MA of the semiconductor device 1. As shown in Figure 15 , the plurality of via holes 59 having the diameter Dv1 are arranged in a 45° staggered manner (45° staggered arrangement) at the pitch Pv1. In other words, the plurality of via holes 59 are arranged at each vertex of a square and at the intersection of the diagonals of the square, respectively.

[0161] In the storage region MA, the insulating film region INS formed in the semiconductor substrate W2 is formed, for example, in a region in which the sense amplifier module 17 is arranged (hereinafter, referred to as "sense amplifier region"). In the sense amplifier region, a plurality of through holes 59 are connected to the corresponding bit lines BL. The plurality of through holes 59 are respectively led out to be connected to the corresponding HV transistors of the sense amplifier unit SAU. In addition, the HV transistors are connected to the LV transistors. The through holes 59 for connecting the HV transistors and the LV transistors are also provided in the insulating film region INS. Therefore, the plurality of through holes 59 are respectively connected to mutually different conductive layers 54 (wiring). In addition, the number of the through holes 59 is relatively large, and therefore the plurality of through holes 59 are arranged as close as possible within the insulating film region INS. In order to arrange the largest number of through holes with the smallest area, the plurality of through holes 59 are preferably arranged in a honeycomb structure.

[0162] Figure 16 is a plan view showing an example of a plan layout of the through holes 59 in the contact region CA of the semiconductor device 1. In Figure 16 , an example in which four through holes pass through the insulating film region INS is shown, and the conductive layers 54 connected to the through holes 59 are shown by broken lines. As shown in Figure 16 , the through holes 59 have, for example, a circular cross-sectional shape in the XY plane. If the diameter of the through hole 59 is set to "diameter Dv1" and the pitch between adjacent two through holes 59 is set to "pitch Pv2", the plurality of through holes 59 having the diameter Dv1 are arranged in a square with the pitch Pv2. That is, the arrangement of the through hole group Gv that passes through the insulating film region INS formed in the contact region CA is different from the arrangement of the through hole group Gv that passes through the insulating film region INS formed in the storage region MA. In addition, the plurality of through holes 59 can be arranged, for example, in a 60° staggered manner, or can be arranged in a 45° staggered manner.

[0163] In the contact region CA, the insulating film region INS formed in the semiconductor substrate W2 is formed, for example, in a region in which the row decoder module 16 is arranged (hereinafter, referred to as "row decoder region"). In the row decoder region, a plurality of through holes 59 are connected to the corresponding word lines WL. The plurality of through holes 59 are respectively led out to be connected to the corresponding transistors of the row decoder RD. Therefore, the plurality of through holes 59 are respectively connected to mutually different conductive layers 54 (wiring). In addition, although the number of the through holes 59 is relatively large, since a relatively high voltage is applied to the row decoder RD, the pitch between adjacent two through holes 59 is set to a distance at which the withstand voltage between the adjacent two through holes 59 can be ensured. Therefore, the pitch Pv2 is larger than the pitch Pv1. That is, the through hole group Gv that passes through the insulating film region INS formed in the contact region CA is arranged at a different pitch from the through hole group Gv that passes through the insulating film region INS formed in the storage region MA.

[0164] Figure 17 FIG. 6 is a cross-sectional view showing an example of a cross-sectional configuration of a peripheral region PR of the semiconductor device 1 according to the embodiment. Figure 17 The cross section of the semiconductor device 1 including the peripheral region PR is shown, and the coordinate axes with the semiconductor substrate W1 as a reference are shown. Further, Figure 17 A state after the semiconductor substrate W3 is removed is shown.

[0165] In the peripheral region PR, the first CMOS layer 100 includes the insulator layers 50 and 51, the conductive layers GC1 and 52 to 54, the contacts 55 to 58, and the via 59, like the core region CR. The first CMOS layer 100 further includes the conductive layer 61. The semiconductor substrate W1 includes two impurity diffusion regions provided in regions corresponding to the source and the drain of the transistor, and the insulating film region STI provided according to the layout of the transistor, like the core region CR.

[0166] The conductive layer GC1 is provided on the gate insulating film provided on the semiconductor substrate W1. The contact 55 is provided on the conductive layer GC1. The two contacts 56 are connected to the two impurity diffusion regions provided on the semiconductor substrate W1. For example, of the two impurity diffusion regions, the impurity diffusion region on the left side of the paper corresponds to the drain of the transistor TRd, and the impurity diffusion region on the right side of the paper corresponds to the source. The plurality of conductive layers 52 are provided on the contact 55 connected to the gate, the contacts 56 connected to the drain, and the contacts 56 connected to the source, respectively. The plurality of contacts 57 are provided on the plurality of conductive layers 52, respectively. The plurality of conductive layers 53 are provided on the plurality of contacts 57, respectively. The conductive layer 53 provided on the contact 57 electrically connected to the gate and the contact 57 electrically connected to the drain includes one conductive layer 53. That is, the transistor TRd is, for example, a diode-connected transistor in which the gate and the drain are connected. The conductive layer 53 electrically connected to the source is connected to the conductive layer 54 via the contact 58.

[0167] The conductive layer 61 is provided on the insulating film provided on the semiconductor substrate W1. The conductive layer 61 is, for example, a resistance element R1. The conductive layer 61 includes, for example, polysilicon. The two contacts 55 are provided on both ends of the conductive layer 61, respectively. The plurality of conductive layers 52 are provided on the plurality of contacts 55, respectively. The plurality of contacts 57 are provided on the plurality of conductive layers 52, respectively. The plurality of conductive layers 53 are provided on the plurality of contacts 57, respectively. The conductive layer 53 electrically connected to one end of the resistance element R1 is connected to the conductive layer 54 via the contact 58. The conductive layer 54 provided on the contact 58 electrically connected to the source of the transistor TRd and the contact 58 electrically connected to one end of the resistance element R1 includes one conductive layer 54. Further, the resistance element R1 can be provided in the second CMOS layer 200.

[0168] In the peripheral region PR, the second CMOS layer 200 contains the insulator layers 70 and 71, the conductive layers GC2 and 72 to 75, the through holes 59, and the contact pieces 76 to 80, as in the core region CR. The semiconductor substrate W2 contains the insulating film region INS through which the plurality of through holes 59 pass, the two impurity diffusion regions provided in regions corresponding to the source and the drain of the transistor, and the insulating film region STI provided according to the layout of the transistor, as in the core region CR. The conductive layer 74 is connected to the transistor TRe provided on the semiconductor substrate W2 via the contact piece 79 (not shown), the contact pieces 77 and 78, and the conductive layers 72 and 73, for example. The transistor TRe is included in the input / output circuit 11, for example. The transistor TRe is an LV transistor, for example. Note that the transistor TRe can be a VLV transistor or an HVN transistor, for example. The conductive layer 72 provided on the plurality of through holes 59 of the through insulating film region INS is composed of one conductive layer 72. Of the plurality of conductive layers 73 provided on the conductive layer 72 connected to the plurality of through holes 59 via the contact piece 78, the conductive layer 73 on the left side of the paper and the conductive layer 73 on the right side of the paper are connected to the conductive layer 75 (bonding pad BP) via the contact piece 79, the conductive layer 74, and the contact piece 80.

[0169] With the above configuration, in the peripheral region PR, the first CMOS chip CCP1 and the second CMOS chip CCP2 are electrically connected via the through hole group Gv of the through insulating film region INS. The through hole group Gv including the plurality of through holes 59 of the through insulating film region INS is connected to one conductive layer 54 (wiring) provided in the wiring layer D2. In addition, the through hole group Gv including the plurality of through holes 59 of the through insulating film region INS is connected to one conductive layer 72 (wiring) provided in the wiring layer D3.

[0170] In the peripheral region PR, the storage layer 300 contains the insulator layers 33 to 35, the conductive layers 21 and 26 to 28, and the contact pieces CC, V1, and V2, as in the core region CR. In addition, the storage layer 300 contains the sacrificial member 37. The conductive layer 21 includes the conductive layer 21a and the conductive layer 21b. The sacrificial member 37 is provided between the conductive layer 21a and the conductive layer 21b.

[0171] The conductive layer 21a, sacrificial member 37, and conductive layer 21b are arranged at the height of the conductive layer 21. Specifically, the height of the lower surface of the conductive layer 21a is the same as the height of the lower surface of the conductive layer 21 (source line SL). The height of the upper surface of the conductive layer 21b is the same as the height of the upper surface of the conductive layer 21 (source line SL). The conductive layer 21 in the core region CR corresponds to a structure in which the sacrificial member 37 is replaced with a conductor after stacking the conductive layer 21a, sacrificial member 37, and conductive layer 21b. That is, the height of the sacrificial member 37 is the same as the height at which the conductive layer 21 and the semiconductor layer 41 in each memory pillar MP are connected. The conductive layers 21a and 21b each contain, for example, polysilicon. The sacrificial member 37 contains, for example, silicon nitride.

[0172] Multiple contacts CC are provided on the conductive layer 26. The upper part of the contacts CC reaches at least the height of the conductive layer 21.

[0173] In the peripheral area PR, the wiring layer 400, like the core area CR, includes insulation layer 91, insulation layer 92, conductor layer 93, insulation layer 94, insulation layer 95, and insulation layer 96.

[0174] A portion of the conductive layer 93 penetrates the conductive layer 21a, the sacrificial member 37, the conductive layer 21b, and the insulating layers 91 and 92. The conductive layer 93 may have a portion that contacts the contact CC. The upper part of the contact CC is covered by the conductive layer 93 and is electrically connected to the conductive layer 93. The conductive layer 93 is insulated from the conductive layers 21a and 21b by the insulating layer 92. A portion of the upper part of the conductive layer 93 is not covered by the insulating layers 94 to 96. This portion functions as a pad PD. Thus, the pad PD is connected to the transistors and resistors disposed on the semiconductor substrate W1 via the contacts CC, V1, V2, 78 to 80 and 56 to 58, the through hole 59, and the conductive layers 26 to 28, 72 to 75, and 52 to 54. In addition, the pad PD is connected to the transistor disposed on the semiconductor substrate W2 via contacts CC, V1, V2 and 77-80, and conductor layers 26-28 and 72-75.

[0175] Furthermore, the pads PD of semiconductor device 1 can be connected to the pads PD of other semiconductor devices 1 via wire bonding. Similarly, more than three semiconductor devices 1 can be connected.

[0176] Figure 18 This is a top view showing an example of the planar layout of through-holes 59 in the peripheral region PR of semiconductor device 1. Figure 18 In the image, an example is shown where 14 through-holes 59 penetrate the insulating film region INS, and the conductive layer 54 connected to the through-holes 59 is represented by a dashed line. (Example:) Figure 18As shown, the through holes 59 have, for example, a circular cross-sectional shape in the XY plane. If the diameter of the through holes 59 is set to "diameter Dv1" and the pitch between adjacent two through holes 59 is set to "pitch Pv3", the plurality of through holes 59 having the diameter Dv1 are arranged at the pitch Pv3 in a 60° staggered manner. This arrangement is an arrangement corresponding to a honeycomb structure. Further, the plurality of through holes 59 may, for example, be arranged in a square arrangement or in a 45° staggered manner.

[0177] Figure 19 is a plan view showing an example of a plan layout of the through holes 59 in the peripheral region PR of the semiconductor device 1. As shown, the through holes 59 have, for example, a circular cross-sectional shape in the XY plane. If the diameter of the through holes 59 is set to "diameter Dv1" and the pitch between adjacent two through holes 59 is set to "pitch Pv3", the plurality of through holes 59 having the diameter Dv1 are arranged at the pitch Pv3 in a 60° staggered manner. This arrangement is an arrangement corresponding to a honeycomb structure. Further, the plurality of through holes 59 may, for example, be arranged in a square arrangement or in a 45° staggered manner. Figure 19 Figure 18 Figure 19 As shown, the conductive layers 75 have, for example, a rectangular cross-sectional shape in the XY plane. If the pitch between adjacent two conductive layers 75 is set to "pitch Pp1", the plurality of conductive layers 75 are arranged in a square arrangement at the pitch Pp1. The pitch Pp1 of the conductive layers 75 is larger than the pitch Pv3 of the through holes 59. Further, if the cross-sectional area of the conductive layers 75 in the XY plane is set to "Sp1" and the cross-sectional area of the through holes 59 in the XY plane is set to "Sv1", the cross-sectional area Sp1 of the conductive layers 75 is larger than the cross-sectional area Sv1 of the through holes 59 in the XY plane.

[0178] Figure 20 is a plan view showing another example of a plan layout of the through holes 59 in the peripheral region PR of the semiconductor device 1. As shown, the plurality of through holes 59 having the diameter Dv1 are arranged in a 45° staggered manner at the pitch Pv3. Figure 20

[0179] Figure 21 is a plan view showing another example of a plan layout of the through holes 59 in the peripheral region PR of the semiconductor device 1. As shown, the plurality of through holes 59 having the diameter Dv1 are arranged in a 45° staggered manner at the pitch Pv3. Figure 21 Figure 20 Figure 21 As shown, the pitch Pp1 of the conductive layers 75 is larger than the pitch Pv3 of the through holes 59. Further, the area Sp1 of the conductive layers 75 is larger than the area Sv1 of the through holes 59.

[0180] ​​​​​In the peripheral region PR, the insulating film region INS formed in the semiconductor substrate W2 is formed, for example, in a region in which the input / output circuit 11 is arranged (hereinafter, referred to as "input / output circuit region"). In the input / output circuit region, a plurality of through holes 59 are connected to the pads PD. The plurality of through holes 59 are respectively led out to be connected to transistors included in the input / output circuit 11 (transistors formed in the semiconductor substrate W1 and transistors formed in the semiconductor substrate W2). In the wiring path connected to the pads PD, it is preferable that the resistance be as low as possible. Therefore, the plurality of through holes 59 are connected to one conductive layer 54 (wiring) and one conductive layer 72 (wiring). In addition, the number of the through holes 59 is relatively large, and thus the plurality of through holes 59 are arranged as close as possible within the insulating film region INS. Therefore, the pitch Pv3 is smaller than the pitch Pv2. In addition, the pitch Pv3 can be equal to the pitch Pv1, can be smaller than the pitch Pv1, or can be larger than the pitch Pv1. In order to arrange the largest number of through holes in the smallest area, the plurality of through holes 59 are preferably arranged in a honeycomb structure.

[0181] Figure 22 FIG. 1 is a sectional view showing an example of a cross-sectional structure of a wall region WR of the semiconductor device 1 according to the embodiment. Figure 22 FIG. 1 is a sectional view showing a cross section of the semiconductor device 1 including the wall region WR, and shows a coordinate axis with the semiconductor substrate W1 as a reference. In addition, Figure 22 FIG. 1 is a sectional view showing a cross section of the semiconductor device 1 including the wall region WR, and shows a coordinate axis with the semiconductor substrate W1 as a reference. In addition,

[0182] In the wall region WR, the first CMOS layer 100 includes the insulator layers 50 and 51, the conductive layers 52 to 54, the contact members 56 to 58, and the through holes 59, like the core region CR. The semiconductor substrate W1 includes a P-type well region PW and an N-type well region NW. The P-type well region PW is a diffusion region of a P-type impurity (p + ) provided near the upper surface of the semiconductor substrate W1. The N-type well region NW is a diffusion region of an N-type impurity (n + ) provided near the upper surface of the semiconductor substrate W1. The P-type well region PW and the N-type well region NW respectively correspond to the sealing portions ES1 and ES2.

[0183] In the wall region WR, the second CMOS layer 200 includes the insulator layers 70 and 71, the conductive layers 72 to 75, the through holes 59, and the contact members 78 to 80, like the core region CR. The semiconductor substrate W2 includes the insulating film region INS through which the plurality of through holes 59 pass, like the core region CR.

[0184] With the above configuration, in the wall region WR, the first CMOS chip CCP1 and the second CMOS chip CCP2 are electrically connected via the via hole group Gv of the through insulating film region INS. The via hole group Gv including the plurality of via holes 59 of the through insulating film region INS is connected to the wiring group Gi including the plurality of conductive layers 54 (wirings) provided in the wiring layer D2. One of the plurality of conductive layers 54 included in the wiring group Gi of the wiring layer D2 is electrically connected to the P-type well region PW provided in the semiconductor substrate W1. Another of the plurality of conductive layers 54 included in the wiring group Gi of the wiring layer D2 is electrically connected to the N-type well region NW provided in the semiconductor substrate W1.

[0185] In the wall region WR, the storage layer 300 contains the insulator layers 33 to 35, the conductive layers 21a, 21b, and 26 to 28, the sacrificial member 37, and the contact pieces CC, V1, and V2, like the peripheral region PR.

[0186] In the wall region WR, the wiring layer 400 contains the insulator layer 91, the insulator layer 92, the conductive layer 93, the insulator layer 94, the insulator layer 95, and the insulator layer 96, like the core region CR.

[0187] A portion of the conductive layer 93 penetrates the conductive layer 21a, the sacrificial member 37, the conductive layer 21b, and the insulator layers 91 and 92. The conductive layer 93 can have a portion that is in contact with the contact piece CC. The upper portion of the contact piece CC is covered with the conductive layer 93 and is electrically connected to the conductive layer 93. Thus, the conductive layer 93 is connected to the P-type well region PW via the contact pieces CC, V1, V2, 78 to 80, and 56 to 58, the via holes 59, and the conductive layers 26 to 28, 72 to 75, and 52 to 54 corresponding to the sealing portion ES1. Further, the conductive layer 93 is connected to the N-type well region NW via the contact pieces CC, V1, V2, 78 to 80, and 56 to 58, the via holes 59, and the conductive layers 26 to 28, 72 to 75, and 52 to 54 corresponding to the sealing portion ES2.

[0188] Although not illustrated, the contact pieces CC, V1, V2, 78 to 80, and 56 to 58, and the group of the via holes 59 and the conductive layers 26 to 28, 72 to 75, and 52 to 54 are arranged in a ring shape in plan view. The insulating film region INS is arranged in a ring shape in plan view. That is, in the wall region WR, the sealing portions ES1 and ES2 are arranged in a quadrangular ring shape so as to surround the outer periphery of the core region CR, and surround the peripheral region PR. The sealing portion ES2 is arranged outward of the sealing portion ES1. The insulating film region INS is also arranged in a quadrangular ring shape so as to surround the outer periphery of the core region CR, and surround the peripheral region PR.

[0189] The sealing portions ES1 and ES2 described above are configurations that can release positive and negative charges generated inside and outside the wall region WR to the semiconductor substrate W1. Furthermore, the sealing portions ES1 and ES2 can each suppress penetration of moisture and the like from the outside of the wall region WR into the core region CR. The sealing portions ES1 and ES2 can each suppress stress generated in the interlayer insulating film (for example, tetraethoxysilane (TEOS)) of the semiconductor device 1. Furthermore, the sealing portions ES1 and ES2 can each function as a crack stopper.

[0190] Figure 23 is a plan view showing an example of a planar layout of the through holes 59 in the wall region WR of the semiconductor device 1. In Figure 23 , an example in which two through holes 59 penetrate the insulating film region INS is shown, and the conductive layer 54 connected to the through holes 59 is shown by a broken line. As shown in Figure 23 , the plurality of through holes 59 are arranged separately from each other. As described above, the through holes 59 are arranged in a ring shape in plan view, and therefore the plurality of through holes 59 are arranged separately in the X direction or the Y direction. In Figure 23 , the plurality of through holes 59 are arranged separately from each other in the Y direction. The through holes 59 have, for example, a cross-sectional shape that is linear in the XY plane. That is, the cross-sectional shape of each of the plurality of through holes 59 formed in the insulating film region INS of the wall region WR is different from the cross-sectional shape of each of the plurality of through holes 59 formed in the insulating film region INS of the memory region MA. Hereinafter, the distance between two adjacent through holes 59 will be referred to as "pitch Pv4".

[0191] In the wall region WR, the insulating film region INS formed in the semiconductor substrate W2 is formed, for example, in a region in which the sealing portion is arranged. In this region, the pitch between two adjacent through holes 59 is set to a distance that enables release of positive charges generated inside and outside the wall region WR to the N-type well region NW of the semiconductor substrate W1 and enables release of negative charges generated inside and outside the wall region WR to the P-type well region PW of the semiconductor substrate W1. Therefore, the pitch Pv4 is greater than the pitch Pv1. That is, the group of through holes Gv formed in the insulating film region INS of the wall region WR is arranged at a different pitch from the group of through holes Gv formed in the insulating film region INS of the memory region MA. In addition, the pitch Pv4 can be equal to the pitch Pv2, can be smaller than the pitch Pv2, or can be greater than the pitch Pv2.

[0192] In the above description, a case in which the HV transistor is arranged in the first CMOS layer 100 and the LV transistor is arranged in the second CMOS layer 200 is exemplified, but the present application is not limited thereto. The arrangement of the transistors in the first CMOS layer 100 and the second CMOS layer 200 can be appropriately changed according to the design of the semiconductor device 1.

[0193] <1-4> Method for manufacturing semiconductor device

[0194] Figure 24 is a flowchart showing an example of the manufacturing method of the semiconductor device 1 of the embodiment. Figures 25-43 are cross-sectional views each showing an example of the cross-sectional structure at an intermediate stage of the manufacturing of the semiconductor device 1 of the embodiment. Hereinafter, appropriate reference will be made to Figure 24 The manufacturing method of the semiconductor device 1 of the embodiment will be described.

[0195] First, a semiconductor substrate W3 formed with a memory layer 300 and a semiconductor substrate W1 formed with a first CMOS layer 100 are prepared (S11). In the memory layer 300 on the prepared semiconductor substrate W3, as shown in Figures 25-27 the insulator layer 35 of the bonding layer B1 and the bonding pad BP (the conductive layers 25 and 28) are exposed. Figure 25 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. Figure 26 is a cross-sectional view showing an example of the cross-sectional structure in the peripheral region PR.

[0196] Figure 27 is a cross-sectional view showing an example of the cross-sectional structure in the wall region WR. In the first CMOS layer 100 on the prepared semiconductor substrate W1, as shown in Figures 28-30 the insulator layer 51 of the bonding layer B2 is exposed. That is, the first CMOS chip CCP1 having the transistor (CMOS circuit) and the insulator layer 51 positioned above the transistor is formed. Figure 28 is a cross-sectional view showing an example of the cross-sectional structure in the core region CR. Figure 29 is a cross-sectional view showing an example of the cross-sectional structure in the peripheral region PR. Figure 30 is a cross-sectional view showing an example of the cross-sectional structure in the wall region WR. In addition, at the time of S11, in the semiconductor substrate W1 and the first CMOS layer 100, a structure corresponding to the through-hole 59 is not formed.

[0197] Next, the semiconductor substrate W1 and the semiconductor substrate W2 are bonded to form a first bonded substrate BW1 (S12). Specifically, before the process of S12, a silicon oxide film (insulating film) is formed on the bonding surface of the semiconductor substrate W2. That is, the second CMOS chip CCP2 having the semiconductor substrate W2 and the silicon oxide film provided on the semiconductor substrate W2 is formed. Then, the silicon oxide film of the second CMOS chip CCP2 is bonded on the insulator layer 51 of the first CMOS chip CCP1. By the bonding process of the semiconductor substrate W1 and the semiconductor substrate W2, the insulator layer 51 (silicon oxide film) of the first CMOS chip CCP1 and the silicon oxide film of the second CMOS chip CCP2 are in contact and bonded. Thus, as shown in Figure 31As shown, a first bonding substrate BW1 having a configuration in which the semiconductor substrate W2 is provided on the insulator layer 51 is formed. Figure 31 is a sectional view showing an example of a cross-sectional configuration in the core region CR.

[0198] Next, a CMP (Chemical Mechanical Polishing) process is performed on the semiconductor substrate W2 included in the first bonding substrate BW1 (S13). By the process of S13, as shown, Figure 32 the semiconductor substrate W2 of the first bonding substrate BW1 is polished (thinned). Figure 32 is a sectional view showing an example of a cross-sectional configuration in the core region CR. The thickness of the semiconductor substrate W2 that is thinned by polishing corresponds to Figure 13 the thickness of the semiconductor substrate W2 shown. The thickness of the semiconductor substrate W2 after the process of S13 is, for example, about 0.5 μm to 2.0 μm.

[0199] Next, a second CMOS layer 200 is formed on the first bonding substrate BW1 (S14). Specifically, the following process is performed.

[0200] First, an insulating film region STI is provided in the vicinity of the upper surface of the semiconductor substrate W2 so as to surround the active region AA of the transistor. The insulating film region STI is in contact with the upper surface of the semiconductor substrate W2. A gate insulating film is provided on the semiconductor substrate W2. A conductive layer GC2 is provided on the gate insulating film. As shown, Figure 33 the conductive layer GC2 is processed. The conductive layer GC2 is used as a mask, and an impurity diffusion region is provided on the semiconductor substrate W2. Thus, a transistor (CMOS circuit) is formed on the semiconductor substrate W2. Figure 33 is a sectional view showing an example of a cross-sectional configuration in the core region CR.

[0201] Next, a first hole that penetrates the semiconductor substrate W2 is formed so as to overlap the conductive layer 54 (wiring) in the Z direction. In the storage region MA, the contact region CA, and the wall region WR, a first hole that penetrates the semiconductor substrate W2 is formed so as to overlap a plurality of conductive layers 54 in the Z direction. In the peripheral region PR, a first hole that penetrates the semiconductor substrate W2 is formed so as to overlap one conductive layer 54. Then, an insulator is buried in the first hole. Thus, as shown, Figure 34 an insulating film region INS that penetrates the semiconductor substrate W2 is formed. Figure 34is a sectional view showing an example of a cross-sectional structure in the core region CR. The insulating film region INS that penetrates the semiconductor substrate W2 is formed in each of the memory region MA, the contact region CA, the peripheral region PR, and the wall region WR. Further, the insulating film region INS can be formed at the same time as the insulating film region STI. In this case, the number of processes and cost can be reduced.

[0202] Next, activation annealing processing is performed on the semiconductor substrate W2 included in the first bonded substrate BW1. Thereby, a source and a drain are formed in the impurity diffusion region of the semiconductor substrate W2. The activation annealing processing is performed, for example, under conditions of 1000°C to 1100°C and 0 seconds to 30 seconds. For example, in order to minimize diffusion of impurities, spike annealing is used. Spike annealing is performed by setting the time at the maximum reached temperature to 0 seconds only by temperature rising and temperature lowering. As described above, as the material of the conductive layers 52 to 54 provided in the first CMOS layer 100, a conductive material having a relatively high melting point is used, and an HV transistor is provided on the semiconductor substrate W1. Therefore, it is possible to suppress the deterioration of the characteristics of the transistor provided on the semiconductor substrate W1. Further, the activation annealing processing can be performed on both the semiconductor substrates W1 and W2.

[0203] Next, as shown in Figure 35 , the insulator layer 70 is formed. Figure 35 is a sectional view showing an example of a cross-sectional structure in the core region CR.

[0204] Next, as shown in Figure 36 , the contact pieces 76 and 77 and the through hole 59 are formed. Figure 36 is a sectional view showing an example of a cross-sectional structure in the core region CR. After the contact pieces 76 and 77 and the through hole 59 are formed, as shown in Figure 37 , the wiring layer D3 (the conductive layer 72) is formed. Figure 37 is a sectional view showing an example of a cross-sectional structure in the core region CR. For example, the contact pieces 76 and 77 and the through hole 59 are formed by single damascene with the wiring layer D3.

[0205] First, for example, by etching, a hole corresponding to each of the contact pieces 76 and 77 and a plurality of second holes formed through the insulating film region INS of the semiconductor substrate W2 are formed at the same time. Thereby, a hole reaching the conductive layer GC2 of the transistor (CMOS circuit) is formed. A hole reaching the source or the drain of the transistor (CMOS circuit) is formed. In each of the memory region MA, the contact region CA, the peripheral region PR, and the wall region WR, a plurality of second holes that penetrate the insulating film region INS are formed. At this time, for example, the plurality of second holes that penetrate the insulating film region INS of the memory region MA and the plurality of second holes that penetrate the insulating film region INS of the contact region CA are formed at different pitches.

[0206] Then, conductors are embedded in the holes corresponding to contacts 76 and 77, and in the second hole penetrating the insulating film region INS, respectively, thereby forming contacts 76 and 77, and through-holes 59. Thus, for example, a contact 76 is formed that connects to the conductive layer GC2 of a transistor (CMOS circuit). A contact 77 is formed that connects to the source or drain of the transistor (CMOS circuit). Furthermore, for example, through-hole groups Gv including multiple through-holes 59 penetrating the insulating film region INS of the storage region MA and through-hole groups Gv including multiple through-holes 59 penetrating the contact region CA of the insulating film region INS are formed at different intervals.

[0207] Next, for example, a trench corresponding to the wiring layer D3 is formed by etching. Then, the wiring layer D3 is formed by embedding a conductor in the trench corresponding to the wiring layer D3. Thus, a conductive layer 72 is formed, for example, on the contact 77 connected to the source or drain of the transistor (CMOS circuit). Furthermore, for example, in each of the storage region MA, contact region CA, peripheral region PR, and wall region WR, a wiring group Gi is formed on the via group Gv that penetrates the insulating film region INS and in the same layer as the conductive layer 72.

[0208] Next, as Figures 38-40 As shown, the wiring layers D4 and D5 and the bonding layer B3 are formed, and the process of S14 is completed. Figure 38 This is a sectional view showing an example of the cross-sectional structure in the core region CR. Figure 39 This is a cross-sectional view showing an example of the cross-sectional structure in the surrounding area PR. Figure 40 This is a sectional view showing an example of the cross-sectional construction in the wall region WR.

[0209] Next, the first bonding substrate BW1 and the semiconductor substrate W3 are bonded to form the second bonding substrate BW2 (S15). Specifically, through the bonding process of the first bonding substrate BW1 and the semiconductor substrate W3, the insulating layer 71 of the second CMOS layer 200 contacts and bonds with the insulating layer 35 of the memory layer 300. Furthermore, the bonding pads BP facing each other between the second CMOS layer 200 and the memory layer 300 contact and bond together. Thus, as... Figures 41-43 As shown, a second bonding substrate BW2 is formed. Figure 41 This is a sectional view showing an example of the cross-sectional structure in the core region CR. Figure 42 This is a cross-sectional view showing an example of the cross-sectional structure in the surrounding area PR. Figure 43 This is a sectional view showing an example of the cross-sectional construction in the wall region WR.

[0210] Next, a CMP process is performed on the semiconductor substrate W3 included in the second bonded substrate BW2 (S16). By the process of S16, the semiconductor substrate W3 of the second bonded substrate BW2 is removed. Alternatively, the semiconductor substrate W3 can be left by only being thinned without being removed.

[0211] Next, a wiring layer 400 is formed on the second bonded substrate BW2 (S17). The insulator layer 91, the insulator layer 92, the conductor layer 93, the insulator layer 94, the insulator layer 95, and the insulator layer 96 are sequentially formed on the conductor layer 21. When the process of S17 is completed, the semiconductor device 1 is completed.

[0212] <1-5> Effects of Embodiments

[0213] According to the semiconductor device 1 of the embodiment, the chip area of the semiconductor device 1 can be reduced. Details of the effects of the embodiment will be described below.

[0214] There is a semiconductor device having an array chip including a memory cell array 10, a first CMOS chip in which a CMOS circuit that controls the memory cell array 10 is arranged on a semiconductor substrate, and a second CMOS chip in which a CMOS circuit that controls the memory cell array 10 is arranged on a semiconductor substrate.

[0215] In such a semiconductor device, for example, the first CMOS chip and the second CMOS chip can be electrically connected by a through-hole whose periphery is covered with an insulating film region. In addition, for example, the CMOS circuits can be arranged in different regions for each use. The number of CMOS circuits arranged in each region can be different depending on the use. That is, the number of CMOS circuits arranged can be different for each region. Therefore, the number of through-holes that connect between the first CMOS chip and the second CMOS chip can also be different depending on the use, and different for each region.

[0216] A memory cell array in which memory cells are three-dimensionally stacked can increase the storage capacity by increasing the number of layers of word lines WL. However, if the number of layers of word lines WL is increased for large capacity, the number of through-holes that connect between the first CMOS chip and the second CMOS chip and are connected to the word lines WL can also increase. When the number of through-holes increases, the area of the insulating film region that covers the periphery of the through-holes becomes larger depending on the number of increases, and thus the chip area of the semiconductor device 1 can become larger.

[0217] In addition, the voltage supplied to the CMOS circuit can be different depending on the use. Therefore, if the distance between two adjacent through-holes is the same distance in any region regardless of the use, for example, depending on the voltage supplied to the CMOS circuit, insulation breakdown can sometimes occur between the two adjacent through-holes.

[0218] In contrast, in the semiconductor device 1 of the embodiment, among the core region CR, the peripheral region PR, and the wall region WR, the semiconductor substrate W2 includes an insulating film region INS that penetrates the semiconductor substrate W2. Each insulating film region INS includes a plurality of through holes 59 that electrically connect the first CMOS chip CCP1 and the second CMOS chip CCP2. In other words, the plurality of through holes 59 that electrically connect the first CMOS chip CCP1 and the second CMOS chip CCP2 penetrate one insulating film region INS. In addition, among the core region CR, the peripheral region PR, and the wall region WR, in the insulating film region INS, the plurality of through holes 59 are arranged at different pitches according to the purpose. Thus, the arrangement of the pitches can be optimized in the insulating film region INS. Therefore, compared with a case where the plurality of through holes 59 are arranged at the same pitch regardless of the purpose in the insulating film region INS, the area of the insulating film region INS can be reduced. Thus, the chip area of the semiconductor device 1 can be reduced.

[0219] In addition, there is a semiconductor device in which the first CMOS chip and the second CMOS chip are joined by a bonding pad provided in the first CMOS chip and a bonding pad provided in the second CMOS chip.

[0220] In such a semiconductor device, the arrangement of the through holes connecting the first CMOS chip and the second CMOS chip is limited by the distance between the two adjacent bonding pads. In addition, when the bonding pads are joined to each other, sometimes, joining failure occurs.

[0221] In contrast, in the embodiment, the insulating film (silicon oxide film) of the semiconductor substrate W2 is joined to the insulating layer 51 of the semiconductor substrate W1 having the CMOS circuit and the insulating layer 51 positioned above the CMOS circuit. That is, a bonding pad is not used. Thus, the through holes 59 connecting the first CMOS chip CCP1 and the second CMOS chip CCP2 can be arranged without being limited by the distance between the bonding pads. Therefore, the chip area of the semiconductor device 1 can be reduced. In addition, since the bonding pad is not used, joining failure between the bonding pads does not occur. Furthermore, compared with a case where the first CMOS chip and the second CMOS chip are joined by the bonding pad, the process can be simplified.

[0222] <1-6> First Modified Example

[0223] A semiconductor device 1A of a first modified example of the embodiment will be described. In the semiconductor device 1A of the present modified example, the configuration around the upper surface of the through hole 59 is different from that of the embodiment. Hereinafter, the description will be made focusing on the points different from the embodiment.

[0224] <1-6-1> Cross-sectional configuration of semiconductor device

[0225] Figure 44 is a cross-sectional view showing an example of a cross-sectional configuration of a core region CR of a semiconductor device 1A of a first modification example. Figure 45 is a cross-sectional view showing an example of a cross-sectional configuration of a peripheral region PR of the semiconductor device 1A of the first modification example. Figure 46 is a cross-sectional view showing an example of a cross-sectional configuration of a wall region WR of the semiconductor device 1A of the first modification example. As shown in Figures 44-46 , in the semiconductor device 1A, the wiring group Gi provided on the through-hole group Gv of the through insulating film region INS and the same layer as the conductive layer 72 are abolished from the semiconductor device 1 of the embodiment. The position of the upper surface of each of the plurality of through holes 59 of the through insulating film region INS is the same as the position of the upper surface of the conductive layer 72 electrically connected to one of the source or the drain of the transistor TRb. Each of the plurality of through holes 59 of the through insulating film region INS is connected to the contact 78.

[0226] The other configurations of the semiconductor device 1A are the same as those of the semiconductor device 1 of the embodiment.

[0227] <1-6-2> Manufacturing method of semiconductor device

[0228] Figure 47 is a flowchart showing an example of a manufacturing method of the semiconductor device 1A of the first modification example. In Figure 47 , the flowchart of the manufacturing method of the semiconductor device 1A is shown. In the flowchart of the manufacturing method of the semiconductor device 1A, S14 of the flowchart of Figure 24 is replaced by S14A. S14A is the same as the flowchart of Figure 24 of the embodiment except for S14A. Figure 48 and Figure 49 are cross-sectional views each showing an example of a cross-sectional configuration of an intermediate of the manufacturing of the semiconductor device 1A of the first modification example. Hereinafter, the manufacturing method of the semiconductor device 1A is described with appropriate reference to Figure 47

[0229] In S14A, the second CMOS layer 200 is formed on the first bonding substrate BW1. Specifically, the following processing is performed.

[0230] The processes from the formation of the transistor (CMOS circuit) to the formation of the insulating layer 70 are the same as those of the embodiment.

[0231] Next, as shown in Figure 48 , the contacts 76 and 77, and the wiring layer D3 (conductive layer 72) are formed. Figure 48 ​is a sectional view showing an example of a cross-sectional structure in the core region CR. For example, the contact members 76 and 77 and the wiring layer D3 are integrally formed by dual damascene.

[0232] First, holes corresponding to the contact members 76 and 77, and a groove corresponding to the wiring layer D3 are formed, for example, by etching. Thereby, holes reaching the conductor layer GC2 of the transistor (CMOS circuit) are formed. Holes reaching the source or drain of the transistor (CMOS circuit) are formed. The groove corresponding to the wiring layer D3 is formed.

[0233] Then, the contact members 76 and 77, and the wiring layer D3 are integrally formed by burying conductors in the holes corresponding to the contact members 76 and 77, and the groove corresponding to the wiring layer D3, respectively. Thereby, for example, the contact member 76 connected to the conductor layer GC2 of the transistor (CMOS circuit) is formed. The contact member 77 connected to the source or drain of the transistor (CMOS circuit) is formed. In addition, for example, the conductor layer 72 is formed on the contact member 76 connected to the conductor layer GC2 of the transistor (CMOS circuit). The conductor layer 72 is formed on the contact member 77 connected to the source or drain of the transistor (CMOS circuit).

[0234] Next, as shown in Figure 49 , the through holes 59 are formed. Figure 49 is a sectional view showing an example of a cross-sectional structure in the core region CR.

[0235] First, a plurality of second holes are formed through the insulating film region INS formed in the semiconductor substrate W2, for example, by etching. Thereby, in each of the memory region MA, the contact region CA, the peripheral region PR, and the wall region WR, a plurality of second holes are formed through the insulating film region INS. At this time, for example, the plurality of second holes through the insulating film region INS in the memory region MA and the plurality of second holes through the insulating film region INS in the contact region CA are formed at different pitches.

[0236] Then, a conductor is buried in the second holes through the insulating film region INS, thereby forming the through holes 59. Thus, for example, a through hole group Gv including a plurality of through holes 59 through the insulating film region INS in the memory region MA and a through hole group Gv including a plurality of through holes 59 through the insulating film region INS in the contact region CA are formed at different pitches.

[0237] The formation processes of the subsequent wiring layers D4 and D5, and the structure of the bonding layer B3 are the same as in the embodiment.

[0238] <1-6-3>Effects of the First Modified Embodiment

[0239] According to the present modified embodiment, the same effects as the embodiment are exerted.

[0240] In addition, in the case where the electrically conductive layer 72 is formed over the through-hole 59, for example, suction of the lower resist film occurs in the through-hole 59 at the time of photolithography of the electrically conductive layer 72, and thus it is possible that pattern destruction of the photolithography occurs. In order to avoid this, it is necessary to repeatedly perform coating and etching back of the lower resist film, and thus the number of processes increases.

[0241] In contrast to this, in the present modification example, the electrically conductive layer 72 is not provided over the through-hole 59. Therefore, according to the present modification example, the number of processes can be reduced as compared with the case where the electrically conductive layer 72 is provided over the through-hole 59.

[0242] <1-7> Second Modification Example

[0243] A semiconductor device 1B of a second modification example of the embodiment will be described. In the semiconductor device 1B of the present modification example, the configuration of the peripheral region PR is different from that of the embodiment. Hereinafter, description will be made focusing on the points different from the embodiment.

[0244] <1-7-1> Cross-sectional Configuration of Semiconductor Device

[0245] Figure 50 is a cross-sectional view showing an example of the cross-sectional configuration of the peripheral region PR of the semiconductor device 1B of the second modification example. As shown in Figure 50 In the semiconductor device 1B, a chip connection portion CP is added to the peripheral region PR of the semiconductor device 1 of the embodiment.

[0246] The chip connection portion CP is disposed separately from the insulating film region INS in the Y direction, for example. The chip connection portion CP includes the insulator layer 81, the through-hole 82, the insulating film region INSc, the electrically conductive layers 74 and 75, the contact pieces 79 and 80, the electrically conductive layers 26 to 28, the contact piece CC, V1 and V2, and the electrically conductive layer 93.

[0247] In the chip interconnect portion CP, an insulating layer 81 is disposed near the upper surface of the semiconductor substrate W1. Through-holes 82 are disposed on the insulating layer 81. Through-holes 82 are included in the first CMOS chip CCP1 and the second CMOS chip CCP2. The lower side and bottom surfaces of the through-holes 82 are covered by the insulating layer 81. The upper surface of the through-hole 82 is located above the upper surfaces of the plurality of through-holes 59 included in the through-hole group Gv. The lower surface of the through-hole 82 is located below the lower surfaces of the plurality of through-holes 59 included in the through-hole group Gv. In the XY plane, the cross-sectional area of ​​the upper surface of the through-hole 82 is larger than the cross-sectional area of ​​the plurality of through-holes 59 included in the through-hole group Gv. An insulating film region INSc penetrating the semiconductor substrate W2 is disposed on the semiconductor substrate W2. That is, the semiconductor substrate W2 includes an insulating film region INSc penetrating the semiconductor substrate W2. Through-hole 82 penetrates insulating layers 50 and 51 and the insulating film region INSc. Through-hole 82 contacts the semiconductor substrate W1 via insulating layer 81. Through-hole 82, for example, has a tapered shape with a cross-sectional area decreasing from the upper surface to the lower surface. Figure 50 In this example, two through-holes 82 are provided. Two contacts 79 are provided on the through-holes 82. Conductor layers 75 are provided on the two contacts 79 connected to one through-hole 82. That is, in the XY plane, the cross-sectional area of ​​the upper surface of the through-hole 82 is larger than the cross-sectional area of ​​the bonding pad BP (conductive layer 75). The through-hole 82 is connected to the conductive layer 93 via contacts 79, conductive layers 74, 80, 75, 28, V2, 27, V1, 26, and CC. Thus, the pad PD is connected to the through-hole 82 via contacts CC, V1, V2, 79 and 80, and conductive layers 26-28, 74 and 75. In addition, the lower end of the through hole 82 may not reach the semiconductor substrate W1, and the lower end of the through hole 82 may also be connected to the wiring layer D0 (conductor layer 52).

[0248] With the above construction, a wiring, i.e., a through-hole 82, is formed in the peripheral region PR, encompassing the first CMOS chip CCP1 and the second CMOS chip CCP2 and penetrating the insulating film region INSc of the semiconductor substrate W2. The through-hole 82 is used, for example, for electrical connection between semiconductor device 1B and other semiconductor devices 1B. Conversely, the through-hole 59 is used, for example, for electrical connection between the first CMOS chip CCP1 and the second CMOS chip CCP2.

[0249] Figure 51 This is a cross-sectional view illustrating an example of a cross-sectional structure when multiple semiconductor devices 1B are stacked. Figure 51In one example, semiconductor device 1B (hereinafter referred to as "semiconductor chip SCP1") is stacked on top of semiconductor device 1B (hereinafter referred to as "semiconductor chip SCP2"). Figure 51 As shown, in semiconductor chip SCP1, conductive layer 93 is exposed, a portion of insulating layer 94 is exposed, and a portion of insulating layer 95 is exposed. In semiconductor chip SCP2, insulating layer 81 is removed. A through-hole 82 of semiconductor chip SCP2 is formed on the conductive layer 93 of semiconductor chip SCP1. Thus, semiconductor chip SCP1 and semiconductor chip SCP2 are electrically connected via through-hole 82. Semiconductor device 1B is capable of... Figure 51 Similarly, the strata are stacked in three or more layers.

[0250] <1-7-2> The effect of the second variation

[0251] According to this variation, the same effect is achieved as in the implementation method. Of course, the first variation can also be applied to this variation.

[0252] Furthermore, according to this modified example, multiple semiconductor devices 1B can be stacked, and the pads PD can be electrically connected to each semiconductor device 1B via through-holes 82.

[0253] <2> other

[0254] As described above, the semiconductor device (1) of the embodiment includes: a first chip (CCP1) having a first substrate (W1) on which a first transistor (TRa) is formed; and a second chip (CCP2) disposed above the first chip having a second substrate (W2) on which a second transistor (TRb) is formed. The second substrate (W2) includes a first insulating film region (INS) and a second insulating film region (INS) respectively penetrating the second substrate. The first chip (CCP1) and the second chip (CCP2) are electrically connected via a first via group (Gv) and a second via group (Gv). The first via group (Gv) includes at least a first through-hole (59) and a second through-hole (59) respectively penetrating the first insulating film region (INS), and the second via group (Gv) includes at least a third through-hole (59) and a fourth through-hole (59) respectively penetrating the second insulating film region (INS). The first via group (Gv) is arranged with a different spacing than the second via group (Gv).

[0255] Furthermore, the implementation method is not limited to the manner described above, and various modifications are possible.

[0256] Furthermore, the flowcharts described in the above embodiments can be modified in the order of their processing as much as possible.

[0257] As the transistor provided to the semiconductor substrate W2, a FinFET (Fin Field-Effect Transistor) can also be used. The FinFET can be applied to the embodiment, the first modification example, and the second modification example. Figure 52 is a cross-sectional view in the XZ plane showing an example of the configuration of the FinFET. Figure 53 is a cross-sectional view in the YZ plane of the FinFET of Figure 52

[0258] As shown in Figure 52 and Figure 53 , a semiconductor layer 201 is provided to the semiconductor substrate W2. The semiconductor layer 201 functions as a channel of the FinFET. A gate insulating film 202 is provided to two of the four side surfaces and the upper surface of the semiconductor layer 201. That is, two of the side surfaces and the upper surface (three surfaces) of the semiconductor layer 201 are covered with the gate insulating film 202. A gate electrode 203 is provided on the gate insulating film 202. An electrode 204 is provided so as to be in contact with one of the two side surfaces of the semiconductor layer 201 which are not covered with the gate insulating film 202. The electrode 204 is one of a source electrode and a drain electrode. The electrode 204 is connected to the contact 77. An electrode 205 is provided so as to be in contact with the other of the two side surfaces of the semiconductor layer 201 which are not covered with the gate insulating film 202. The electrode 205 is the other of the source electrode and the drain electrode. The electrode 205 is connected to the contact 77. An insulating film region 206 (insulating film region STI) is provided under the gate insulating film 202 of the semiconductor substrate W2. By using the FinFET, the leakage current can be reduced.

[0259] As the transistor provided to the semiconductor substrate W2, a transistor having a GAA (Gate All Around) configuration (hereinafter, also referred to as "GAA transistor") can also be used. The GAA transistor can be applied to the embodiment, the first modification example, and the second modification example. Figure 54 is a cross-sectional view in the XZ plane showing an example of the configuration of the GAA transistor. Figure 55 is a cross-sectional view in the YZ plane of the GAA transistor of Figure 54 Figure 54 In the example of Figure 55 , two semiconductor layers 201 and two gate insulating films 202 are provided.

[0260] As shown in Figure 54 and Figure 55 ​​As shown, a gate electrode 203 is provided on the semiconductor substrate W2. The semiconductor layer 201 has a plate-like shape extending in the X direction, and penetrates the gate electrode 203. The two semiconductor layers 201 are arranged separately from each other in the Z direction. The gate insulating film 202 has a ring-like shape extending in the X direction, and penetrates the gate electrode 203. The two gate insulating films 202 are arranged separately from each other in the Z direction. The gate insulating film 202 is provided on two of the four side surfaces of the semiconductor layer 201, the upper surface, and the lower surface. That is, two of the side surfaces, the upper surface, and the lower surface (four surfaces) of the semiconductor layer 201 are covered with the gate insulating film 202. The electrode 204 is provided so as to be in contact with one of the two side surfaces of the semiconductor layer 201 which are not covered with the gate insulating film 202. The electrode 204 is one of a source electrode or a drain electrode. The electrode 205 is provided so as to be in contact with the other of the two side surfaces of the semiconductor layer 201 which are not covered with the gate insulating film 202. The electrode 205 is the other of the source electrode or the drain electrode. An insulating film region 206 (insulating film region STI) is provided in the vicinity of the upper surface of the semiconductor substrate W2. An epitaxial layer 207 is provided on the semiconductor substrate W2 so as to be in contact with the electrode 204. The epitaxial layer 207 is provided on the semiconductor substrate W2 so as to be in contact with the electrode 205. A contact 77 is provided on the epitaxial layer 207. By using a GAA transistor, the leakage current can be reduced as compared with a FinFET.

[0261] In a case where the HV transistor is configured in the first CMOS layer 100 and the LV transistor is configured in the second CMOS layer 200, the impurity concentration of the semiconductor substrates W1 and W2 can be set respectively according to the kind of the transistor configured.

[0262] For example, the impurity concentration of the semiconductor substrate W1 in which the HV transistor is formed can be set to 1.0 x 10 14 ~ 1.0 x 10 15 [cm -3 ]. The impurity concentration of the semiconductor substrate W2 in which the LV transistor is formed can be set to 5.0 x 10 14 ~ 1.0 x 10 16 [cm -3 ].

[0263] In a case where the HV transistor is configured in the first CMOS layer 100 and the LV transistor is configured in the second CMOS layer 200, the notch of the semiconductor substrates W1 and W2 can also be set respectively according to the kind of the transistor configured. In the present specification, the "notch" is a portion provided in correspondence with the crystal orientation of the semiconductor substrate, and is used as a reference for the orientation of the substrate held by a semiconductor manufacturing apparatus.

[0264] For example, in the semiconductor substrate W1 in which the HV transistor is formed, the Miller indices of the crystal orientation corresponding to the X direction and the Y direction, that is, the Miller indices of the crystal orientation corresponding to the extension direction of the channel of the transistor can be set to <110>. In this case, the semiconductor substrate W1 has a cutout configured so as to correspond to <110>. The semiconductor substrate W1 can also be referred to as a "0-degree cutout substrate".

[0265] In the semiconductor substrate W2 in which the LV transistor is formed, the Miller indices of the crystal orientation corresponding to the X direction and the Y direction, that is, the Miller indices of the crystal orientation corresponding to the extension direction of the channel of the transistor can be set to <100>. In this case, the semiconductor substrate W2 has a cutout configured so as to correspond to <100>. The semiconductor substrate W2 has a configuration in which a cutout is provided in a portion that is rotated by 45 degrees with the semiconductor substrate W1 as a reference, and thus can also be referred to as a "45-degree cutout substrate". By using the 45-degree cutout substrate as the semiconductor substrate W2, the mobility of the carrier can be increased, and the LV transistor can be caused to operate at higher speed.

[0266] In a case where the HV transistor is configured in the first CMOS layer 100 and the LV transistor is configured in the second CMOS layer 200, the configuration of the channel of the transistor formed in the semiconductor substrate W1 and the semiconductor substrate W2, respectively, can be set in accordance with the type of the transistor configured, respectively.

[0267] For example, the configuration of the channel of the HV transistor formed in the semiconductor substrate W1 can be silicon.

[0268] For example, the configuration of the channel of the LV transistor formed in the semiconductor substrate W2 can be a configuration in which SiGe is epitaxially grown on the semiconductor substrate W2. Thereby, the characteristics of the LV transistor can be improved.

[0269] In a case where the HV transistor is configured in the first CMOS layer 100 and the LV transistor is configured in the second CMOS layer 200, the configuration of the gate electrode of the transistor formed in the semiconductor substrate W1 and the semiconductor substrate W2, respectively, can be set in accordance with the type of the transistor configured, respectively.

[0270] For example, a WSi gate configuration, a W multi-metal configuration, or the like can be applied to the gate electrode of the HV transistor formed in the semiconductor substrate W1.

[0271] The HV transistor of the WSi gate configuration has, for example, a configuration in which, on a gate insulating film (an oxide film), polycrystal silicon (Poly-Si), tungsten silicide (WSi), and titanium nitride (TiN) are sequentially stacked as a gate electrode, and silicon nitride (SiN) is formed on the gate electrode as a protective layer.

[0272] The HV transistor of the W multi-metal structure has, for example, a structure in which poly-silicon (Poly-Si), titanium nitride (TiN), tungsten nitride (WN), and tungsten (W) are sequentially stacked on a gate insulating film (oxide film) as a gate electrode, and silicon nitride (SiN) is formed on the gate electrode as a protective layer. Such a structure of the gate electrode can be referred to as a "W multi-metal gate".

[0273] A self-aligned silicide structure can be applied to the gate electrode of the LV transistor formed in the semiconductor substrate W2, for example.

[0274] The LV transistor of the self-aligned silicide structure has, for example, a structure in which poly-silicon (Poly-Si) and nickel platinum silicide (NiPtSi) are formed on a gate insulating film (oxide film) as a gate electrode. Such a structure of the gate electrode can also be referred to as a "NiPtSi gate".

[0275] The structures of the gate electrodes of the semiconductor substrate W1 and the semiconductor substrate W2 are designed, for example, in accordance with a reduction in chip area, a performance requirement of the input / output circuit 11, and the like.

[0276] The semiconductor device 1 is not limited to a NAND-type flash memory, and can be a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory). In addition, the semiconductor device 1 can be a memory device in which a transition metal oxide element having a variable resistance characteristic is used as a storage element (a resistance change memory such as a ReRAM (Resistive Random Access Memory)), a memory device in which a phase change element is used as a storage element (a phase change memory such as a PCRAM (Phase Change Random Access Memory)), or a memory device in which a ferroelectric element is used as a storage element (a ferroelectric memory such as a FeRAM (Ferroelectric Random Access Memory)). Furthermore, it is also possible to be used for other memories, other devices.

[0277] Although several embodiments of the present application have been described, these embodiments are presented by way of example and are not intended to limit the scope of the application. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the application. These embodiments and modifications thereof are included in the scope or spirit of the application and are included in the scope of the application as recited in the claims and equivalents thereof.

[0278] Explanation of Reference Signs

[0279] 1, 1A, 1B... semiconductor device, 2... memory controller, 10... memory cell array, 11... input / output circuit, 12... logic controller, 13... register circuit, 14... sequencer, 15... driver circuit, 16... row decoder module, 17... sense amplifier module, 21-28... conductor layer, 31-35... insulator layer, 36... insulating member, 37... sacrificial member, 40... core member, 41... semiconductor layer, 42... laminated film, 43... tunnel insulating film, 44... insulating film, 45... barrier insulating film, 50, 51... insulator layer, 52-54... conductor layer, 55-59... contact, 61... conductor layer, 70, 71... insulator layer, 72-75... conductor layer, 76-80... contact, 81... insulator layer, 82... through hole, 91, 92... insulator layer, 93... conductor layer, 94-96... insulator layer, 100... first CMOS layer, 200... second CMOS layer, 300... memory layer, 400... wiring layer, W1-W3... semiconductor substrate, BW1... first bonded substrate, BW2... second bonded substrate.

Claims

1. A semiconductor device, characterized in that, have: A first chip, comprising a first substrate having a first transistor formed thereon; and The second chip, disposed above the first chip, has a second substrate on which the second transistor is formed. The second substrate includes a first insulating film region and a second insulating film region that respectively penetrate the second substrate. The first chip and the second chip are electrically connected via a first through-hole group and a second through-hole group. The first through-hole group includes at least a first through-hole and a second through-hole respectively penetrating the region of the first insulating film. The second through-hole group includes at least a third through-hole and a fourth through-hole respectively penetrating the region of the second insulating film. The first through-hole group is configured with a different spacing than the second through-hole group.

2. The semiconductor device according to claim 1, characterized in that, The second substrate further includes a third insulating film region that surrounds the active region of the second transistor. The thickness of the third insulating film region is thinner than the thickness of the first insulating film region and the second insulating film region.

3. The semiconductor device according to claim 1, characterized in that, The configuration of the first through hole group is different from that of the second through hole group.

4. The semiconductor device according to claim 3, characterized in that, The spacing between the second through-hole group is greater than the spacing between the first through-hole group. The first through-hole group is configured in an alternating pattern. The second through hole group is configured in a square configuration.

5. The semiconductor device according to claim 1, characterized in that, In a cross section parallel to the surface of the first substrate, the cross-sectional shape of each of the plurality of through holes included in the first through hole group is different from the cross-sectional shape of each of the plurality of through holes included in the second through hole group.

6. The semiconductor device according to claim 5, characterized in that, The cross-sectional shape of each of the plurality of through holes included in the first through hole group is circular. The cross-sectional shape of each of the plurality of through holes included in the second through hole group is a linear shape.

7. The semiconductor device according to claim 1, characterized in that, The first chip also has: The first wiring group includes at least a first wiring and a second wiring respectively disposed on the same layer; and The third wiring is electrically connected to the first transistor. The first through hole is connected to the first wiring. The second through hole is connected to the second wiring. The first wiring is electrically connected to the third wiring.

8. The semiconductor device according to claim 7, characterized in that, The first chip also has a fourth wiring disposed on the same layer as the first wiring group. The third through hole and the fourth through hole are connected to the fourth wiring.

9. The semiconductor device according to claim 7, characterized in that, The first chip also has a second wiring group, which includes at least a fifth wiring and a sixth wiring respectively disposed on the same layer as the first wiring group. The first substrate includes a first impurity diffusion region and a second impurity diffusion region. The third through hole is connected to the fifth wiring. The fourth through hole is connected to the sixth wiring. The fifth wiring is electrically connected to the first impurity diffusion region. The sixth wiring is electrically connected to the second impurity diffusion region.

10. The semiconductor device according to claim 7, characterized in that, The second chip also has a seventh wiring electrically connected to the second transistor. The positions of the upper surfaces of the first through hole and the second through hole are the same as the positions of the upper surfaces of the seventh wiring.

11. The semiconductor device according to claim 1, characterized in that, It also has a fifth through hole. The second substrate further includes a fourth insulating film region extending through the second substrate. The fifth via is contained in the first chip and the second chip, and penetrates the fourth insulating film region.

12. The semiconductor device according to claim 11, characterized in that, The upper surface of the fifth through hole is located above the upper surfaces of each of the multiple through holes included in the first through hole group. The lower surface of the fifth through hole is located below the lower surfaces of each of the multiple through holes included in the first through hole group. In a cross-section parallel to the surface of the first substrate, the cross-sectional area of ​​the upper surface of the fifth through hole is greater than the cross-sectional area of ​​each of the multiple through holes included in the first through hole group.

13. The semiconductor device according to claim 1, characterized in that, It also includes an array chip disposed above the second chip, electrically connected to the first transistor and the second transistor, and having a memory cell array comprising a plurality of memory cells arranged in the stacking direction of the first substrate and the second substrate.

14. The semiconductor device according to claim 13, characterized in that, The second chip includes multiple pads that are bonded to the array chip. In a cross-section parallel to the surface of the first substrate, the cross-sectional area of ​​each of the plurality of pads is larger than the cross-sectional area of ​​each of the plurality of vias included in the first through-hole group. The spacing between the plurality of pads is larger than the spacing between the first through-hole group.

15. The semiconductor device according to claim 13, characterized in that, It also includes a first sense amplifier having the first transistor and the second transistor. The first sense amplifier is contained in the first chip and the second chip. The storage cell array has a first bit line that is electrically connected to a first storage cell among the plurality of storage cells. The first through-hole and the second through-hole are electrically connected to the first transistor. The second transistor is electrically connected to the first transistor via the second via. The first transistor is electrically connected to the first bit line via the first via.

16. The semiconductor device according to claim 13, characterized in that, It also includes a first-line decoder with a third transistor. The first line decoder is contained in the first chip. The storage cell array has a first word line electrically connected to a first storage cell among the plurality of storage cells. The third through-hole is electrically connected to the third transistor. The third transistor is electrically connected to the first word line via the third via.

17. The semiconductor device according to claim 16, characterized in that, The spacing between the second through-hole group is greater than the spacing between the first through-hole group.

18. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: A first chip is formed, the first chip having a first transistor and a first insulating layer located above the first transistor; A second chip is formed, the second chip having a substrate and a first insulating film disposed on the substrate; A first insulating film of the second chip is bonded on top of the first insulating layer of the first chip; Forming a first insulating film region and a second insulating film region that respectively penetrate the substrate; and A first through-hole group and a second through-hole group are formed at different intervals. The first through-hole group includes a plurality of through holes that penetrate the first insulating film region, and the second through-hole group includes a plurality of through holes that penetrate the second insulating film region.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, It also includes the following steps: A second transistor is formed on the substrate; Forming a first contact connected to the second transistor; and After forming the first contact, the first through-hole group, and the second through-hole group, a first wiring is formed on the first contact, a first wiring group is formed on the first through-hole group and in the same layer as the first wiring, and a second wiring group is formed on the second through-hole group and in the same layer as the first wiring.

20. The method for manufacturing a semiconductor device according to claim 18, characterized in that, It also includes the following steps: A second transistor is formed on the substrate; A first contact is formed to connect to the second transistor; as well as A first wiring is formed on the first contact. The steps of forming the first through-hole group and the second through-hole group include: after forming the first wiring, forming the first through-hole group and the second through-hole group until they are at the same height as the upper surface of the first wiring.

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