Silicon carbide suspended structure trench power device and preparation method thereof, chip

Abstract

This application belongs to the field of power device technology and provides a silicon carbide suspended trench power device and its fabrication method and chip. By forming a P-type deep well and a well interconnect layer extending into the central region of the N-type drift region in the intersection region of the trench gate, a suspended P-well is formed in the N-type drift region. The suspended P-well is located below the trench gate and is opposite to the trench gate. The suspended P-well is electrically connected to the well interconnect layer. The doping concentration of the N-type drift region above the suspended P-well is greater than the doping concentration of the N-type doped region below the suspended P-well. This allows for a higher doping concentration in the N-type drift region surrounded by the gate structure, improving the conduction performance of the device. Furthermore, the suspended P-well suppresses the electric field peak in the central region to below the suspended junction, while the electric field in the outer region is located at the corners on both sides of the suspended junction, optimizing the gate reliability of the device.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and particularly relates to a silicon carbide suspended trench power device and its preparation method and chip. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, is widely used in electric vehicles, charging piles, and data electronics due to its advantages such as wide bandgap, high critical breakdown electric field, and high saturation drift velocity. Compared to SiC planar MOSFETs, SiC trench MOSFETs have higher current and power densities, lower on-resistance, higher switching speeds, and better thermal performance. However, due to the high breakdown field strength of SiC material and gate oxide interface defects, the gate corners of SiC trenches need to withstand ultra-high electric fields, which may lead to electrical performance degradation and gate oxide failure, posing a challenge to device reliability.

[0003] From a process technology perspective, existing technologies can effectively reduce the electric field strength at the gate corner of SiC trenches and optimize reliability, but they often bring the side effect of increased on-resistance.

[0004] From a layout design perspective, while existing layout structures such as square, staggered square, and hexagonal layouts optimize the electric field distribution to some extent, they still suffer from problems such as high on-resistance, low current density, and poor short-circuit characteristics. Therefore, there is an urgent need for a technical solution that can improve the trade-off between trench gate reliability and on-resistance. Summary of the Invention

[0005] To address the aforementioned technical issues, this application provides a silicon carbide suspended trench power device, its fabrication method, and a chip, aiming to optimize the performance of the trench silicon carbide power device.

[0006] The first aspect of this application provides a silicon carbide suspended trench power device, the trench silicon carbide power device comprising:

[0007] A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate;

[0008] The interlayer dielectric layer and the trench gate and gate dielectric layer formed in the N-type drift region, wherein the trench gate has a cross-shaped structure and is wrapped by the gate dielectric layer and the interlayer dielectric layer;

[0009] A P-type deep well is formed in the intersection region of the trench gate and extends into the central region of the N-type drift region;

[0010] A well interconnect layer is formed below the P-type deep well, and the well interconnect layer is electrically connected to the P-type deep well;

[0011] A suspending P-well is formed within the N-type drift region. The suspending P-well is located below the trench gate and is disposed opposite to the trench gate. The suspending P-well is electrically connected to the well interconnect layer, and the width of the suspending P-well is greater than the width of the P-type deep well. The doping concentration of the N-type drift region above the suspending P-well is greater than the doping concentration of the N-type drift region below the suspending P-well.

[0012] A heavily doped P-type region formed on and in contact with the P-type deep well;

[0013] Multiple P-type well regions are formed on the N-type drift region and N-type heavily doped regions are located on the P-type well regions; adjacent P-type well regions and adjacent N-type heavily doped regions are isolated by the trench gate; and the P-type well regions and the trench gate are isolated by the gate dielectric layer.

[0014] A first electrode is covered on the interlayer dielectric layer, and the first electrode is electrically connected to the P-type heavily doped region through a contact hole on the interlayer dielectric layer; the contact hole is located above the P-type heavily doped region.

[0015] A second electrode is formed on the back side of the silicon carbide substrate.

[0016] In some embodiments, trench gates are provided around both the P-type deep well and the P-type heavily doped region, and are isolated by a gate dielectric layer.

[0017] The depth of the P-type deep well is greater than the depth of the trench gate, and the depth of the P-type well region is less than the depth of the trench gate.

[0018] In some embodiments, the levitated P-well has a cross-shaped structure, adjacent P-type deep wells are electrically connected through the interconnect layer and the levitated P-well, and the levitated P-well below the trench gate divides the N-type drift region into multiple regions.

[0019] In some embodiments, the suspended P-well is a multi-layered cross-shaped structure, and adjacent layers of the cross-shaped structure are electrically connected through the well interconnection layer.

[0020] In some embodiments, the width of the levitated P-well is the same as the width of the trench gate.

[0021] In some embodiments, the trench gate includes four gates, and adjacent gates are electrically connected to each other through an arched interconnect layer; wherein the included angle between adjacent gates is 90 degrees, the arched interconnect layer is located on the heavily doped P-type region, and is isolated from the heavily doped P-type region by the gate dielectric layer.

[0022] In some embodiments, the depth of the P-type heavily doped region is greater than the depth of the gate dielectric layer, and the levitated P-well is integrally formed with the well interconnect layer.

[0023] In some embodiments, the silicon carbide substrate is a P-type substrate;

[0024] The second electrode is the collector, and the first electrode is the emitter.

[0025] A second aspect of this application also provides a method for fabricating a suspended P-well silicon carbide device as described in any of the preceding claims, the method comprising:

[0026] An N-type drift region is formed on the front side of a silicon carbide substrate by epitaxial growth of an N-type material with a first doping concentration, and a suspended P-well is formed on the N-type drift region.

[0027] A thicker N-type drift region is formed by epitaxy using N-type material with a second doping concentration, and P-type dopant ions are implanted on its surface to form a P-type well region; wherein the second doping concentration is greater than the first doping concentration;

[0028] Under the protection of the first hard film, an N-type heavily doped region is formed in a predetermined region of the P-type well region using an N-type ion implantation process;

[0029] Under the protection of the second hard film, a well interconnect layer, a P-type deep well, and a P-type heavily doped region are formed by multiple P-ion implantation processes, extending into the N-type drift region. The well interconnect layer is in contact with the P-type deep well and the suspended P-well, respectively. The depth of the P-type well region is less than the depth of the P-type deep well, and the P-type heavily doped region is formed on the P-type deep well.

[0030] The gate trench is etched deep into the N-type drift region, and after forming a gate dielectric layer, the gate material is filled to form a trench gate; wherein, the trench gate has a cross-shaped structure, and the P-type heavily doped region is located in the intersection region of the cross-shaped structure;

[0031] An interlayer dielectric layer is formed to cover the trench gate, such that the trench gate is enclosed by the gate dielectric layer and the interlayer dielectric layer;

[0032] Contact holes are formed by etching along a portion of the interlayer dielectric layer, and a first electrode is formed covering the interlayer dielectric layer and contacting the P-type heavily doped region and the N-type heavily doped region, and a second electrode is formed covering the back side of the silicon carbide substrate.

[0033] A third aspect of this application also provides a chip including a trench silicon carbide power device as described in any of the above embodiments.

[0034] The beneficial effects of this application embodiment are as follows: By forming a P-type deep well and a well interconnect layer extending into the central region of the N-type drift region within the cross region of the trench gate, a floating P-well is formed within the N-type drift region. The floating P-well is located below the trench gate and is disposed opposite to the trench gate. The floating P-well is electrically connected to the well interconnect layer, and the doping concentration of the N-type drift region above the floating P-well is greater than the doping concentration of the N-type doped region below the floating P-well. This allows for a higher doping concentration within the N-type drift region enclosed by the gate structure, improving the device's conduction performance. Furthermore, the floating P-well suppresses the electric field peak in the central region to below the floating junction, while the electric field in the peripheral region is located at the corners on both sides of the floating junction, optimizing the device's gate reliability. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a trench silicon carbide power device provided in an embodiment of this application;

[0036] Figure 2 This is another schematic diagram of the trench silicon carbide power device provided in the embodiments of this application;

[0037] Figure 3 This is another schematic diagram of the trench silicon carbide power device provided in the embodiments of this application;

[0038] Figure 4 This is another schematic diagram of the trench silicon carbide power device provided in the embodiments of this application;

[0039] Figure 5 This is another schematic diagram of the trench silicon carbide power device provided in the embodiments of this application;

[0040] Figure 6 This is another schematic diagram of the trench silicon carbide power device provided in the embodiments of this application;

[0041] Figure 7 This is another schematic diagram of the trench silicon carbide power device provided in the embodiments of this application;

[0042] Figure 8 This is a schematic flowchart of the fabrication method of the trench silicon carbide power device provided in the embodiments of this application;

[0043] Figure 9 This is a partial schematic diagram of the fabrication method of the trench silicon carbide power device provided in the embodiments of this application;

[0044] Figure 10 This is a partial schematic diagram of the fabrication method of the trench silicon carbide power device provided in the embodiments of this application;

[0045] Figure 11a , Figure 11bThis is a partial schematic diagram of the fabrication method of the trench silicon carbide power device provided in the embodiments of this application;

[0046] Figure 12 This is a partial schematic diagram of the fabrication method of the trench silicon carbide power device provided in the embodiments of this application;

[0047] Figure 13a , Figure 13b This is a partial schematic diagram of the fabrication method of the trench silicon carbide power device provided in the embodiments of this application;

[0048] Figure 14 This is a partial schematic diagram of the fabrication method of the trench silicon carbide power device provided in the embodiments of this application;

[0049] Figure 15 This is a partial schematic diagram of the fabrication method of the trench silicon carbide power device provided in the embodiments of this application. Detailed Implementation

[0050] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0051] The gate oxide of SiC MOSFET devices is prone to degradation under high electric fields, leading to excessively high electric field strength within the gate oxide layer and affecting device reliability. In traditional SiC MOSFET structures, the JFET region is often designed with a wide width to achieve low on-resistance, but this design may cause the gate oxide layer to withstand excessively high voltage under reverse bias, triggering premature device breakdown. On the other hand, while existing square, staggered square, and hexagonal layout structures optimize the electric field distribution to some extent, they still suffer from problems such as high on-resistance, low current density, and poor short-circuit characteristics.

[0052] To address the aforementioned technical problems, embodiments of this application provide a silicon carbide suspended trench power device, such as... Figure 1 As shown, Figure 1 The schematic diagram (a) shows a horizontal cross-section of a trench silicon carbide power device. Figure 1 The schematic diagram (b) shows a cross-section A of the trench silicon carbide power device. Figure 1 The schematic diagram (c) shows a cross-section B of the trench silicon carbide power device. Figure 1 The schematic diagram (d) shows a cross-sectional view (C) of a trench silicon carbide power device. See also... Figure 1As shown, the trench silicon carbide power device in this embodiment includes: a silicon carbide substrate 210, an N-type drift region 220, a trench gate 320, a gate dielectric layer 310, an interlayer dielectric layer 311, a P-type deep well 410, a well interconnect layer 411, a floating P-well 421, a heavily doped P-type region 420, a P-type well region 231, a heavily doped N-type region 232, a first electrode 110, and a second electrode 120.

[0053] An N-type drift region 220 is formed on the front side of a silicon carbide substrate 210. A gate dielectric layer 310 is formed on the inner wall of a trench within the N-type drift region 220. A trench gate 320 is disposed in the trench. An interlayer dielectric layer 311 is disposed on the trench gate 320. The trench gate 320 is enclosed by the gate dielectric layer 310 and the interlayer dielectric layer 311.

[0054] A P-type deep well 410 is formed in the intersection region of the trench gate 320 and extends into the central region of the N-type drift region 220. A well interconnect layer 411 is formed below the P-type deep well 410 and is electrically connected to the P-type deep well 410. A levitated P-well 421 is formed within the N-type drift region 220. The levitated P-well 421 is located below the trench gate 320 and is disposed opposite to the trench gate 320. The levitated P-well 421 is electrically connected to the well interconnect layer 411, and the width of the levitated P-well 421 is greater than the width of the P-type deep well 410. The doping concentration of the N-type drift region 220 above the levitated P-well 421 is greater than the doping concentration of the N-type drift region 220 below the levitated P-well 421.

[0055] P-type heavily doped regions 420 are formed on and in contact with P-type deep wells 410. Multiple P-type well regions 231 are formed on N-type drift regions 220. N-type heavily doped regions 232 are located on P-type well regions 231. Adjacent P-type well regions 231 and adjacent N-type heavily doped regions 232 are isolated by trench gates 320. Furthermore, P-type well regions 231 and trench gates 320 are isolated by a gate dielectric layer 310. A first electrode 110 covers the gate dielectric layer 310 and is electrically connected to the P-type heavily doped regions 420 via contact holes on the gate dielectric layer 310. The contact holes are located above the P-type heavily doped regions 420. A second electrode 120 is formed on the back side of the silicon carbide substrate 210.

[0056] In this embodiment, a P-type deep well 410 and a well interconnect layer 411 extending into the central region of the N-type drift region 220 are formed in the intersection region of the trench gate 320. A floating P-well 421 is formed within the N-type drift region 220. The floating P-well 421 is located below the trench gate 320 and is disposed opposite to the trench gate 320. The floating P-well 421 is electrically connected to the well interconnect layer 411. The width of the floating P-well 421 is greater than the width of the P-type deep well 410. The doping concentration of the N-type drift region 220 above the floating P-well 421 is greater than the doping concentration of the N-type doped region below the floating P-well 421. This allows for a higher doping concentration within the N-type drift region 220 enclosed by the gate structure, improving the device's conduction performance. Furthermore, the floating P-well 421 suppresses the electric field peak in the central region to below the floating junction, while the electric field in the peripheral region is located at the corners on both sides of the floating junction, optimizing the device's gate reliability.

[0057] In some embodiments, combined with Figure 1 As shown, the trench gate 320 includes four branches, adjacent branches are perpendicular in the horizontal cross section, and the four branches of the trench gate 320 are electrically connected to each other in their intersection region. In the cross-shaped intersection region of the trench gate 320, a double-layer structure of P-type deep well 410 and P-type heavily doped region 420 is provided. The first electrode 110 is electrically connected to the P-type heavily doped region 420 through a contact hole on the interlayer dielectric layer 311. Two branches of the trench gate 320 are opposite each other and are located in a first direction, and the other two branches are opposite each other and are located in a second direction. The first direction is perpendicular to the second direction. The trench gate 320 in the first direction has N-type heavily doped regions 232 on both sides. The trench gate 320 and P-type heavily doped region 420 in the first direction are periodically alternated, so that the device in this embodiment has a high channel density.

[0058] Furthermore, in some embodiments, combined with Figure 1 and Figure 2 As shown, within the regions of cross sections A and B, the doping concentration of the epitaxial region (a portion of the N-type drift region 220) enclosed by the P-type deep well 410, the floating P-well 421, and the gate dielectric layer 310 is at least 10 times higher than the doping concentration of the N-type drift region 220 below the floating P-well 421. The floating junction is grounded through the P-type deep well 410, which helps improve the device's conduction performance. Furthermore, the floating P-well 421 is positioned closer to the silicon carbide substrate 210, and the well interconnect layer 411 connects the P-type deep well 410 and the floating P-well 421 directly below the gate. This allows the device to have a stronger saturation current clamping capability and a more uniform current distribution across the entire device cross section. This avoids the problem of current concentration near the top active region during short circuits, which can lead to heat concentration and meltdown of the top metal.

[0059] In some embodiments, trench gates 320 are provided around both the P-type deep well 410 and the P-type heavily doped region 420, and are isolated by a gate dielectric layer 310. The depth of the P-type deep well 410 is greater than the depth of the trench gate 320, and the depth of the P-type well region 231 is less than the depth of the trench gate 320.

[0060] In this embodiment, the depth of the trench gate 320 is less than the depth of the P-type deep well 410. The P-type deep well 410 and the P-type heavily doped region 420 divide the trench gate 320 into four parts. The gate polysilicon of the four parts can be interconnected through contact holes to transmit gate electrical signals, or they can be interconnected by polysilicon arch bridges.

[0061] In some embodiments, combined with Figure 1 or Figure 2 As shown in section A, the trench gate 320 in section A is led out to the gate electrode through corresponding contact holes, thereby connecting the trench gate 320 (e.g., gate polysilicon material) to realize the transmission of gate electrical signals.

[0062] In some embodiments, see Figure 2 As shown, the suspended P-well 421 has a cross-shaped structure. Adjacent P-type deep wells 410 are electrically connected through an interconnect layer and the suspended P-well 421. Furthermore, the suspended P-well 421 below the trench gate 320 divides the N-type drift region 220 into multiple regions.

[0063] In this embodiment, Figure 2 The schematic diagram (b) shows a cross-section A of the trench silicon carbide power device. Figure 2 The schematic diagram (c) shows a cross-section B of the trench silicon carbide power device. Figure 2 The schematic diagram (d) shows a cross-section C of a trench silicon carbide power device. Adjacent P-type deep wells 410 are electrically connected via an interconnect layer and a floating P-well 421. The floating P-well 421 has a cross-shaped structure in the horizontal cross-section. Thus, the opposing P-type drift regions of the trench gate 320 are divided into upper and lower regions in the vertical cross-section. The doping concentration of the N-type drift region 220 above the floating P-well 421 is greater than that of the N-type drift region 220 below the floating P-well 421, thereby suppressing the electric field peaks in regions A and B below the floating P-well 421 (e.g., ...). Figure 2 (See schematic structures (b) and (c)). The electric field peak in the region of section C is located at the two corners of the suspended P-well 421 (as shown in the diagram). Figure 2The schematic structure (d) shown in the diagram helps improve the reliability of the gate dielectric layer 310. On the other hand, the floating P-well 421 below the gate dielectric layer 310 can form a depletion layer capacitance Cpn in a very large area, which can effectively reduce the total gate-drain parasitic capacitance CGD of the device and improve the switching frequency of the device. In addition, the P-type deep well 410 and the floating P-well 421 increase the overlap area of ​​the same trench gate 320, enhance the gate-source coupling effect, and can play a role in shunting the displacement current in high dV / dt applications, reducing the voltage drop formed by the displacement current in the gate circuit, thereby avoiding gate mis-turn-on, which is conducive to achieving zero-voltage turn-off, reducing the complexity of the application system and switching losses.

[0064] In some embodiments, combined with Figure 3 As shown, the suspended P-well 421 has a multi-layered cross-shaped structure, and each adjacent cross-shaped structure is electrically connected through a well interconnection layer 411.

[0065] In this embodiment, Figure 3 The schematic diagram (b) shows a cross-section A of the trench silicon carbide power device. Figure 3 The schematic diagram (c) shows a cross-section B of the trench silicon carbide power device. Figure 3 The schematic structure (d) is a cross-sectional diagram of the trench silicon carbide power device. The suspended P-well 421 is a multi-layer cross-shaped structure. The horizontal cross-section of each layer of suspended P-well 421 is a cross-shaped structure. Adjacent suspended P-wells 421 are connected by a well interconnect layer 411.

[0066] In some embodiments, in the direction from the silicon carbide substrate 210 to the source layer, the N-type drift region 220 between the lowest first-layer suspended P-well 421 and the silicon carbide substrate 210 is the first-layer drift region, the N-type drift region 221 between the second-layer suspended P-well 421 and the first-layer suspended P-well 421 is the second-layer drift region, and so on.

[0067] In some embodiments, the width of the levitated P-well 421 is the same as the width of the trench gate 320.

[0068] In this embodiment, the levitated P-well 421 has the same width as the trench gate 320. In the horizontal cross-section, the levitated P-well 421 and the trench gate 320 have the same shape, such that each region of the trench gate 320 has a corresponding levitated P-well 421 in the drain layer direction. The doping concentration of the N-type drift region 220 above the levitated P-well 421 is greater than the doping concentration of the N-type drift region 220 below the levitated P-well 421, thereby suppressing the electric field peaks in regions A and B below the levitated P-well 421 (e.g., ...). Figure 2 (See schematic structures (b) and (c)). The electric field peak in the region of section C is located at the two corners of the suspended P-well 421 (as shown in the diagram). Figure 2The schematic structure (d) shown in the figure helps to improve the reliability of the gate dielectric layer 310. On the other hand, the floating P-well 421 below the gate dielectric layer 310 can form a depletion layer capacitance Cpn in a very large area. Since 1 / CGD=1 / gd+1 / Cpn, the total gate-drain parasitic capacitance CGD of the device can be effectively reduced, thereby increasing the switching frequency of the device.

[0069] In some embodiments, combined with Figure 4 As shown, the trench gate 320 includes four gates, and adjacent gates are electrically connected to each other through an arched interconnect layer; wherein, the included angle between adjacent gates is 90 degrees, the arched interconnect layer is located on the P-type heavily doped region 420, and is isolated from the P-type heavily doped region 420 by the gate dielectric layer 310.

[0070] In this embodiment, Figure 4 The schematic diagram (b) shows a cross-section A of the trench silicon carbide power device. Figure 4 The schematic diagram (c) shows a cross-section B of the trench silicon carbide power device. Figure 4 The schematic diagram (d) shows a cross-sectional view (C) of a trench silicon carbide power device. The four polysilicon gates of the trench gate 320 extend into the N-type drift region 220. The upper surface of each polysilicon gate can be flush with the upper surface of the heavily doped P-type region 420. This increases the thickness of the field oxide layer, reduces the distance between the gate polysilicon and the source layer, and minimizes the influence of the gate layer on the gate polysilicon. Furthermore, in this configuration, gate electrical signals can be transmitted between adjacent gate polysilicon layers via an arched interconnect layer. This arched interconnect layer is disposed on the heavily doped P-type region 420, and is isolated from the heavily doped P-type region 420 by the gate dielectric layer 310.

[0071] In some embodiments, see Figure 5 As shown, the depth of the P-type heavily doped region 420 is greater than the depth of the gate dielectric layer 310, and the suspended P-well 421 is integrally formed with the well interconnect layer 411.

[0072] In this embodiment, Figure 5 The schematic diagram (b) shows a cross-section A of the trench silicon carbide power device. Figure 5 The schematic diagram (c) shows a cross-section B of the trench silicon carbide power device. Figure 5 The schematic diagram (d) shows the cross-sectional view (C) of a trench silicon carbide power device. Figure 5As shown, the floating P-well 421 is disposed below the gate and grounded through the P-type deep well 410. In sections A and B, the gate dielectric layer 310 is located on the N-type drift region 220, and part of the trench gate 320 is located on the N-type drift region 220. In section C, the gate dielectric layer 310 extends into the N-type drift region 220, and the P-type well region 231 and the N-type heavily doped region 232 are located on both sides of the trench gate 320.

[0073] In some embodiments, the suspended P-well 421 and the well interconnect layer 411 are integrally formed, and P-type doped ions can be injected through the same photomask to form the suspended P-well 421 and the well interconnect layer 411.

[0074] In some embodiments, see Figure 6 As shown, the first electrode 110 has a convex structure, and the protrusion of the first electrode 110 extends into the P-type heavily doped region 420.

[0075] Figure 5 The schematic diagram (a) shows a horizontal cross-section of a trench-gate silicon carbide power device. Figure 5 The schematic diagram (b) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 5 The schematic diagram (c) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 5 The schematic diagram (d) shows a cross-sectional view of the trench gate silicon carbide power device. In this embodiment, the protrusion of the first electrode 110 extends into the groove of the heavily doped P-type region 420. The protrusion of the first electrode 110 is surrounded by the heavily doped P-type region 420 in the horizontal cross-section. The heavily doped P-type region 420 is annular in the horizontal cross-section, which has a stronger depletion effect compared with other layouts. This is beneficial for the device to enter the saturation region, clamp the saturation current, and optimize the short-circuit characteristics of the device.

[0076] In some embodiments, see Figure 7 As shown, the first electrode 110 has a convex structure. The protrusion of the first electrode 110 contacts the N-type drift region 220 through the contact holes of the P-type heavily doped region 420 and the P-type deep well 410. A Schottky metal layer is also provided between the protrusion of the first electrode 110 and the N-type drift region 220.

[0077] Figure 7 The schematic diagram (a) shows a horizontal cross-section of a trench-gate silicon carbide power device. Figure 7 The schematic diagram (b) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 7 The schematic diagram (c) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 7The schematic diagram (d) shows a cross-sectional view of the trench-gate silicon carbide power device. In this embodiment, a Schottky metal layer 510 is provided between the protrusion of the first electrode 110 and the N-type drift region 220, thereby forming a Schottky diode between the first electrode 110 and the N-type drift region 220. By integrating the Schottky diode, it plays a role in reverse freewheeling, reducing the reverse freewheeling voltage of the device to 1-1.5V and improving the reverse freewheeling characteristics of the device.

[0078] In some embodiments, the silicon carbide substrate 210 is a P-type substrate; the second electrode 120 is a collector electrode, and the first electrode 110 is an emitter electrode.

[0079] In this embodiment, when the silicon carbide substrate 210 is a P-type substrate, the trench silicon carbide power device can be an IGBT structure, with the first electrode 110 being the emitter and the second electrode 120 being the collector.

[0080] In some embodiments, the silicon carbide substrate 210 can be N-type doped, in which case the trench silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain.

[0081] In some embodiments, the silicon carbide substrate 210 includes a P-type substrate and an N-type substrate, with the N-type substrate located in the peripheral region of the P-type substrate. In this case, the trench silicon carbide power device can be an IGBT structure, with the first electrode 110 being the emitter and the second electrode 120 being the collector.

[0082] This application also provides a method for fabricating a trench silicon carbide power device, see [link to relevant documentation]. Figure 8 As shown, the preparation method includes steps S100 to S700.

[0083] In step S100, an N-type drift region 220 is epitaxially formed on the front side of the silicon carbide substrate 210 using an N-type material with a first doping concentration, and a suspended P-well 421 is formed on the N-type drift region 220.

[0084] In this embodiment, combined with Figure 9 As shown, the silicon carbide substrate 210 can be a highly doped substrate, and a lightly doped epitaxial layer is formed on the silicon carbide substrate 210 as an N-type drift region 220.

[0085] In some embodiments, the injection depth of the suspended P-well 421 is 0.4-0.6 μm.

[0086] In some embodiments, the number of implantations into the suspended P-well 421 is 3-5, with the implantation energy decreasing sequentially, and the doping concentration being 1E16 cm⁻¹. -3 -2E18 cm -3 .

[0087] In step S200, an N-type drift region 220 is formed by epitaxy using N-type material with a second doping concentration, and P-type dopant ions are implanted on its surface to form a P-type well region 231.

[0088] In this embodiment, combined with Figure 10 As shown, after forming the levitated P-well 421, a second epitaxial layer of N-type material is formed. The second epitaxial layer uses a doped material with a higher doping concentration. The doping concentration of the N-type material in the second epitaxial layer is the second doping concentration, which is greater than the first doping concentration. This is beneficial to improve the conduction performance of the device and to form a charge balance with the levitated P-well 421.

[0089] In some embodiments, the doping concentration of the N-type drift region 220 is 3E15-1.5E16 cm⁻¹. -3 .

[0090] In some embodiments, the thickness and concentration of the N-type drift region 220 depend on the device withstand voltage rating.

[0091] In some embodiments, a hard mask is formed using a P-well photolithography mask, and a P-type well region 231 is formed by ion implantation with an implantation depth of 0.4-0.6 μm. The P-type ion implantation process is performed 3-5 times, with the implantation energy decreasing sequentially. The doping concentration of the P-type well region 231 is 1E16-2E18 cm⁻¹. -3 .

[0092] In step S300, under the protection of the first hard film 601, an N-type heavily doped region 232 is formed in a preset region of the P-type well region 231 using an N-type ion implantation process.

[0093] In this embodiment, an N-type heavily doped region 232 is formed using an N-type ion implantation process under the protection of the first hard film 601. The implantation depth of the N-type ion implantation process is 0.2-0.3 μm, the number of implantation cycles is 3-4, the energy of the N-type ion implantation process decreases sequentially, and the doping concentration of the N-type heavily doped region 232 is 1E19-1E20 cm⁻¹. -3 .

[0094] In some embodiments, if the silicon carbide substrate 210 is P-type doped, the trench silicon carbide power device is an IGBT structure. In the IGBT structure fabrication process, a hard mask can be formed by isotropic CVD deposition of silicon oxide, followed by anisotropic dry etching of the silicon oxide hard mask. The silicon oxide on the SiC surface is etched away, leaving the silicon oxide hard masks on both sides of the hard mask. The silicon oxide hard masks on both sides of the hard mask effectively mask the channel, and ion implantation forms an N-type heavily doped region 232.

[0095] In step S400, under the protection of the second hard film 602, a well interconnect layer extending into the N-type drift region 220, a P-type deep well 410, and a P-type heavily doped region 420 are formed by multiple P-ion implantation processes.

[0096] In this embodiment, combined with Figure 12 As shown, under the protection of the second hard film, P-type doped ions are implanted in a preset region through multiple P-type ion implantation processes with different implantation energies and different implantation doses, thereby forming a well interconnect layer 411, a P-type deep well 410, and a P-type heavily doped region 420 in sequence. The well interconnect layer is in contact with the P-type deep well 410 and the suspended P-well, respectively. The depth of the P-type well region 231 is less than the depth of the P-type deep well 410, and the P-type heavily doped region 420 is formed on the P-type deep well 410.

[0097] In some embodiments, the doping concentrations of the well interconnect layer 411, the P-type deep well 410, and the P-type heavily doped region 420 increase sequentially.

[0098] In some embodiments, under the protection of the second hard film 602, high-energy P-type ion implantation forms a well interconnect layer and a P-type deep well 410 (or channel implantation). The implantation depth of the P-type ion implantation process is 1.0-4.0 μm, the number of implantation cycles is 4-6, and the doping concentration is 1E16-2E18 cm⁻¹. -3 .

[0099] In some embodiments, after forming the P-type deep well 410, a second P-type ion implantation process is performed to form a heavily doped P-type region 420, the implantation depth of which is approximately 0.2-0.6 μm.

[0100] In some embodiments, the P-type heavily doped region 420 is implanted 2-4 times, the implantation energy of the P-type heavily doped region 420 decreases sequentially, and the doping concentration of the P-type heavily doped region 420 is greater than 1E19cm⁻¹. -3 After the P-type ion implantation process is completed, the device is annealed at 1600-1800℃.

[0101] In step S500, the gate trench 603 is etched deep into the N-type drift region 220, and after forming the gate dielectric layer 310, the gate material is filled to form the trench gate 320.

[0102] Combination Figure 13a and Figure 13b As shown, Figure 13a for Figure 2 The diagram shows a cross-section C of the structure during a portion of the fabrication process. Figure 13b yes Figure 2The diagram shows cross-sections A and B of the structure in part of the fabrication process. In this embodiment, the gate trench 603 is formed by dry etching. The depth of the gate trench 603 is about 0.8-2.0 μm. Sacrificial oxidation improves the morphology of the trench and SiC surface. The gate trench 603 has a cross-shaped structure in the horizontal cross section. The trench gate 320 has a cross-shaped structure. The P-type heavily doped region 420 is located in the intersection region of the cross-shaped structure.

[0103] In some embodiments, combined with Figure 14 As shown, gate oxide is formed through thermal oxidation and CVD deposition. The thickness of the gate oxide on the trench sidewall and the bottom is basically the same. Polysilicon material is deposited to form the gate layer, and TEOS & BPSG are deposited to form the gate dielectric layer 310 (or field oxide layer).

[0104] In step S600, an interlayer dielectric layer 311 is formed to cover the trench gate 320, so that the trench gate 320 is wrapped by the gate dielectric layer 310 and the interlayer dielectric layer 311.

[0105] Combination Figure 14 As shown, an interlayer dielectric layer 311 is formed by depositing a relatively thick insulating dielectric material.

[0106] In step S700, a contact hole is formed by etching along a portion of the interlayer dielectric layer, and a first electrode is formed covering the interlayer dielectric layer and contacting the P-type heavily doped region and the N-type heavily doped region, and a second electrode is formed covering the back side of the silicon carbide substrate.

[0107] In this embodiment, combined with Figure 15 As shown, a contact hole is formed by etching along the region above the P-type heavily doped region 420, and a first electrode 110 is formed covering the gate dielectric layer 310 and contacting the P-type heavily doped region 420 and the N-type heavily doped region 232, and a second electrode 120 is formed covering the back side of the silicon carbide substrate 210.

[0108] In some embodiments, the first electrode 110 is formed by depositing a metal material and contacts the N-type drift region 220 through a contact hole in the P-type heavily doped region 420 via a Schottky metal layer.

[0109] In some embodiments, if the silicon carbide substrate 210 in step S100 can be N-type doped, the trench silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain.

[0110] In some embodiments, the source and drain can be formed by metal deposition, thereby forming an ohmic contact between the source and drain and the semiconductor material.

[0111] In some embodiments, if the silicon carbide substrate 210 in step S100 can be P-type doped, then the trench silicon carbide power device can be an IGBT structure.

[0112] This application also provides a chip including a trench silicon carbide power device as described in any of the above embodiments.

[0113] In some embodiments, the chip includes a chip substrate on which one or more trench silicon carbide power devices are disposed, the trench silicon carbide power devices including those described in any of the above embodiments.

[0114] In one specific application embodiment, when the silicon carbide substrate 210 is N-type doped, the trench silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain. When the silicon carbide substrate 210 is P-type doped, the trench silicon carbide power device can be an IGBT structure, with the first electrode 110 as the emitter and the second electrode 120 as the collector.

[0115] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.

[0116] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0117] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0118] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0119] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0120] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0121] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A suspended P-well silicon carbide device, characterized in that, The suspended P-well silicon carbide device includes: A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate; The interlayer dielectric layer and the trench gate and gate dielectric layer formed in the N-type drift region, wherein the trench gate has a cross-shaped structure and is wrapped by the gate dielectric layer and the interlayer dielectric layer; A P-type deep well is formed in the intersection region of the trench gate and extends into the central region of the N-type drift region; A well interconnect layer is formed below the P-type deep well, and the well interconnect layer is electrically connected to the P-type deep well; A suspending P-well is formed within the N-type drift region. The suspending P-well is located below the trench gate and is disposed opposite to the trench gate. The suspending P-well is electrically connected to the well interconnect layer, and the width of the suspending P-well is greater than the width of the P-type deep well. The doping concentration of the N-type drift region above the suspending P-well is greater than the doping concentration of the N-type drift region below the suspending P-well. A heavily doped P-type region formed on and in contact with the P-type deep well; Multiple P-type well regions formed on the N-type drift region and N-type heavily doped regions located on the P-type well regions; The adjacent P-type well regions and the adjacent heavily doped N-type regions are isolated by the trench gate; and the P-type well regions and the trench gate are isolated by the gate dielectric layer. A first electrode is covered on the interlayer dielectric layer, and the first electrode is electrically connected to the P-type heavily doped region through a contact hole on the interlayer dielectric layer; the contact hole is located above the P-type heavily doped region. A second electrode is formed on the back side of the silicon carbide substrate.

2. The suspended P-well silicon carbide device as described in claim 1, characterized in that, The periphery of both the P-type deep well and the P-type heavily doped region is provided with a trench gate, which is isolated by a gate dielectric layer. The depth of the P-type deep well is greater than the depth of the trench gate, and the depth of the P-type well region is less than the depth of the trench gate.

3. The suspended P-well silicon carbide device as described in claim 1, characterized in that, The suspended P-well has a cross-shaped structure. Adjacent P-type deep wells are electrically connected through the interconnect layer and the suspended P-well. Furthermore, the suspended P-well below the trench gate divides the N-type drift region into multiple areas.

4. The suspended P-well silicon carbide device as described in claim 1, characterized in that, The suspended P-well is a multi-layered cross-shaped structure, and each adjacent layer of the cross-shaped structure is electrically connected through the well interconnection layer.

5. The suspended P-well silicon carbide device as described in claim 3 or 4, characterized in that, The width of the suspended P-well is the same as the width of the trench gate.

6. The suspended P-well silicon carbide device as described in claim 1, characterized in that, The trench gate includes four gates, and adjacent gates are electrically connected to each other through an arched interconnect layer; wherein the included angle between adjacent gates is 90 degrees, the arched interconnect layer is located on the P-type heavily doped region, and is isolated from the P-type heavily doped region by the gate dielectric layer.

7. The suspended P-well silicon carbide device as described in claim 1, characterized in that, The depth of the P-type heavily doped region is greater than the depth of the gate dielectric layer, and the levitated P-well is integrally formed with the well interconnect layer.

8. The suspended P-well silicon carbide device as described in claim 1, characterized in that, The silicon carbide substrate is a P-type substrate; The second electrode is the collector, and the first electrode is the emitter.

9. A method for fabricating a suspended P-well silicon carbide device as described in any one of claims 1-8, characterized in that, The preparation method includes: An N-type drift region is formed on the front side of a silicon carbide substrate by epitaxial growth of an N-type material with a first doping concentration, and a suspended P-well is formed on the N-type drift region. A thicker N-type drift region is formed by epitaxy using N-type material with a second doping concentration, and P-type dopant ions are implanted on its surface to form a P-type well region; wherein the second doping concentration is greater than the first doping concentration; Under the protection of the first hard film, an N-type heavily doped region is formed in a predetermined region of the P-type well region using an N-type ion implantation process; Under the protection of the second hard film, a well interconnect layer, a P-type deep well, and a P-type heavily doped region are formed by multiple P-ion implantation processes, extending into the N-type drift region. The well interconnect layer is in contact with the P-type deep well and the suspended P-well, respectively. The depth of the P-type well region is less than the depth of the P-type deep well, and the P-type heavily doped region is formed on the P-type deep well. The gate trench is etched deep into the N-type drift region, and after forming a gate dielectric layer, the gate material is filled to form a trench gate; wherein, the trench gate has a cross-shaped structure, and the P-type heavily doped region is located in the intersection region of the cross-shaped structure; An interlayer dielectric layer is formed to cover the trench gate, such that the trench gate is enclosed by the gate dielectric layer and the interlayer dielectric layer; Contact holes are formed by etching along a portion of the interlayer dielectric layer, and a first electrode is formed covering the interlayer dielectric layer and contacting the P-type heavily doped region and the N-type heavily doped region, and a second electrode is formed covering the back side of the silicon carbide substrate.

10. A chip, characterized in that, Including the suspended P-well silicon carbide device as described in any one of claims 1-8.

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