Double-source transverse silicon carbide power device with partitioned doped floating island
By employing a partitioned doped floating island design in lateral silicon carbide power devices, the electric field distribution is optimized, solving the problem of dynamic on-resistance degradation and achieving a synergistic improvement in low on-resistance and high breakdown voltage.
Patent Information
- Application Number
- CN202511739091.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-02-13
AI Technical Summary
Existing lateral silicon carbide power devices suffer from dynamic on-resistance degradation during dynamic processes, and the contradiction between breakdown voltage and on-resistance is difficult to reconcile.
A partitioned doped floating island design is adopted, which includes setting multiple P-type doped semiconductor floating islands in the drift region. By increasing the ion implantation dose and source metal connection in the side floating island region, the floating island potential is reduced to zero and auxiliary depletion is achieved, thus optimizing the electric field distribution.
It significantly reduces the degradation of dynamic on-resistance of the device, improves the breakdown voltage, enhances the overall performance of the device, and achieves a balance between low on-resistance and high breakdown voltage.
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Abstract
Description
Technical Field
[0001] This invention relates to the field of silicon carbide power device technology, and in particular to a dual-source lateral silicon carbide power device with partitioned doped floating islands. Background Technology
[0002] Silicon carbide (SiC) power devices have become a core research direction for next-generation high-voltage, high-power electronic devices due to their advantages such as wide bandgap, high breakdown field strength, and high thermal conductivity. In applications such as new energy vehicles, smart grids, and high-frequency power electronic systems, SiC devices can operate at higher voltages and frequencies compared to silicon devices, while significantly reducing conduction and switching losses. Therefore, they are widely considered a key technology for achieving efficient energy conversion. However, with the widespread adoption of lateral silicon carbide power devices in practical applications, the degradation of their dynamic on-resistance will gradually become a significant bottleneck limiting device performance.
[0003] The drift region structure of conventional floating island devices is relatively simple, typically consisting of a single doped region. During device operation, the electric field distribution in the drift region is difficult to precisely control, easily leading to electric field concentration. This concentration makes it difficult to increase the device's breakdown voltage, limiting its breakdown voltage capability. Simultaneously, due to the lack of an effective auxiliary depletion mechanism, the drift region's depletion is insufficient, resulting in a relatively high on-resistance. After the device undergoes multiple switching and other dynamic processes, the on-resistance further increases, exhibiting dynamic on-resistance degradation. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a dual-source lateral silicon carbide power device with partitioned doped floating islands. This dual-source lateral silicon carbide power device with partitioned doped floating islands can achieve a smaller difference between the dynamic resistance after the switching process and the static resistance before the switching process, that is, to achieve low dynamic resistance degradation, while improving the contradictory relationship between the device breakdown voltage and on-resistance.
[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:
[0006] A dual-source lateral silicon carbide power device with partitioned doped floating islands includes an N-type doped semiconductor epitaxial layer of silicon carbide, a P-type doped semiconductor well, two source metals, and several P-type doped semiconductor floating islands.
[0007] P-type doped semiconductor wells are arranged on the top side of the silicon carbide N-type doped semiconductor epitaxial layer.
[0008] Several P-type doped semiconductor floating islands are arranged equidistantly on the top of the silicon carbide N-type doped semiconductor epitaxial layer on one side of the P-type doped semiconductor well.
[0009] Each P-type doped semiconductor island includes a central island region and side island regions arranged on both sides of the central island region; wherein the P-type doping concentration of each side island region is greater than the doping concentration of the central island region.
[0010] The P-type doped semiconductor island adjacent to the P-type doped semiconductor well is called the first floating island. One source metal is placed on the top of the P-type doped semiconductor well, and the bottom surface of the other source metal is placed close to the upper surface of the first floating island.
[0011] The lateral spacing between the first floating island and the P-type doped semiconductor well is not less than A; where A is the minimum distance required for the device current to be turned on.
[0012] The number of floating islands in a P-type doped semiconductor is greater than or equal to 2.
[0013] The two side island regions in each P-type doped semiconductor island are of equal length and have the same P-type doping concentration.
[0014] The central island region and the two side island regions of each P-type doped semiconductor island are of equal length.
[0015] Let wpi be the distance between two adjacent P-type doped semiconductor floating islands, then wpi ≤ W D And wpi < 1µm; where W D The width of the depletion region formed by the side floating island region and the silicon carbide N-type doped semiconductor epitaxial layer.
[0016] W D The calculation formula is:
[0017]
[0018] in:
[0019]
[0020] In the formula, ε s V is the dielectric constant of SiC; bi q represents the built-in potential of the side floating island region; q represents the elementary charge.
[0021] 'a' represents the slope of the net doping concentration as a function of spatial location; where net doping is the absolute value of the difference between the P-type doping concentration and the concentration of the N-type doped semiconductor epitaxial layer in the side floating island region.
[0022] k is the Boltzmann constant, T is the ambient temperature, and n i denoted as the intrinsic carrier concentration of SiC, and denoted as a constant.
[0023] NA The P-type doping concentration in the side floating island region; N D The concentration of the N-type doped semiconductor epitaxial layer.
[0024] The optimal value of wpi is selected based on the simulation results of the device's dynamic resistance degradation.
[0025] The difference in P-type doping concentration between the side island region and the central island region in each P-type doped semiconductor island is denoted as ΔN. mpi Then ΔN mpi The optimal value is selected based on the co-simulation results of the device's dynamic resistance degradation degree and device quality factors.
[0026] The number of floating islands in a P-type doped semiconductor is four, the optimal value for wpi is 0.3µm, and ΔN mpi The optimal value is 1.9 × 10 17 cm -3 .
[0027] The present invention has the following beneficial effects:
[0028] 1. This invention achieves zeroing of the floating island potential and auxiliary depletion by increasing the source metal connected to the first floating island potential. Simultaneously, by increasing the ion implantation dose in the two side floating island regions, the concentration difference and built-in potential between the P-type doped semiconductor floating island and the silicon carbide N-type doped semiconductor epitaxial layer are increased. This results in complete depletion of the silicon carbide N-type doped semiconductor epitaxial layer between the P-type doped semiconductor floating islands under static conditions, thereby achieving potential clamping. Holes can be transported through the built-in potential, thus achieving low dynamic on-resistance degradation of the device.
[0029] 2. In this invention, each P-type doped semiconductor floating island is partitioned doped to form a synergistic effect of charge compensation and electric field shaping, which helps to deplete the drift region and thus allows for an increase in the doping concentration of the epitaxial layer. This achieves low on-resistance while effectively taking into account the high breakdown voltage of the device, thereby improving the contradictory relationship between the breakdown voltage and on-resistance of the device.
[0030] 3. This invention is of great significance in balancing performance improvement and process feasibility, and provides a new solution for the design of high-performance lateral silicon carbide power devices. Attached Figure Description
[0031] Figure 1 The diagram shows a structural schematic of a dual-source lateral silicon carbide power device with partitioned doped floating islands according to the present invention (the device provided in this embodiment).
[0032] Figure 2 A schematic diagram of a conventional floating island device is shown.
[0033] Figure 3 The results show the trend of dynamic on-resistance degradation of conventional floating island devices under different wpi and the device provided in this embodiment under different wpi and different ΔNmpi conditions.
[0034] Figure 4 The breakdown voltage of the device provided in this embodiment varies under different wpi and different ΔNmpi conditions.
[0035] Figure 5 The results show the dynamic on-resistance variation trend of the device provided in this embodiment under different wpi and different ΔNmpi conditions.
[0036] Figure 6 The results show the trend of FOM value variation of the device provided in this embodiment under different wpi and different ΔNmpi conditions.
[0037] Figure 7 This embodiment shows the doping concentration N in different drift regions of the device provided at the same wpi. d The trend of dynamic on-resistance degradation of the device under different ΔNmpi.
[0038] Figure 8 This embodiment shows the doping concentration N in different drift regions of the device provided at the same wpi. d The breakdown voltage of the device varies under different ΔNmpi.
[0039] Figure 9 This embodiment shows the doping concentration N in different drift regions of the device provided at the same wpi. d The dynamic on-resistance of the device varies under different ΔNmpi.
[0040] Figure 10 This shows that, under the same wpi, conventional floating island devices at different N values... d The following and this embodiment provide devices in different N d The trend of FOM value variation of the device under different ΔNmpi conditions.
[0041] Figure 11 This diagram shows the result after the silicon carbide N-type doped semiconductor epitaxial layer is prepared in step 1.
[0042] Figure 12 The diagram shows the result after the P-type doped semiconductor well is fabricated in step 2.
[0043] Figure 13 This diagram shows a complete fabrication of the semiconductor N+ source region and semiconductor drain region in step 3.
[0044] Figure 14The diagram shows the completed semiconductor body contact P+ region fabrication in step 4.
[0045] Figure 15 This diagram shows the completed fabrication of the central floating island region of the three P-type doped semiconductor floating islands in step 5.
[0046] Figure 16 The diagram shows the completed fabrication of the two side island regions of the three P-type doped semiconductor floating islands in step 6.
[0047] Figure 17 The diagram shows the result after the gate oxide layer is fabricated in step 7.
[0048] Figure 18 This diagram shows the result after the metal gate fabrication is completed in step 8.
[0049] Figure 19 This shows a schematic diagram after the mid-field oxide layer is prepared in step 9.
[0050] Figure 20 The diagram shows the result after the electrode contact hole is prepared in step 10.
[0051] Figure 21 The diagram shows a complete preparation of the source metal and drain metal in step 11.
[0052] Among them are:
[0053] 1. Silicon substrate; 2. Buried oxide layer; 3. Silicon carbide N-type doped semiconductor epitaxial layer; 4. Side floating island region; 5. Central floating island region; 6. Semiconductor drain region; 7. P-type doped semiconductor region; 8. Semiconductor bulk contact P+ region; 9. Semiconductor N+ source region; 10. P-type doped semiconductor well; 11. Gate oxide layer; 12. Source metal; 13. Gate metal; 14. Drain metal; 15. Field oxide layer. Detailed Implementation
[0054] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.
[0055] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.
[0056] like Figure 1 As shown, a dual-source lateral silicon carbide power device with partitioned doped floating islands includes a silicon substrate 1, a buried oxide layer 2, a silicon carbide N-type doped semiconductor epitaxial layer 3, several P-type doped semiconductor floating islands, a semiconductor drain region 6, a P-type doped semiconductor region 7, a semiconductor body contact P+ region 8, a semiconductor N+ source region 9, a P-type doped semiconductor well 10, a gate oxide layer 11, two source metals 12, a gate metal 13, a drain metal 14, and a field oxide layer 15.
[0057] The silicon substrate 1, buried oxide layer 2, silicon carbide N-type doped semiconductor epitaxial layer 3, and field oxide layer 15 are arranged sequentially from bottom to top. The insulating dielectric of the gate oxide layer is preferably SiO2, but can also be a high-k dielectric such as HfO2.
[0058] The aforementioned P-type doped semiconductor well 10 and semiconductor drain region 6 are disposed on the top two sides of the silicon carbide N-type doped semiconductor epitaxial layer; the semiconductor body contact P+ region 8 and semiconductor N+ source region 9 are disposed side by side on the top of the P-type doped semiconductor well. In this embodiment, the right side of the semiconductor body contact P+ region and the left side of the semiconductor N+ source region are closely connected, and both are completely surrounded by the P-type doped semiconductor well.
[0059] Several P-type doped semiconductor islands are equidistantly arranged side-by-side on top of the silicon carbide N-type doped semiconductor epitaxial layer between the P-type doped semiconductor well and the semiconductor drain region. Each P-type doped semiconductor island includes a central island region 5 and side island regions 4 arranged on both sides of the central island region.
[0060] Furthermore, the number of P-type doped semiconductor floating islands is preferably 2 to 4. In this embodiment, it is preferably four, which are the first floating island, the second floating island, the third floating island, and the fourth floating island from the P-type doped semiconductor well to the semiconductor drain region.
[0061] The lateral spacing between the first floating island and the P-type doped semiconductor well is not less than A; where A is the minimum distance required for the device current to conduct. In this embodiment, A is preferably 0.8µm.
[0062] In each P-type doped semiconductor floating island, the two side floating island regions are of equal length, and the P-type doping concentration in each side floating island region is greater than that in the central floating island region. In this embodiment, the lengths of the central floating island region and the two side floating island regions of each P-type doped semiconductor floating island are preferably equal, and the P-type doping concentrations in the two side floating island regions are equal.
[0063] One of the two source metals is placed on top of the P-type doped semiconductor well, and the other source metal is placed on the bottom surface of the first floating island.
[0064] like Figure 2As shown, the drift region structure of a conventional floating island is relatively simple, typically consisting of a single doped region. During device operation, the electric field distribution in the drift region is difficult to precisely control, easily leading to electric field concentration. This concentration makes it difficult to increase the device's breakdown voltage, limiting its breakdown voltage capability. Simultaneously, due to the lack of an effective auxiliary depletion mechanism in the drift region, the depletion level is insufficient, resulting in a relatively high on-resistance. After the device undergoes multiple switching and other dynamic processes, the on-resistance further increases, exhibiting dynamic resistance degradation.
[0065] The dual-source lateral silicon carbide power device with partitioned doped floating islands provided in this embodiment (hereinafter referred to as the device provided in this embodiment) achieves zeroing of the floating island potential and auxiliary depletion by adding a source metal connected to the potential of the first floating island. At the same time, by increasing the ion implantation dose in the two side floating island regions, the concentration difference and built-in potential between the P-type doped semiconductor floating island and the silicon carbide N-type doped semiconductor epitaxial layer are increased, so that the silicon carbide N-type doped semiconductor epitaxial layer between the P-type doped semiconductor floating islands is completely depleted under static conditions, thereby achieving potential clamping. Holes can be transported through the built-in potential. This not only significantly reduces the local electric field intensity in the drift region, but also ensures that the device can quickly recover its low-resistance conduction characteristics after being turned off, thereby effectively improving the degradation of low dynamic on-resistance while maintaining the breakdown voltage.
[0066] Let wpi be the distance between two adjacent P-type doped semiconductor floating islands, then wpi ≤ W D And wpi < 1µm; where W D The width of the depletion region formed by the side floating island region and the silicon carbide N-type doped semiconductor epitaxial layer.
[0067] W D The calculation formula is:
[0068]
[0069] in:
[0070]
[0071] In the formula, ε s V is the dielectric constant of SiC; bi q represents the built-in potential of the side floating island region; q represents the elementary charge.
[0072] 'a' represents the slope of the net doping concentration as a function of spatial location; where net doping is the absolute value of the difference between the P-type doping concentration and the concentration of the N-type doped semiconductor epitaxial layer in the side floating island region.
[0073] k is the Boltzmann constant, T is the ambient temperature, and n idenoted as the intrinsic carrier concentration of SiC, and denoted as a constant.
[0074] N A The P-type doping concentration in the side floating island region; N D The concentration of the N-type doped semiconductor epitaxial layer.
[0075] The optimal value of wpi is selected based on the simulation results of the device's dynamic resistance degradation. The difference in P-type doping concentration between the side floating island region and the central floating island region in each P-type doped semiconductor floating island is set as ΔNmpi. The optimal value of ΔNmpi is then selected based on the co-simulation results of the device's dynamic resistance degradation and device quality factors.
[0076] like Figure 3 As shown, the dynamic on-resistance degradation of the conventional floating island structure is consistently higher than that of the device provided in this embodiment, indicating that the partitioned doping design has a significant advantage in suppressing dynamic degradation. Under the same adjacent floating island spacing wpi, the degradation degree of the conventional structure is around 14%, while the optimized doped structure can reduce it to as low as about 8%, a decrease of nearly 40%. Under the same wpi condition, the higher the ΔNmpi, the higher the dynamic on-resistance degradation. This may be because while a high ΔNmpi can increase the concentration difference and built-in potential between the P-type floating island and the N-type epitaxial layer, it may also lead to uneven carrier distribution within the floating island, thus exacerbating dynamic resistance degradation. Under the same ΔNmpi condition, when wpi is in the range of 0.3~0.5 μm, the overall degradation degree is lower. A slight increase occurs beyond 0.5 μm because the larger spacing results in incomplete coverage of the depletion region between the floating islands, weakening the potential clamping effect. The lowest dynamic on-resistance degradation is observed at 0.3 μm and 0.4 μm.
[0077] At the same time, such as Figure 4 and Figure 5 As shown, the dynamic on-resistance decreases with increasing ΔNmpi, because high ΔNmpi promotes the depletion of the drift region and reduces conduction losses. Simultaneously, the breakdown voltage also increases, demonstrating the optimizing effect of partitioned doping on the device's on-resistance and breakdown voltage. Increasing wpi causes a slight increase in dynamic on-resistance and a small fluctuation in breakdown voltage, achieving a good balance between on-resistance and breakdown voltage around 0.3 μm.
[0078] like Figure 6 As shown, conventional floating island structures, lacking the control of partitioned doping, exhibit significantly lower FOM values than the optimized structure under the same spacing conditions. This demonstrates that partitioned doping of floating islands effectively improves the electric field distribution in the drift region, reduces conduction losses, and enhances breakdown voltage, thereby significantly improving device performance.
[0079] Based on the co-simulation results of the device's dynamic resistance degradation degree and device quality factors, ΔN mpi The optimal value is 1.9 × 10 17 cm -3 At this point, the P-type doping concentration in each central floating island region is 4 × 10⁻⁶. 16 cm -3 The P-type doping concentration of each side floating island region is 2.3 × 10⁻⁶. 17 cm -3 .
[0080] like Figure 7 As shown, in the same N d Under the same conditions, the degree of degradation of dynamic on-resistance does not change significantly; however, under the same ΔNmpi conditions, N d An increase in N will slightly increase the degree of degradation, possibly because increasing N... d The reduced depletable range of the drift region results in more residual carriers after switching and slower recovery, causing the on-resistance to increase under dynamic conditions.
[0081] like Figure 8 and Figure 9 As shown, under the same ΔNmpi condition, as N... d As the N value increases, the dynamic on-resistance of the device decreases significantly, while the breakdown voltage shows a trend of first increasing and then decreasing; this is mainly due to the higher N value. d Increasing the carrier concentration in the drift region reduces the resistance in the on-state; however, when N d When the voltage is too high, the depletion capacity of the drift region weakens, the local electric field concentrates, and the breakdown voltage of the device decreases accordingly, thus forming the peak characteristic of the breakdown voltage. For different ΔNmpi, it can be seen that the higher the ΔNmpi, the higher the corresponding maximum BV value. This is because a higher ΔNmpi enhances the built-in potential between the P-type floating island and the N-type epitaxial layer, making it easier for the drift region between adjacent floating islands to be completely depleted under static conditions. The electric field distribution is more uniform, and the potential clamping effect is stronger, thus effectively improving the breakdown voltage of the device.
[0082] like Figure 10 As shown, the FOM value of the conventional floating island structure is lower than that of the structure optimized by introducing partitioned doping, indicating that the partitioned doping floating island design can significantly improve the overall performance of the device. After introducing partitioned doping, the concentration gradient formed by the floating island and the epitaxial layer enhances the electric field modulation capability, thereby simultaneously optimizing the breakdown voltage and conduction performance, and improving the overall FOM by about 30–50%.
[0083] A method for fabricating a dual-source lateral silicon carbide power device with partitioned doped floating islands includes the following steps.
[0084] Step 1: Prepare a silicon carbide N-type doped semiconductor epitaxial layer: such as Figure 11 As shown, a buried oxide layer is generated on a semiconductor silicon substrate by oxidation, and then an N-type doped silicon carbide semiconductor epitaxial layer is grown epitaxially.
[0085] Step 2: Fabrication of a P-type doped semiconductor well: such as Figure 12 As shown, a specific ion implantation mask layer is formed on the upper surface of the device formed in step 1, and then ion implantation is performed. After removing the mask layer and annealing at high temperature, a P-type doped semiconductor well is formed.
[0086] Step 3: Fabricate the semiconductor N+ source region and semiconductor drain region: (e.g.) Figure 13 As shown, for the device formed in step 2, specific ion implantation mask layers are formed on the left and right sides of its upper surface. High-dose ion implantation is performed, and after removing the mask layers and performing high-temperature annealing, semiconductor N+ source region and semiconductor drain region are formed.
[0087] Step 4: Prepare the semiconductor bulk contact P+ region: such as Figure 14 As shown, for the device formed in step 3, a specific ion implantation mask layer is formed on its upper surface, high-dose ion implantation is performed, the mask layer is removed and high-temperature annealing is performed to form the semiconductor body contact P+ region.
[0088] Step 5: Prepare the central region of three P-type doped semiconductor floating islands: as shown in the figure. Figure 15 As shown, for the device prepared in step 4, a specific ion implantation mask layer is formed on its upper surface. After ion implantation, the mask layer is removed and high-temperature annealing is performed to form a lightly doped region of three P-type doped semiconductor floating islands.
[0089] Step 6: Prepare the side island regions of the three P-type doped semiconductor floating islands: as shown in the figure. Figure 16 As shown, for the device prepared in step 5, a specific ion implantation mask layer is formed on its upper surface, high-dose ion implantation is performed, the mask layer is removed and high-temperature annealing is performed to form the side floating island regions of three P-type doped semiconductor floating islands.
[0090] Step 7: Fabricate the device gate oxide layer: such as Figure 17 As shown, for the device formed in step 6, a thin layer of silicon dioxide is deposited on its surface.
[0091] Step 8: Prepare the gate metal: such as Figure 18 As shown, for the device formed in step 7, after surface planarization, a layer of metal is deposited, and the excess part is etched to obtain the gate metal.
[0092] Step 9: Prepare the field oxide layer on the device surface: such as Figure 19 As shown, for the device formed in step 8, after removing the excess thin layer of silicon dioxide from the surface, a layer of silicon dioxide is deposited on the entire surface and planarized.
[0093] Step 10, Prepare electrode contact holes: such as Figure 20 As shown, for the device formed in step 9, two source regions and a drain region are etched out using a mask and the mask layer is removed.
[0094] Step 11, Deposit source and drain metals: such as Figure 21 As shown, for the device formed in step 10, metal is deposited into the electrode contact holes, and then the excess metal portions that are interconnected are etched away to form source metal and drain metal.
[0095] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.
Claims
1. A dual-source lateral silicon carbide power device with partitioned doped floating islands, characterized in that: It includes a silicon carbide N-type doped semiconductor epitaxial layer, a P-type doped semiconductor well, two source metals, and several P-type doped semiconductor floating islands; P-type doped semiconductor wells are arranged on one side of the top of the silicon carbide N-type doped semiconductor epitaxial layer; Several P-type doped semiconductor floating islands are arranged equidistantly on the top of the silicon carbide N-type doped semiconductor epitaxial layer on one side of the P-type doped semiconductor well. Each P-type doped semiconductor island includes a central island region and side island regions arranged on both sides of the central island region; wherein the P-type doping concentration of each side island region is greater than the doping concentration of the central island region. The P-type doped semiconductor island adjacent to the P-type doped semiconductor well is called the first floating island. One source metal is placed on the top of the P-type doped semiconductor well, and the bottom surface of the other source metal is placed close to the upper surface of the first floating island.
2. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 1, characterized in that: The lateral spacing between the first floating island and the P-type doped semiconductor well is not less than A; where A is the minimum distance required for the device current to be turned on.
3. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 1, characterized in that: The number of floating islands in a P-type doped semiconductor is greater than or equal to 2.
4. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 1, characterized in that: The two side island regions in each P-type doped semiconductor island are of equal length and have the same P-type doping concentration.
5. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 4, characterized in that: The central island region and the two side island regions of each P-type doped semiconductor island are of equal length.
6. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 4, characterized in that: Let wpi be the distance between two adjacent P-type doped semiconductor floating islands, then wpi ≤ W D And wpi < 1µm; where W D The width of the depletion region formed by the side floating island region and the silicon carbide N-type doped semiconductor epitaxial layer.
7. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 6, characterized in that: W D The calculation formula is: ； in: ； In the formula, ε s V is the dielectric constant of SiC; bi q represents the built-in potential of the side floating island region; q is the elementary charge. a is the slope of the net doping concentration as a function of spatial position; where net doping is the absolute value of the difference between the P-type doping concentration and the concentration of the N-type doped semiconductor epitaxial layer in the side floating island region. k is the Boltzmann constant, T is the ambient temperature, and n i is the intrinsic carrier concentration of SiC, which is a constant; N A The P-type doping concentration in the side floating island region; N D The concentration of the N-type doped semiconductor epitaxial layer.
8. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 6, characterized in that: The optimal value of wpi is selected based on the simulation results of the device's dynamic resistance degradation.
9. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 8, characterized in that: The difference in P-type doping concentration between the side island region and the central island region in each P-type doped semiconductor island is denoted as ΔN. mpi Then ΔN mpi The optimal value is selected based on the co-simulation results of the device's dynamic resistance degradation degree and device quality factors.
10. The dual-source lateral silicon carbide power device with partitioned doped floating islands according to claim 9, characterized in that: The number of floating islands in a P-type doped semiconductor is four, the optimal value for wpi is 0.3µm, and ΔN mpi The optimal value is 1.9 × 10 17 cm -3 .