Power semiconductor package comprising PCB and method for manufacturing the same

Abstract

A power semiconductor package includes: a metal plate including a first side and an opposite second side; a side wall extending along an edge of the first side of the metal plate and surrounding an inner portion of the first side of the metal plate; at least one die carrier disposed over an inner portion of the first side of the metal plate; a power semiconductor die disposed over the at least one die carrier and electrically coupled to the at least one die carrier, where the at least one die carrier electrically isolates the power semiconductor die from the metal plate; and a printed circuit board arranged over the sidewalls and covering an inner portion of the first side of the metal plate such that the at least one die carrier and the power semiconductor die are arranged within an inner volume of the power semiconductor package enclosed by the inner portion of the first side of the metal plate, the sidewalls and the printed circuit board.

Description

Technical Field

[0001] This disclosure relates to power semiconductor packaging, particularly power semiconductor packaging including a PCB, and methods for manufacturing power semiconductor packaging. Background Technology

[0002] Semiconductor packages (especially power semiconductor packages) may include one or more semiconductor dies disposed on a die carrier and an encapsulation (e.g., a molded body) that encapsulates and thereby protects the semiconductor dies from environmental influences. Such power semiconductor packages may also include electrical interconnects for electrical signals and power distribution, such as bonding wires, contact clips, etc. These electrical interconnects are disposed on the semiconductor die in one or more separate processes prior to the fabrication of the encapsulation, which may add additional cost and / or manufacturing time. Furthermore, adapting such power semiconductor packages to different requirements can be complex. Moreover, such power semiconductor packages may exhibit relatively large stray inductance. Improved power semiconductor packages and improved methods for manufacturing power semiconductor packages can help address these and other issues. Summary of the Invention

[0003] Various aspects relate to a power semiconductor package, comprising: a metal plate including a first side and an opposing second side; a sidewall extending along an edge of the first side of the metal plate and surrounding an inner portion of the first side of the metal plate; at least one die carrier disposed over the inner portion of the first side of the metal plate; a power semiconductor die disposed over and electrically coupled to the at least one die carrier, wherein the at least one die carrier electrically isolates the power semiconductor die from the metal plate; and a printed circuit board disposed over the sidewall and covering the inner portion of the first side of the metal plate, such that the at least one die carrier and the power semiconductor die are disposed within an inner volume of the power semiconductor package enclosed by the inner portion of the first side of the metal plate, the sidewall, and the printed circuit board.

[0004] Various aspects relate to a method for manufacturing a power semiconductor package, the method comprising: providing a metal plate including a first side and an opposing second side; arranging sidewalls along an edge of the first side of the metal plate such that the sidewalls surround an interior portion of the first side of the metal plate; arranging at least one die carrier over the interior portion of the first side of the metal plate; arranging a power semiconductor die over the at least one die carrier and electrically coupling the power semiconductor die to the at least one die carrier, wherein the at least one die carrier electrically isolates the power semiconductor die from the metal plate; and mechanically coupling a printed circuit board to the sidewalls such that the at least one die carrier and the power semiconductor die are arranged within an interior volume of the power semiconductor package enclosed by the interior portion of the first side of the metal plate, the sidewalls, and the printed circuit board.

[0005] Those skilled in the art will recognize the additional features and advantages after reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0006] This disclosure is shown by way of example and not limitation in the various figures of the accompanying drawings, wherein the same reference numerals denote similar or identical elements. The elements in the figures are not necessarily drawn to scale relative to each other. Features of the various examples shown can be combined unless they are mutually exclusive.

[0007] Figure 1 A cross-sectional view of an exemplary power semiconductor package is shown, wherein the PCB is part of the encapsulation of the hermetically sealed semiconductor die.

[0008] Figure 2 A cross-sectional view of another exemplary power semiconductor package is shown, which includes an internal volume of a semiconductor die that is at least partially filled with gel.

[0009] Figure 3 A cross-sectional view of another exemplary power semiconductor package is shown, in which an electrical connector connects the semiconductor die to a PCB.

[0010] Figure 4 It is shown that it is configured in a power semiconductor package (such as Figures 1 to 3 A perspective view of an exemplary metal plate used in a power semiconductor package shown.

[0011] Figure 5 A perspective view of another exemplary metal plate is shown, in which multiple single-chip die carriers are arranged on the metal plate.

[0012] Figure 6A and Figure 6B A cross-sectional view of a power semiconductor die arranged on an exemplary single-chip die carrier is shown. Figure 6A ) and floor plan ( Figure 6B ).

[0013] Figure 7 It shows Figure 5 A perspective view of a metal plate, in which sidewalls have been arranged on the metal plate, with the sidewalls surrounding the semiconductor die and die carrier on four sides.

[0014] Figure 8 A perspective view of another exemplary power semiconductor package is shown, in which the PCB has been connected... Figure 7 The sidewalls and metal plates shown.

[0015] Figure 9 This is a flowchart of an exemplary method for manufacturing a power semiconductor package. Detailed Implementation

[0016] In the following detailed description, known structures and elements are illustrated schematically to facilitate the description of one or more aspects of this disclosure. For this purpose, directional terms such as “top,” “bottom,” “left,” “right,” “upper,” and “lower” are used with reference to the orientation of the described figures. Because the components of this disclosure can be positioned in a variety of different orientations, directional terms are used only for illustrative purposes. It should be understood that other examples can be utilized, and structural or logical changes can be made.

[0017] Additionally, while specific features or aspects may be disclosed only with respect to one embodiment of several implementations, such features or aspects may be combined with one or more other features or aspects of other embodiments as may be desired and advantageous for any given or particular application, unless otherwise specifically stated or technically limited. Furthermore, to the extent that the terms “comprising,” “having,” “having,” or other variations thereof are used in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term “including.” The terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical or electrical contact, or whether they are not in direct contact with each other; an intermediate element or layer may be provided between elements that are “joined,” “attached,” or “connected.” However, elements that are “joined,” “attached,” or “connected” may also be in direct contact with each other. Moreover, the term “exemplary” is meant only as an example, not as best or optimal.

[0018] The examples of power semiconductor packages described below can use various types of semiconductor dies or circuits incorporated in a semiconductor die, including AC / DC or DC / DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (junction gate field-effect transistors), power bipolar transistors, power integrated circuits, etc.

[0019] One or more power semiconductor dies may be made of specific semiconductor materials, such as Si, SiC, SiGe, GaAs, GaN, or any other semiconductor material, and may further contain one or more non-semiconductor inorganic and organic materials, such as insulators, plastics, or metals. One or more semiconductor dies may have contact pads (or terminals) that may be arranged all only on one main side of one or more semiconductor dies or on both main sides of one or more semiconductor dies.

[0020] In several examples, layers or stacks of layers are applied to each other or materials are applied to or deposited onto the layers. It should be understood that any terms such as “applied” or “deposited” are intended to cover, in a literal sense, all kinds and techniques of applying layers to each other. In particular, they are intended to cover techniques that apply the layers as a whole at once (e.g., lamination) and techniques that deposit the layers in a continuous manner (e.g., sputtering, plating, molding, CVD, etc.).

[0021] Effective power semiconductor packaging and effective methods for manufacturing power semiconductor packages can, for example, reduce material consumption, ohmic losses, chemical waste, etc., and thus achieve energy and / or resource savings. The improved power semiconductor packaging and improved methods for manufacturing power semiconductor packages, as detailed in this specification, can therefore at least indirectly contribute to green technology solutions, i.e., climate-friendly solutions that reduce energy and / or resource usage.

[0022] Figure 1 A cross-sectional view of a power semiconductor package 100 is shown, comprising a metal plate 110, sidewalls 120, a die carrier 130, a power semiconductor die 140, and a printed circuit board (PCB) 150. The power semiconductor package 100 may be configured, for example, to operate at high voltages (e.g., 100V or higher, or 500V or higher, or 1kV or higher) and / or high currents (e.g., 1A or higher, or 10A or higher, or 50A or higher).

[0023] The power semiconductor package 100 may include any suitable circuitry, or the power semiconductor package 100 may be configured as part of any suitable circuitry. For example, the power semiconductor package 100 may include a half-bridge circuit, a full-bridge circuit, a converter circuit, an inverter circuit, etc. According to the example, the metal plate 110 may provide sufficient space to accommodate two applications in the power semiconductor package 100, such as a traction inverter circuit and an on-board charger circuit.

[0024] The power semiconductor package 100 can be configured for any suitable type of application, such as automotive, industrial, or home applications. The power semiconductor package 100 can be configured to connect to driver circuitry configured to drive one or more power semiconductor dies 140 of the power semiconductor package 100. This driver circuitry can be arranged, for example, on a driver board, which can be arranged, for example, above a PCB 150. Alternatively, the driver circuitry can be arranged on the PCB 150 itself. This can, for example, reduce stray inductance in the power semiconductor package 100. Furthermore, gate drivers and / or gate resistors can be placed close to one or more power semiconductor dies 140, which can improve switching behavior.

[0025] The metal plate 110 includes a first side 111 and an opposing second side 112. The first side 111 faces the power semiconductor die 140 and the PCB 150. The metal plate 110 may be, for example, a substrate. According to another example, the metal plate 110 is a heat sink and may include, for example, a cooling structure on the second side 112. Such a cooling structure may include, for example, a plurality of pin fins or a plurality of strips. In other words, the metal plate 110 may be configured to dissipate heat generated by the power semiconductor die(s) 140(s) during operation. According to another example, the cooling structure may not be present.

[0026] The metal plate 110 may comprise or be composed of any suitable metal or metal alloy. By way of example, the metal plate 110 comprises or is composed of Al or Cu. The metal plate 110 may have any suitable shape and any suitable size. For example, the metal plate 110 may have a substantially rectangular or square shape as viewed from above the first side 111. The metal plate 110 may, for example, have an edge length of 2 cm or more, or 5 cm or more, or 10 cm or more, or 15 cm or more as viewed from above the first side 111. The thickness of the metal plate, measured between the first side 111 and the second side 112, may, for example, range from about 0.5 mm to about 5 mm. The lower limit of this range may also be about 1 mm or about 1.5 mm, and the upper limit may also be about 3 mm or about 2 mm.

[0027] The sidewall 120 extends along the edge of the first side 111 of the metal plate 110 and surrounds the inner portion of the first side 111 of the metal plate 110. The sidewall 120 may completely surround the inner portion, especially on all four sides.

[0028] According to the example, sidewall 120 and metal plate 110 are integral parts. In other words, sidewall 120 and metal plate 110 can be manufactured from a single workpiece (e.g., metal plate). According to another example, sidewall 120 and metal plate 110 are two distinct parts, particularly those comprising or composed of different materials or material compositions.

[0029] The sidewall 120 may include or be composed of any suitable material. For example, the sidewall 120 may include a metal (such as Al or Cu) or a metal alloy or a polymer or plastic (especially thermoplastic), or be composed of a metal (such as Al or Cu) or a metal alloy or a polymer or plastic (especially thermoplastic). Thermoplastic is a plastic material that becomes malleable when heated and solidifies when cooled again.

[0030] The sidewall 120 can have any suitable dimensions. For example, the sidewall 120 can have a height measured perpendicular to the first side 111 of the metal plate, ranging from about 0.5 mm to about 3 mm. The lower limit of this range can also be about 0.8 mm, or about 1 mm, or about 1.2 mm, and the upper limit can also be about 2.5 mm, or about 2 mm, or about 1.5 mm. The sidewall 120 can, for example, have a width measured parallel to the first side 111, within a similar range to the height. However, the height and width of the sidewall 120 need not be the same.

[0031] The sidewall 120 can have any suitable cross-section, such as a substantially rectangular or square cross-section (compare). Figure 1 The sidewall 120 may include, for example, a top side 121 and a lateral side 122. The top side 121 may be configured, for example, to be in direct contact with the PCB 150. According to another example, an adhesive layer (e.g., a solder layer) may be disposed on the top side 121 and may couple the PCB 150 to the sidewall 120.

[0032] At least one die carrier 130 is disposed on the inner portion of the first side 111 of the metal plate 110. According to one example, the power semiconductor package 100 includes a single die carrier 130. According to another example, the power semiconductor package 100 includes a plurality of die carriers 130, such as two, four, six, eight, etc. In the latter case, the die carriers 130 may all be of the same type and / or have the same size and / or the same shape, or the die carriers 130 may be of different types and / or have different sizes and / or different shapes.

[0033] The die carrier 130 may be, for example, a power electronics substrate. The die carrier 130 may include, for example, a conductive layer and an electrically insulating layer disposed beneath the conductive layer and configured to insulate the conductive layer from the metal plate 110. The die carrier 130 may be, for example, a direct copper bond (DCB), a direct aluminum bond (DAB), an active metal bond (AMB), an insulating metal substrate (IMS), a lead frame, or a PCB. The die carrier 130 may be, for example, soldered, sintered, or glued to a first side 111 of the metal plate 110.

[0034] A power semiconductor die 140 is disposed on and electrically coupled to at least one die carrier 130. According to an example, a single power semiconductor die 140 is disposed on the die carrier 130, or a single power semiconductor die 140 is disposed on each of a plurality of die carriers 130. According to another example, at least two power semiconductor dies 140 may be disposed on a common die carrier 130. At least one die carrier 130 is configured to electrically isolate the power semiconductor die(s) 140(s) from the metal plate 110. The power semiconductor die 140 may, for example, be soldered, sintered, or glued to the die carrier 130 using conductive adhesive.

[0035] PCB 150 is disposed above sidewall 120 and covers the inner portion of the first side 111 of metal plate 110. This means that at least one die carrier 130 and power semiconductor die 140 are disposed within the internal volume 160 of power semiconductor package 100. The internal volume 160 is enclosed on all sides by the inner portion of the first side 111 of metal plate 110, sidewall 120, and PCB 150. This specifically means that power semiconductor die 140 is sealed within internal volume 160, wherein PCB 150 acts as a cap that seals the top of the internal volume by coupling to sidewall 120. In this way, metal plate 110, sidewall 120, and PCB 150 can be used as a seal equivalent to a molded body to protect power semiconductor die 140 from environmental influences.

[0036] Figure 2 A cross-sectional view of another power semiconductor package 200, which may be similar to or the same as power semiconductor package 100, is shown, except for the differences described below.

[0037] The power semiconductor package 200 includes all the components described with respect to the power semiconductor package 100, and the power semiconductor package 200 further includes a gel (or a molding compound without filler particles) 210 disposed within an internal volume 160 of the power semiconductor package 200. Figure 2In this example, gel 210 is shown to completely fill the internal volume 160. However, according to another example, gel 210 only partially fills the internal volume 160. For example, only the lower portion of the internal volume 160 is filled with gel 210, and the upper portion of the internal volume 160 is not filled with gel 210. Additionally or alternatively, the internal volume 160 may include one or more voids not filled by gel 210.

[0038] In any case, gel 210 can be configured to electrically isolate the terminals of power semiconductor dies 130 (e.g., gate terminal, drain terminal, and source terminal) from each other and / or to electrically isolate multiple power semiconductor dies 130 from each other. For this purpose, gel 210 may comprise or be composed of any suitable dielectric material.

[0039] According to an exemplary method for manufacturing semiconductor package 200, after PCB 150 has been attached to sidewall 120, gel 210 is filled into internal volume 160. For this reason, PCB 150 may include one or more holes 220 configured to fill internal volume 160 with gel 210. For example, one or more first holes 220 may be configured as inlets for gel 210, and one or more second holes 220 may be configured as outlets for gas removal from internal volume 160. Figure 2 As shown, gel 210 can at least partially or even completely fill one or more pores 220.

[0040] Figure 3 A cross-sectional view of another power semiconductor package 300, which may be similar to or the same as power semiconductor package 100 or 200, is shown, except for the differences described below.

[0041] Specifically, the power semiconductor package 300 includes an electrical connector 310 that electrically connects the power semiconductor die 140 to a PCB 150. The electrical connector 310 may connect, in particular, the power terminals (e.g., source terminal, drain terminal, emitter terminal, or collector terminal) of the power semiconductor die 140 to the PCB 150. The power semiconductor package may also include a gel 210 (…). Figure 3 (Not shown in the image).

[0042] like Figure 3 As shown, the electrical connector 310 may be disposed on the upper side of one or more die carriers 130 and / or the upper side of the power semiconductor die 140. The electrical connector 310 may, for example, be soldered to one or more die carriers 130 and / or the power semiconductor die 140.

[0043] Electrical connector 310 may extend partially or completely through through-hole 320 in PCB 150. Through-hole 320 may be different from one or more holes 220 (compare). Figure 2 The PCB 150 can be specifically configured to receive an electrical connector 310. Furthermore, the electrical connector 310 can be electrically connected, for example, via a through-hole 320 to one or more conductive traces 330 on the PCB 150. The through-hole 320 can have any suitable diameter, for example, about 1 mm, or about 1.5 mm, or about 2 mm.

[0044] PCB 150 can provide a redistributed structure for semiconductor package 300. For example, individual power semiconductor dies 140 can be electrically connected to each other via electrical connector 310 and conductive traces 330 of PCB 150. In other words, there is no need for lateral connectors similar to contact clips between the individual power semiconductor dies 140 in the internal volume 160, because PCB 150 can fulfill this function. PCB 150 can be a redistributed structure, in particular, for both power and signal connections.

[0045] Electrical connector 310 may comprise or be composed of any suitable metal or metal alloy. As an example, electrical connector 310 is composed of solder material. Manufacturing electrical connector 310 may include, for example, the process of depositing solder paste or solder preforms (e.g., preform wires) on power semiconductor die 140 and / or (one or more) die carriers 130 via through-hole 320, and then soldering the solder paste or solder preforms.

[0046] According to the example, PCB 150 includes an external power supply terminal for power semiconductor package 300. Figure 3 (Not shown in the image). External power supply terminals can be connected to the power semiconductor die 140 via conductive trace 330 and electrical connector 310. External power supply terminals may include, for example, terminals for positive power supply voltage, terminals for negative power supply voltage, and phase current terminals.

[0047] Figure 4 A perspective view of a metal plate 110 according to a specific example is shown. Figure 4 In the example shown, the sidewall 120 and the metal plate 110 are integral components. Manufacturing the sidewall 120 may include, for example, a stamping process. Alternatively, a metal frame structure may be arranged on and coupled to the first side 111 of the metal plate 110 to provide the sidewall 120, wherein the coupling process includes, for example, welding.

[0048] according to Figure 4In the example shown, the second side 112 of the metal plate 110 includes a cooling structure 114. The cooling structure 114 may in particular include a plurality of pin-shaped fins or a plurality of strips. The second side 112 (and therefore also the cooling structure 114) may be configured to be in direct contact with a cooling fluid (such as water or air).

[0049] The metal plate 110 may also include a spacer 116 disposed on the first side 111 and configured to set the distance between the first side 111 and the PCB 150. For this purpose, the spacer 116 may extend (slightly) vertically beyond the height of the sidewall 120, such that a solder layer or a layer including adhesive can be disposed between the PCB 150 and the upper side 121 of the sidewall 120. The spacer 116 can be used because the desired height of the spacer can be set with the desired accuracy (e.g., ±15 μm) more easily than setting the desired height with the desired accuracy along the entire length of the sidewall 120.

[0050] The metal plate 110 may also include a locating pin 118 configured to insert into a corresponding locating hole on the PCB 150 to ensure that the PCB 150 is positioned correctly on the metal plate 110. The metal plate 110 and the spacer 116 and / or the locating pin 118 may be, for example, an integral part.

[0051] If the sidewall 120 comprises or is composed of metal or metal alloy, the PCB 150 may be soldered to the sidewall 120, for example. For this purpose, solder preforms may be deposited on the upper side 121 of the sidewall 120.

[0052] Figure 5 A perspective view of a metal plate 110 according to another specific example is shown. Figure 5 Example metal plate 110 can be used with according to Figure 4 The metal plate 110 shown in the example is similar or identical, except for the differences described below.

[0053] Specifically, in Figure 5 In the example, the metal plate 110 and the sidewall 120 are not integral parts. This could mean, for example, that the sidewall 120 comprises or is composed of a material different from the metal plate 110 (e.g., a thermoplastic material), and that the sidewall 120 is configured to be attached to the metal plate using, for example, a hot-melt process and / or adhesive.

[0054] like Figure 5 As shown, the edge of the first side 111 of the metal plate 110 may include a plurality of connection holes 119, which can be configured to receive pins of the sidewall 120. In this way, the mechanical coupling between the metal plate 110 and the sidewall 120 can be improved.

[0055] The edge of a first side 111 of the metal plate 110 surrounds an inner portion of the first side 111, wherein the inner portion is configured to receive at least one die carrier 130. Figure 5 As shown in the example, multiple core carriers 130 can be arranged on the inner portion of the first side 111.

[0056] Figure 5 The example specifically illustrates each of the power semiconductor dies 140 arranged on a single die carrier 130. The die carrier 130 can be arranged on a first side 111 of a metal plate 110, for example, using a pick-and-place process. The die carrier 130 can be arranged on the first side 111 in any suitable pattern (e.g., in a row or multiple rows, or in a matrix). The die carrier 130 can also be arranged, for example, in a so-called “supersymmetric” pattern, which provides optimized switching behavior for the power semiconductor dies 140. The die carriers 130 can be arranged with minimal distance between each other, particularly ensuring a minimum distance for proper electrical insulation between adjacent die carriers within the die carrier 130.

[0057] Figure 6A Cross-sectional views of the die carrier 130 and the power semiconductor die 140 according to a specific example are shown, and Figure 6B A plan view of die carrier 130 and power semiconductor die 140 according to a specific example is shown. Figure 6A and 6B The example die carrier 130 is configured to carry a single power semiconductor die 140. For this reason, the outer periphery of the die carrier 130 may extend only slightly beyond the outer periphery of the power semiconductor die 140 (e.g., no more than 2 mm or no more than 1 mm), or the outer periphery of the die carrier 130 may be substantially flush with the outer periphery of the power semiconductor die 140, as observed from above the power semiconductor die 140. However, the outer periphery of the die carrier 130 may extend significantly beyond the outer periphery of the power semiconductor die 140 at a single edge (e.g., greater than 3 mm) to provide space for the electrical connector 310 on the upper side of the die carrier 130 and laterally next to the power semiconductor die 140 (this is the case in...). Figure 6A and 6B (as shown in the image).

[0058] The die carrier 130 may, for example, include a metal layer or metal element 132 disposed on an electrically insulating layer 134, wherein the insulating layer 134 is configured to insulate the metal layer or metal element 132 from the metal plate 110. The insulating layer 134 may, for example, be a ceramic layer or a polymer layer, particularly a polymer foil. According to an example, the die carrier 130 may include another metal layer disposed beneath the insulating layer 134.

[0059] When the insulating layer 134 is a polymer layer, the insulating layer may have adhesive properties and may be configured to attach the die carrier 130 to the metal plate 110. When the insulating layer 134 is a ceramic layer, an additional adhesive layer (e.g., a layer including solder material, sintering material, or glue) may be used to attach the die carrier 130 to the metal plate 110.

[0060] Since each die carrier 130 can be configured to carry a single power semiconductor die 140, the size of each die carrier 130 can be minimized, as described above. This can reduce the cost of power semiconductor packages 100 to 300, since the die carrier 130 may account for a significant portion of the total cost of the semiconductor package. Furthermore, for the different individual power semiconductor dies 140 of the power semiconductor packages 100 to 300, different types of die carriers 130 and / or die carriers 130 with different shapes and / or different sizes can be used. This can also reduce the cost of the semiconductor package and / or improve the electrical and / or thermal characteristics of the semiconductor package. Additionally, this makes the power semiconductor packages 100 to 300 more easily adaptable to different requirements or applications.

[0061] Figure 7 The metal plate 110 according to an example of FIG6 is shown after the sidewall 120 has been attached to the metal plate 110. The sidewall 120 may, for example, comprise or be composed of a thermoplastic material, and the sidewall 120 may be attached to the metal plate 110 using a heat-fusion connection.

[0062] like Figure 7 As shown, sidewall 120 may include a plurality of pins 124 configured to insert into corresponding holes in PCB 150. This can improve the mechanical engagement between sidewall 120 and PCB 150.

[0063] Figure 8 A perspective view of a power semiconductor package 800, which may be similar to or the same as power semiconductor packages 100 to 300, is shown. Figure 8 Specifically, it is shown that PCB 150 has been arranged on Figure 7 The power semiconductor package 800 is shown above the metal plate 110 and sidewall 120. The PCB 150 can be coupled to the sidewall 120 via thermoforming and / or adhesive bonding. Figure 8 As shown, the pin 124 of the sidewall 120 can extend through a corresponding hole in the PCB 150 to improve the mechanical strength of the thermoplastic connection. In the case where the sidewall 120 and the metal plate are integral components, the PCB 150 can alternatively be soldered to the sidewall 120.

[0064] Note that in Figure 8In this case, PCB 150 is larger than metal plate 110, as can be seen from above PCB 150. The reason for this may be that, for example, PCB 150 includes external power terminals for semiconductor package 800, which are configured to connect power semiconductor package 800 to external devices, and therefore PCB 150 needs to be large enough to accommodate these external power terminals.

[0065] like Figure 8 As shown, the PCB 150 of the power semiconductor package 800 may, for example, include holes 220 for filling the gel 210 into the internal volume 160 of the semiconductor package 800 (compare). Figure 2 PCB 150 may include a through-hole 320 configured to receive an electrical connector 310 (compare). Figure 3 ).

[0066] Figure 9 This is a flowchart of an exemplary method 900 for manufacturing a power semiconductor package. Method 900 can be used, for example, to manufacture power semiconductor packages 100 to 800.

[0067] Method 900 includes: at 901 providing a metal plate including a first side and an opposing second side; at 902 arranging a sidewall along an edge of the first side of the metal plate such that the sidewall surrounds an inner portion of the first side of the metal plate; at 903 arranging at least one die carrier over the inner portion of the first side of the metal plate; at 904 arranging a power semiconductor die on the at least one die carrier and electrically coupling the power semiconductor die to the at least one die carrier, wherein the at least one die carrier electrically isolates the power semiconductor die from the metal plate; and at 905 mechanically coupling a printed circuit board to the sidewall such that the at least one die carrier and the power semiconductor die are arranged within an inner volume of a power semiconductor package enclosed by the inner portion of the first side of the metal plate, the sidewall, and the printed circuit board.

[0068] The process 902 of arranging the sidewall along the edge of the first side of the metal plate may, for example, include providing the metal plate and the sidewall as an integral component. According to another example, the sidewall may, for example, be attached to the metal plate using a hot-melt process.

[0069] Method 900 may include, for example, another process of inserting a solder preform into a through-hole in a printed circuit board and soldering the solder preform to manufacture an electrical connector that electrically connects the power terminals of a power semiconductor die to conductive traces on the printed circuit board.

[0070] Example

[0071] The following sections use specific examples to further explain power semiconductor packaging and methods for manufacturing power semiconductor packages.

[0072] Example 1 is a power semiconductor package comprising: a metal plate including a first side and an opposing second side; a sidewall extending along an edge of the first side of the metal plate and surrounding an inner portion of the first side of the metal plate; at least one die carrier disposed over the inner portion of the first side of the metal plate; a power semiconductor die disposed over and electrically coupled to the at least one die carrier, wherein the at least one die carrier electrically isolates the power semiconductor die from the metal plate; and a printed circuit board disposed over the sidewall and covering the inner portion of the first side of the metal plate such that the at least one die carrier and the power semiconductor die are disposed within an inner volume of the power semiconductor package enclosed by the inner portion of the first side of the metal plate, the sidewall, and the printed circuit board.

[0073] Example 2 is a power semiconductor package according to Example 1, wherein the sidewalls are integral parts of a metal plate.

[0074] Example 3 is a power semiconductor package according to Example 2, wherein a printed circuit board is soldered to the sidewall.

[0075] Example 4 is a power semiconductor package according to Example 1, wherein the sidewalls are plastic frames.

[0076] Example 5 is a power semiconductor package according to Example 4, wherein a printed circuit board is mechanically coupled to a plastic frame via a thermocoupled connection.

[0077] Example 6 is a power semiconductor package according to one of the examples above, wherein the internal volume is at least partially filled with gel.

[0078] Example 7 is a power semiconductor package according to one of the foregoing examples, further comprising: an electrical connector extending through a through-hole in a printed circuit board and electrically connecting a power terminal of a power semiconductor die to a conductive trace on the printed circuit board.

[0079] Example 8 is a power semiconductor package according to Example 7, wherein the electrical connector is composed of solder material.

[0080] Example 9 is a power semiconductor package according to one of the preceding examples, wherein the printed circuit board includes an external power supply terminal for the power semiconductor package.

[0081] Example 10 is a power semiconductor package according to one of the examples above, wherein the power semiconductor package includes a plurality of die carriers and a plurality of semiconductor dies, and wherein each of the power semiconductor dies is disposed on a single die carrier.

[0082] Example 11 is a power semiconductor package according to Example 10, wherein each die carrier includes a metal element or metal layer and an electrically insulating layer disposed between the metal element or metal layer and a metal plate.

[0083] Example 12 is a power semiconductor package according to Example 11, wherein the insulating layer is a ceramic layer.

[0084] Example 13 is a power semiconductor package according to Example 11, wherein the insulating layer is a polymer layer.

[0085] Example 14 is a power semiconductor package according to one of Examples 10 to 13, wherein a plurality of die carriers include at least two different types of die carriers, and wherein the different types of die carriers have different sizes and / or different shapes, and / or wherein different types of power semiconductor dies are arranged on different types of die carriers.

[0086] Example 15 is a power semiconductor package according to one of the foregoing examples, wherein the second side of the metal plate includes a cooling structure, and in particular, the second side of the metal plate includes a plurality of pin fins or a plurality of strips.

[0087] Example 16 is a power semiconductor package according to one of the examples above, wherein each power semiconductor die includes a gate terminal and a source terminal disposed on a first side of the power semiconductor die, and wherein the first side of each power semiconductor die faces the printed circuit board.

[0088] Example 17 is a method for manufacturing a power semiconductor package, the method comprising: providing a metal plate including a first side and an opposing second side; arranging sidewalls along an edge of the first side of the metal plate such that the sidewalls surround an inner portion of the first side of the metal plate; arranging at least one die carrier over the inner portion of the first side of the metal plate; arranging a power semiconductor die over the at least one die carrier and electrically coupling the power semiconductor die to the at least one die carrier, wherein the at least one die carrier electrically isolates the power semiconductor die from the metal plate; and mechanically coupling a printed circuit board to the sidewalls such that the at least one die carrier and the power semiconductor die are arranged within an inner volume of the power semiconductor package enclosed by the inner portion of the first side of the metal plate, the sidewalls, and the printed circuit board.

[0089] Example 18 is the method according to Example 17, further comprising: at least partially filling the internal volume with gel, wherein the gel fills the internal volume through one or more holes in the printed circuit board.

[0090] Example 19 is the method according to Example 17 or 18, further comprising: inserting a solder preform into a through-hole in a printed circuit board; and soldering the solder preform to manufacture an electrical connector that electrically connects the power terminals of a power semiconductor die to conductive traces on the printed circuit board.

[0091] Example 20 is a method according to one of Examples 17 to 19, wherein mechanically coupling the printed circuit board to the sidewall includes soldering or thermally fusion of the printed circuit board to the sidewall.

[0092] Example 21 is an apparatus including a unit for performing the method according to any one of Examples 17 to 20.

[0093] While specific examples have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent embodiments may be substituted for the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

[0094] It should be noted that the methods and apparatuses, including their preferred embodiments as outlined in this document, can be used alone or in combination with other methods and apparatuses disclosed in this document. Furthermore, features outlined in the context of the apparatus also apply to the corresponding methods, and vice versa. Moreover, all aspects of the methods and apparatuses outlined in this document can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner.

[0095] It should be noted that the specification and accompanying drawings only illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements, although not explicitly described or shown herein, which embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined in this document are primarily and explicitly intended for illustrative purposes only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein providing the principles, aspects, and embodiments of the invention and their specific examples are intended to cover their equivalents.

Claims

1. A power semiconductor package (100, 200, 300), comprising: A metal plate (110), the metal plate (110) including a first side (111) and an opposing second side (112), A sidewall (120) extends along the edge of the first side (111) of the metal plate (110) and surrounds the inner portion of the first side (111) of the metal plate (110). At least one die carrier (130) is disposed on the inner portion of the first side (111) of the metal plate (110). A power semiconductor die (140) is disposed on and electrically coupled to the at least one die carrier (130), wherein the at least one die carrier (130) electrically isolates the power semiconductor die (140) from the metal plate (110), and A printed circuit board (150) is disposed above the sidewall (120) and covers the inner portion of the first side (111) of the metal plate (110), such that the at least one die carrier (130) and the power semiconductor die (140) are disposed within the inner volume (160) of the power semiconductor package (100, 200, 300) enclosed by the inner portion of the first side (111) of the metal plate (110), the sidewall (120) and the printed circuit board (150).

2. The power semiconductor package (100, 200, 300) according to claim 1, wherein, The sidewall (120) is an integral part of the metal plate (110).

3. The power semiconductor package (100, 200, 300) according to claim 2, wherein, The printed circuit board (150) is soldered to the sidewall (120).

4. The power semiconductor package (100, 200, 300) according to claim 1, wherein, The sidewall (120) is a plastic frame.

5. The power semiconductor package (100, 200, 300) according to claim 4, wherein, The printed circuit board (150) is mechanically coupled to the plastic frame via a thermoweld connection.

6. The power semiconductor package (100, 200, 300) according to any one of the preceding claims, wherein, The internal volume (160) is at least partially filled with gel.

7. The power semiconductor package (100, 200, 300) according to any one of the preceding claims further includes: An electrical connector (310) extends through a through-hole (320) in the printed circuit board (150) and electrically connects the power terminal of the power semiconductor die (140) to the conductive trace (330) of the printed circuit board (150).

8. The power semiconductor package (100, 200, 300) according to claim 7, wherein, The electrical connector (310) is made of solder material.

9. The power semiconductor package (100, 200, 300) according to any one of the preceding claims, wherein, The printed circuit board (150) includes external power terminals of the power semiconductor packages (100, 200, 300).

10. The power semiconductor package (100, 200, 300) according to any one of the preceding claims, wherein, The power semiconductor package (100, 200, 300) includes multiple die carriers (130) and multiple semiconductor dies (140), and Each of the power semiconductor dies (140) is arranged on a single die carrier (130).

11. The power semiconductor package (100, 200, 300) according to claim 10, wherein, Each core carrier (130) includes a metal element or metal layer (132) and an electrical insulating layer (134) disposed between the metal element or metal layer (132) and the metal plate (110).

12. The power semiconductor package (100, 200, 300) according to claim 11, wherein, The electrical insulating layer (134) is a ceramic layer.

13. The power semiconductor package (100, 200, 300) according to claim 11, wherein, The electrical insulating layer (134) is a polymer layer.

14. The power semiconductor package (100, 200, 300) according to any one of claims 10-13, wherein, The plurality of die carriers (130) include at least two different types of die carriers, wherein the different types of die carriers have different sizes and / or different shapes, and / or Different types of power semiconductor dies (140) are arranged on the different types of die carriers (130).

15. The power semiconductor package (100, 200, 300) according to any one of the preceding claims, wherein, The second side (112) of the metal plate (110) includes a cooling structure (114), and in particular, the second side (112) of the metal plate (110) includes a plurality of pin-shaped fins or a plurality of strips.

16. The power semiconductor package (100, 200, 300) according to any one of the preceding claims, wherein, Each power semiconductor die (140) includes a gate terminal and a source terminal disposed on a first side of the power semiconductor die (140), and In this case, the first side of each power semiconductor die (140) faces the printed circuit board (150).

17. A method (900) for manufacturing a power semiconductor package, the method (900) comprising: Provided (901) a metal plate including a first side and an opposite second side, A sidewall (902) is arranged along the edge of the first side of the metal plate, such that the sidewall surrounds the inner portion of the first side of the metal plate. At least one core carrier is arranged (903) on the inner portion of the first side of the metal plate. A power semiconductor die (904) is disposed on the at least one die carrier and electrically coupled to the at least one die carrier, wherein the at least one die carrier electrically isolates the power semiconductor die from the metal plate, and The printed circuit board is mechanically coupled (905) to the sidewall such that the at least one die carrier and the power semiconductor die are arranged within the internal volume of the power semiconductor package enclosed by the first side of the metal plate, the sidewall, and the printed circuit board.

18. The method (900) according to claim 17, further comprising: The internal volume is at least partially filled with gel. The gel is filled into the internal volume through one or more holes in the printed circuit board.

19. The method (900) according to claim 17 or 18, further comprising: The solder preform is inserted into the through-hole in the printed circuit board, and Solder the solder preform to manufacture an electrical connector that electrically connects the power terminals of the power semiconductor die to the conductive traces of the printed circuit board.

20. The method (900) according to any one of claims 17-19, wherein, Mechanically coupling (905) the printed circuit board to the sidewall includes soldering or thermally fusing the printed circuit board to the sidewall.

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