Formation method for back etching of source and drain silicon in transistor

Abstract

A method for forming back etching of source and drain silicon in a transistor comprises the steps that a substrate is provided, the substrate comprises a device area, and a channel protruding part protrudes from the top of the substrate in the device area; in the device region, forming a gate structure crossing the channel lug boss, and covering a part of the top and a part of the side wall of the channel lug boss by the gate structure; forming a side wall material layer on the surface of the channel lug boss and the surface of the gate structure; removing the side wall material layer covering the surface of the channel lug boss and the top of the gate structure; and forming a source-drain doping layer in the channel lug bosses at the two sides of the gate structure. According to the method, the side wall material layer covering the surface of the channel lug boss and the top of the gate structure is removed completely, so that the cleanliness of the surface of the channel lug boss can be improved, the morphology of a source-drain groove formed in the channel lug boss subsequently is further improved, the stress action of the source-drain region from top to bottom in the channel structure is more uniform, and the reliability of the device is improved. Therefore, the performance of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular to a method for forming source / drain silicon recess in a transistor. BACKGROUND

[0002] With the improvement of the element density and integration of semiconductor transistors, in order to adapt to the reduction of the process node, it is necessary to continuously reduce the feature size of the transistor, and at the same time improve the performance of a single transistor to improve the overall performance of the integrated circuit. In terms of improving the performance of a single transistor, stress engineering is a relatively successful technology. In a transistor device, by means of source / drain silicon recess (S / D Si Recess), and then using a selective epitaxial growth process (Selective Epitaxial Growth) to form source / drain electrodes such as SiGe, SiC and SiP, it is an important method to improve the performance of a single device. Because the lattice constant between alloy materials such as SiGe and crystalline Si is different, a specific stress can be applied to the channel by the lattice stress of the source / drain region to improve the carrier mobility in the channel. In the source / drain related process, the source / drain silicon recess morphology has a very important influence on the performance of the transistor. In the existing more advanced integrated circuit technology, such as fin field-effect transistor (FinFET) and gate-all-around (GAA) transistor, due to the complex front-end structure, the source / drain region recess process usually faces great challenges. In the structure of fin-type transistor, the source / drain silicon recess shape usually has "O type", "U type" and "rectangular" according to the side wall morphology. Among them, the "rectangular" morphology is more conducive to the optimization of channel stress and resistance, and is closer to the ideal shape. However, due to the influence of the upper stack material (such as the side wall material above the source / drain region and the side wall material) during the source / drain silicon recess, it is difficult to obtain an ideal shape.

[0003] At present, the performance optimization of the source / drain silicon recess process in the formed semiconductor device needs to be improved. SUMMARY

[0004] Therefore, embodiments of the present application provide a method for forming source / drain silicon recess in a transistor, which improves the performance of the semiconductor structure.

[0005] To solve the above problems, the embodiment of the present application provides a forming method of source-drain silicon etching in a transistor, which selectively removes the gate side wall above the source-drain and the side wall by controlling the direction of plasma, optimizes the topography after the source-drain silicon etching, and the specific method comprises the following steps: providing a substrate, wherein the substrate comprises a device region, and a channel protrusion is arranged on the top of the substrate of the device region; forming a gate structure across the channel protrusion in the device region, and the gate structure covers part of the top and part of the side wall of the channel protrusion; forming a side wall material layer on the surface of the channel protrusion and the surface of the gate structure; selectively removing the side wall material layer covering the surface of the channel protrusion and the top of the gate structure; removing the source-drain channel by source-drain region etching to obtain a nearly rectangular etching topography; and forming a source-drain doped layer by epitaxy on both sides of the source-drain etching region of the gate structure.

[0006] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0007] The embodiment of the present application provides a forming method of source-drain silicon etching in a transistor, wherein a channel protrusion is arranged on the top of the substrate of the device region, and a gate structure is formed across the channel protrusion in the device region, and the side wall material layer covering the surface of the channel protrusion and the top of the gate structure is removed completely before the conventional source-drain region etching process, so that the cleanliness of the surface of the channel protrusion is improved, and the topography of the source-drain groove formed in the channel protrusion is improved, so that the stress of the source-drain region on the channel structure is more uniform from top to bottom, thereby improving the performance of the semiconductor structure.

[0008] In an optional solution, the process of removing the side wall material layer covering the surface of the channel protrusion and the top of the gate structure comprises a dry etching process, and the dry etching process comprises a scanning reactive ion etching process. Since the scanning reactive ion etching process has high anisotropy, can realize etching in a specific direction, and has precise ion beam control, in the embodiment of the present application, the side wall material layer on the surface of the channel protrusion is removed by scanning reactive ion etching, so that the surface material (for example, the side wall material layer) of the channel protrusion can be removed completely, the difficulty of the source-drain region etching process is reduced, and the side wall material layer in the direction of the gate side wall is reserved. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figures 1-8 is a structure diagram corresponding to each step in the forming method of the source-drain region structure in the semiconductor device (for example, a fin-type transistor structure);

[0010] Figures 9-33 is a structure diagram corresponding to each step in the forming method of the source-drain region structure in the semiconductor device (for example, a fin-type transistor structure). DETAILED DESCRIPTION

[0011] Figures 1-8 are structure diagrams corresponding to each step in the method for forming a source-drain region structure in a semiconductor device. In this embodiment, a fin field effect transistor (FinFET) is taken as an example for illustration. Specifically, Figure 1 Figure 3 and Figure 5 are cross-sectional diagrams along a direction parallel to the extension direction of the fin, Figure 2 Figure 4 and Figure 6 are cross-sectional diagrams along a direction perpendicular to the extension direction of the fin.

[0012] Referring to Figures 1-2 , a substrate 10 is provided, the substrate 10 including a device region, which can include a first device region 11A and a second device region 11B, a top portion of the substrate of the first device region 11A and the second device region 11B being formed with a fin 12 standing up, an isolation layer 13 being formed on the substrate at the side of the fin 12, and a gate oxide layer 14 being formed on the surface of the fin 12; in the first device region 11A and the second device region 11B, a gate structure 15 is formed across the fin 12, and the gate structure 15 covers part of the top portion and part of the sidewall of the fin 12; a sidewall material layer 16 is formed on the surface of the fin 12 exposed and the surface of the gate structure 15.

[0013] Referring to Figures 2-4 , the sidewall material layer 16 on the top portion and the side portion of the fin 12 and the top portion of the gate structure 15 is removed.

[0014] Specifically, taking the removal of the sidewall material layer in the first device region 11A as an example, the step includes: forming a mask layer 17 in the second device region 11B, which surrounds the surface of the fin in the second device region 11B, and removing the sidewall material layer 16 covering the surface of the fin 12 in the first device region 11A.

[0015] Referring to Figures 5-6 , the fin 12 is etched to form a recess 18.

[0016] It has been found through research that the performance of a semiconductor device is related to the recess morphology of the source-drain doped layer, and the recess morphology is rectangular (see Figure 7 , which helps to improve the stress of the source-drain region on the channel and improve the performance of the semiconductor device. Before etching the source-drain recess, the cleanliness of the surface of the channel protruding portion directly affects the morphology of the source-drain recess formed subsequently. For example, in the removal of the sidewall material layer on the surface of the channel protruding portion, the removal process adopted in the prior art needs to remove the sidewall material of the source-drain region and the channel at the same time (see Figure 6 ​​), resulting in poor source-drain recess morphology formed by subsequent etching, for example, the recess morphology can form an O shape (refer to Figure 8 ) or a U shape (refer to Figure 5 ).

[0017] To solve the technical problem, an embodiment of the present application provides a forming method of source-drain silicon etching in a transistor, comprising: providing a substrate, the substrate comprising a device region, and a top portion of the substrate of the device region standing a channel protrusion; in the device region, forming a gate structure across the channel protrusion, and the gate structure covering part of the top portion and part of the sidewall of the channel protrusion; forming a sidewall material layer on the surface of the channel protrusion and the surface of the gate structure; removing the sidewall material layer covering the surface of the channel protrusion by a direction-selective etching technology; and then removing the source-drain region channel by a source-drain region etching, and forming a source-drain doped layer on both sides of the gate structure by an epitaxial method.

[0018] In the scheme disclosed by the embodiment of the present application, after the sidewall material layer is formed on the surface of the channel protrusion and the surface of the gate structure, the sidewall material layer covering the surface of the channel protrusion and the top portion of the gate structure is removed completely, which can improve the cleanliness of the surface of the channel protrusion, and then improve the morphology of the source-drain recess formed in the channel protrusion subsequently, so that the dopant distribution of the source-drain region is more uniform, which is helpful for the subsequent epitaxial growth of the source-drain, thereby improving the performance of the semiconductor structure.

[0019] To make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0020] Figures 9-33 is a structure schematic diagram corresponding to each step in an embodiment of the present application, which is an optimized forming method of a source-drain region structure in a semiconductor device. In the embodiment, the channel protrusion can comprise a fin.

[0021] Referring to Figures 9-10 , specifically, Figure 9 is a top view based on Figure 10 , Figure 10 is a sectional view along a direction perpendicular to the extension direction of the fin (i.e. AA1 direction in Figure 9 .

[0022] With reference to Figure 9 and Figure 10 , a substrate 100 is provided, the substrate 100 comprising a device region, the device region can comprise a first device region 101A and a second device region 101B, and a top portion of the substrate 100 of the first device region 101A and the second device region 101B stands a fin 102, and a fin mask layer 103 is formed on the top portion of the fin 102.

[0023] The substrate 100 provides a process platform for subsequent process.

[0024] In this embodiment, the material of the substrate 100 is silicon, and in other embodiments, the material of the semiconductor substrate can be a group IV semiconductor material such as germanium, silicon germanium, silicon carbide, or a group III-V semiconductor material such as gallium arsenide or indium gallium arsenide, or other materials, and the semiconductor substrate can also be a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate, or other types of semiconductor substrates. The material of the semiconductor substrate can be a material suitable for process needs or easy to integrate.

[0025] In this embodiment, the first device region can be a PMOS region for forming a PMOS transistor, and the second device region can be an NMOS region for forming an NMOS transistor. In other embodiments, the first device region can be an NMOS region, and the second device region can be a PMOS region.

[0026] In this embodiment, the material of the fin 102 can include one or more of silicon, silicon germanium, germanium, and a group III-V semiconductor material, and the material of the fin 102 is determined according to the channel conductivity type and performance requirements of the transistor.

[0027] Reference Figures 11-12 , specifically, Figure 11 is a top view based on Figure 12 , and Figure 12 is a cross-sectional view along a direction perpendicular to the extension direction of the fin, that is, the AA1 direction in Figure 11 .

[0028] In combination with Figures 11-12 , an isolation layer 104 is formed on the substrate 100 at the side of the fin 102, and the top of the isolation layer 104 is lower than the top of the fin 102.

[0029] It should be noted that the top of the isolation layer 104 is lower than the top of the fin 102, and the isolation layer 104 exposes a portion of the height of the fin 102.

[0030] It should also be noted that the isolation layer 104 exposes a portion of the height of the fin 102, which is used as an effective fin.

[0031] The isolation layer 104 is used to isolate adjacent devices to prevent leakage current between devices. Specifically, the isolation layer 104 is used as a shallow trench isolation structure (STI).

[0032] It should be noted that the material of the isolation layer 104 can be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0033] Specifically, the step of forming the isolation layer 104 includes: forming an isolation material layer (not shown in the figure) on the exposed substrate of the fin 102, the isolation material layer surrounding the sidewall covering the fin 102; planarizing the top of the isolation material layer to expose the top of the fin mask layer 103; after planarizing the top of the isolation material layer, removing part of the thickness of the remaining isolation material layer to form the isolation layer 104.

[0034] Reference Figures 13-14 , specifically, Figure 13 is a top view based on Figure 14 , and Figure 14 is a cross-sectional view along a direction perpendicular to the extension direction of the fin, that is, the AA1 direction in Figure 13 .

[0035] In combination Figures 13-14 , the gate structure 105 is formed across the fin 102, and the gate structure 105 covers part of the top and part of the sidewall of the fin 102.

[0036] In this embodiment, the gate structure 105 is a dummy gate structure, and the gate structure 105 is used to occupy a space position for subsequent formation of a metal gate structure.

[0037] In this embodiment, the gate structure 105 can be a laminated structure, and the gate structure 105 includes a gate oxide layer 106 and a dummy gate layer (not shown in the figure) located on the gate oxide layer 106. Wherein, the gate oxide layer 106 covers the top and sidewall of the fin 102.

[0038] In this embodiment, the material of the gate oxide layer can be silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.

[0039] In this embodiment, the material of the dummy gate layer can be polysilicon. In other embodiments, the material of the dummy gate layer can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, silicon carbon oxynitride, or amorphous carbon and other materials.

[0040] In other embodiments, the dummy gate structure can also be a single-layer structure, and the dummy gate structure accordingly only includes the dummy gate layer.

[0041] Specifically, the step of forming the gate structure 105 includes: forming a gate structure material layer (not shown in the figure) covering the fin 102, the gate structure material layer covering the top and sidewall of the fin 102; referring to Figure 14 , forming a gate mask layer 107 on the top of the gate structure material layer; patterning the gate structure material layer with the gate mask layer 107 as a mask to form the gate structure 105 across the fin 102.

[0042] In other embodiments, the gate structure can also be a device gate structure for controlling the turn-on and turn-off of a conductive channel (not shown) in the device fin 102 according to actual process requirements. As an example, the gate structure can be a metal gate structure.

[0043] Referring to Figures 15-17 , in particular, Figure 15 is a top view based on Figure 16 , and Figure 16 is a cross-sectional view along a direction perpendicular to the fin extension direction (i.e., the AA1 direction in Figure 15 , and Figure 17 is a cross-sectional view along a direction parallel to the fin extension direction (i.e., the BB1 direction in Figure 15 .

[0044] In combination with Figures 15-17 , a sidewall material layer 108 is deposited on the surface of the fin 102 and the surface of the gate structure 105.

[0045] The sidewall material layer 108 can protect the gate structure 105 and the fin 102 from chemical or physical damage, help reduce gate leakage current, and improve the performance of the semiconductor structure

[0046] In particular, the sidewall material layer 108 located on the sidewall of the gate structure 105 is used as a sidewall structure (not shown) for protecting the sidewall of the gate structure 105, and for defining the formation position of the source / drain doped layer.

[0047] In this embodiment, the material of the sidewall material layer 108 can include a low-k dielectric material, which is beneficial for reducing the capacitive coupling effect of the gate structure 105 and other device structures.

[0048] In this embodiment, the process for forming the sidewall material layer 108 can include an atomic layer deposition (ALD) process.

[0049] The atomic layer deposition process can deposit a highly uniform thin film on a three-dimensional structure, which is beneficial for achieving precise coverage of the sidewall material layer. At the same time, the atomic layer deposition process can achieve atomic layer-level growth and regulation, so that the thickness of the sidewall material layer can be precisely controlled, and a high-performance semiconductor structure can be manufactured.

[0050] Referring to Figures 18-21 , in particular, Figure 19 is a top view based on Figure 20 , and Figure 20 is a cross-sectional view along a direction perpendicular to the fin extension direction (i.e., the AA1 direction in Figure 19 , andFigure 21 is a cross-sectional view along a direction parallel to the extension direction of the fin (i.e. Figure 19 the BB1 direction in FIG.

[0051] In combination with Figures 18-21 , the sidewall material layer 108 covering the surface of the fin 102 and the top of the gate structure 105 is removed;

[0052] In order to perform subsequent process flow of forming a semiconductor structure, a source-drain doped layer is formed in the fin, it is necessary to remove the sidewall material layer covering the surface of the fin.

[0053] In this embodiment, the process of removing the sidewall material layer 108 covering the surface of the fin 102 and the top of the gate structure 105 can include a dry etching process.

[0054] In this embodiment, the dry etching process can include a scanning reactive ion etching process (Scanning RIE).

[0055] Scanning RIE combines the high anisotropy of reactive ion etching (RIE) and the precise control ability of ion beam etching (IBE), and achieves high precision and high selectivity etching by using a focused ion beam to scan the fin surface. Therefore, by scanning reactive ion etching process, it can be achieved to remove the material in a specific area (such as the sidewall material layer on the source-drain region fin) in a specific direction (such as the arrow direction shown in FIG. Figure 18 , and by adjusting the energy of the ion beam, the etching process can be precisely controlled, so that Scanning RIE can effectively remove the residual material on the surface of the fin without damaging the surrounding structure, reduce the complexity of the material on the surface of the fin, and provide a process basis for subsequent formation of ideal etch-back topography and source-drain doped layer.

[0056] It should be noted that, Figure 18 The arrow direction shown is an example of the scanning direction of the scanning reactive ion etching process in the embodiment of the present application. In the embodiment of the present application, it can be realized by physical etching based on inert gases such as Ar, N2, etc., reactive etching based on fluorocarbon gas (CHF3, CF4, etc.), and a combination of the two.

[0057] In this embodiment, the process parameters of the scanning reactive ion etching process can include related parameters when the etching gas is dissociated, such as reactive gas based on Ar / N2 / CHF3 / CF4, gas pressure range about 1-100mTorr, etching temperature (0-200℃), and ion beam scanning angle (angle range -45-45°) and scanning time, etc.

[0058] In the embodiment, the step of removing the sidewall material layer covering the surface of the fin includes: removing the sidewall material layer of the top and sidewall of the fin. In the step of removing the sidewall material layer of the sidewall of the fin, the scanning direction of the ion beam of the Scanning RIE can be perpendicular or parallel to the extension direction of the channel, so that the sidewall material layer of the sidewall of the fin can be completely removed, and the subsequent fin etching back is facilitated.

[0059] Referring to Figures 22-24 , specifically, Figure 22 is a top view based on Figure 23 , and Figure 23 is a cross-sectional view along a direction perpendicular to the extension direction of the fin, i.e., the AA1 direction in Figure 22 , and Figure 24 is a cross-sectional view along a direction parallel to the extension direction of the fin, i.e., the BB1 direction in Figure 22 .

[0060] Referring to Figures 22-24 , a mask layer 109 is formed on the surface of the second device region 101B.

[0061] In the embodiment, when the etching is performed to form the source-drain recess in the first device region 101A, the mask layer 109 can be covered on the surface of the second device region 101B to accurately position the region to be etched (the first device region 101A) and protect the region not to be etched (the second device region 101B).

[0062] In the embodiment, the material of the mask layer 109 can include photoresist (PR).

[0063] Referring to Figures 25-27 , specifically, Figure 25 is a top view based on Figure 26 , and Figure 26 is a cross-sectional view along a direction perpendicular to the extension direction of the fin, i.e., the AA1 direction in Figure 25 , and Figure 27 is a cross-sectional view along a direction parallel to the extension direction of the fin, i.e., the BB1 direction in Figure 25 .

[0064] Referring to Figures 25-27 , a recess 110 is formed in the fin 102 on both sides of the gate structure 105 in the first device region 101A.

[0065] Specifically, the fin 102 on both sides of the gate structure 105 in the first device region 101A is etched to a proper depth to form the recess 110.

[0066] The recess 110 is used for subsequent formation of a source-drain doped layer.

[0067] It should be noted that in this embodiment, the fin portion 102 can be etched to the same height as the top of the isolation layer 104; in other embodiments, the depth of the etching inside the fin portion can be precisely controlled according to actual process requirements to ensure that the size and depth of the source-drain groove meet the process requirements.

[0068] In this embodiment, the process of forming the groove 110 can include a scanning reactive ion etching process, and the shape of the groove 110 can include a rectangle.

[0069] In this embodiment, the scanning reactive ion etching process removes the material residues of the sidewall material layer on the surface of the fin portion 102, and the scanning reactive ion etching process etches the source-drain groove, so that the source-drain groove formed has a rectangular shape.

[0070] It should be noted that the rectangular source-drain groove can make the distribution of the doped material filled in the source-drain groove more uniform, which is beneficial to the epitaxial growth of the source-drain.

[0071] Reference Figures 28-30 , specifically, Figure 28 is a top view based on Figure 29 , and Figure 29 is a cross-sectional view along a direction perpendicular to the extension direction of the fin, that is, the AA1 direction in Figure 28 , and Figure 30 is a cross-sectional view along a direction parallel to the extension direction of the fin, that is, the BB1 direction in Figure 28 .

[0072] In combination with Figures 28-30 , the source-drain material is deposited in the groove 110 formed in the first device area 101A to form a P-type source-drain doped layer 111.

[0073] In this embodiment, the first device area 101A is a PMOS area, and the source-drain doped layer formed in the PMOS area can be a P-type source-drain doped layer 111. Therefore, the material used to form the P-type source-drain doped layer 111 filled in the groove 110 can include silicon germanium (SiGe).

[0074] In this embodiment, the process of forming the source-drain doped layer can include an epitaxial growth process (EPI, Epitaxy).

[0075] The epitaxial growth process has the advantages of simple process, fast growth, low cost, no need for ultra-high vacuum, and easy industrialization, and using the epitaxial growth process can improve the formation quality and material purity of the P-type source-drain doped layer 111, thereby facilitating the improvement of the quality of the source-drain doped layer.

[0076] In a specific implementation, the process for forming the source / drain doped layer may further include ion implantation. Ion implantation allows for precise control of the dopant concentration and depth, which is beneficial for forming source / drain regions with specific electrical characteristics, thereby improving the performance of the final semiconductor structure.

[0077] refer to Figures 31-33 , specifically, Figure 31 For based on Figure 32 Top view, Figure 32 Along the direction perpendicular to the extension of the fin (i.e. Figure 31 A cross-sectional view along the AA1 direction in the diagram. Figure 33 Along the direction parallel to the extension of the fin (i.e. Figure 31 A cross-sectional view (in the BB1 ​​direction).

[0078] Combination Figures 31-33 An N-type source / drain doped layer 112 is formed in the second device region 101B.

[0079] For a detailed description of the formation of the N-type source / drain doped layer 112, please refer to the foregoing description of the formation of the P-type source / drain doped layer 111, which will not be repeated here.

[0080] The material used to form the N-type source / drain doped layer 112 may include silicon phosphide (SiP).

[0081] In this embodiment, the method for forming the source / drain region further includes: forming an interlayer dielectric layer (not shown in the figure) covering the source / drain doped layer, and performing planarization treatment on the interlayer dielectric layer to ensure the flatness of the interlayer dielectric layer, providing a good foundation for subsequent metal layer deposition. It should be noted that the subsequent process flows for forming the semiconductor structure will not be described in detail in this embodiment of the invention.

[0082] It should be noted that this method can also be applied to the Gate-all-around (GAA) transistor process. The difference from the previous embodiment is that the channel protrusions in the GAA transistor are a stacked structure, the gate structure completely surrounds the channel, and the final semiconductor structure formed in this embodiment is a Gate-all-around (GAA) transistor.

[0083] The above describes the multiple embodiment schemes provided by the embodiments of the present application. The optional modes introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending multiple possible embodiment schemes, which can be considered as the embodiments disclosed and published by the embodiments of the present application. Although the embodiments of the present application are disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the range defined by the claims.

Claims

1. A method for forming source and drain silicon etch-back in a transistor, characterized in that, include: A substrate is provided, the substrate including a device region, and a channel protrusion is formed on the top of the substrate of the device region; In the device region, a gate structure is formed across the channel protrusion, and the gate structure covers part of the top and part of the sidewall of the channel protrusion; A sidewall material layer is formed on the surface of the channel protrusion and the surface of the gate structure; Remove the sidewall material layer covering the surface of the channel protrusion and the top of the gate structure; Source and drain doped layers are formed in the channel protrusions on both sides of the gate structure.

2. The method for forming source and drain silicon etchback in a transistor as described in claim 1, characterized in that, The process of forming a sidewall material layer on the surface of the channel protrusion and the surface of the gate structure includes: atomic layer deposition process.

3. The method for forming source and drain silicon etchback in a transistor as described in claim 2, characterized in that, In the step of forming the sidewall material layer, the material of the sidewall material layer includes: a low-k dielectric material.

4. The method for forming source and drain silicon etchback in a transistor as described in claim 3, characterized in that, The process for removing the surface of the channel protrusion and the sidewall material layer on top of the gate structure includes a dry etching process.

5. The method for forming source and drain silicon etchback in a transistor as described in claim 4, characterized in that, The dry etching process includes: scanning reactive ion etching process.

6. The method for forming source and drain silicon etchback in a transistor as described in claim 5, characterized in that, The process parameters of the scanning reactive ion etching process include: etching temperature, ion beam scanning angle, and scanning time; The etching temperature ranges from 0 to 200°C, and the ion beam scanning angle ranges from -45° to 45°.

7. The method for forming source and drain silicon etchback in a transistor as described in claim 6, characterized in that, The step of removing the sidewall material layer from the surface of the groove protrusion includes: Remove the exposed top and sidewall material layers of the protruding part of the channel.

8. The method for forming source and drain silicon etchback in a transistor as described in claim 7, characterized in that, In the step of removing the sidewall material layer of the sidewall of the channel protrusion, the working direction of the scanning reactive ion etching process is perpendicular or parallel to the extension direction of the channel protrusion.

9. The method for forming source and drain silicon etchback in a transistor as described in claim 8, characterized in that, The step of forming source / drain doped layers in the channel protrusions on both sides of the gate structure includes: Grooves are formed in the channel protrusions on both sides of the gate structure, and source / drain doped layers are formed in the grooves.

10. The method for forming source and drain silicon etchback in a transistor as described in claim 9, characterized in that, The process for forming the groove includes: scanning reactive ion etching process.

11. The method for forming source and drain silicon etch-back in a transistor as described in claim 10, characterized in that, The process of forming source / drain doped layers in the groove includes an epitaxial growth process.

12. The method for forming source and drain silicon etchback in a transistor as described in claim 11, characterized in that, In the step of forming the groove, the shape of the groove includes a rectangle.

13. The method for forming source and drain silicon etch-back in a transistor as described in claim 1, characterized in that, In the step of providing the substrate, the device region includes a first device region and a second device region, wherein the first device region is a PMOS region and the second device region is an NMOS region.

14. The method for forming source and drain silicon etch-back in a transistor as described in claim 13, characterized in that, In the step of forming the source / drain doped layer, the source / drain doped layer formed in the PMOS region is a P-type source / drain doped layer, and the material for forming the P-type source / drain doped layer includes silicon germanide. The source / drain doped layer formed in the NMOS region is an N-type source / drain doped layer, and the material forming the N-type source / drain doped layer includes silicon phosphide.

Images