Silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure

Abstract

The invention relates to the technical field of gallium nitride transistors, and discloses a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure, which comprises a silicon carbide device consisting of a plurality of parallel MOS (Metal Oxide Semiconductor) cells and a gallium nitride device consisting of two GaN structures, and is characterized in that the gallium nitride device is positioned on the back surface of the silicon carbide device; each MOS cell comprises a semiconductor epitaxial layer, an MOS source electrode, an MOS grid electrode and an MOS dielectric layer covering the surface of the MOS grid electrode; wherein the semiconductor epitaxial layer comprises an N substrate layer and an N diffusion layer from top to bottom. The transverse high electron mobility characteristic of the GaN HEMT and the longitudinal voltage withstanding advantage of the SiC MOSFET are combined, cooperative work of two wide bandgap semiconductors is achieved on a single substrate, the structure effectively utilizes the excellent heat conduction and voltage withstanding performance of the SiC substrate as a common carrier, meanwhile, through the series voltage withstanding design of the device level, the performance of the device level is improved, and the performance of the device level is improved. And the overall breakdown voltage is obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of gallium nitride transistors, and particularly relates to a silicon carbide-gallium nitride hetero-integrated high-voltage power device structure. BACKGROUND

[0002] With the development of microelectronic technology, as a representative of power semiconductor devices, gallium nitride high electron mobility transistors (HEMT) have great market potential in high-frequency application fields. Wide-bandgap semiconductor GaN material has an ultra-high critical breakdown field, nearly 10 times that of silicon (Si), and a heterojunction composed of AlGaN and GaN has a very strong two-dimensional electron gas. Therefore, under the same withstand voltage condition, the on-resistance of a GaN power device is nearly three orders of magnitude lower than that of a Si device, greatly reducing the chip area and the weight of the driving circuit. Moreover, gallium nitride (GaN) material has good thermal conductivity and has great application value in high-temperature power electronic devices. In the future, GaN-based power electronics may become a substitute for Si-based power devices and play an important role in smart grids, hybrid electric vehicles, aerospace, high-speed railways and other new industries.

[0003] However, the existing GaN HEMT is a two-dimensional device, and as the withstand voltage increases, the area also increases, and the defects also increase with the increase of the area, and the device reliability decreases greatly. Therefore, although GaN HEMT has many advantages, it still cannot be well applied in the high-voltage field.

[0004] Compared with GaN HEMT, the main withstand voltage mode of SiC MOSFET device is longitudinal withstand voltage, which can well avoid the shortcomings of GaN HEMT lateral withstand voltage, and the thermal conductivity, high frequency and low resistance of silicon carbide are much higher than those of silicon. Therefore, replacing the substrate of GaN HEMT from silicon to silicon carbide and performing special structure design can bring a major breakthrough in the withstand voltage field of power devices.

[0005] The existing patent discloses CN115832040A-silicon carbide-based gallium nitride device and a preparation method thereof. The existing silicon carbide-based GaN HEMT device is still limited by the two-dimensional electron gas lateral withstand voltage capacity and the problem that the single-device withstand voltage improvement is accompanied by an increase in area and defects under high voltage. SUMMARY

[0006] The present application provides a silicon carbide-gallium nitride hetero-integrated high-voltage power device structure to solve the existing technical problems, and solves the inherent problems of area increase and reliability decrease of traditional GaN devices under high voltage.

[0007] To solve the above technical problems, according to one aspect of the present application, more specifically, a silicon carbide-gallium nitride hetero-integrated high-voltage power device structure, comprising a silicon carbide device composed of a plurality of parallel MOS cells, and a gallium nitride device composed of two GaN structures, wherein the gallium nitride device is located on the back of the silicon carbide device; Each of the MOS cells comprises a semiconductor epitaxial layer, a MOS source, a MOS gate, and a MOS dielectric layer covering the surface of the MOS gate. The semiconductor epitaxial layer comprises an N substrate layer and an N diffusion layer from top to bottom, respectively; a P well layer one is formed by ion implantation in the interior of the N diffusion layer and between adjacent two MOS cells; and two non-contact N well layers are formed by ion implantation in the interior of each P well layer one. Each of the GaN structures comprises a buffer layer, a GaN channel layer, an AlGaN barrier layer, a covering dielectric layer, and a GaN gate from bottom to top. Two independent barrier dielectric layers are deposited between adjacent two GaN structures, and the two barrier dielectric layers are in direct contact with the buffer layer and the GaN channel layer on the two GaN structures, respectively. A GaN source is also deposited between adjacent two GaN structures; and a GaN drain is deposited on each GaN structure and located away from the GaN source.

[0008] Further, the P well layer one is in ohmic contact with the MOS source, and the two non-contact N well layers are also in ohmic contact with the MOS source.

[0009] Further, the side edge of the GaN source is in ohmic contact with the GaN channel layer and the AlGaN barrier layer; and the bottom edge of the GaN source is in ohmic contact with the N substrate layer.

[0010] Further, the GaN gates on the two GaN structures are independent of each other, and the GaN gates are located close to the GaN source.

[0011] Further, the GaN sources on adjacent two GaN structures are integrated.

[0012] Further, the GaN source comprises two independent sources that are not in contact with each other, and the two independent sources are in ohmic contact with the GaN channel layer and the AlGaN barrier layer on the two GaN structures, respectively.

[0013] Further, a P well layer two is formed by ion implantation in the interior of the N substrate layer and between the two GaN structures.

[0014] Further, the covering medium layer comprises a through medium layer, another end of the through medium layer penetrates and extends to between the two independent sources and directly contacts the N substrate layer.

[0015] Further, the GaN gate comprises a T-shaped gate, two adjacent T-shaped gates on the GaN structure are integrated, and a cross-sectional profile of the T-shaped gate is in a "T" shape. A horizontal part of the "T" shape of the T-shaped gate is located above the through medium layer, and a longitudinal part of the "T" shape of the T-shaped gate penetrates and extends to the second surface of the P well layer.

[0016] The silicon carbide-gallium nitride hetero-integrated high-voltage power device structure provided by the application has the following effects compared with the prior art: 1. The GaN HEMT transverse high electron mobility characteristics are combined with the longitudinal voltage resistance advantages of the SiC MOSFET, the synergistic work of the two wide-bandgap semiconductors on a single substrate is realized, the excellent heat conduction and voltage resistance performance of the SiC substrate are effectively utilized as a common carrier, the overall breakdown voltage is significantly improved through the device-level series voltage resistance design, the inherent limitations of the traditional GaN device in the area increase and reliability decrease under high voltage are overcome, a compact and efficient solution is provided for high-voltage and high-frequency power applications.

[0017] 2. The GaN gate potential is automatically stabilized without external clamping elements through the integrated potential self-clamping structure; specifically, the internal PN junction formed by the second P well layer and the N substrate layer is introduced, the integrated design of the through medium layer and the T-shaped gate is matched, the gate potential can be synchronously floated with the source potential, so that the GaN HEMT can be reliably cut off in the off state of the device, and the gate overvoltage damage is avoided. This not only enhances the safety and reliability of the device under high-voltage blocking, but also simplifies the peripheral circuit and packaging process.

[0018] 3. The GaN device is placed on the back of the SiC MOSFET, and the N substrate layer and the N diffusion layer are shared to realize electrical interconnection and heat management, and the power density of the chip is greatly improved. This design of combining longitudinal stacking and horizontal array realizes higher current processing capacity and better heat dissipation path in a limited area, which helps to reduce the on-resistance and improve the overall energy efficiency.

[0019] 4、The application finally presents as a standardized device with only three external electrodes, i.e. gate, drain and source, which is fully compatible with the pin definition of mainstream power MOSFET. This makes the high-performance heterogeneous integrated device capable of directly replacing existing silicon-based or single wide-bandgap devices without changing the driving circuit or system design, greatly reducing the barriers and costs of technology upgrading in high-voltage applications such as power conversion and motor driving, and accelerating the popularization and application of wide-bandgap semiconductor technology in the high-end power field. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a structural schematic diagram in the embodiment one of the application; Figure 2 is a structural schematic diagram in the embodiment two of the application; Figure 3 is a structural relationship diagram of the embodiment one of the application.

[0021] In the figure: 1, MOS cell; 2, GaN structure; 101, MOS source; 102, MOS gate; 103, MOS dielectric layer; 104, P well layer one; 105, N well layer; 106, N diffusion layer; 107, N substrate layer; 201, buffer layer; 202, GaN channel layer; 203, GaN drain; 204, AlGaN barrier layer; 205, GaN gate; 206, GaN source; 207, covering dielectric layer; 208, blocking dielectric layer; 209, P well layer two; 2051, T-shaped gate; 2061, independent source; 2071, through dielectric layer. DETAILED DESCRIPTION

[0022] In order to make the technical scheme of the application clearer, the application will be further described in detail below in combination with the drawings and specific embodiments.

[0023] Embodiment 1 As Figure 1 , Figure 3As shown, a silicon carbide-gallium nitride hetero-integrated high-voltage power device structure includes a silicon carbide device composed of a plurality of mutually juxtaposed MOS cells 1, and a gallium nitride device composed of two GaN structures 2, wherein the gallium nitride device is located on the back of the silicon carbide device; a single MOS cell 1 includes a semiconductor epitaxial layer, a MOS source 101, a MOS gate 102, and a MOS dielectric layer 103 covering the surface of the MOS gate 102; wherein the semiconductor epitaxial layer includes an N substrate layer 107 and an N diffusion layer 106 from top to bottom; a P well layer 104 is formed by ion implantation inside the N diffusion layer 106 and between adjacent two MOS cells 1, and two mutually non-contacting N well layers 105 are formed by ion implantation inside a single P well layer 104; a single GaN structure 2 includes a buffer layer 201, a GaN channel layer 202, an AlGaN barrier layer 204, a covering dielectric layer 207, and a GaN gate 205 from bottom to top; wherein two independent blocking dielectric layers 208 are deposited between adjacent two GaN structures 2, and the two blocking dielectric layers 208 are in direct contact with the buffer layer 201 and the GaN channel layer 202 on the two GaN structures 2, respectively; a GaN source 206 is also deposited between adjacent two GaN structures 2; a GaN drain 203 is deposited on a single GaN structure 2 and on the side away from the GaN source 206.

[0024] The P well layer 104 is in ohmic contact with the MOS source 101, and the two mutually non-contacting N well layers 105 are also in ohmic contact with the MOS source 101. The side edge of the GaN source 206 is in ohmic contact with the GaN channel layer 202 and the AlGaN barrier layer 204; the bottom edge of the GaN source 206 is in ohmic contact with the N substrate layer 107. The GaN gates 205 on the two GaN structures 2 are independent of each other and are located close to the GaN source 206. The GaN sources 206 on adjacent two GaN structures 2 are integrated.

[0025] In this embodiment, the substrate of the GaN structure 2 is replaced by the N substrate layer 107 and the N diffusion layer 107 of silicon carbide, and a silicon carbide MOSFET device (MOSFET device composed of a plurality of MOS cells 1) is manufactured on the silicon carbide N diffusion layer 107, which reasonably and sufficiently utilizes the lateral space and the vertical space of the device; The drain of the MOSFET device and the source of the GaN structure 2 are combined into an electrode S1 (GaN source 206), and the overall withstand voltage is increased by the series connection of the two types of voltage-resistant devices; And the GaN HEMT adopted is a depletion mode device structure, which will lead to four electrodes when the device is packaged, namely the GaN drain 203, the GaN gate 205, the MOS gate 102, and the MOS source 101; In the packaging process, the clamping diode can be used to clamp the voltage between the G1 electrode (GaN gate 205) and the S1 electrode (GaN source 206), so that the GaN HEMT can be exactly turned off without damaging the G1 electrode (GaN gate 205) due to bearing a large voltage when the device is in the blocking state, and the device pin after packaging becomes normal G (MOS gate 102), D (GaN drain 203), and S (MOS source 101).

[0026] In the embodiment, the structure is realized by replacing the substrate of the GaN HEMT with an N substrate layer 107 and an N diffusion layer 106 of silicon carbide, and integrating multiple MOS cells 1 on the surface thereof to form a SiC MOSFET device, realizing the heterogeneous integration of the SiC longitudinal withstand voltage and the GaN high electron mobility. The core innovation is to combine the drain function of the MOSFET to the GaN source 206 to form a series voltage withstand structure, and to realize the reliable turn-off of the GaN device in the blocking state through the external clamping circuit between the GaN gate 205 and the GaN source 206, thereby significantly improving the overall withstand voltage capability, and only connecting the G (MOS gate 102), D (GaN drain 203), and S (MOS source 101) three electrodes, simplifying the packaging and application.

[0027] Embodiment 2 As shown in Figure 2 A silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure includes a silicon carbide device composed of a plurality of parallel MOS cells 1, and a gallium nitride device composed of two GaN structures 2, wherein the gallium nitride device is located on the back surface of the silicon carbide device; a single MOS cell 1 includes a semiconductor epitaxial layer, a MOS source 101, a MOS gate 102, and a MOS dielectric layer 103 covering the surface of the MOS gate 102; wherein the semiconductor epitaxial layer includes an N substrate layer 107 and an N diffusion layer 106 from top to bottom; an internal P well layer 104 is formed between adjacent two MOS cells 1 in the N diffusion layer 106 by ion implantation, and two N well layers 105 are formed in the internal P well layer 104 by ion implantation; a single GaN structure 2 includes a buffer layer 201, a GaN channel layer 202, an AlGaN barrier layer 204, a covering dielectric layer 207, and a GaN gate 205 from bottom to top; wherein two independent barrier dielectric layers 208 are deposited between adjacent two GaN structures 2, and the two barrier dielectric layers 208 are in direct contact with the buffer layer 201 and the GaN channel layer 202 on the two GaN structures 2, respectively; a GaN source 206 is also deposited between adjacent two GaN structures 2; a GaN drain 203 is deposited on a single GaN structure 2 and located away from the GaN source 206.

[0028] P well layer 104 is ohmic contact with MOS source 101, two N well layers 105 are ohmic contact with MOS source 101. The side of GaN source 206 is ohmic contact with GaN channel layer 202 and AlGaN barrier layer 204, and the bottom of GaN source 206 is ohmic contact with N substrate layer 107. GaN source 206 includes two independent sources 2061, and the two independent sources 2061 are ohmic contact with GaN channel layer 202 and AlGaN barrier layer 204 on the two GaN structures 2 respectively. The inside of N substrate layer 107 and between the two GaN structures 2 is formed with P well layer 209 by ion implantation. Covering medium layer 207 includes a through medium layer 2071, the other end of the through medium layer 2071 penetrates and extends between the two independent sources 2061 and is in direct contact with N substrate layer 107. GaN gate 205 includes T-shaped gate 2051, the two T-shaped gates 2051 on the adjacent two GaN structures 2 are integrated, and the cross-sectional profile of the T-shaped gate 2051 is in the shape of "T". The horizontal part of the "T" shape of the T-shaped gate 2051 is above the through medium layer 2071, and the vertical part of the "T" shape of the T-shaped gate 2051 penetrates and extends to the surface of P well layer 209.

[0029] In this embodiment, P well layer 209 is formed on N substrate layer 107 by implanting P impurities, thereby forming a pn junction with N substrate layer 107 (the principle of this part is that after the pn junction is formed, the electric charge can only flow in one direction. If the potential of independent source 2061 is reduced, the potential of T-shaped gate 2051 is relatively increased), wherein the implantation concentration and depth of P well layer 209 can be determined by the designer, and it is necessary to ensure that the potential of S1 pole (independent source 2061) is higher than the potential of G1 pole (T-shaped gate 2015) so that the GaN HEMT can be kept off when the device is blocked, and it is not too high to make G1 pole (T-shaped gate 2015) and S1 pole (independent source 2061) breakdown.

[0030] This embodiment structure has three external electrodes as the electrodes of the whole structure, which are G (MOS gate 102), D (GaN drain), and S (MOS source) electrodes shown in the figure. Figure 2 The specific working principle is as follows: When the G (MOS gate 102) pole applies a voltage to turn on the device, the potential of S1 pole (independent source 2061) is reduced, and the potential of G1 pole (T-shaped gate 2051) is higher than that of S1 pole (independent source 2061) by a threshold voltage of a pn junction. The GaN HEMT device is turned on, and the current flows from D pole (GaN drain) to S1 pole (independent source 2061) and finally to S pole (MOS source).

[0031] When the G pole (MOS gate 102) voltage drops to 0, the MOSFET structure part is partially turned off, the S1 pole (independent source 2061) potential increases, and when the S1 pole (independent source 2061) and the G1 pole (T-shaped gate 2051) potential difference is higher than the pn junction blocking voltage, the G1 pole (T-shaped gate 2051) potential starts to rise synchronously with the S1 pole (independent source 2061), and at the same time, the GaN HEMT structure starts to turn off the pressure.

[0032] In this embodiment, the substrate of the GaN HEMT is replaced by a silicon carbide N substrate layer 107 and an N diffusion layer 107, and a silicon carbide MOSFET device is manufactured on the silicon carbide N diffusion layer 107, which reasonably and fully utilizes the lateral space and the longitudinal space of the device.

[0033] This embodiment is further optimized on the basis of embodiment 1, the GaN source 206 is designed as two independent sources 2061, and a P well layer two 209 is formed by implantation in the N substrate layer 107, the covering dielectric layer 207 is improved to a through dielectric layer 2071, and an integrated T-shaped gate 2051 is adopted to penetrate to the surface of the P well layer two 209. This combined structure realizes the function of self-holding potential: when the S1 pole (independent source 2061) potential changes, the PN junction formed by the P well layer two 209 and the N substrate layer 107 automatically adjusts the T-shaped gate 2051 potential, thereby ensuring that the GaN HEMT can be reliably turned off in the blocking state without the need for external clamping circuit, while optimizing the electric field distribution, further improving the high-voltage reliability and integration of the device.

[0034] The above-described embodiments only express several embodiments of the present application, which are described in detail and in detail, but cannot be understood as limiting the scope of the present application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure, characterized in that, The silicon carbide device comprises a plurality of MOS cells (1) arranged side by side, and a gallium nitride device comprising two GaN structures (2), wherein the gallium nitride device is located on the back of the silicon carbide device; Each of the MOS cells (1) comprises a semiconductor epitaxial layer, a MOS source (101), a MOS gate (102), and a MOS dielectric layer (103) covering the surface of the MOS gate (102); The semiconductor epitaxial layer comprises an N substrate layer (107) and an N diffusion layer (106) from top to bottom; a P well layer (104) is formed by ion implantation in the N diffusion layer (106) and between two adjacent MOS cells (1); and two N well layers (105) are formed by ion implantation in the P well layer (104). Each of the GaN structures (2) comprises a buffer layer (201), a GaN channel layer (202), an AlGaN barrier layer (204), a covering dielectric layer (207), and a GaN gate (205) from bottom to top; Two independent barrier dielectric layers (208) are deposited between two adjacent GaN structures (2), and the two barrier dielectric layers (208) are in direct contact with the buffer layer (201) and the GaN channel layer (202) of the two GaN structures (2), respectively. A GaN source (206) is deposited between two adjacent GaN structures (2); and a GaN drain (203) is deposited on each of the GaN structures (2) and away from the GaN source (206).

2. The silicon carbide-gallium nitride hetero-integrated high voltage power device structure of claim 1, wherein: The P well layer (104) is in ohmic contact with the MOS source (101); and the two N well layers (105) are in ohmic contact with the MOS source (101).

3. The silicon carbide-gallium nitride hetero-integrated high voltage power device structure of claim 1, wherein: The side of the GaN source (206) is in ohmic contact with the GaN channel layer (202) and the AlGaN barrier layer (204); and the bottom of the GaN source (206) is in ohmic contact with the N substrate layer (107).

4. The silicon carbide-gallium nitride hetero-integrated high voltage power device structure of claim 3, wherein: The GaN gates (205) of the two GaN structures (2) are independent of each other and located close to the GaN source (206).

5. The silicon carbide-gallium nitride hetero-integrated high voltage power device structure of claim 4, wherein: The GaN sources (206) of two adjacent GaN structures (2) are integrated.

6. The silicon carbide-gallium nitride hetero-integrated high voltage power device structure of claim 3, wherein: The GaN source (206) comprises two independent sources (2061) that are not in contact with each other, and the two independent sources (2061) are in ohmic contact with the GaN channel layer (202) and the AlGaN barrier layer (204) of the two GaN structures (2), respectively.

7. The silicon carbide-gallium nitride hetero-integrated high voltage power device structure of claim 6, wherein: A P well layer (209) is formed by ion implantation in the N substrate layer (107) and between the two GaN structures (2).

8. The silicon carbide-gallium nitride hetero-integrated high voltage power device structure of claim 7, wherein: The covering dielectric layer (207) comprises a through dielectric layer (2071) that extends to the N substrate layer (107) and between the two independent sources (2061).

9. The silicon carbide-gallium nitride hetero-integrated high voltage power device structure of claim 8, wherein: The GaN gate (205) includes a T-shaped gate (2051), two adjacent T-shaped gates (2051) on the GaN structure (2) are integrated, and the cross-sectional profile of the T-shaped gate (2051) is in the shape of a "T" character; The horizontal part of the "T" shape of the T-shaped gate (2051) is located above the dielectric layer (2071), and the longitudinal part of the "T" shape of the T-shaped gate (2051) penetrates and extends to the surface of the P-well layer two (209).

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