Semiconductor structure and forming method thereof
By designing a discontinuous first semiconductor layer and isolation structure in the semiconductor structure, the risks of short circuits and leakage caused by the growth of germanium-silicon layers during the formation of PMOS transistors are solved, thereby improving the electrical performance and lifespan of the device.
Patent Information
- Application Number
- CN202511639179.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-10
- Publication Date
- 2026-02-13
AI Technical Summary
When forming a PMOS transistor, the height of the shallow trench isolation structure is lower than the top surface of the active region. This means that when selectively growing a germanium-silicon layer, the top surface and sidewalls of the active region are simultaneously exposed in the epitaxial reaction cavity, which may lead to short circuits or leakage risks in the semiconductor device.
In the design of the semiconductor structure, the first part and the second part of the first semiconductor layer are discontinuous, with only the gate structure connected to the first part. The first semiconductor layer is formed by selective epitaxy, covering different parts of the top surface and sidewalls of the active region, and forming an isolation structure between the active regions to avoid current paths between adjacent transistors.
It effectively improves the problems of short circuits and leakage between devices, enhances the electrical performance and service life of semiconductor products, and reduces the risk of short circuits and leakage between devices.
Smart Images
Figure CN121531775A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] In semiconductor manufacturing processes, when forming PMOS transistors, in order to improve the hole mobility of PMOS transistors, a germanium-silicon layer is usually selectively epitaxially grown on the top surface of the active region to generate compressive stress and improve the hole mobility of PMOS transistors.
[0003] However, during the formation of shallow trench isolation structures, the height of some shallow trench isolation structures is lower than the top surface of the active region. This results in the top surface and sidewalls of the active region being exposed in the epitaxial reaction cavity during selective epitaxial growth of germanium-silicon layers. The germanium-silicon layers grow not only on the top surface of the active region but also on the sidewalls of the active region, which may lead to short circuits or leakage risks in semiconductor devices. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor structure and its formation method to address the problems existing in the prior art.
[0005] To achieve the above objectives, this application provides a semiconductor structure, comprising:
[0006] The substrate includes a plurality of spaced-apart active regions and an isolation structure disposed between the active regions;
[0007] The first semiconductor layer includes a first portion that is in direct contact with the top surface of the active region and a second portion that is in direct contact with the sidewall of the active region.
[0008] A gate structure is located on the active region and covers the top surface of the first semiconductor layer;
[0009] A contact plug passes through the first semiconductor layer and connects to the substrate;
[0010] Wherein, the first portion of the first semiconductor layer is discontinuous with the second portion.
[0011] Optionally, the semiconductor structure also includes:
[0012] A second semiconductor layer covers the first portion and the second portion of the first semiconductor layer, and the second semiconductor layer is in direct contact with the active region.
[0013] Optionally, the second semiconductor layer is in direct contact with the top surface of the active region not covered by the first portion, and the second semiconductor layer is in direct contact with a portion of the sidewall of the active region not covered by the second portion.
[0014] Optionally, the semiconductor structure also includes:
[0015] A gate dielectric layer is located between the gate structure and the second semiconductor layer;
[0016] The gate structure includes a gate stack layer and a gate cap layer sequentially stacked on the active region;
[0017] The gate dielectric layer is in direct contact with the bottom surface of the gate stack layer and the top surface of the second semiconductor layer.
[0018] Optionally, the gate dielectric layer is in direct contact with the isolation structure.
[0019] On the other hand, this application provides a method for forming a semiconductor structure, including:
[0020] An initial substrate is provided, the initial substrate including an isolation trench that divides the initial substrate into a plurality of spaced active regions;
[0021] An isolation structure is formed in the isolation trench, and an isolation section is also formed, the isolation section covering part of the top surface and sidewall of the active area;
[0022] A first semiconductor layer is epitaxially formed on the surface exposed in the active region. The first semiconductor layer includes a first portion that is in direct contact with the top surface of the active region and a second portion that is in direct contact with the sidewall of the active region. The first portion and the second portion are discontinuous.
[0023] A gate structure is formed on the active region, and the gate structure covers the top surface of the first semiconductor layer;
[0024] A contact plug is formed, which passes through the first semiconductor layer and connects to the substrate.
[0025] Optionally, the process of forming an isolation structure and an isolation section in the isolation trench includes:
[0026] A first isolation layer is deposited to cover the walls of the isolation trench and the top surface of the active region; the deposition process of the first isolation layer is controlled so that the deposition rate at the corner of the isolation trench is greater than the deposition rate in other areas, and the first isolation layer forms a protrusion at the corner;
[0027] The first isolation layer is etched back to expose a portion of the top surface of the active region to form the isolation structure, while the protrusion is etched into the isolation portion that is separated from the isolation structure.
[0028] Optionally, after forming the first semiconductor layer, the method further includes:
[0029] The isolation portion is etched away to expose the active region covered by the isolation portion.
[0030] Optionally, after forming the first semiconductor layer, the method further includes:
[0031] A second semiconductor layer is formed, covering the first portion and the second portion of the first semiconductor layer, and the active region between the first portion and the second portion.
[0032] Optionally, the second semiconductor layer is in direct contact with the top surface of the active region not covered by the first portion, and the second semiconductor layer is in direct contact with a portion of the sidewall of the active region not covered by the second portion.
[0033] Optionally, before forming the gate structure on the active region, the process includes:
[0034] A gate dielectric layer is formed on the second semiconductor layer; the gate structure is formed on the gate dielectric layer.
[0035] Optionally, forming a gate structure on the active region includes:
[0036] A gate stack layer and a gate cap layer are sequentially formed on the gate dielectric layer;
[0037] The gate cap layer and the gate stack layer are etched to form the gate structure; the gate dielectric layer directly contacts the bottom surface of the gate stack layer and the top surface of the second semiconductor layer.
[0038] The semiconductor structure and its formation method disclosed in this application include a first semiconductor layer comprising two discontinuous parts. The first part covers the top surface of the active region and is in direct contact with the top surface of the active region. The second part covers a portion of the active region protruding from the sidewall of the isolation structure, and the first part and the second part are not connected. The gate structure of the transistor is only connected to the first part of the first semiconductor layer. Since the first part and the second part are discontinuous, even if the spacing between the active regions is very small and the second part of the sidewall of the adjacent active regions is very close or even partially connected, a current path cannot be formed between two adjacent transistors. This effectively improves the problems of short circuits and leakage between devices and can improve the electrical performance and operating life of semiconductor products. Attached Figure Description
[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0040] Figure 1 This is a planar schematic diagram of a semiconductor structure provided in one embodiment;
[0041] Figure 2 for Figure 1 Cross-sectional view along line a-a';
[0042] Figure 3 for Figure 1 Cross-sectional view along line b-b';
[0043] Figure 4 This is a process flow diagram of a method for forming a semiconductor structure provided in one embodiment;
[0044] Figure 5 As provided in one embodiment, after the initial substrate has been formed with isolation trenches along... Figure 1 Cross-sectional view of line a-a' in the middle;
[0045] Figure 6 As provided in one embodiment, after forming the first isolation layer along Figure 1 Cross-sectional view of line a-a' in the middle;
[0046] Figure 7 In one embodiment, after forming the second and third isolation layers, along... Figure 1 Cross-sectional view of line a-a' in the middle;
[0047] Figure 8 In one embodiment, the third isolation layer and the second isolation layer are etched back along... Figure 1 Cross-sectional view of line a-a' in the middle;
[0048] Figure 9 As provided in one embodiment, after forming the isolation structure and isolation portion, along Figure 1 Cross-sectional view of line a-a' in the middle;
[0049] Figure 10 In one embodiment, after forming the first semiconductor layer, along... Figure 1 Cross-sectional view of line a-a' in the middle;
[0050] Figure 11 As provided in one embodiment, after forming the second semiconductor layer along Figure 1 Cross-sectional view of line a-a' in the middle;
[0051] Figure 12 In one embodiment, after forming the gate stack layer and the gate cap layer, along... Figure 1 Cross-sectional view of line a-a' in the middle.
[0052] Explanation of reference numerals in the attached figures:
[0053] 10. Substrate; 10a. Initial substrate; 101. Isolation trench; 21. First semiconductor layer; 211. First portion; 212. Second portion; 22. Second semiconductor layer; 30. Gate structure; 31. Gate dielectric layer; 32. Gate stack layer; 321. Barrier layer; 322. Gate conductive layer; 33. Gate capping layer; 34. Gate sidewall; 40. Contact plug; 500. Protrusion; 51. First isolation layer; 52. Second isolation layer; 53. Third isolation layer;
[0054] AA, active region; STI, isolation structure; IS, isolation section; D1, first direction; D2, second direction. Detailed Implementation
[0055] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0057] According to an exemplary embodiment, this embodiment provides a semiconductor structure, with reference to... Figure 1 , Figure 2 , Figure 3 As shown, the semiconductor structure includes a substrate 10, a first semiconductor layer 21, a gate structure 30, and a contact plug 40. The substrate 10 includes multiple spaced active regions AA and an isolation structure STI disposed between the active regions AA. The first semiconductor layer 21 includes a first portion 211 that directly contacts the top surface of the active regions AA, and a second portion 212 that directly contacts the sidewalls of the active regions AA. The gate structure 30 is located on the active regions AA and covers the top surface of the first semiconductor layer 21. The contact plug 40 passes through the first semiconductor layer 21 and connects to the substrate 10. The first portion 211 and the second portion 212 of the first semiconductor layer 21 are discontinuous.
[0058] The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, or a fully depleted silicon-on-insulator substrate, and is not limited thereto. The substrate 10 includes a plurality of spaced-apart active regions AA and an isolation structure STI disposed between the active regions AA. Adjacent active regions AA are separated by the isolation structures STI. The top surface of the isolation structure STI is lower than the top surface of the active regions AA; that is, the top surface of the active regions AA and the portion of the sidewalls connected to the top surface protrude from the isolation structure STI. The active regions AA can extend along a first direction D1 and be spaced apart along a second direction D2, where the second direction D2 is perpendicular to the first direction D1. The length of the active regions AA along the first direction D1 is greater than the length along the second direction D2.
[0059] The substrate 10 can be divided into a storage area and a peripheral area surrounding the storage area. In this embodiment, the active area AA can be the peripheral active area located in the peripheral area.
[0060] Among them, reference Figures 5-9 An isolation trench 101 is formed on the substrate 10, and an isolation structure STI is disposed in the isolation trench 101. The isolation structure STI may include a single layer or multiple layers of insulating dielectric film. For example, the isolation structure STI may include a first isolation layer 51, a second isolation layer 52, and a third isolation layer 53 that sequentially cover the trench walls of the isolation trench 101. The first isolation layer 51 conformally covers the trench walls of the isolation trench 101, the second isolation layer 52 conformally covers the inner sidewall of the first isolation layer 51, and the third isolation layer 53 covers the inner sidewall of the second isolation layer 52 and fills the unfilled portion of the isolation trench 101 inside the second isolation layer 52. The second isolation layer 52 is made of a different material than the first isolation layer 51, and the third isolation layer 53 is made of a different material than the second isolation layer 52. For example, the first isolation layer 51 may be made of silicon oxide, the second isolation layer 52 may be made of silicon nitride, and the third isolation layer 53 may be made of silicon oxide.
[0061] It is understood that the top surface of the isolation structure STI being lower than the top surface of the active region AA means that the top surface of any layer of the isolation structure STI is lower than the top surface of the active region AA. However, the top surface height of each insulating layer in the isolation structure STI is not limited to being completely consistent. For example, due to the influence of the etching ratio, the top surface of the second isolation layer 52 can be higher than the top surfaces of the first isolation layer 51 and the third isolation layer 53, but lower than the top surface of the active region AA.
[0062] Reference Figure 1 , Figure 2 , Figure 3As shown, the first semiconductor layer 21 can be epitaxially formed on the exposed surface of the active region AA. However, the first semiconductor layer 21 includes two discontinuous parts. The first part 211 covers the top surface of the active region AA and is in direct contact with it. The second part 212 covers a portion of the sidewall of the active region AA that protrudes from the isolation structure STI. The first part 211 and the second part 212 are not connected, and there is a sidewall of the active region AA that is not covered by the first semiconductor layer 21 between the first part 211 and the second part 212. In this embodiment, the first semiconductor layer 21 can be a germanium-silicon layer.
[0063] Reference Figure 1 , Figure 2 , Figure 3 As shown, the gate structure 30 is located on the active region AA and covers the top surface of the first semiconductor layer 21, wherein the gate structure 30 covers a portion of the top surface of the first semiconductor layer 21. The projection of the gate structure 30 onto the substrate 10 overlaps with the middle region of the active region AA, and the two ends of the active region AA are not covered by the projection of the gate structure 30. The two ends of the active region AA are respectively formed as the source and drain of a transistor. The gate structure 30 may include a single layer or multiple layers stacked together, wherein the gate structure 30 includes at least one conductive film layer.
[0064] Reference Figure 1 , Figure 2 , Figure 3 As shown, two contact plugs 40 are disposed on the active region AA along the first direction D1, respectively, on both sides of the gate structure 30. The contact plugs 40 pass through the first semiconductor layer 21 and connect to the substrate 10, respectively connecting to the source and drain of the transistor to electrically lead out the source or drain of the transistor for connection to other devices. The material of the contact plugs 40 may include metal silicides, such as titanium silicides. Metal silicides have lower contact resistance with the semiconductor material of the active region AA, allowing the contact plugs 40 to form good ohmic contact with the source or drain. Alternatively, the material of the contact plugs 40 may include conductive metals, such as tungsten or titanium.
[0065] In this embodiment, the semiconductor structure has a first semiconductor layer 21 comprising two discontinuous parts. The first part 211 covers the top surface of the active region AA and is in direct contact with the top surface of the active region AA. The second part 212 covers the active region AA and protrudes from the sidewall of the isolation structure STI. The first part 211 and the second part 212 are not connected. The gate structure 30 of the transistor is only connected to the first part 211 of the first semiconductor layer 21. Since the first part 211 and the second part 212 are discontinuous, even if the spacing between the active regions AA is very small and the second part 212 of the sidewall of the adjacent active regions AA is very close or even partially connected, a current path cannot be formed between two adjacent transistors. This effectively improves the problems of short circuits and leakage between devices and can improve the electrical performance and service life of semiconductor products.
[0066] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 As shown, the semiconductor structure also includes a second semiconductor layer 22, which covers the first portion 211 and the second portion 212 of the first semiconductor layer 21. The second semiconductor layer 22 is in direct contact with the active region AA. The material of the second semiconductor layer 22 may include semiconductor materials, such as silicon. The second semiconductor layer 22 covering the first portion 211 and the second portion 212 of the first semiconductor layer 21 can further improve the isolation effect between the first portion 211 and the second portion 212, reduce the risk of short circuit between the first portion 211 and the second portion 212, thereby reducing the probability of short circuits and leakage between devices and improving the electrical performance and service life of semiconductor products.
[0067] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 As shown, the second semiconductor layer 22 is in direct contact with the top surface of the active region AA not covered by the first portion 211, and the second semiconductor layer 22 is in direct contact with a portion of the sidewall of the active region AA not covered by the second portion 212. In this way, the second semiconductor layer 22 continuously covers the first portion 211, the exposed top surface and sidewall of the active region AA between the first portion 211 and the second portion 212, and the second portion 212, further improving the isolation effect between the first portion 211 and the second portion 212, and mitigating the problems of short circuits and leakage between devices.
[0068] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3As shown, the first portion 211 and the second portion 212 of the first semiconductor layer 21 are disconnected at the junction (corner) of the top surface and sidewall of the active region AA. The first portion 211 covers part of the top surface of the active region AA and exposes a portion of the top surface of the active region AA near its edge; the second portion 212 covers the lower region of the sidewall of the active region AA and is adjacent to the isolation structure STI. Along the height direction of the active region AA, the upper edge of the second portion 212 is lower than the top surface of the active region AA, exposing the upper region of the sidewall of the active region AA. The second semiconductor layer 22 covers the first portion 211 and the second portion 212 of the first semiconductor layer 21, as well as the exposed corner surface of the active region AA.
[0069] It is understandable that electric fields tend to accumulate at corners, and strong electric fields can exacerbate the tunneling effect of charge carriers, leading to increased gate-to-drain leakage current and potentially causing problems such as hot carrier injection, thereby compromising the long-term stability of the device. In this embodiment, the first portion 211 and the second portion 212 of the first semiconductor layer 21 are disconnected at the corner of the active region AA, disrupting the electric field distribution at the corner of the active region AA, reducing the leakage current driven by the concentrated electric field, and simultaneously, by alleviating the electric field stress, effectively suppressing the hot carrier effect and extending the device lifetime.
[0070] In some embodiments, the corners of the active region AA are rounded. In semiconductor devices, sharp corners tend to concentrate the electric field, exacerbating gate-drain leakage and causing reliability issues. In this embodiment, designing the corners of the active region AA as rounded corners can smooth the electric field distribution, reduce leakage current, and improve the long-term operational stability of the device.
[0071] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 As shown, the semiconductor structure also includes a gate dielectric layer 31, which is located between the gate structure 30 and the second semiconductor layer 22. The gate structure 30 includes a gate stack layer 32 and a gate cap layer 33 sequentially stacked on the active region AA; wherein, the gate dielectric layer 31 directly contacts the bottom surface of the gate stack layer 32 and the top surface of the second semiconductor layer 22.
[0072] The gate dielectric layer 31 may be formed and / or comprise, for example, silicon oxide, silicon oxynitride, or a combination thereof, using an insulating material with a low dielectric constant (k value). Alternatively, the gate dielectric layer 31 may also be formed using an insulating material with a high dielectric constant (k value), such as a metal oxide (hafnium dioxide, zirconium oxide, hafnium zirconium oxide, etc.).
[0073] It can be understood that in the semiconductor structure of this embodiment, the second semiconductor layer 22 and the gate dielectric layer 31 are stacked between the first part 211 and the gate structure 30. The threshold voltage of the transistor can be flexibly adjusted by adjusting the thickness and material of the second semiconductor layer 22 and the gate dielectric layer 31 to meet the working requirements of different circuits.
[0074] The transistor is a PMOS transistor; the barrier layer 321 can be a metal nitride layer, which is used to block the diffusion of the material in the upper metal layer. For example, the material of the barrier layer 321 may include titanium nitride (TiN), titanium carbonitride (TiCN), tantalum nitride (TaN), tantalum carbonitride (TaCN), or a combination thereof.
[0075] In this embodiment, the gate stack layer 32 includes a barrier layer 321 and a gate conductive layer 322 sequentially stacked on the gate dielectric layer 31. The gate conductive layer 322 is made of a metal, such as at least one of tungsten or tungsten nitride, titanium or titanium nitride. The gate cap layer 33 is made of an insulating material, such as silicon nitride.
[0076] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 As shown, the semiconductor structure also includes a gate sidewall 34, which covers the sidewalls of the gate dielectric layer 31, the gate stack layer 32, and the gate cap layer 33. The gate sidewall 34 is disposed on the second semiconductor layer 22, or on the isolation structure STI. The gate sidewall 34 may include a single layer or multiple layers of insulating film. The gate sidewall 34 may be formed and / or include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon carbonitride (SiOCN) film, air, and combinations thereof, but is not limited thereto.
[0077] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 As shown, along the first direction D1, the length of the active region AA is greater than the length of the gate structure 30, and along the first direction D1, the two ends of the active region AA are not covered by the gate structure 30. The gate structure 30 only covers the middle region of the active region AA to form the channel of the transistor. The regions at both ends of the active region AA that are not covered by the gate structure 30 form the source and drain of the transistor, respectively.
[0078] Along the second direction D2, the width of the active region AA is smaller than the width of the gate structure 30, and along the second direction D2, the two ends of the gate structure 30 extend laterally to form the active region AA, covering the top surface of the isolation structure STI on both sides.
[0079] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 As shown, the gate dielectric layer 31 is in direct contact with the isolation structure STI. Along the cross-section of the second direction D2, the gate dielectric layer 31 extends into the active region AA. The gate dielectric layer 31 is located between the top surface of the gate structure 30 and the isolation structure STI to ensure reliable electrical isolation between the gate structure 30 and the substrate 10 and other devices in the second direction D2.
[0080] According to an exemplary embodiment, this embodiment provides a method for forming a semiconductor structure, referring to... Figure 4 As shown, the method for forming a semiconductor structure includes the following steps:
[0081] Step S101: Provide an initial substrate 10a, the initial substrate 10a including an isolation trench 101, the isolation trench 101 dividing the initial substrate 10a into a plurality of spaced active regions AA.
[0082] Step S102: An isolation structure STI is formed in the isolation trench 101, and an isolation section IS is formed at the same time. The isolation section IS covers part of the top surface and sidewall of the active region AA.
[0083] Step S103: Epitaxially form a first semiconductor layer 21 on the exposed surface of the active region AA. The first semiconductor layer 21 includes a first portion 211 that is in direct contact with the top surface of the active region AA and a second portion 212 that is in direct contact with the sidewall of the active region AA. The first portion 211 and the second portion 212 are discontinuous.
[0084] Step S104: A gate structure 30 is formed on the active region AA, and the gate structure 30 covers the top surface of the first semiconductor layer 21.
[0085] Step S105: Form a contact plug 40, which passes through the first semiconductor layer 21 and connects to the substrate 10.
[0086] The semiconductor structure formation method of this embodiment forms an isolation portion IS covering part of the top surface and sidewalls of the active region AA while forming the isolation structure STI. The isolation portion IS defines the window for epitaxial growth of the first semiconductor layer 21. The first semiconductor layer 21 is formed by selective epitaxy. The first semiconductor layer includes a first portion 211 and a second portion 212 that are separately disposed. This improves the risk of short circuits and leakage caused by epitaxial growth of the epitaxial layer on the sidewalls of the active region AA. It eliminates the need for complex additional photolithography or etching steps, thereby improving the reliability and yield of the device.
[0087] The gate structure 30 of the transistor is only connected to the first part 211 of the first semiconductor layer 21. Since the first part 211 is not connected to the second part 212, even if the spacing between the active regions AA is very small and the second part 212 of the sidewalls of the adjacent active regions AA is very close or even partially connected, a current path cannot be formed between two adjacent transistors. This effectively improves the problem of short circuit and leakage between devices and can improve the electrical performance and service life of semiconductor products.
[0088] In step S101, refer to Figure 5 The initial substrate 10a can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, or a fully depleted silicon-on-insulator substrate, but is not limited to these.
[0089] An initial substrate 10a is patterned and etched to form an isolation trench 101, which divides the initial substrate 10a into a plurality of spaced semiconductor fins, i.e., active regions AA. The active regions AA extend along a first direction D1 and are spaced along a second direction D2 perpendicular to the first direction D1. The depth of the isolation trench 101 is less than the thickness of the initial substrate 10a.
[0090] In step S102, refer to Figures 5-9 An insulating medium is filled into the isolation trench 101, and the insulating medium is etched back to expose the top surface of the active region AA, so as to form an isolation structure STI in the isolation trench 101. By controlling the deposition of the insulating medium and the etching back process, an isolation portion IS covering part of the top surface and sidewalls of the active region AA is formed.
[0091] The isolation structure STI can include a single or multiple insulating dielectric film layers, and the isolation section IS can be formed by controlling the process parameters of the deposition and / or etch-back of one or more insulating dielectric film layers.
[0092] In some embodiments, step S102, which involves forming an isolation structure STI in the isolation trench 101 and simultaneously forming an isolation portion IS, includes:
[0093] Step S1021: Deposit the first isolation layer 51 to cover the trench wall of the isolation trench 101 and the top surface of the active area AA; control the deposition process of the first isolation layer 51 so that the deposition rate at the corner of the isolation trench 101 is greater than the deposition rate in other areas, and the first isolation layer 51 forms a protrusion 500 at the corner.
[0094] Step S1022: The first isolation layer 51 is etched back to expose part of the top surface of the active region AA to form the isolation structure STI, while the protrusion 500 is etched into an isolation portion IS that is separated from the isolation structure STI.
[0095] In this embodiment, refer to Figure 6During the deposition of the first isolation layer 51, deposition parameters such as temperature, pressure, gas ratio, and RF power are adjusted to provide deposition conditions that increase the deposition rate at corners. This ensures that the deposition rate of the insulating medium at the chamfer at the top of the active region AA is higher than the deposition rate on the top surface of the active region AA and the wall of the isolation trench 101, resulting in a local protrusion of the first isolation layer 51 at the top corner of the active region AA. The thickness of the protrusion 500 is greater than the thickness of the first isolation layer 51 located on the top surface of the active region AA and the thickness of the first isolation layer 51 covering the wall of the isolation trench 101.
[0096] Reference Figure 9 During the process of etching the first isolation layer 51, since the thickness of the protrusion 500 is greater than the thickness of the first isolation layer 51 located on the top surface of the active region AA and the trench wall of the isolation trench 101, after the first isolation layer 51 in the middle area of the top surface of the active region AA is etched away, there is an unetched first isolation layer 51 at the corner to form an isolation part IS. The isolation part IS covers the edge area of the top surface of the active region AA and part of the sidewall of the upper area of the active region AA.
[0097] The isolation structure STI formed in this embodiment includes at least a first isolation layer 51, or the isolation structure STI may also include a multilayer insulating dielectric film layer stacked with the first isolation layer 51.
[0098] For example, refer to Figure 6 , Figure 7 A first isolation layer 51 is deposited to cover the walls of the isolation trench 101 and the top surface of the active region AA. After forming a protrusion 500 at the corner of the active region AA, a second isolation layer 52 is deposited to conformally cover the first isolation layer 51. Then, a third isolation layer 53 is deposited to cover the second isolation layer 52 and fill the isolation trench 101. (Refer to...) Figure 8 Then, the third isolation layer 53 and the second isolation layer 52 are etched back sequentially, and the top surfaces of the third isolation layer 53 and the second isolation layer 52 are etched down to below the top surface of the active region AA. Then, refer to Figure 9 The first isolation layer 51 is then etched back to expose the top surface of the active region AA that is not covered by the isolation section IS, thus exposing the sidewall of the active region AA between the first isolation layer 51 and the isolation section IS on the trench wall of the isolation trench 101. The first isolation layer 51, the second isolation layer 52, and the third isolation layer 53, which are connected sequentially within the isolation trench 101, together form the isolation structure STI, and the top surface of the isolation structure STI is lower than the top surface of the active region AA.
[0099] In this embodiment, the second isolation layer 52 is made of a different material than the first isolation layer 51, and the third isolation layer 53 is made of a different material than the second isolation layer 52. For example, the material of the first isolation layer 51 may include silicon oxide, the material of the second isolation layer 52 may include silicon nitride, and the material of the third isolation layer 53 may include silicon oxide.
[0100] It is understood that the top surface of the isolation structure STI being lower than the top surface of the active region AA means that the top surface of any layer of the isolation structure STI is lower than the top surface of the active region AA. However, the top surface height of each insulating layer in the isolation structure STI is not limited to being completely consistent. For example, due to the influence of the etching ratio, the top surface of the second isolation layer 52 can be higher than the top surfaces of the first isolation layer 51 and the third isolation layer 53, but lower than the top surface of the active region AA.
[0101] For example, a first isolation layer 51 can be formed by chemical vapor deposition (CVD).
[0102] For example, an atomic layer deposition (ALD) process can be used to deposit a second isolation layer 52.
[0103] For example, a third isolation layer 53 can be formed by chemical vapor deposition.
[0104] In step S103, refer to Figure 10 Using the isolation region IS as a mask, selective epitaxial growth is performed on the exposed surface of the active region AA to form a first semiconductor layer 21. The first semiconductor layer 21 includes a first portion 211 grown on the top surface of the active region AA in direct contact with the top surface of the active region AA, and a second portion 212 grown below the isolation region IS, with the second portion 212 in direct contact with the sidewall of the active region AA below the isolation region IS. The presence of the isolation region IS makes the first portion 211 and the second portion 212 of the first semiconductor layer 21 discontinuous, thus preventing potential electrical bridging between adjacent devices from the source. Simultaneously, during the selective epitaxy process, the first portion 211 on the top surface of the active region AA and the second portion 212 on the sidewall of the active region AA grow synchronously, increasing the process window, reducing process difficulty, and helping to save process costs.
[0105] In some embodiments, after step S103 forms the first semiconductor layer 21, the following steps are also performed:
[0106] Step S103-1: Etch away the isolation section IS to expose the active region AA covered by the isolation section IS.
[0107] In this embodiment, refer to Figure 10The isolation section IS can be etched away using either a dry or wet process to expose the surface of the active region AA that was originally covered by the isolation section IS.
[0108] In some embodiments, after step S103 forms the first semiconductor layer 21, the following steps are performed:
[0109] Step S103-2: Form a second semiconductor layer 22, covering the first portion 211 and the second portion 212 of the first semiconductor layer 21, and the active region AA between the first portion 211 and the second portion 212.
[0110] In this embodiment, step S103-2 is executed after step S103-1, referring to... Figure 11 A second semiconductor layer 22 is epitaxially grown on the first semiconductor layer 21. By controlling the epitaxial growth time, the second semiconductor layer 22 on the first part 211 is connected to the second semiconductor layer 22 on the second part 212, and the second semiconductor layer 22 is a continuous layer.
[0111] The second semiconductor layer 22 is in direct contact with the top surface of the active region AA that is not covered by the first portion 211, and the second semiconductor layer 22 is in direct contact with a portion of the sidewall of the active region AA that is not covered by the second portion 212.
[0112] The material of the second semiconductor layer 22 may include semiconductor materials, such as silicon. The second semiconductor layer 22 covers the first part 211 and the second part 212 of the first semiconductor layer 21, which can further improve the isolation effect between the first part 211 and the second part 212, reduce the risk of short circuit between the first part 211 and the second part 212, thereby reducing the probability of short circuit and leakage between devices and improving the electrical performance and service life of semiconductor products.
[0113] In some embodiments, before forming the gate structure 30 on the active region AA in step S104, the following steps are also performed:
[0114] Step S104-1: Form a gate dielectric layer 31 on the second semiconductor layer 22; form a gate structure 30 on the gate dielectric layer 31.
[0115] In this embodiment, refer to Figure 12 The gate dielectric layer 31 can be formed by atomic layer deposition or chemical vapor deposition, and the gate dielectric layer 31 covers the second semiconductor layer 22 and the top surface of the isolation structure STI.
[0116] The gate dielectric layer 31 may be formed and / or comprise, for example, silicon oxide, silicon oxynitride, or a combination thereof, of an insulating material with a low dielectric constant (k value). Alternatively, the gate dielectric layer 31 may also be formed of an insulating material with a high dielectric constant (k value), such as a metal oxide (hafnium dioxide, zirconium oxide, hafnium zirconium oxide, etc.).
[0117] It can be understood that in the semiconductor structure of this embodiment, the second semiconductor layer 22 and the gate dielectric layer 31 are stacked between the first portion 211 and the gate structure 30, which is equivalent to the transistor including two gate insulating dielectric layers. The threshold voltage of the transistor can be flexibly adjusted by adjusting the thickness and material of the second semiconductor layer 22 and the gate dielectric layer 31 to meet the operating requirements of different circuits.
[0118] In some embodiments, step S104, forming a gate structure 30 on the active region AA, includes:
[0119] Step S1041: A gate stack layer 32 and a gate cap layer 33 are sequentially formed on the gate dielectric layer 31.
[0120] In this embodiment, the gate stack layer 32 includes a barrier layer 321 and a gate conductive layer 322 sequentially stacked on the gate dielectric layer 31.
[0121] Reference Figure 12 A barrier layer 321, a gate conductive layer 322, and a gate capping layer 33 can be sequentially deposited on the gate dielectric layer 31.
[0122] The transistor is a PMOS transistor; the barrier layer 321 is made of metal nitride. For example, the barrier layer 321 may be made of titanium nitride (TiN), titanium carbonitride (TiCN), tantalum nitride (TaN), tantalum carbonitride (TaCN), or a combination thereof.
[0123] For example, the material of the gate conductive layer 322 is a metal, such as at least one of tungsten or tungsten nitride, titanium or titanium nitride.
[0124] For example, the material of the gate cap 33 includes an insulating material, such as silicon nitride.
[0125] For example, one or more of atomic layer deposition, chemical vapor deposition, and physical vapor deposition (PVD) can be used to form the barrier layer 321, the gate conductive layer 322, and the gate capping layer 33.
[0126] Step S1042: Etch the gate cap layer 33 and the gate stack layer 32 to form the gate structure 30; the gate dielectric layer 31 directly contacts the bottom surface of the gate stack layer 32 and the top surface of the second semiconductor layer 22.
[0127] In this embodiment, refer to Figure 1 , Figure 2 , Figure 3 A mask layer is formed on the top surface of the gate capping layer 33. The gate capping layer 33 and the gate stacking layer 32 are etched layer by layer according to the mask layer to form an independently set gate structure 30. Then, the gate dielectric layer 31 exposed by the gate structure 30 is etched away. The gate dielectric layer 31 directly contacts the bottom surface of the gate stacking layer 32 and the top surface of the second semiconductor layer 22.
[0128] In this embodiment, along the first direction D1, the length of the active region AA is greater than the length of the gate structure 30. The two ends of the active region AA are not covered by the gate structure 30, and the gate structure 30 only covers the middle region of the active region AA to form the channel of the transistor. The regions at both ends of the active region AA that are not covered by the gate structure 30 are used to form the source and drain of the transistor, respectively.
[0129] Along the second direction D2, the width of the active region AA is smaller than the width of the gate structure 30. The active regions AA extend laterally from both ends of the gate structure 30 and cover the top surfaces of the isolation structures STI on both sides. Along the cross section of the second direction D2, the gate dielectric layer 31 extends out of the active region AA. The gate dielectric layer 31 is located between the gate structure 30 and the top surfaces of the isolation structures STI to ensure reliable electrical isolation between the gate structure 30 and the substrate 10 and other devices in the second direction D2.
[0130] In this embodiment, after forming the gate structure 30, the following steps are performed: forming a gate sidewall 34, which covers the sidewalls of the gate dielectric layer 31, the gate stack layer 32, and the gate cap layer 33. The gate sidewall 34 may include a single layer or multiple layers of insulating film. The gate sidewall 34 may be formed and / or include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon carbonitride (SiOCN) film, air, and combinations thereof, but is not limited thereto.
[0131] In this embodiment, a single or multiple insulating film layer is deposited to cover the gate structure 30, the top surface of the isolation structure STI between the gate structures 30, and the second semiconductor layer 22 not covered by the gate structure 30. Then, the insulating film layer on the top surface of the isolation structure STI is etched back to remove it and expose the top surface of the gate capping layer 33. The remaining insulating film layer is etched to form the gate sidewall 34.
[0132] In step S105, a dielectric layer (not shown in the figure) can be deposited first to fill the space between adjacent gate structures 30. Then, the dielectric layer, the second semiconductor layer 22, and the first portion 211 are etched to form contact holes on both sides of the gate structure 30 along the first direction D1, with the contact holes extending to the active region AA. Then, conductive material is deposited into the contact holes to form contact plugs 40.
[0133] In this embodiment, two contact plugs 40 are formed on the active region AA. Along the first direction D1, the two contact plugs 40 are respectively disposed on both sides of the gate structure 30. The contact plugs 40 pass through the first semiconductor layer 21 and connect to the substrate 10, respectively connecting to the source and drain of the transistor, so as to electrically lead out the source or drain of the transistor and connect it to other devices. The material of the contact plugs 40 may include metal silicides, such as titanium silicides. Metal silicides have lower contact resistance with the semiconductor material of the active region AA, allowing the contact plugs 40 to form good ohmic contacts with the source or drain. Alternatively, the material of the contact plugs 40 may include conductive metals, such as tungsten or titanium.
[0134] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0135] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes a plurality of spaced-apart active regions and an isolation structure disposed between the active regions; The first semiconductor layer includes a first portion that is in direct contact with the top surface of the active region and a second portion that is in direct contact with the sidewall of the active region. A gate structure is located on the active region and covers the top surface of the first semiconductor layer; A contact plug passes through the first semiconductor layer and connects to the substrate; Wherein, the first portion of the first semiconductor layer is discontinuous with the second portion.
2. The semiconductor structure according to claim 1, characterized in that, Also includes: A second semiconductor layer covers the first portion and the second portion of the first semiconductor layer, and the second semiconductor layer is in direct contact with the active region.
3. The semiconductor structure according to claim 2, characterized in that, The second semiconductor layer is in direct contact with the top surface of the active region not covered by the first portion, and the second semiconductor layer is in direct contact with a portion of the sidewall of the active region not covered by the second portion.
4. The semiconductor structure according to claim 2, characterized in that, Also includes: A gate dielectric layer is located between the gate structure and the second semiconductor layer; The gate structure includes a gate stack layer and a gate cap layer sequentially stacked on the active region; The gate dielectric layer is in direct contact with the bottom surface of the gate stack layer and the top surface of the second semiconductor layer.
5. The semiconductor structure according to claim 4, characterized in that, The gate dielectric layer is in direct contact with the isolation structure.
6. A method for forming a semiconductor structure, characterized in that, include: An initial substrate is provided, the initial substrate including an isolation trench that divides the initial substrate into a plurality of spaced active regions; An isolation structure is formed in the isolation trench, and an isolation section is also formed, the isolation section covering part of the top surface and sidewall of the active area; A first semiconductor layer is epitaxially formed on the surface exposed in the active region. The first semiconductor layer includes a first portion that is in direct contact with the top surface of the active region and a second portion that is in direct contact with the sidewall of the active region. The first portion and the second portion are discontinuous. A gate structure is formed on the active region, and the gate structure covers the top surface of the first semiconductor layer; A contact plug is formed, which passes through the first semiconductor layer and connects to the substrate.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, The process of forming an isolation structure and an isolation section in the isolation trench includes: A first isolation layer is deposited to cover the walls of the isolation trench and the top surface of the active region; the deposition process of the first isolation layer is controlled so that the deposition rate at the corner of the isolation trench is greater than the deposition rate in other areas, and the first isolation layer forms a protrusion at the corner; The first isolation layer is etched back to expose a portion of the top surface of the active region to form the isolation structure, while the protrusion is etched into the isolation portion that is separated from the isolation structure.
8. The method for forming a semiconductor structure according to claim 6, characterized in that, After forming the first semiconductor layer, the process further includes: The isolation portion is etched away to expose the active region covered by the isolation portion.
9. The method for forming a semiconductor structure according to claim 8, characterized in that, After forming the first semiconductor layer, the process further includes: A second semiconductor layer is formed, covering the first portion and the second portion of the first semiconductor layer, and the active region between the first portion and the second portion.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The second semiconductor layer is in direct contact with the top surface of the active region not covered by the first portion, and the second semiconductor layer is in direct contact with a portion of the sidewall of the active region not covered by the second portion.
11. The method for forming a semiconductor structure according to claim 9, characterized in that, Before forming the gate structure on the active region, the process includes: A gate dielectric layer is formed on the second semiconductor layer; the gate structure is formed on the gate dielectric layer.
12. The method for forming a semiconductor structure according to claim 11, characterized in that, The formation of the gate structure on the active region includes: A gate stack layer and a gate cap layer are sequentially formed on the gate dielectric layer; The gate cap layer and the gate stack layer are etched to form the gate structure; the gate dielectric layer directly contacts the bottom surface of the gate stack layer and the top surface of the second semiconductor layer.