Semiconductor device

Abstract

A semiconductor device includes: active patterns spaced apart from each other in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source / drain pattern on the active pattern, in which the lower channel pattern and the lower source / drain pattern are alternately arranged in the second direction; an upper channel pattern and an upper source / drain pattern, the upper channel pattern on the lower channel pattern, the upper source / drain pattern on the lower source / drain pattern; a gate pattern on the active pattern and on the lower channel pattern and the upper channel pattern; and an intra-gate spacer between the gate pattern and the lower source / drain pattern and the upper source / drain pattern.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0107424, filed on August 12, 2024, in the Korean Intellectual Property Office, the contents of which are hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor device. BACKGROUND

[0003] Semiconductors are materials that belong to an intermediate region between conductors and insulators, and refer to materials that conduct electricity under certain conditions. Various semiconductor devices (e.g., memory devices) can be manufactured using these semiconductor materials. Such semiconductor devices can be used in various electronic devices.

[0004] As the electronic industry develops, requirements for characteristics of semiconductor devices are increasing. For example, there are increasing requirements for high reliability, high speed, and / or multi-functionality in semiconductor devices. To meet these requirements for characteristics, structures within semiconductor devices are becoming more and more complex and integrated. SUMMARY

[0005] In general, the present disclosure relates to a semiconductor device.

[0006] According to some embodiments, the present disclosure relates to a semiconductor device that is capable of forming a lower source / drain contact and a lower gate contact by self-alignment without an additional structure such as a spacer, preventing a gate pattern from being damaged when forming a lower source / drain contact, controlling lateral growth of a lower source / drain pattern and an upper source / drain pattern, preventing a lower surface of a gate pattern from being highly recessed to reduce a parasitic capacitance, simplifying a cutting process of a gate pattern, minimizing a change in a threshold voltage (V t ) by protecting an escape work metal of a gate pattern, and / or controlling and minimizing a change in a threshold voltage (V t ) between a lower gate structure and an upper gate structure of a gate pattern. t

[0007] ​According to some embodiments, the present disclosure relates to a semiconductor device including: active patterns arranged spaced apart in a first direction and extending in a second direction different from the first direction; lower channel patterns and lower source / drain patterns located on the active patterns and arranged alternately in the second direction; upper channel patterns and upper source / drain patterns, the upper channel patterns being located on the lower channel patterns, the upper source / drain patterns being located on the lower source / drain patterns; gate patterns located on the active patterns and located on the lower channel patterns and the upper channel patterns; and gate-in intra-spacers located between the gate patterns and the lower source / drain patterns and the upper source / drain patterns; wherein the gate-in intra-spacers have a superposed portion superposed on the upper channel patterns and the lower channel patterns in a third direction perpendicular to the first direction and the second direction, and a non-superposed portion not superposed on the upper channel patterns and the lower channel patterns in the third direction.

[0008] According to some embodiments, the present disclosure relates to a semiconductor device including: active patterns arranged spaced apart in a first direction and extending in a second direction different from the first direction; lower channel patterns and lower source / drain patterns located on the active patterns and arranged alternately in the second direction; upper channel patterns and upper source / drain patterns, the upper channel patterns being located on the lower channel patterns, the upper source / drain patterns being located on the lower source / drain patterns; gate patterns located on the active patterns and located on the lower channel patterns and the upper channel patterns; lower source / drain contacts located below the lower source / drain patterns and connected to the lower source / drain patterns; and a separation wall pattern provided spaced apart in the first direction, extending across the gate patterns in the second direction, and provided alternately with the active patterns in the first direction; wherein the separation wall pattern extends from a level lower than an upper surface of the lower source / drain contacts to a level lower than an upper surface of the gate patterns in a third direction perpendicular to the first direction and the second direction.

[0009] According to some embodiments, the present disclosure relates to a semiconductor device including: active patterns arranged apart in a first direction and extending in a second direction different from the first direction; lower channel patterns and lower source / drain patterns located on the active patterns and alternately arranged in the second direction; upper channel patterns and upper source / drain patterns, the upper channel patterns being located on the lower channel patterns, the upper source / drain patterns being located on the lower source / drain patterns; gate patterns located on the active patterns and on the lower channel patterns and the upper channel patterns; and gate-in-spacers located between the gate patterns and the lower source / drain patterns and the upper source / drain patterns and having a superposed portion superposed on the upper channel patterns and the lower channel patterns in a third direction perpendicular to the first direction and the second direction, and a non-superposed portion not superposed on the upper channel patterns and the lower channel patterns in the third direction; and a separation wall pattern arranged apart in the first direction, extending in the second direction, and alternately arranged with the active patterns in the first direction; wherein two side surfaces of the lower source / drain patterns and the upper source / drain patterns in the first direction are surrounded by the separation wall pattern, and two side surfaces of the lower source / drain patterns and the upper source / drain patterns in the second direction are surrounded by the superposed portion and the non-superposed portion of the gate-in-spacers.

[0010] According to some embodiments, the present disclosure relates to a semiconductor device that can form lower source / drain contacts and lower gate contacts by self-alignment without an additional structure such as a placeholder, can prevent a gate pattern from being damaged when forming lower source / drain contacts, can control lateral growth of lower source / drain patterns and upper source / drain patterns, can reduce parasitic capacitance by preventing a lower surface of a gate pattern from being highly recessed, can simplify a cutting process of a gate pattern, can minimize variation in threshold voltage (V t ) by protecting a work function metal of a gate pattern, and / or can control and minimize variation in threshold voltage (V t ) between a lower gate structure and an upper gate structure of a gate pattern. t BRIEF DESCRIPTION OF DRAWINGS

[0011] The example embodiments will become more fully understood from the detailed description given herein below, and the accompanying drawings.

[0012] Figure 1 is a plan view showing an example of a semiconductor device according to some embodiments.

[0013] Figure 2 shows cross-sectional views taken along lines X1-X1' and X2-X2' of Figure 1 according to some embodiments. ​

[0014] Figure 3 shows a cross-sectional view taken along the line Y1-Y1', the line Y2-Y2', and the line Y3-Y3' of the semiconductor device 1 according to some embodiments. Figure 1

[0015] Figure 4 is a cross-sectional view showing an example of a semiconductor device taken along the line X1-X1' of the semiconductor device 1 according to some embodiments. Figure 1

[0016] Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 and Figure 29 are cross-sectional views showing examples of a method for manufacturing a semiconductor device taken along the line X1-X1' and the line X2-X2' of the semiconductor device 1 according to some embodiments. Figure 1

[0017] Figure 6 and Figure 8 are cross-sectional views showing examples of a method for manufacturing a semiconductor device taken along the line Y1-Y1' of the semiconductor device 1 according to some embodiments. Figure 1

[0018] Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 and Figure 30 are cross-sectional views showing examples of a method for manufacturing a semiconductor device taken along the line Y1-Y1', the line Y2-Y2', and the line Y3-Y3' of the semiconductor device 1 according to some embodiments. Figure 1 DETAILED DESCRIPTION

[0019] Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

[0020] For the sake of clear explanation of the present disclosure, parts irrelevant to the explanation are omitted, and the same reference numerals are assigned to equivalent or similar components throughout the specification.

[0021] ​​​​​For better understanding and ease of description, the size and thickness of each constituent element shown in the drawings are arbitrarily specified, and the present disclosure is not necessarily limited as shown. In the drawings, the thickness of layers, regions, and the like is exaggerated for clarity. Furthermore, in the drawings, the thickness of some layers and regions is exaggerated for better understanding and ease of description.

[0022] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The words "on" or "above" mean that an object is disposed on or below the upper side of the object, without necessarily meaning that it is disposed on the upper side of the object based on the direction of gravity.

[0023] Furthermore, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. In addition, in the present disclosure, the phrase "on plane" means that a target portion is observed from the top, and the phrase "on cross section" means that a cross section formed by vertically cutting a target portion is observed from the side. Furthermore, throughout the present disclosure, two directions intersecting in parallel with the upper surface of a substrate are defined as a first direction D1 and a second direction D2, respectively, and a direction perpendicular to the upper surface of the substrate is described as a third direction D3. For example, the first direction D1 and the second direction D2 can be perpendicular to each other.

[0024] Figure 1 is a plan view showing an example of a semiconductor device according to some embodiments. Figure 2 shows a cross-sectional view taken along Figure 1 line X1-X1' and line X2-X2' of Figure 3 shows a cross-sectional view taken along Figure 1 line Y1-Y1', line Y2-Y2', and line Y3-Y3' of

[0025] For a clear understanding and easy description, Figure 1 focus is placed on a cell region in which a logic cell constituting a logic circuit is arranged, and the illustration of a peripheral region arranged around the cell region is omitted. Furthermore, in Figure 1 , among the cell region, an active pattern AP1, a gate pattern GE, a gate inner spacer GIS, an upper source / drain pattern USD1, and a separation wall pattern 150 are mainly shown.

[0026] For example, the semiconductor device can be a three-dimensional semiconductor device (e.g., a stacked transistor). In other words, transistors can be stacked in the third direction D3 in a cell region. For example, a single-height cell (SHC) can be disposed between a first power line and a second power line, and the single-height cell can include a first active region AR1 as a bottom layer (bottom level), and a second active region AR2 can be stacked on the first active region AR1 as a top layer (top level).

[0027] For example, an NMOSFET in the first active region AR1 can be disposed, and a PMOSFET in the second active region AR2 can be stacked on the NMOSFET. The first active region AR1 and the second active region AR2 can be spaced apart from each other in the third direction D3.

[0028] In other words, the three-dimensional semiconductor device can have the first active region AR1 and the second active region AR2 stacked in the third direction D3. Accordingly, the semiconductor device can improve the degree of integration by reducing the area of a logic cell.

[0029] Meanwhile, in some embodiments, a peripheral region in which transistors constituting a processor core or an I / O terminal are arranged can be located around the cell region. In other words, the peripheral region can be a core / peripheral region. As an example, the peripheral region can include long gate transistors (or long channel transistors) having a relatively long gate length (i.e., channel length). The transistors in the peripheral region can operate at a higher power compared to the transistors in the cell region. For example, the transistors in the cell region can be single gate (SG) devices, and the transistors in the peripheral region can be extra gate (EG) devices.

[0030] The active pattern AP1 can be defined by a trench in the cell region. In other words, the active pattern AP1 can be a portion that protrudes vertically in the third direction D3. In a plan view (e.g., a plan view of the semiconductor device), the active pattern AP1 can have a bar shape spaced apart in the first direction D1 and extending in the second direction D2. The first active region AR1 and the second active region AR2 can be sequentially stacked on the active pattern AP1. For example, the active pattern AP1 can include a semiconductor material such as silicon, germanium, or silicon germanium, and can include, for example, silicon. Figure 1

[0031] ​The device isolation layer (or device separation layer) ST can fill a trench between the active patterns AP1. For example, the device isolation layer ST can be located on a side of the active pattern AP1 in the first direction D1. For example, the device isolation layer ST can include silicon oxide. An upper surface of the device isolation layer ST can be coplanar with or lower than an upper surface of the active pattern AP1. In some embodiments, the upper surface of the device isolation layer ST can be higher than the upper surface of the active pattern AP1. The device isolation layer ST can not cover the later-described lower channel pattern LCH1 and the upper channel pattern UCH1.

[0032] The separation wall pattern 150 can be located between one active pattern AP1 and another active pattern AP1 adjacent to the one active pattern AP1 in the first direction D1. The separation wall pattern 150 can extend parallel to the second direction D2 along the active pattern AP1. In a plan view (e.g., Figure 1 ), the separation wall pattern 150 can have a bar shape spaced apart in the first direction D1 and extending in the second direction D2.

[0033] For example, the separation wall pattern 150 can be arranged alternately with the active pattern AP1 in the first direction D1. The separation wall pattern 150 can be spaced apart from the active pattern AP1 in the first direction D1, and the device isolation layer ST can be located between the separation wall pattern 150 and the active pattern AP1.

[0034] The separation wall pattern 150 can be a portion protruding vertically in the third direction D3. For example, the separation wall pattern 150 can extend in the third direction D3 from a level lower than an upper surface of the later-described lower source / drain contact bCA to a level lower than an upper surface of the main gate structure MGE of the later-described gate pattern GE.

[0035] Here, the level of the upper surface of the lower source / drain contact bCA or the upper surface of the gate pattern GE can mean a shortest distance in the third direction D3 from a lower surface of the active pattern AP1 to the upper surface of the lower source / drain contact bCA or the upper surface of the gate pattern GE.

[0036] For example, the separation wall pattern 150 can extend from a level substantially the same as a lower surface of the lower source / drain contact bCA or a lower surface of the later-described lower gate contact bCB to a level substantially the same as an upper surface of the later-described upper gate structure UGE.

[0037] Accordingly, the separation wall pattern 150 can be located between one lower source / drain pattern LSD1 and another lower source / drain pattern LSD1 adjacent to the one lower source / drain pattern LSD1 in the first direction D1. The separation wall pattern 150 can be located between one upper source / drain pattern USD1 and another upper source / drain pattern USD1 adjacent to the one upper source / drain pattern USD1 in the first direction D1. The separation wall pattern 150 can be located between one lower gate structure LGE and another lower gate structure LGE adjacent to the one lower gate structure LGE in the first direction D1. The separation wall pattern 150 can be located between one upper gate structure UGE and another upper gate structure UGE adjacent to the one upper gate structure UGE in the first direction D1. The separation wall pattern 150 can be located between a lower source / drain contact bCA and another lower source / drain contact bCA adjacent to the lower source / drain contact bCA in the first direction D1. The separation wall pattern 150 can be located between a lower gate contact bCB and another lower gate contact bCB adjacent to the lower gate contact bCB in the first direction D1.

[0038] In other words, since the lower source / drain contact bCA and the lower gate contact bCB can be located between one separation wall pattern 150 and another separation wall pattern 150 adjacent to the one separation wall pattern 150 in the first direction D1, the lower source / drain contact bCA and the lower gate contact bCB can be formed by self-alignment without an additional structure such as a placeholder, and damage to the gate pattern GE when forming the lower source / drain contact bCA can be prevented.

[0039] Further, since the lower source / drain pattern LSD1 and the upper source / drain pattern USD1 can be located between one separation wall pattern 150 and another separation wall pattern 150 adjacent to the one separation wall pattern 150 in the first direction D1, the lower source / drain pattern LSD1 and the upper source / drain pattern USD1 can be laterally self-isolated by the separation wall pattern 150 in the first direction D1, thereby controlling lateral growth of the lower source / drain pattern LSD1 and the upper source / drain pattern USD1.

[0040] Further, one lower gate structure LGE of the gate pattern GE and an upper gate structure UGE located on the one lower gate structure LGE can be separated from another lower gate structure LGE and an upper gate structure UGE located on the another lower gate structure LGE which are adjacent to the one lower gate structure LGE and the upper gate structure UGE in the first direction D1 by the separation wall pattern 150. In other words, the separation wall pattern 150 can extend in the second direction D2 across the gate pattern GE, and the separation wall pattern 150 can penetrate the lower gate structure LGE and the upper gate structure UGE of the gate pattern GE.

[0041] Further, the connection of the main gate structure MGE can be cut by the gate cut pattern CT which is later described located on the separation wall pattern 150, and only the main gate structure MGE can be connected by the main gate connection part P08 which is later described located on the separation wall pattern 150. Therefore, since the gate pattern GE is extended or cut only on the separation wall pattern 150 in the first direction D1, it is possible to prevent the height of the lower surface of the extended portion of the gate pattern GE from being deeply recessed, thereby reducing a parasitic capacitance, simplifying a cutting process of the gate pattern GE, and minimizing a change in threshold voltage (V t ) due to the metal of the gate pattern GE being protected by the separation wall pattern 150.

[0042] For example, the separation wall pattern 150 can include an insulating material, and the insulating material can include SiON, SiCN, SiOCN, SiN, or a combination thereof (e.g., can include SiOCN).

[0043] The second hard mask HM2 can be located on the separation wall pattern 150. Further, the gate cut pattern CT can be located on the separation wall pattern 150. For example, the second hard mask HM2 can be located between the separation wall pattern 150 and the gate cut pattern CT. In this case, the lengths of the second hard mask HM2 and the gate cut pattern CT in the first direction D1 can be substantially the same as the length of the separation wall pattern 150 in the first direction D1. The lengths of the second hard mask HM2 and the gate cut pattern CT in the second direction D2 can be greater than the length of the main gate structure MGE in the second direction D2, and can be substantially the same as the length of the upper channel pattern UCH1 in the second direction D2 which is later described. Therefore, the connection of the main gate structure MGE can be cut by the second hard mask HM2 and the gate cut pattern CT which are located on the separation wall pattern 150.

[0044] For example, a level of a lower surface of the second hard mask HM2 can be lower than a level of a lower surface of the main gate electrode structure MGE. In some embodiments, a level of a lower surface of the second hard mask HM2 can be higher than a level of a lower surface of the main gate electrode structure MGE. In some embodiments, a level of a lower surface of the second hard mask HM2 can be substantially the same as a level of a lower surface of the main gate electrode structure MGE. For example, a level of an upper surface of the second hard mask HM2 in the third direction D3 can be lower than a level of an upper surface of the main gate electrode structure MGE in the third direction D3.

[0045] Further, a level of a lower surface of the gate cut pattern CT can be higher than a level of an upper surface of the upper gate electrode structure UGE and lower than a level of an upper surface of the main gate electrode structure MGE. For example, a level of an upper surface of the gate cut pattern CT can be higher than a level of an upper surface of the main gate electrode structure MGE.

[0046] Here, a level of a lower surface or an upper surface of the second hard mask HM2 can mean a shortest distance in the third direction D3 from a lower surface of the active pattern API to the lower surface or the upper surface of the second hard mask HM2.

[0047] Further, a level of a lower surface or an upper surface of the gate cut pattern CT can mean a shortest distance in the third direction D3 from a lower surface of the active pattern API to the lower surface or the upper surface of the gate cut pattern CT.

[0048] When the main gate electrode connection portion P08 is located on the separation wall pattern 150, the second hard mask HM2 can be located on each side of the main gate electrode connection portion P08 in the second direction D2. At this time, a length of the second hard mask HM2 in the second direction D2 can be substantially the same as a length of the gate spacer GS in the second direction D2, which will be described later.

[0049] For example, the second hard mask HM2 can include an insulating material, and the insulating material can include SiCN, SiOCN, SiN, or a combination thereof. The second hard mask HM2 can include a plurality of layers, each layer including SiCN, SiOCN, SiN, or a combination thereof.

[0050] Further, the gate cut pattern CT can include an insulating material, and the insulating material can include SiCN, SiOCN, SiN, or a combination thereof. The gate cut pattern CT can include a plurality of layers, each layer including SiCN, SiOCN, SiN, or a combination thereof.

[0051] A first active region AR1 including a lower channel pattern LCH1 and a lower source / drain pattern LSD1 can be located on the active pattern API. The lower channel pattern LCH1 can be disposed between one lower source / drain pattern LSD1 and another lower source / drain pattern LSD1 adjacent to the one lower source / drain pattern LSD1 in the second direction D2. The lower channel pattern LCH1 can connect a pair of lower source / drain patterns LSD1 to each other. For example, the lower channel pattern LCH1 and the lower source / drain pattern LSD1 can be alternately arranged in the second direction D2.

[0052] The lower channel pattern LCH1 can include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked on the third direction D3 and spaced apart from each other. However, the disclosure is not limited thereto, and the lower channel pattern LCH1 can include three or more semiconductor patterns. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can include crystalline silicon.

[0053] The lower insulating structure BDI can be located between the active pattern API and the lower channel pattern LCH1. For example, the lower insulating structure BDI can be located between the active pattern API and the first semiconductor pattern SP1 positioned at the lowermost position in the lower channel pattern LCH1. In addition, the lower insulating structure BDI can be located between the active pattern API and a first sub-gate portion P01 positioned at a lowermost portion of a later-described lower gate structure LGE.

[0054] The lower insulating structure BDI can separate the active pattern API and the lower channel pattern LCH1 from each other in the third direction D3. The lower insulating structure BDI can be overlapped with the lower channel pattern LCH1 and a later-described upper channel pattern UCH1 in the third direction D3. In addition, the lower insulating structure BDI can be overlapped with a later-described middle insulating structure MDI in the third direction D3. In addition, the lower insulating structure BDI can be overlapped with upper gate structures UGE and lower gate structures LGE of a gate pattern GE and an overlapped portion IS1 of a later-described gate inner spacer GIS in the third direction D3. Meanwhile, the lower insulating structure BDI can not be overlapped with a later-described sub-gate connection portion P07 of the gate pattern GE and a non-overlapped portion IS2 of the later-described gate inner spacer GIS in the third direction D3.

[0055] For example, the lower insulating structure BDI can include an insulating material. For example, the lower insulating structure BDI can include silicon oxide, silicon nitride, or silicon oxynitride.

[0056] The gate pattern GE can be prevented from being damaged when the lower source / drain contact bCA is formed, and the work function metal of the gate pattern GE can be protected, thereby minimizing a change in threshold voltage (V t

[0057] At least one dummy channel pattern can be disposed between the lower insulating structure BDI and the lower channel pattern LCH1, and the lower insulating structure BDI can be disposed between the dummy channel patterns. For example, a first dummy channel pattern can be located between the lower insulating structure BDI and the lower channel pattern LCH1.

[0058] For example, the first dummy channel pattern can be located between the lower insulating structure BDI and a first semiconductor pattern SP1 positioned at a lowermost portion of the lower channel pattern LCH1. Also, the first dummy channel pattern can be located between the active pattern AP1 and a first sub-gate portion P01 positioned at a lowermost portion of the lower gate structure LGE.

[0059] In other words, the active pattern AP1, the lower insulating structure BDI, the first dummy channel pattern, the first sub-gate portion P01 of the lower gate structure LGE, and the first semiconductor pattern SP1 of the lower channel pattern LCH1 can be sequentially stacked in the third direction D3. The first dummy channel pattern can include a semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (SiGe), or a silicon-based insulating material such as silicon oxide or silicon nitride. For example, the first dummy channel pattern can include a silicon-based insulating material.

[0060] The lower source / drain pattern LSD1 can be doped with an impurity to have a first conductivity type. The first conductivity type can be either one of an N-type and a P-type. For example, the first conductivity type can be an N-type. The lower source / drain pattern LSD1 can include silicon (Si) or silicon germanium (SiGe).

[0061] The lower source / drain pattern LSD1 can be doped with an impurity to have a first conductivity type. The first conductivity type can be either one of an N-type and a P-type. For example, the first conductivity type can be an N-type. The lower source / drain pattern LSD1 can include silicon (Si) or silicon germanium (SiGe).

[0062] In some embodiments, the semiconductor device can further include a first interlayer insulating layer. The first interlayer insulating layer can be located on a side surface of the lower gate structure LGE and an upper surface of the lower source / drain pattern LSD1. For example, the first interlayer insulating layer can be located between the spacer pattern 150 and the side surface of the lower gate structure LGE. For example, the first interlayer insulating layer can include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k material.

[0063] ​In some embodiments, a first interlayer stop layer can be further located between the lower gate structure LGE and the first interlayer insulating layer and between the lower source / drain pattern LSD1 and the first interlayer insulating layer. The first interlayer stop layer can include a material having etch selectivity with respect to the first interlayer insulating layer. The first interlayer stop layer can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon carbon oxide (SiOC).

[0064] The second active region AR2 can be located on the first active region AR1. The second active region AR2 can include an upper channel pattern UCH1 and an upper source / drain pattern USD1.

[0065] The upper channel pattern UCH1 can be located on the lower channel pattern LCH1. The upper source / drain pattern USD1 can be located on the lower source / drain pattern LSD1. In other words, the upper channel pattern UCH1 can be superposed on the lower channel pattern LCH1 in the third direction D3. The upper source / drain pattern USD1 can be superposed on the lower source / drain pattern LSD1 in the third direction D3. The upper channel pattern UCH1 can be interposed between one upper source / drain pattern USD1 and another upper source / drain pattern USD1 adjacent to the one upper source / drain pattern USD1 in the second direction D2. The upper channel pattern UCH1 can connect a pair of upper source / drain patterns USD1 to each other. For example, the upper channel pattern UCH1 and the upper source / drain pattern USD1 can be alternately arranged in the second direction D2.

[0066] The upper channel pattern UCH1 can include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked in the third direction D3 and spaced apart from each other. However, the disclosure is not limited thereto, and the upper channel pattern UCH1 can include three or more semiconductor patterns. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH1 can include the same semiconductor material as the semiconductor material of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH1 described above.

[0067] The intermediate insulating structure MDI can be located between the lower channel pattern LCH1 and the upper channel pattern UCH1 on the lower channel pattern LCH1. For example, the intermediate insulating structure MDI can be located between the second semiconductor pattern SP2 positioned at the uppermost portion of the lower channel pattern LCH1 and the third semiconductor pattern SP3 positioned at the lowermost portion of the upper channel pattern UCH1. In addition, the intermediate insulating structure MDI can be located between the third sub-gate portion P03 positioned at the uppermost portion in the lower gate structure LGE described later and the fourth sub-gate portion P04 positioned at the lowermost portion in the upper gate structure UGE described later.

[0068] The middle insulating structure MDI can separate the lower channel pattern LCH1 and the upper channel pattern UCH1 from each other in the third direction D3. The middle insulating structure MDI can be stacked with the lower channel pattern LCH1 and the upper channel pattern UCH1 in the third direction D3. Also, the middle insulating structure MDI can be stacked with the lower insulating structure BDI in the third direction D3.

[0069] Also, the middle insulating structure MDI can be stacked with the upper gate structure UGE and the lower gate structure LGE of the gate pattern GE and the stacked portion IS1 of the gate inner spacer GIS in the third direction D3. Meanwhile, the middle insulating structure MDI can not be stacked with the sub gate connection portion P07 of the gate pattern GE and the non-stacked portion IS2 of the gate inner spacer GIS in the third direction D3.

[0070] For example, the middle insulating structure MDI can include an insulating material. For example, the middle insulating structure MDI can include silicon oxide, silicon nitride, or silicon oxynitride.

[0071] At least one dummy channel pattern can be positioned between the lower channel pattern LCH1 and the upper channel pattern UCH1 on the lower channel pattern LCH1, and the middle insulating structure MDI can be positioned between the dummy channel patterns. For example, the second dummy channel pattern DS2 and the third dummy channel pattern DS3 can be positioned between the lower channel pattern LCH1 and the upper channel pattern UCH1, and the middle insulating structure MDI can be positioned between the second dummy channel pattern DS2 and the third dummy channel pattern DS3.

[0072] For example, the second dummy channel pattern DS2 and the third dummy channel pattern DS3 can be positioned between the second semiconductor pattern SP2 positioned at the uppermost position in the lower channel pattern LCH1 and the third semiconductor pattern SP3 positioned at the lowermost position in the upper channel pattern UCH1. Also, the second dummy channel pattern DS2 and the third dummy channel pattern DS3 can be positioned between the third sub gate portion P03 positioned at the uppermost portion in the lower gate structure LGE and the fourth sub gate portion P04 positioned at the lowermost portion in the upper gate structure UGE.

[0073] In other words, the second semiconductor pattern SP2 of the lower channel pattern LCH1, the third sub gate portion P03 of the lower gate structure LGE, the second dummy channel pattern DS2, the middle insulating structure MDI, the third dummy channel pattern DS3, the fourth sub gate portion P04 of the upper gate structure UGE, and the third semiconductor pattern SP3 of the upper channel pattern UCH1 can be sequentially stacked in the third direction D3.

[0074] The second dummy channel pattern DS2 and the third dummy channel pattern DS3 can be spaced apart from the lower source / drain pattern LSD1 and the upper source / drain pattern USD1. For example, a later-described buried insulating layer SDI can be located next to the second dummy channel pattern DS2 and the third dummy channel pattern DS3 in the second direction D2, and the lower source / drain pattern LSD1 and the upper source / drain pattern USD1 can not be located next to the second dummy channel pattern DS2 and the third dummy channel pattern DS3 in the second direction D2. Accordingly, the second dummy channel pattern DS2 and the third dummy channel pattern DS3 can not be connected to any source / drain pattern.

[0075] With the aid of the intermediate insulating structure MDI and the third dummy channel pattern DS3 and the second dummy channel pattern DS2 located above and below the intermediate insulating structure MDI, the threshold voltage (V t ) between the lower gate structure LGE and the upper gate structure UGE of the gate electrode pattern GE can be controlled, and variations in the threshold voltage (V t ) can be minimized.

[0076] At least one dummy channel pattern can be located on the upper channel pattern UCH1. For example, a fourth dummy channel pattern DS4 can be located on the upper channel pattern UCH1.

[0077] For example, the fourth dummy channel pattern DS4 can be located on a fourth semiconductor pattern SP4 located at an uppermost position of the upper channel pattern UCH1. In addition, the fourth dummy channel pattern DS4 can be located on a sixth sub-gate portion P06, which is later described, located at an uppermost position of the upper gate structure UGE.

[0078] In other words, the fourth semiconductor pattern SP4 of the upper channel pattern UCH1, the sixth sub-gate portion P06 of the upper gate structure UGE, and the fourth dummy channel pattern DS4 can be sequentially stacked in the third direction D3.

[0079] The second dummy channel pattern DS2, the third dummy channel pattern DS3, and the fourth dummy channel pattern DS4 can include a semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (SiGe) or a silicon-based insulating material such as silicon oxide or silicon nitride. For example, the second dummy channel pattern DS2, the third dummy channel pattern DS3, and the fourth dummy channel pattern DS4 can include a silicon-based insulating material.

[0080] A first hard mask HM1 can be located on the fourth dummy channel pattern DS4. For example, the first hard mask HM1 can be located on each side of the main gate structure MGE in the second direction D2.

[0081] For example, a level of a lower surface of the first hard mask HM1 can be lower than a level of a lower surface of the main gate electrode structure MGE. In some embodiments, the level of the lower surface of the first hard mask HM1 can be higher than the level of the lower surface of the main gate electrode structure MGE. In some embodiments, the level of the lower surface of the first hard mask HM1 can be substantially the same as the level of the lower surface of the main gate electrode structure MGE. For example, a level of an upper surface of the first hard mask HM1 can be lower than a level of an upper surface of the main gate electrode structure MGE.

[0082] Here, the level of the lower surface or the upper surface of the first hard mask HM1 can mean a shortest distance in the third direction D3 from a lower surface of the active pattern AP1 to the lower surface or the upper surface of the first hard mask HM1.

[0083] For example, the first hard mask HM1 can include an insulating material, and the insulating material can include SiCN, SiOCN, SiN, or a combination thereof. The first hard mask HM1 can include a plurality of layers, each layer including SiCN, SiOCN, SiN, or a combination thereof.

[0084] The first etch stop layer ESL1 can be located on the first hard mask HM1 and the second hard mask HM2. However, the first etch stop layer ESL1 can not be located on the main gate electrode structure MGE. Further, the first etch stop layer ESL1 can not be located between the second hard mask HM2 and the gate cut pattern CT. For example, the first etch stop layer ESL1 can be located on each side of the main gate electrode structure MGE in the second direction D2. Further, the first etch stop layer ESL1 can be located on the non-overlapped portion IS2 of the gate inner spacer GIS.

[0085] The first etch stop layer ESL1 can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon oxycarbide (SiOC).

[0086] The upper source / drain pattern USD1 can be located on an upper surface of the buried insulating layer SDI. The upper source / drain pattern USD1 can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, an upper surface of the upper source / drain pattern USD1 can be higher than an upper surface of the fourth semiconductor pattern SP4 of the upper channel pattern UCH1.

[0087] The upper source / drain pattern USD1 can be doped with an impurity to have a second conductivity type. The second conductivity type can be different from a first conductivity type of the lower source / drain pattern LSD1. For example, the second conductivity type can be P-type. The upper source / drain pattern USD1 can include silicon germanium (SiGe) or silicon (Si).

[0088] A buried insulating layer SDI can be disposed between the lower source / drain pattern LSD1 and the upper source / drain pattern USD1 on the lower source / drain pattern LSD1. For example, the buried insulating layer SDI can be located between an upper surface of the lower source / drain pattern LSD1 and a lower surface of the upper source / drain pattern USD1.

[0089] The buried insulating layer SDI can separate the lower source / drain pattern LSD1 and the upper source / drain pattern USD1 from each other in the third direction D3. The buried insulating layer SDI can be superposed with the lower source / drain pattern LSD1 and the upper source / drain pattern USD1 in the third direction D3.

[0090] The buried insulating layer SDI can include an insulating material. For example, the buried insulating layer SDI can include silicon nitride, silicon oxynitride, or a combination thereof.

[0091] The semiconductor device can further include a second interlayer insulating layer 120. The second interlayer insulating layer 120 can be located on an upper surface of the upper source / drain pattern USD1. The second interlayer insulating layer 120 can be located on an upper surface of the separation wall pattern 150. The second interlayer insulating layer 120 can be located on a side surface of the main gate electrode structure MGE. The second interlayer insulating layer 120 can be located on a side surface of a gate cover pattern GP and a side surface of a gate cut pattern CT, which will be described later. For example, the second interlayer insulating layer 120 can include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k material.

[0092] In some embodiments, a second interlayer stop layer can be further located between the upper gate electrode structure UGE and the second interlayer insulating layer and between the upper source / drain pattern USD1 and the second interlayer insulating layer. The second interlayer stop layer can include a material having etch selectivity with respect to the second interlayer insulating layer. The second interlayer stop layer can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon carbon oxide (SiOC).

[0093] The gate pattern GE can be located on the lower channel pattern LCH1 and the upper channel pattern UCH1. The gate pattern GE can be superposed with the stacked lower channel pattern LCH1 and the upper channel pattern UCH1 in the third direction D3.

[0094] The gate pattern GE can extend in the third direction D3 from an upper surface of the device isolation layer ST or an upper surface of the active pattern API to the gate cap pattern GP. The gate pattern GE can extend in the third direction D3 from the lower channel pattern LCH1 of the first active region AR1 to the upper channel pattern UCH1 of the second active region AR2. In other words, the gate pattern GE can extend in the third direction D3 from the first semiconductor pattern SP1 at the lowermost portion to the fourth semiconductor pattern SP4 at the uppermost portion.

[0095] The gate pattern GE can be located on an upper surface, a bottom surface, and two side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. In other words, the logic cell can include a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate pattern GE three-dimensionally surrounds the channel.

[0096] The gate pattern GE can have a lower gate structure LGE located within the first active region AR1, an upper gate structure UGE located within the second active region AR2, and a main gate structure MGE located on the upper gate structure UGE. The lower gate structure LGE, the upper gate structure UGE, and the main gate structure MGE can be stacked on each other in the third direction D3. The lower gate structure LGE, the upper gate structure UGE, and the main gate structure MGE can be connected to each other. In other words, the gate pattern GE can be a common gate electrode in which the lower gate structure LGE on the lower channel pattern LCH1, the upper gate structure UGE on the upper channel pattern UCH1, and the main gate structure MGE are connected to each other.

[0097] The lower gate structure LGE can have a first sub-gate portion P01 interposed between the active pattern API and the first semiconductor pattern SP1, a second sub-gate portion P02 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third sub-gate portion P03 interposed between the second semiconductor pattern SP2 and the second dummy channel pattern DS2.

[0098] The upper gate structure UGE can have a fourth sub-gate portion P04 interposed between the third dummy channel pattern DS3 and the third semiconductor pattern SP3, a fifth sub-gate portion P05 interposed between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and a sixth sub-gate portion P06 interposed between the fourth semiconductor pattern SP4 and the fourth dummy channel pattern DS4.

[0099] The main gate structure MGE can be located on the sixth sub-gate portion P06 of the upper gate structure UGE. For example, the main gate structure MGE can be located on the upper channel pattern UCH1 and can be located on the fourth semiconductor pattern SP4 positioned at the uppermost end of the upper channel pattern UCH1. For example, the main gate structure MGE can be located on the fourth dummy channel pattern DS4.

[0100] For example, the lower gate structure LGE can include a first work function metal pattern located on the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The upper gate structure UGE and the main gate structure MGE can include a second work function metal pattern located on the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4. Each of the first work function metal pattern and the second work function metal pattern can include nitrogen (N) and a metal including titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), or a combination thereof. The first work function metal pattern and the second work function metal pattern can have different work functions. The gate pattern GE can include a low-resistivity metal including, for example, tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), or a combination thereof on the first work function metal pattern and the second work function metal pattern. For example, the main gate structure MGE can include the low-resistivity metal.

[0101] The gate pattern GE can further have a sub-gate connection portion P07 located on both sides of the lower channel pattern LCH1 and the upper channel pattern UCH1 in the first direction D1. For example, the sub-gate connection portion P07 can be located on both sides of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 in the first direction D1. For example, the sub-gate connection portion P07 can be in contact with both side surfaces of the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4 in the first direction D1.

[0102] The sub-gate connection portion P07 can be located on both sides of the first sub-gate portion P01 to the sixth sub-gate portion P06 in the first direction D1, and the sub-gate connection portion P07 can be in contact with both sides of the first sub-gate portion P01 to the sixth sub-gate portion P06 in the first direction D1. In addition, the sub-gate connection portion P07 extends from the first sub-gate portion P01 located at the lowermost end to the sixth sub-gate portion P06 located at the uppermost end in the third direction D3 to pass through the side surfaces of the first sub-gate portion P01 to the sixth sub-gate portion P06 and connect the first sub-gate portion P01 to the sixth sub-gate portion P06. For example, the sub-gate connection portion P07 can extend from the upper surface of the device isolation layer ST to the lower surface of the main gate structure MGE in the third direction D3.

[0103] The sub-gate connection portion P07 can not overlap the lower channel pattern LCH1 and the upper channel pattern UCH1 in the third direction D3. For example, the sub-gate connection portion P07 can not overlap the first to fourth semiconductor patterns SP1 to SP4 in the third direction D3.

[0104] Meanwhile, the first to sixth sub-gate portions P01 to P06 can overlap the first to fourth semiconductor patterns SP1 to SP4 in the third direction D3. Accordingly, the sub-gate connection portion P07 can not overlap the first to sixth sub-gate portions P01 to P06 in the third direction D3.

[0105] Further, the first to sixth sub-gate portions P01 to P06 can be located on the active pattern AP1. On the other hand, the sub-gate connection portion P07 can be located on the device isolation layer ST.

[0106] As described above, one lower gate structure LGE of the gate pattern GE and an upper gate structure UGE located on the one lower gate structure LGE can be separated from another lower gate structure LGE and an upper gate structure UGE located on the another lower gate structure LGE adjacent to the one lower gate structure LGE and the upper gate structure UGE in the second direction D2 by the spacer pattern 150.

[0107] The first to sixth sub-gate portions P01 to P06 of the gate pattern GE can be located between the spacer patterns 150 in the first direction D1, and the first to sixth sub-gate portions P01 to P06 can not contact the spacer patterns 150, but the sub-gate connection portion P07 can be located between the first to sixth sub-gate portions P01 to P06 and the spacer patterns 150 and can contact the first to sixth sub-gate portions P01 to P06 and the spacer patterns 150.

[0108] Accordingly, the gate pattern GE can extend in the first direction D1 from one spacer pattern 150 to another spacer pattern 150 adjacent to the one spacer pattern 150 in the first direction D1. For example, one gate pattern GE can contact one spacer pattern 150 and another spacer pattern 150 adjacent to the one spacer pattern 150 in the first direction D1. The gate pattern GE can also have a main gate connection portion P08 located on the spacer pattern 150.

[0109] The main gate connection portion P08 can be located between one main gate structure MGE disposed in the first direction D1 and another main gate structure MGE with one of the separation wall patterns 150 interposed therebetween. The one main gate structure MGE and the another main gate structure MGE disposed in the first direction D1 with one of the separation wall patterns 150 interposed therebetween can be connected to each other by the main gate connection portion P08. Thereby, the gate pattern GE can be extended in the first direction D1.

[0110] Since the gate pattern GE is extended in the first direction D1 only on the separation wall pattern 150, a height of a lower surface of the gate pattern GE can be prevented from being deeply recessed, thereby reducing a parasitic capacitance, and since the metal of the gate pattern GE is protected by the separation wall pattern 150, a variation in threshold voltage (V t ) can be minimized.

[0111] For example, a level of a lower surface of the main gate connection portion P08 can be lower than a level of a lower surface of the main gate structure MGE. In some embodiments, the level of the lower surface of the main gate connection portion P08 can be higher than the level of the lower surface of the main gate structure MGE. In some embodiments, the level of the lower surface of the main gate connection portion P08 can be substantially the same as the level of the lower surface of the main gate structure MGE.

[0112] Here, the level of the lower surface of the main gate connection portion P08 or the lower surface of the main gate structure MGE can mean a shortest distance in the third direction D3 from a lower surface of the active pattern API to the lower surface of the main gate connection portion P08 or the lower surface of the main gate structure MGE.

[0113] The gate-in spacer GIS can be located between the gate pattern GE and the lower source / drain pattern LSD1 and the upper source / drain pattern USD1. For example, the gate-in spacer GIS can be located between the first to third sub gate portions P01 to P03 of the lower gate structure LGE and the lower source / drain pattern LSD1, and can be located between the fourth to sixth sub gate portions P04 to P06 of the upper gate structure UGE and the upper source / drain pattern USD1. The gate-in spacer GIS can extend in the first direction D1 along the gate pattern GE.

[0114] For example, in a cross-sectional view (for example, Figure 2 ), the gate-in spacer GIS can be located on each side of the first to sixth sub gate portions P01 to P06 in the second direction D2.

[0115] The gate inner spacer GIS can have an overlapping portion IS1 overlapping the upper channel pattern UCH1 and the lower channel pattern LCH1 in the third direction D3, and a non-overlapping portion IS2 not overlapping the upper channel pattern UCH1 and the lower channel pattern LCH1 in the third direction D3.

[0116] For example, the overlapping portion IS1 can be located between the first to fourth semiconductor patterns SP1 to SP4 in the third direction D3. For example, the overlapping portion IS1 can be located between the active pattern AP1 and the first semiconductor pattern SP1, between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, between the second semiconductor pattern SP2 and the second dummy channel pattern DS2, between the third dummy channel pattern DS3 and the third semiconductor pattern SP3, between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and between the fourth semiconductor pattern SP4 and the fourth dummy channel pattern DS4, respectively.

[0117] For example, the non-overlapping portion IS2 can be located on both sides of the first to fourth semiconductor patterns SP1 to SP4 in the first direction D1. For example, the non-overlapping portion IS2 can be in contact with both side surfaces of the first to fourth semiconductor patterns SP1 to SP4 in the first direction D1. In addition, the non-overlapping portion IS2 can be located on both sides of the overlapping portion IS1 in the first direction D1, and the non-overlapping portion IS2 can be in contact with both sides of the overlapping portion IS1 in the first direction D1.

[0118] The non-overlapping portion IS2 can extend from the first semiconductor pattern SP1 located at the lowermost end to the fourth semiconductor pattern SP4 located at the uppermost end in the third direction D3. In addition, the non-overlapping portion IS2 can extend from the overlapping portion IS1 located at the bottom to the overlapping portion IS1 located at the uppermost end in the third direction D3, passing through the side of the overlapping portion IS1 and connecting the overlapping portion IS1. For example, the non-overlapping portion IS2 can extend from the upper surface of the device isolation layer ST to the lower surface of the first etching stop layer ESL1 in the third direction. The non-overlapping portion IS2 can be in contact with the upper surface of the device isolation layer ST and the lower surface of the first etching stop layer ESL1.

[0119] At the same time, the overlying portion IS1 can be located on the active pattern API, and the non-overlying portion IS2 can be located on the device isolation layer ST. For example, one gate inner spacer GIS can be separated from another gate inner spacer GIS adjacent to the one gate inner spacer GIS in the first direction D1 by the spacer wall pattern 150. The overlying portion IS1 of the gate inner spacer GIS is located between the spacer wall patterns 150 in the first direction D1, and the overlying portion IS1 does not contact (e.g., is spaced apart from) the spacer wall pattern 150, but the non-overlying portion IS2 is located between the overlying portion IS1 and the spacer wall pattern 150 and can contact the overlying portion IS1 and the spacer wall pattern 150.

[0120] Accordingly, the gate inner spacer GIS can extend in the first direction D1 from one spacer wall pattern 150 to another spacer wall pattern 150 adjacent to the one spacer wall pattern 150 in the first direction D1. For example, the gate inner spacer GIS can contact one spacer wall pattern 150 and another spacer wall pattern 150 adjacent to the one spacer wall pattern 150 in the first direction D1.

[0121] For example, the thickness of the overlying portion IS1 and the non-overlying portion IS2 of the gate inner spacer GIS in the second direction D2 can be substantially the same. For example, the thickness of the overlying portion IS1 and the non-overlying portion IS2 in the second direction D2 can be about 4 nm or greater, about 5 nm or greater, about 6 nm or greater, or about 7 nm or greater, and can be about 8 nm or less, about 7 nm or less, about 6 nm or less, or about 5 nm or less, for example, about 4 nm to about 8 nm.

[0122] The length of the non-overlying portion IS2 in the first direction D1 can be about 4 nm or greater, about 5 nm or greater, about 6 nm or greater, about 7 nm or greater, about 8 nm or greater, about 9 nm or greater, about 10 nm or greater, about 11 nm or greater, about 12 nm or greater, about 13 nm or greater, or about 14 nm or greater, and can be about 15 nm or less, about 14 nm or less, about 13 nm or less, about 12 nm or less, about 11 nm or less, about 10 nm or less, about 9 nm or less, about 8 nm or less, about 7 nm or less, or about 6 nm or less, for example, about 5 nm to about 15 nm.

[0123] As an example, the gate-intra-space piece GIS can include a low-k material. The low-k material can include silicon oxide or a material having a dielectric constant lower than that of silicon oxide. For example, the low-k material can include silicon oxide, silicon oxide doped with fluorine or carbon, porous silicon oxide, or an organic polymer dielectric. However, the disclosure is not limited thereto, and the gate-intra-space piece GIS can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof.

[0124] In this way, the gate-intra-space piece GIS has an overlapping portion IS1 overlapping the lower channel pattern LCH1 and the upper channel pattern UCH1 in the third direction D3 and a non-overlapping portion IS2 not overlapping the lower channel pattern LCH1 and the upper channel pattern UCH1 in the third direction D3, and the gate-intra-space piece GIS extends in the first direction D1 to one separation wall pattern 150 and another separation wall pattern 150 adjacent to the one separation wall pattern 150 in the first direction D1, so that the gate-intra-space piece GIS can be located on the entire surface of the gate pattern GE opposite the lower source / drain pattern LSD1 and the upper source / drain pattern USD1, thereby preventing the gate pattern GE from being damaged when the lower source / drain contact bCA is formed.

[0125] A pair of gate spacers GS can be placed on two side surfaces of the sixth sub-gate portion P06 of the gate pattern GE, respectively. The gate spacer GS can extend in the first direction D1 along the gate pattern GE.

[0126] The upper surface of the gate spacer GS can be higher than the upper surface of the gate pattern GE. The upper surface of the gate spacer GS can be coplanar with the upper surface of the second interlayer insulating layer 120.

[0127] The gate spacer GS can include SiCN, SiOCN, SiN, or a combination thereof. For example, the gate spacer GS can include a plurality of layers, each layer including SiCN, SiOCN, SiN, or a combination thereof.

[0128] The gate cover pattern GP can be located on the upper surface of the gate pattern GE. The gate cover pattern GP can extend in the first direction D1 along the gate pattern GE. For example, the gate cover pattern GP can include SiON, SiCN, SiOCN, SiN, or a combination thereof.

[0129] In some embodiments, a gate insulating layer can be disposed between the gate pattern GE and the first to fourth semiconductor patterns SP1 to SP4. The gate insulating layer can include a silicon oxide layer, a silicon oxynitride layer, a high-k layer, or a combination thereof. For example, the gate insulating layer can include a silicon oxide layer directly covering surfaces of the first to fourth semiconductor patterns SP1 to SP4 and a high-k layer on the silicon oxide layer. In other words, the gate insulating layer can include a multi-layer of a silicon oxide layer and a high-k layer.

[0130] The high-k layer can include a high-k material having a dielectric constant higher than that of silicon oxide. For example, the high-k material can include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0131] The upper source / drain contact aCA can be electrically connected to the upper source / drain pattern USD1 by penetrating the second interlayer insulating layer 120. Also, the upper gate contact aCB can be electrically connected to the main gate structure MGE by penetrating the second interlayer insulating layer 120 and the gate cover pattern GP.

[0132] In some embodiments, each of the upper source / drain contact aCA and the upper gate contact aCB can include a conductive pattern and a barrier pattern surrounding the conductive pattern. For example, the conductive pattern can include aluminum, copper, tungsten, molybdenum, or a combination thereof. The barrier pattern can cover side surfaces and a bottom surface of the conductive pattern. The barrier pattern can include a metal layer or a metal nitride layer. The metal layer can include titanium, tantalum, tungsten, nickel, cobalt, platinum, or a combination thereof. The metal nitride layer can include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or a combination thereof.

[0133] In some embodiments, a silicide pattern can be disposed between the upper source / drain contact aCA and the upper source / drain pattern USD1 and between the upper gate contact aCB and the main gate structure MGE. The upper source / drain contact aCA can be electrically connected to the upper source / drain pattern USD1 by the silicide pattern, and the upper gate contact aCB can be electrically connected to the main gate structure MGE by the silicide pattern. The silicide pattern can include a metal silicide (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, or a combination thereof).

[0134] In some embodiments, a first upper interlayer insulating layer can be located on the upper source / drain contact aCA and the upper gate contact aCB and can cover the upper source / drain contact aCA and the upper gate contact aCB.

[0135] Further, a first upper metal layer can be disposed within the first upper interlayer dielectric layer. The first upper metal layer can include a first upper power routing, a first upper routing, and a first upper via. The first upper via can be located below the first upper power routing and the first upper routing. The first upper via can be disposed between the upper source / drain contact aCA and the first upper power routing and the first upper routing, respectively. Further, the first upper via can be disposed between the upper gate contact aCB and the first upper routing, respectively.

[0136] The first upper power routing and the first upper routing of the first upper metal layer can include the same or different conductive materials. For example, the first upper power routing and the first upper routing can include aluminum, copper, tungsten, molybdenum, cobalt, or a combination thereof.

[0137] In some implementations, an additional upper metal layer can be disposed on the first upper interlayer dielectric layer. Each of the stacked upper metal layers can include a routing.

[0138] The lower source / drain contact bCA can be located below the lower source / drain pattern LSD1 and can be electrically connected to the lower source / drain pattern LSD1. For example, the lower source / drain contact bCA can penetrate the active pattern API and can be electrically connected to the lower source / drain pattern LSD1.

[0139] Further, the lower gate contact bCB can be located below the lower gate structure LGE and can be electrically connected to the lower gate structure LGE. For example, the lower gate contact bCB can penetrate the active pattern API and can be electrically connected to the lower gate structure LGE.

[0140] The insulating liner CBL can further be located between the lower source / drain contact bCA and the adjacent lower gate contact bCB. The insulating liner CBL can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon oxycarbide (SiOC).

[0141] In some implementations, each of the lower source / drain contact bCA and the lower gate contact bCB can include a conductive pattern and a barrier pattern surrounding the conductive pattern. For example, the conductive pattern can include a metal including aluminum, copper, tungsten, molybdenum, or a combination thereof. The barrier pattern can cover side surfaces and a bottom surface of the conductive pattern. The barrier pattern can include a metal layer or a metal nitride layer. The metal layer can include titanium, tantalum, tungsten, nickel, cobalt, platinum, or a combination thereof. The metal nitride layer can include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or a combination thereof.

[0142] In some embodiments, a silicide pattern can be disposed between the lower source / drain contact bCA and the lower source / drain pattern LSD1 and between the lower gate contact bCB and the lower gate structure LGE. The lower source / drain contact bCA can be electrically connected to the lower source / drain pattern LSD1 by the silicide pattern, and the lower gate contact bCB can be electrically connected to the lower gate structure LGE by the silicide pattern. The silicide pattern can include a metal silicide (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, or a combination thereof).

[0143] In some embodiments, a first lower interlayer insulating layer can be located below the lower source / drain contact bCA and the lower gate contact bCB, and can cover the lower source / drain contact bCA and the lower gate contact bCB.

[0144] Further, a first lower metal layer can be disposed within the first lower interlayer insulating layer. The first lower metal layer can include a first lower power wiring, a first lower wiring, and a first lower via. The first lower via can be located on the first lower power wiring and the first lower wiring. The first lower via can be disposed between the lower source / drain contact bCA and the first lower power wiring and the first lower wiring, respectively. Further, the first lower via can be disposed between the lower gate contact bCB and the first lower wiring, respectively.

[0145] The first lower power wiring and the first lower wiring of the first lower metal layer can include the same or different conductive materials. For example, the first lower power wiring and the first lower wiring can include aluminum, copper, tungsten, molybdenum, cobalt, or a combination thereof.

[0146] In some embodiments, an additional lower metal layer can be located below the first lower interlayer insulating layer. Each of the stacked lower metal layers can include a routing lower wiring.

[0147] Figure 4 is a cross-sectional view illustrating an example of a semiconductor device taken along a line X1-X1' of Figure 1 is a cross-sectional view illustrating an example of a semiconductor device taken along a line X1-X1' of Figure 4 The embodiment shown in Figure 2 is substantially the same as the embodiment shown in and repetitive description thereof will be omitted and differences will be mainly explained. Further, the same reference numerals are used for components identical to those in the previous embodiment.

[0148] In Figure 2 , the length of the lower insulating structure BDI in the second direction D2 is shown to be substantially the same as the length of the middle insulating structure MDI in the second direction D2, and the lengths of the first to third sub-gate portions P01 to P03 of the lower gate structure LGE in the second direction D2 are shown to be substantially the same as the lengths of the fourth to sixth sub-gate portions P04 to P06 of the upper gate structure UGE in the second direction D2.

[0149] In Figure 4 the lower insulating structure BDI can have a length in the second direction D2 that is greater than a length of the middle insulating structure MDI in the second direction D2. Further, the first to third sub-gate portions P01 to P03 of the lower gate structure LGE can have lengths in the second direction D2 that are greater than lengths of the fourth to sixth sub-gate portions P04 to P06 of the upper gate structure UGE in the second direction D2.

[0150] Thus, the lower source / drain contact bCA and the lower gate contact bCB can be more easily formed by self-alignment without additional structures such as a spacer, damage to the gate pattern GE when forming the lower source / drain contact bCA can be prevented, and the work function metal of the gate pattern GE can be protected so that a threshold voltage (V t ) change can be minimized.

[0151] For example, the lower insulating structure BDI can have a length in the second direction D2 that is greater than lengths of the first to third sub-gate portions P01 to P03 of the lower gate structure LGE in the second direction D2.

[0152] The lengths of the first to third sub-gate portions P01 to P03 of the lower gate structure LGE in the second direction D2 can decrease as they move upward in the third direction D3. For example, the first sub-gate portion P01 can have a length in the second direction D2 that is greater than a length of the second sub-gate portion P02 in the second direction D2. The second sub-gate portion P02 can have a length in the second direction D2 that is greater than a length of the third sub-gate portion P03 in the second direction D2.

[0153] The lengths of the first to third sub-gate portions P01 to P03 of the lower gate structure LGE in the second direction D2 can be greater than a length of the middle insulating structure MDI in the second direction D2. For example, the third sub-gate portion P03 of the lower gate structure LGE can have a length in the second direction D2 that is greater than a length of the middle insulating structure MDI in the second direction D2.

[0154] The middle insulating structure MDI can have a length in the second direction D2 that is greater than lengths of the fourth to sixth sub-gate portions P04 to P06 of the upper gate structure UGE in the second direction D2. For example, the middle insulating structure MDI can have a length in the second direction D2 that is greater than a length of the fourth sub-gate portion P04 of the upper gate structure UGE in the second direction D2.

[0155] The length of the fourth to sixth sub-gate portions P04 to P06 of the upper gate structure UGE in the second direction D2 can be smaller as it moves upward in the third direction D3. For example, the length of the fourth sub-gate portion P04 in the second direction D2 can be larger than the length of the fifth sub-gate portion P05 in the second direction D2. The length of the fifth sub-gate portion P05 in the second direction D2 can be larger than the length of the sixth sub-gate portion P06 in the second direction D2.

[0156] For example, the length of the lower insulating structure BDI in the second direction D2 can be about 1 nm or more (e.g., about 2 nm or more, about 3 nm or more, about 4 nm or more, or about 5 nm or more) longer than the length of the middle insulating structure MDI in the second direction D2.

[0157] Further, the length of the first to third sub-gate portions P01 to P03 of the lower gate structure LGE in the second direction D2 can be about 1 nm or more (e.g., about 2 nm or more, about 3 nm or more, about 4 nm or more, or about 5 nm or more) larger than the length of the fourth to sixth sub-gate portions P04 to P06 of the upper gate structure UGE in the second direction D2.

[0158] Next, an example of a method for manufacturing a semiconductor device according to some embodiments will be described with reference to Figures 5 to 30 Further, reference can be made to the above description of the semiconductor device. Figures 1 to 3

[0159] Figures 5 to 30 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to some embodiments. Figure 5 illustrates a cross-sectional view taken along the line X1-X1' and the line X2-X2' of Figure 1 Figure 6 illustrates a cross-sectional view taken along the line Y1-Y1' of Figure 1 At this time, a cross-sectional view cut along the line Y2-Y2' and the line Y3-Y3' of Figure 1 may be the same as Figure 6 and is omitted.

[0160] In Figure 5 and Figure 6 ​​In the embodiment, the first high-concentration sacrificial layer SCL1 can be stacked on the lower substrate 101, and the first to third low-concentration sacrificial layers SAL1 to SAL3 and the first and second active layers ACL1 and ACL2 can be alternately stacked on the first high-concentration sacrificial layer SCL1. In other words, the first high-concentration sacrificial layer SCL1, the first low-concentration sacrificial layer SAL1, the first active layer ACL1, the second low-concentration sacrificial layer SAL2, the second active layer ACL2, and the third low-concentration sacrificial layer SAL3 can be sequentially stacked. Further, the second dummy layer DSL2, the second high-concentration sacrificial layer SCL2, and the third dummy layer DSL3 can be sequentially stacked on the third low-concentration sacrificial layer SAL3.

[0161] Further, the fourth to sixth low-concentration sacrificial layers SAL4 to SAL6 and the third and fourth active layers ACL3 and ACL4 can be alternately stacked on the third dummy layer DSL3. In other words, the third dummy layer DSL3, the fourth low-concentration sacrificial layer SAL4, the third active layer ACL3, the fifth low-concentration sacrificial layer SAL5, the fourth active layer ACL4, and the sixth low-concentration sacrificial layer SAL6 can be sequentially stacked.

[0162] Further, the fourth dummy layer DSL4 can be stacked on the sixth low-concentration sacrificial layer SAL6.

[0163] The lower substrate 101 can be a semiconductor substrate including silicon, germanium, silicon germanium, or the like, or a compound semiconductor substrate. For example, the lower substrate 101 can be a silicon substrate.

[0164] The first to sixth low-concentration sacrificial layers SAL1 to SAL6 can include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the first to sixth low-concentration sacrificial layers SAL1 to SAL6 can include silicon germanium (SiGe), and the concentration of germanium (Ge) in each of the first to sixth low-concentration sacrificial layers SAL1 to SAL6 can be about 10 at% (atomic percent) to about 30 at%.

[0165] The first and second high-concentration sacrificial layers SCL1 and SCL2 can include silicon (Si) or silicon germanium (SiGe). When the first and second high-concentration sacrificial layers SCL1 and SCL2 include silicon germanium (SiGe), the concentration of germanium (Ge) in the first and second high-concentration sacrificial layers SCL1 and SCL2 can be greater than the concentration of germanium (Ge) in the first to sixth low-concentration sacrificial layers SAL1 to SAL6. For example, the concentration of germanium (Ge) in the first and second high-concentration sacrificial layers SCL1 and SCL2 can be about 40 at% to about 90 at%.

[0166] The first to fourth active layers ACL1-ACL4 can include another one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the first to fourth active layers ACL1-ACL4 can include silicon (Si).

[0167] The second to fourth dummy layers DSL2-DSL4 can include another one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the second to fourth dummy layers DSL2-DSL4 can include silicon (Si).

[0168] The first high-concentration sacrificial layer SCL1, the first low-concentration sacrificial layer SAL1, the first active layer ACL1, the second low-concentration sacrificial layer SAL2, the second active layer ACL2, the third low-concentration sacrificial layer SAL3, the second dummy layer DSL2, the second high-concentration sacrificial layer SCL2, the third dummy layer DSL3, the fourth low-concentration sacrificial layer SAL4, the third active layer ACL3, the fifth low-concentration sacrificial layer SAL5, the fourth active layer ACL4, the sixth low-concentration sacrificial layer SAL6, and the fourth dummy layer DSL4 can be patterned to form a stack pattern STP.

[0169] For example, the stack pattern STP can be formed by forming a first hard mask layer HML1 on the fourth dummy layer DSL4 at the uppermost portion and etching the stack layers on the lower substrate 101 using the first hard mask layer HML1 as an etching mask. At the same time of forming the stack pattern STP, an upper portion of the lower substrate 101 can be patterned to form a trench defining an active pattern AP1. The stack pattern STP can have a bar shape extending in the second direction D2.

[0170] The first hard mask layer HML1 can include SiCN, SiOCN, SiN, or a combination thereof. For example, the first hard mask layer HML1 can include a plurality of layers, each layer including SiCN, SiOCN, SiN, or a combination thereof.

[0171] The stack pattern STP can include a lower stack pattern STP1 on the active pattern AP1 and an upper stack pattern STP2 on the lower stack pattern STP1. The lower stack pattern STP1 can include the first to third low-concentration sacrificial layers SAL1-SAL3 and the first and second active layers ACL1-ACL2 alternately stacked. The upper stack pattern STP2 can include the fourth to sixth low-concentration sacrificial layers SAL4-SAL6 and the third and fourth active layers ACL3-ACL4 alternately stacked.

[0172] A trench-filling device isolation layer ST can be formed on the lower substrate 101. For example, an insulating layer can be formed on the entire surface of the lower substrate 101 covering the active pattern AP1 and the stack pattern STP. The insulating layer can be recessed until the stack pattern STP is exposed, thereby forming the device isolation layer ST. For example, the device isolation layer ST can expose the first low-concentration sacrificial layer SAL1 of the stack pattern STP while covering the first high-concentration sacrificial layer SCL1.

[0173] A seventh low-concentration sacrificial layer SAL7 covering the stack pattern STP can be formed on the device isolation layer ST. For example, a low-concentration sacrificial layer material is deposited on the stack pattern STP to form the seventh low-concentration sacrificial layer SAL7. The seventh low-concentration sacrificial layer SAL7 can cover the upper surface and two side surfaces of the stack pattern STP in the first direction D1. The seventh low-concentration sacrificial layer SAL7 can be conformally formed. In other words, a thickness of the seventh low-concentration sacrificial layer SAL7 on the upper surface of the stack pattern STP in the third direction D3 can be similar to a thickness of the seventh low-concentration sacrificial layer SAL7 on the side surface of the stack pattern STP in the first direction D1.

[0174] The seventh low-concentration sacrificial layer SAL7 can include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the seventh low-concentration sacrificial layer SAL7 can include silicon germanium (SiGe), and a concentration of germanium (Ge) in the seventh low-concentration sacrificial layer SAL7 can be about 10 at% to about 30 at%.

[0175] Figure 7 A cross-sectional view taken along lines X1-X1' and X2-X2' of FIG. 1A is illustrated according to some embodiments. Figure 1 A cross-sectional view taken along lines X1-X1' and X2-X2' of FIG. 1A is illustrated according to some embodiments. Figure 8 A cross-sectional view taken along line Y1-Y1' of FIG. 1A is illustrated according to some embodiments. At this time, cross-sectional views cut along lines Y2-Y2' and Y3-Y3' of FIG. 1A can be the same as Figure 1 A cross-sectional view taken along line Y1-Y1' of FIG. 1A is illustrated according to some embodiments. At this time, cross-sectional views cut along lines Y2-Y2' and Y3-Y3' of FIG. 1A can be the same as Figure 1 A cross-sectional view taken along line Y1-Y1' of FIG. 1A is illustrated according to some embodiments. At this time, cross-sectional views cut along lines Y2-Y2' and Y3-Y3' of FIG. 1A can be the same as Figure 8 A cross-sectional view taken along line Y1-Y1' of FIG. 1A is illustrated according to some embodiments. At this time, cross-sectional views cut along lines Y2-Y2' and Y3-Y3' of FIG. 1A can be the same as

[0176] In Figure 7 and Figure 8 , after etching back the device isolation layer ST until the lower substrate 101 is exposed, a spacer pattern 150 is formed in the space between the stack patterns STP. For example, the spacer pattern 150 can be formed by filling an insulating material in the space between the stack patterns STP and planarizing the insulating material until the first hard mask layer HML1 is exposed. The planarization of the insulating material can be performed using an etch-back process or a chemical mechanical polishing (CMP) process.

[0177] During the planarization process, the seventh low-concentration sacrificial layer SAL7 located on the upper surface of the stack pattern STP can be removed, leaving only the seventh low-concentration sacrificial layer SAL7 located on the side surface of the stack pattern STP. In addition, during the planarization process, the first hard mask layer HML1 can be completely removed or partially remain.

[0178] As a result, the separation wall pattern 150 can extend in the third direction D3 from a level lower than the upper surface of the active pattern AP1 to a level higher than the upper surface of the sixth low-concentration sacrificial layer SAL6 of the upper stack pattern STP2. For example, the lower surface of the separation wall pattern 150 can be coplanar with the upper surface of the lower substrate 101, and the upper surface of the separation wall pattern 150 can be coplanar with the upper surface of the fourth dummy layer DSL4 and the lower surface of the first hard mask layer HML1.

[0179] A second hard mask layer HML2 can be formed on the upper surface of the separation wall pattern 150 and in the space between the stack patterns STP. For example, the second hard mask layer HML2 can be formed on the upper surface of the separation wall pattern 150 and the upper surface of the stack pattern STP, and the second hard mask layer HML2 can be planarized until the first hard mask layer HML1 is exposed. The planarization of the second hard mask layer HML2 can be performed using an etch-back process or a CMP (chemical mechanical polishing) process.

[0180] The second hard mask layer HML2 can include SiCN, SiOCN, SiN, or a combination thereof. For example, the second hard mask layer HML2 can include a plurality of layers, each layer including SiCN, SiOCN, SiN, or a combination thereof.

[0181] A first etch stop layer ESL1 can be conformally formed on the first hard mask layer HML1 and the second hard mask layer HML2. The first etch stop layer ESL1 can cover the upper surface of the separation wall pattern 150 and the upper surface of the stack pattern STP.

[0182] Figure 9 shows a cross-sectional view taken along lines X1-X1' and X2-X2' of Figure 1 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of Figure 10 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of Figure 1 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of

[0183] In Figure 9 and Figure 10In some embodiments, a plurality of sacrificial patterns PP can be formed across the stack pattern STP. Each of the sacrificial patterns PP can be formed in a line shape extending in the first direction D1. For example, the sacrificial patterns PP can be formed by forming a sacrificial layer on the first etch stop layer ESL1, forming a hard mask pattern on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern as an etch mask. The sacrificial layer can include amorphous silicon or polysilicon.

[0184] A pair of gate spacers GS can be formed on two side surfaces of the sacrificial patterns PP in the second direction D2. For example, a spacer layer can be conformally formed on the entire surface of the first etch stop layer ESL1 and the sacrificial patterns PP. The spacer layer can cover the first etch stop layer ESL1 and the sacrificial patterns PP. For example, the spacer layer can include SiCN, SiOCN, SiN, or a combination thereof.

[0185] Figure 11 shows cross-sectional views taken along lines X1-X1' and X2-X2' of FIG. 1A, in accordance with some embodiments. Figure 1 shows cross-sectional views taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 1A, in accordance with some embodiments. Figure 12 shows cross-sectional views taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 1A, in accordance with some embodiments. Figure 1

[0186] In Figure 11 and Figure 12 An etching process can be performed on the stack pattern STP using the gate spacers GS and the sacrificial patterns PP as etch masks.

[0187] For example, by the etching process, the first high-concentration sacrificial layer SCL1, the first low-concentration sacrificial layer SAL1, the first active layer ACL1, the second low-concentration sacrificial layer SAL2, the second active layer ACL2, the third low-concentration sacrificial layer SAL3, the second dummy layer DSL2, the second high-concentration sacrificial layer SCL2, the third dummy layer DSL3, the fourth low-concentration sacrificial layer SAL4, the third active layer ACL3, the fifth low-concentration sacrificial layer SAL5, the fourth active layer ACL4, the sixth low-concentration sacrificial layer SAL6, and the fourth dummy layer DSL4 of the stack can be patterned to form a lower channel pattern LCH1 and an upper channel pattern UCH1.

[0188] The lower channel pattern LCH1 can include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked in the third direction D3 and spaced apart from each other, and the upper channel pattern UCH1 can include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked in the third direction D3 and spaced apart from each other.

[0189] ​Meanwhile, the first to third low-concentration sacrificial layers SAL1 to SAL3 can be alternately stacked with the first and second semiconductor patterns SP1 and SP2 of the lower channel pattern LCH1, and the fourth to sixth low-concentration sacrificial layers SAL4 to SAL6 can be alternately stacked with the third and fourth semiconductor patterns SP3 and SP4 of the upper channel pattern UCH1.

[0190] In addition, the second to fourth dummy layers DSL2 to DSL4 can also be patterned to form the second to fourth dummy channel patterns DS2 to DS4, respectively.

[0191] In addition, the first and second hard mask layers HML1 and HML2 can also be patterned to form the first and second hard masks HM1 and HM2, respectively.

[0192] Accordingly, the first recess ET1 can be formed between the lower channel patterns LCH1 and between the upper channel patterns UCH1.

[0193] Figure 13 shows a cross-sectional view taken along lines X1-X1' and X2-X2' of Figure 1 , according to some embodiments. Figure 14 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of Figure 1 , according to some embodiments.

[0194] Referring to Figure 13 and Figure 14 , a portion of two side surfaces of the first to sixth low-concentration sacrificial layers SAL1 to SAL6 exposed in the second direction D2 by the first recess ET1 can be removed, and a gate inner spacer GIS can be formed in the removed space.

[0195] For example, an indent (or recess) process is performed on the first to sixth low-concentration sacrificial layers SAL1 to SAL6. In the indent process, the first to sixth low-concentration sacrificial layers SAL1 to SAL6 are etched using a wet etching method or a dry etching method, thereby reducing the length of the first to sixth low-concentration sacrificial layers SAL1 to SAL6 in the second direction D2.

[0196] At this time, the etchant used in the indentation process has selectivity to the first to sixth low-concentration sacrificial layers SAL1 to SAL6 compared to the first and second high-concentration sacrificial layers SCL1 and SCL2, so that the first and second high-concentration sacrificial layers SCL1 and SCL2 are not etched, and only the first to sixth low-concentration sacrificial layers SAL1 to SAL6 are etched.

[0197] Meanwhile, the seventh low-concentration sacrificial layer SAL7 covering both side surfaces of the lower channel pattern LCH1 and the upper channel pattern UCH1 in the first direction D1 is also partially removed in the second direction D2 by the indentation process, and the length of the seventh low-concentration sacrificial layer SAL7 is reduced in the second direction D2.

[0198] Next, a low-k material can be filled in the space in which the first to seventh low-concentration sacrificial layers SAL1 to SAL7 are partially removed by the indentation process to form the gate inner spacer GIS. For example, a stacked portion IS1 of the gate inner spacer GIS can be formed in the space in which a portion of the first to sixth low-concentration sacrificial layers SAL1 to SAL6 is removed, and a non-stacked portion IS2 of the gate inner spacer GIS can be formed in the space in which a portion of the seventh low-concentration sacrificial layer SAL7 is removed.

[0199] The low-k material can be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process.

[0200] Figure 15 shows a cross-sectional view taken along lines X1-X1' and X2-X2' of Figure 1 according to some embodiments. Figure 16 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of Figure 1 according to some embodiments.

[0201] In Figure 15 and Figure 16 , the first and second high-concentration sacrificial layers SCL1 and SCL2 exposed by the first recess ET1 can be selectively removed, and a lower insulating structure BDI and an intermediate insulating structure MDI can be formed in the removed space, respectively.

[0202] For example, wet etching or dry etching methods can be used to remove the first high-concentration sacrificial layer SCL1 and the second high-concentration sacrificial layer SCL2. In this case, the etchant used to etch the first high-concentration sacrificial layer SCL1 and the second high-concentration sacrificial layer SCL2 has selectivity for the first high-concentration sacrificial layer SCL1 and the second high-concentration sacrificial layer SCL2 compared with the first low-concentration sacrificial layers SAL1 to the sixth low-concentration sacrificial layers SAL6, so that only the first high-concentration sacrificial layer SCL1 and the second high-concentration sacrificial layer SCL2 can be etched without etching the first low-concentration sacrificial layers SAL1 to the sixth low-concentration sacrificial layers SAL6.

[0203] Next, insulating material can be filled into the spaces where the first high-concentration sacrificial layer SCL1 and the second high-concentration sacrificial layer SCL2 have been removed, to form the lower insulation structure BDI and the intermediate insulation structure MDI, respectively.

[0204] Atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes can be used to deposit insulating materials.

[0205] Figure 17 The following is shown according to some implementation methods. Figure 1 A sectional view taken by lines X1-X1' and X2-X2'. Figure 18 The following is shown according to some implementation methods. Figure 1 The sectional views taken by lines Y1-Y1', Y2-Y2', and Y3-Y3'.

[0206] exist Figure 17 and Figure 18 In this process, a lower source / drain pattern LSD1, a buried insulating layer SDI, and an upper source / drain pattern USD1 can be formed within the first recess ET1.

[0207] First, a lower source / drain pattern LSD1 can be formed within the first recess ET1. For example, a selective epitaxial growth (SEG) process can be performed using the exposed side surface of the lower channel pattern LCH1 and the upper surface of the active pattern AP1 as seed layers to form the lower source / drain pattern LSD1. The lower source / drain pattern LSD1 can be grown using the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the active pattern AP1 exposed by the first recess ET1 as seeds. For example, the selective epitaxial growth (SEG) process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0208] During a selective epitaxial growth (SEG) process, impurities can be in-situ implanted into the lower source / drain patterns LSD1. As another example, after the lower source / drain patterns LSD1 are formed, impurities can be implanted into the lower source / drain patterns LSD1. The lower source / drain patterns LSD1 can be doped to have a first conductivity type (e.g., N-type).

[0209] At this time, although not shown, in some embodiments, the side surfaces of the upper stack pattern STP2 can be covered by the liner layer. In other words, during the selective epitaxial growth (SEG) process of the lower source / drain patterns LSD1, the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper stack pattern STP2 can not be exposed by the liner layer. Thus, during the selective epitaxial growth (SEG) process, a separate semiconductor layer can not be grown on the upper channel pattern UCH1.

[0210] The first semiconductor pattern SP1 and the second semiconductor pattern SP2 disposed between the pair of lower source / drain patterns LSD1 can form a lower channel pattern LCH1. The lower channel pattern LCH1 and the lower source / drain patterns LSD1 can form a first active region AR1 that is a bottom layer of a three-dimensional device.

[0211] A buried insulating layer SDI can be formed within the first recess ET1. For example, the buried insulating layer SDI can fill the first recess ET1 to a level that covers the third dummy channel pattern DS3.

[0212] Next, the liner layer is removed so that two side surfaces of the upper channel pattern UCH1 can be exposed by the first recess ET1.

[0213] Upper source / drain patterns USD1 can be formed between the upper channel patterns UCH1 within the first recess ET1. For example, the upper source / drain patterns USD1 can be formed by performing a selective epitaxial growth (SEG) process using the exposed side surfaces of the upper stack pattern STP2 as seed layers. The upper source / drain patterns USD1 can be grown using the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 exposed by the first recess ET1 as seeds. For example, the selective epitaxial growth (SEG) process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0214] During the selective epitaxial growth (SEG) process, impurities can be in-situ implanted into the upper source / drain patterns USD1. As another example, after the upper source / drain patterns USD1 are formed, impurities can be implanted into the upper source / drain patterns USD1. The upper source / drain patterns USD1 can be doped to have a second conductivity type (e.g., P-type) that is different from the first conductivity type (e.g., N-type) of the lower source / drain patterns LSD1.

[0215] A third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 disposed between a pair of upper source / drain patterns USD1 can form an upper channel pattern UCH1. The upper channel pattern UCH1 and the upper source / drain patterns USD1 can form a second active region AR2 as a top layer of a three-dimensional device.

[0216] A second interlayer insulating layer 120 can be formed on the upper source / drain patterns USD1 and the spacer patterns 150. For example, the second interlayer insulating layer 120 can be formed by depositing an insulating material on the upper source / drain patterns USD1 and the spacer patterns 150, and the second interlayer insulating layer 120 can be planarized until the upper surfaces of the sacrificial patterns PP are exposed.

[0217] The insulating material can be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. The planarization of the second interlayer insulating layer 120 can be performed using an etch-back process or a CMP (chemical mechanical polishing) process. During the planarization process, the hard mask patterns can be completely removed. As a result, the upper surface of the second interlayer insulating layer 120 can be coplanar with the upper surface of the sacrificial patterns PP and the upper surface of the gate spacers GS.

[0218] Figure 19 FIG. 6 illustrates cross-sectional views taken along lines X1-X1' and X2-X2' of FIG. 5, according to some embodiments. Figure 1 FIG. 7 illustrates cross-sectional views taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 6, according to some embodiments. Figure 20 FIG. 8 illustrates cross-sectional views taken along lines X1-X1' and X2-X2' of FIG. 7, according to some embodiments. Figure 1 FIG. 9 illustrates cross-sectional views taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 8, according to some embodiments.

[0219] In FIGS. 10 and 11, a gate cut pattern CT can be formed that penetrates the sacrificial patterns PP. For example, the exposed sacrificial patterns PP can be selectively removed using a hard mask, and for example, a portion of the sacrificial patterns PP located on the spacer patterns 150 can be removed. Figure 19 Figure 20 The length of the removed sacrificial patterns PP in the first direction D1 can be substantially the same as the length of the spacer patterns 150 in the first direction D1. The length of the removed sacrificial patterns PP in the second direction D2 can be substantially the same as the length of the first hard mask HM1 in the second direction D2. Thus, the connection of the main gate electrode structure MGE can be cut by the gate cut pattern CT on the spacer patterns 150.

[0220] The removal of the sacrificial patterns PP can be accomplished by wet etching using an etchant that selectively etches polysilicon. By removing the sacrificial patterns PP, the second hard mask HM2 located on the spacer patterns 150 can be exposed.

[0221] The removal of the sacrificial patterns PP can be accomplished by wet etching using an etchant that selectively etches polysilicon. By removing the sacrificial patterns PP, the second hard mask HM2 located on the spacer patterns 150 can be exposed. ​

[0222] The insulating material can be filled in the space where the sacrificial pattern PP has been removed to form a gate cut pattern CT. The insulating material can be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process.

[0223] Figure 21 shows a cross-sectional view taken along lines X1-X1' and X2-X2' of FIG. 1A, according to some embodiments. Figure 1 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 1A, according to some embodiments. Figure 22 shows a cross-sectional view taken along lines X1-X1' and X2-X2' of FIG. 1A, according to some embodiments. Figure 1 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 1A, according to some embodiments.

[0224] In Figure 21 and Figure 22 , the exposed sacrificial pattern PP, as well as the first hard mask HM1 and the second hard mask HM2, can be selectively removed, and a second recess ET2 can be formed. The removal of the sacrificial pattern PP can be accomplished by a wet etch using an etchant that selectively etches polysilicon. By removing the sacrificial pattern PP, as well as the first hard mask HM1 and the second hard mask HM2, the first low-concentration sacrificial layer SAL1 through the seventh low-concentration sacrificial layer SAL7 can be exposed.

[0225] By performing an etching process that selectively etches the first low-concentration sacrificial layer SAL1 through the seventh low-concentration sacrificial layer SAL7 exposed by the second recess ET2, only the first low-concentration sacrificial layer SAL1 through the seventh low-concentration sacrificial layer SAL7 can be removed, while leaving the first semiconductor pattern SP1 through the fourth semiconductor pattern SP4 and the second dummy channel pattern DS2 through the fourth dummy channel pattern DS4 intact. The etching process can have a high etch rate for silicon germanium. For example, the etching process can have a high etch rate for silicon germanium having a germanium concentration greater than about 10 at%.

[0226] Figure 23 shows a cross-sectional view taken along lines X1-X1' and X2-X2' of FIG. 1A, according to some embodiments. Figure 1 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 1A, according to some embodiments. Figure 24 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 1A, according to some embodiments. Figure 1 shows a cross-sectional view taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of FIG. 1A, according to some embodiments.

[0227] In Figure 23 and Figure 24 , a gate pattern GE can be formed within the region where the sacrificial pattern PP and the first low-concentration sacrificial layer SAL1 through the seventh low-concentration sacrificial layer SAL7 have been removed.

[0228] First, in some embodiments, a gate insulating layer may be conformally formed in the region where the sacrificial pattern PP and the first low-concentration sacrificial layers SAL1 to the seventh low-concentration sacrificial layers SAL7 have been removed.

[0229] A gate pattern GE can be formed on the gate insulating layer. The gate pattern GE can be formed by forming a lower gate structure LGE including a first sub-gate portion P01 to a third sub-gate portion P03 between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, forming an upper gate structure UGE including a fourth sub-gate portion P04 to a sixth sub-gate portion P06 between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and forming a main gate structure MGE in the region where the sacrificial pattern PP has been removed.

[0230] The gate pattern GE can be recessed to reduce its height. A gate overlay pattern GP can be formed on the recessed gate pattern GE. A planarization process can be performed on the gate overlay pattern GP so that the upper surface of the gate overlay pattern GP is coplanar with the upper surface of the second interlayer insulating layer 120.

[0231] Figure 25 The following is shown according to some implementation methods. Figure 1 A sectional view taken by lines X1-X1' and X2-X2'. Figure 26 The following is shown according to some implementation methods. Figure 1 The sectional views taken by lines Y1-Y1', Y2-Y2', and Y3-Y3'.

[0232] exist Figure 25 and Figure 26 In this process, an upper source / drain contact aCA is formed that is connected to the upper source / drain pattern USD1, and an upper gate contact aCB is formed that is connected to the main gate structure MGE of the gate pattern GE. For example, a hard mask pattern is formed on the second interlayer insulating layer 120, and the second interlayer insulating layer 120 is patterned using the hard mask pattern as an etching mask, thereby forming a first contact hole penetrating the second interlayer insulating layer 120 in the third direction D3 on the upper surface of the upper source / drain pattern USD1. For example, the patterning can be performed using dry etching.

[0233] In addition, a second contact hole is formed, which penetrates the gate cover pattern GP on the third direction D3 to expose the upper surface of the main gate structure MGE of the gate pattern GE.

[0234] Metal is filled into the first contact hole and the second contact hole to form an upper source / drain contact aCA connected to the upper source / drain pattern USD1 in the first contact hole, and an upper gate contact aCB connected to the main gate structure MGE connected to the gate pattern GE in the second contact hole.

[0235] In the above, a case where the upper source / drain contact aCA and the upper gate contact aCB are formed in separate processes has been described, but the present disclosure is not limited thereto, and the upper source / drain contact aCA and the upper gate contact aCB can be formed simultaneously, or the upper gate contact aCB can be formed first, and then the upper source / drain contact aCA can be formed.

[0236] In some embodiments, a first upper interlayer insulating layer and a first upper metal layer electrically connected to the upper source / drain contact aCA and the upper gate contact aCB can be formed on the upper surface of the second interlayer insulating layer 120.

[0237] Figure 27 shows cross-sectional views taken along lines X1-X1' and X2-X2' of Figure 1 shows cross-sectional views taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of Figure 28 shows cross-sectional views taken along lines X1-X1' and X2-X2' of Figure 1 shows cross-sectional views taken along lines Y1-Y1', Y2-Y2', and Y3-Y3' of

[0238] In Figure 27 and Figure 28 the lower substrate 101 is removed.

[0239] First, the semiconductor device can be rotated.

[0240] For example, in some embodiments, the rotated semiconductor device can be positioned on a carrier substrate. At this time, the upper surface of the semiconductor device can be positioned to face the carrier substrate, and then the upper surface of the semiconductor device can be attached to the carrier substrate. That is, the first upper interlayer insulating layer located on the upper surface of the semiconductor device can be attached on the carrier substrate. An adhesive material or an adhesive member can be placed between the first upper interlayer insulating layer and the carrier substrate.

[0241] The carrier substrate can have an area substantially the same as that of the semiconductor device or can have a larger area. The carrier substrate can be, for example, a semiconductor wafer, a ceramic substrate, or a glass substrate. The adhesive member can be in the form of a film.

[0242] The adhesive member can include a base film and an adhesive layer attached to both sides of the base film. The base film can be, for example, a polyester-based film such as polyethylene terephthalate (PET) or polyethylene 2,6-naphthalate (PEN) or a polyolefin-based film. The base film can be formed by coating a polyester film or a polyolefin film with silicone or Teflon (tetrafluoroethylene). The adhesive layer can be made of, for example, an acrylic polymer resin, an epoxy resin, or a mixture thereof.

[0243] Next, an etching process can be performed to remove the lower substrate 101. The etching process can be performed by, for example, a wet etching method, but is not limited thereto.

[0244] As the lower base 101 is removed, the lower surface of the spacer wall pattern 150 can be exposed. Thus, by utilizing the exposed spacer wall pattern 150, the lower source / drain contact bCA and the lower gate contact bCB can be formed by self-alignment without additional structures such as a placeholder.

[0245] Further, since the gate inner spacer GIS extends to one spacer wall pattern 150 in the first direction D1 and another spacer wall pattern 150 adjacent to the one spacer wall pattern 150 in the first direction D1, the gate inner spacer GIS is located on the entire surface of the gate pattern GE opposite to the lower source / drain pattern LSD1 and the upper source / drain pattern USD1, and the lower portion of the gate pattern GE is protected by the lower insulating structure BDI, thus it is possible to prevent the gate pattern GE from being damaged when the lower source / drain contact bCA is formed.

[0246] Figure 29 shows a cross-sectional view taken along the line X1-X1' and the line X2-X2' of FIG. 1A according to some embodiments. Figure 1 shows a cross-sectional view taken along the line Y1-Y1', the line Y2-Y2', and the line Y3-Y3' of FIG. 1A according to some embodiments. Figure 30 shows a cross-sectional view taken along the line X1-X1' and the line X2-X2' of FIG. 1A according to some embodiments. Figure 1 shows a cross-sectional view taken along the line Y1-Y1', the line Y2-Y2', and the line Y3-Y3' of FIG. 1A according to some embodiments.

[0247] In Figure 29 and Figure 30 , the lower source / drain contact bCA connected to the lower source / drain pattern LSD1 is formed, and the lower gate contact bCB connected to the lower gate structure LGE of the gate pattern GE is formed. For example, a patterning process can be performed to remove a portion of the active pattern AP1 to form a third contact hole exposing the lower source / drain pattern LSD1. At this time, the third contact hole can penetrate the active pattern AP1. In other words, the side surface of the third contact hole can be surrounded by the active pattern AP1.

[0248] Next, the third contact hole is filled to form the lower source / drain contact bCA electrically connected to the lower source / drain pattern LSD1.

[0249] Next, a patterning process can be performed to remove a portion of the active pattern AP1 to form a fourth contact hole exposing the first sub-gate portion P01 of the gate pattern GE. At this time, the fourth contact hole can penetrate the active pattern AP1. In other words, the side surface of the fourth contact hole can be surrounded by the active pattern AP1.

[0250] Next, the insulating liner CBL is conformally applied to the side surface of the fourth contact hole, and then the fourth contact hole is filled to form the lower gate contact bCB electrically connected to the first sub-gate portion P01 of the gate pattern GE.

[0251] In the above, a case where the lower source / drain contact bCA and the lower gate contact bCB are formed in separate processes has been described, but the present disclosure is not limited thereto, and the lower source / drain contact bCA and the lower gate contact bCB can be formed at the same time, or the lower gate contact bCB can be formed first, and then the lower source / drain contact bCA can be formed.

[0252] In some embodiments, a first lower interlayer insulating layer and a first lower metal layer electrically connected to the lower source / drain contact bCA and the lower gate contact bCB can be formed on the active pattern AP1 and the lower surface of the device isolation layer ST.

[0253] While the present disclosure includes many specific implementation details, these implementation details should not be construed as limiting the scope of what can be claimed, equivalents, and the appended claims. Certain features that are described in the context of separate embodiments in this disclosure also can be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment also can be implemented separately or in any suitable subcombination. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a combination can in some cases be deleted from the combination, and the combination can be directed to subcombinations or variations of subcombinations.

Claims

1. A semiconductor device, comprising: The active patterns are spaced apart from each other in a first direction and extend in a second direction different from the first direction; The lower channel pattern and the lower source / drain pattern are arranged alternately in the second direction on the active pattern. The upper groove pattern is above the lower groove pattern; The upper source / drain pattern is on the lower source / drain pattern; Gate pattern, on the active pattern and on the lower channel pattern and the upper channel pattern; and The gate spacer is located between the gate pattern and the lower source / drain pattern and the upper source / drain pattern; The gate spacer has a stacked portion and a non-stacked portion. The stacked portion is stacked with the upper channel pattern and the lower channel pattern in a third direction perpendicular to the first direction and the second direction. The non-stacked portion is not stacked with the upper channel pattern and the lower channel pattern in a third direction.

2. The semiconductor device according to claim 1, in, The lower channel pattern and the upper channel pattern comprise multiple semiconductor patterns stacked upwards and spaced apart from each other. The stacked portions of the gate spacers are located between adjacent semiconductor patterns in the plurality of semiconductor patterns, and The non-overlapping portion of the gate spacer is located on the side of the plurality of semiconductor patterns in a first direction, and extends in a third direction from the first semiconductor pattern located at the lowermost end of the non-overlapping portion of the plurality of semiconductor patterns to the second semiconductor pattern located at the uppermost end of the non-overlapping portion of the plurality of semiconductor patterns.

3. The semiconductor device according to claim 2, in, The semiconductor device further includes: Device separation layer, located on the side of the active pattern in the first direction; The first hard mask is on the upper channel pattern; and Etch stop layer on the first hard mask. In this process, the non-stacked portion of the gate spacer extends from the upper surface of the device separation layer to the lower surface of the etch stop layer in a third-order direction.

4. The semiconductor device according to claim 2, further comprising: The partition wall pattern includes a plurality of partition walls spaced apart from each other in a first direction, extending in a second direction, and arranged alternately with the active pattern in the first direction. The gate spacer extends in a first direction from a first partition wall among the plurality of partition walls to another partition wall among the plurality of partition walls that is adjacent to the first partition wall in the first direction.

5. The semiconductor device according to claim 4, in, The stacked portion of the gate spacer is between the first spacer wall and the other spacer wall. The non-stacked portion of the gate spacer is located between the stacked portion and the first spacer wall, and between the stacked portion and the other spacer wall. The overlapping portion is spaced apart from the partition wall pattern, and Among them, the non-overlapping part contacts the partition wall pattern.

6. The semiconductor device according to claim 2, wherein, Gate patterns include: A lower gate structure on an active pattern, wherein the lower gate structure includes a plurality of lower sub-gate portions between adjacent semiconductor patterns in the plurality of semiconductor patterns; An upper gate structure on a lower gate structure, wherein the upper gate structure includes a plurality of upper sub-gate portions located between adjacent semiconductor patterns in the plurality of semiconductor patterns; The main gate structure is located on the upper gate structure; and The sub-gate connection portion is located on the side surface of the plurality of lower sub-gate portions and the plurality of upper sub-gate portions in the first direction. The sub-gate connection portion extends, in a third-order direction, from the lower sub-gate portion located at the lowest end of the plurality of lower sub-gate portions to the upper sub-gate portion located at the highest end of the plurality of upper sub-gate portions, and... The sub-gate connection portion is not superimposed on the upper and lower channel patterns in the third direction.

7. The semiconductor device according to claim 6, in, The semiconductor device further includes: a partition wall pattern comprising a plurality of partition walls spaced apart from each other in a first direction, extending in a second direction, and arranged alternately with the active pattern in the first direction; The gate pattern extends in a first direction from a first partition wall among the plurality of partition walls to another partition wall among the plurality of partition walls that is adjacent to the first partition wall in the first direction.

8. The semiconductor device according to claim 7, in, The plurality of lower sub-gate portions and the plurality of upper sub-gate portions of the gate pattern are located between the first partition wall and the other partition wall, and the sub-gate connection portion is located between the plurality of lower sub-gate portions and the plurality of upper sub-gate portions and the first partition wall, and between the plurality of lower sub-gate portions and the plurality of upper sub-gate portions and the other partition wall. Wherein, the plurality of lower sub-gate portions and the plurality of upper sub-gate portions do not contact the partition wall pattern, and The sub-gate connection portion contacts the partition wall pattern.

9. The semiconductor device according to claim 6, wherein, The semiconductor device further includes: The lower insulating structure is located between the active pattern and the lower gate structure; and An intermediate insulating structure is located between the lower gate structure and the upper gate structure.

10. The semiconductor device according to claim 9, in, The lower insulating structure and the intermediate insulating structure are stacked in a third-party direction with the stacked portions of the lower channel pattern, the upper channel pattern, the upper gate structure and the lower gate structure of the gate pattern, and the gate spacers. Among them, the lower insulating structure and the intermediate insulating structure are not stacked with the sub-gate connection portion of the gate pattern and the non-stacked portion of the gate spacer in the third direction.

11. The semiconductor device according to claim 9, in, The length of the lower insulation structure in the second direction is greater than the length of the middle insulation structure in the second direction, and In this configuration, the length of the plurality of lower sub-gate portions of the lower gate structure in the second direction is greater than the length of the plurality of upper sub-gate portions of the upper gate structure in the second direction.

12. A semiconductor device, comprising: The active patterns are spaced apart from each other in a first direction and extend in a second direction different from the first direction; The lower channel pattern and the lower source / drain pattern are arranged alternately in the second direction on the active pattern. The upper channel pattern and the upper source / drain pattern are located on the lower channel pattern, and the upper source / drain pattern is located on the lower source / drain pattern. Gate patterns are found on active patterns, lower channel patterns, and upper channel patterns; Lower source / drain contacts are located below the lower source / drain pattern and connected to the lower source / drain pattern; and The partition wall pattern includes partition walls spaced apart from each other in a first direction, extending across the gate pattern in a second direction, and alternately disposed with the active pattern in the first direction; In the third direction perpendicular to the first and second directions, the partition wall extends from a level lower than the upper surface of the lower source / drain contact to a level lower than the upper surface of the gate pattern.

13. The semiconductor device according to claim 12, wherein, Gate patterns include: A lower gate structure is on an active pattern and includes a plurality of lower sub-gate portions between semiconductor patterns included in a lower channel pattern. An upper gate structure, on a lower gate structure, and including a plurality of upper sub-gate portions, said plurality of upper sub-gate portions being spaced between semiconductor patterns included in an upper channel pattern; and The main gate structure is located on the upper gate structure.

14. The semiconductor device according to claim 13, in, A partition wall is located between one gate structure and the other gate structure in the lower and upper gate structures, wherein the other gate structure is adjacent to the first gate structure in a first direction. Wherein, at least one of the plurality of lower sub-gate portions, the plurality of upper sub-gate portions, and the sub-gate connection portions located on the sides of the plurality of lower sub-gate portions and the plurality of upper sub-gate portions is separated from another portion of the plurality of lower sub-gate portions, the plurality of upper sub-gate portions, and the sub-gate connection portions by a partition wall pattern, and the other portion of the plurality of lower sub-gate portions, the plurality of upper sub-gate portions, and the sub-gate connection portions is adjacent to at least one portion of the plurality of lower sub-gate portions, the plurality of upper sub-gate portions, and the sub-gate connection portions in a first direction.

15. The semiconductor device according to claim 14, wherein, Gate patterns also include: The main gate connection portion, on any of the partition walls, The main gate structure includes a first main gate structure and a second main gate structure that are spaced apart from each other in a first direction, with one of the partition walls located therebetween. The first main gate structure and the second main gate structure are connected through the main gate connection portion.

16. The semiconductor device according to claim 14, wherein, The semiconductor device further includes: A second hard mask and a gate dicing pattern, the second hard mask being on one of the partition walls, and the gate dicing pattern being on the second hard mask, and In this configuration, a main gate structure and another main gate structure, which are spaced apart in a first direction and have one of the partition walls placed between them, are separated by a gate cutting pattern.

17. The semiconductor device according to claim 14, in, The lower source / drain pattern includes multiple lower source / drain patterns. The partition wall is located between the first lower source / drain pattern in the plurality of lower source / drain patterns and the second lower source / drain pattern that is adjacent to the first lower source / drain pattern in a first direction. The upper source / drain pattern includes multiple upper source / drain patterns. The partition wall is located between the first source / drain pattern in the plurality of source / drain patterns and the second source / drain pattern that is adjacent to the first source / drain pattern in the first direction among the plurality of source / drain patterns. The lower gate structure includes multiple lower gate structures. The partition wall is located between the first lower gate structure and the second lower gate structure that is adjacent to the first lower gate structure in a first direction among the plurality of lower gate structures. The upper gate structure includes multiple upper gate structures, and The partition wall is located between the first upper gate structure in the plurality of upper gate structures and the second upper gate structure in the plurality of upper gate structures that is adjacent to the first upper gate structure in a first direction.

18. The semiconductor device according to claim 14, in, The semiconductor device further includes: a lower gate contact located below the gate pattern and connected to the gate pattern. The lower source / drain contact includes multiple lower source / drain contacts. The partition wall is located between the first lower source / drain contact among the plurality of lower source / drain contacts and the second lower source / drain contact among the plurality of lower source / drain contacts that is adjacent to the first lower source / drain contact in a first direction. The lower gate contact includes multiple lower gate contacts, and The partition wall is located between the first lower gate contact among the plurality of lower gate contacts and the second lower gate contact among the plurality of lower gate contacts that is adjacent to the first lower gate contact in a first direction.

19. A semiconductor device, comprising: The active patterns are spaced apart from each other in a first direction and extend in a second direction different from the first direction; The lower channel pattern and the lower source / drain pattern are arranged alternately on the active pattern in the second direction; The upper groove pattern is above the lower groove pattern; The upper source / drain pattern is on the lower source / drain pattern; Gate pattern, on the active pattern and on the lower channel pattern and the upper channel pattern; The gate spacer is located between the gate of the gate pattern and the lower source / drain pattern and the upper source / drain pattern, and has a stacked portion and a non-stacked portion. The stacked portion is stacked with the upper channel pattern and the lower channel pattern in a third direction perpendicular to the first direction and the second direction, and the non-stacked portion is not stacked with the upper channel pattern and the lower channel pattern in a third direction. as well as The partition wall pattern includes a plurality of partition walls spaced apart from each other in a first direction, extending in a second direction, and arranged alternately with the active pattern in the first direction; In this configuration, the lower source / drain pattern and the upper source / drain pattern are surrounded by a partition wall pattern on their side surfaces in the first direction, and The lower source / drain pattern and the upper source / drain pattern are surrounded on the side surfaces in the second direction by the stacked and non-stacked portions of the gate spacers.

20. The semiconductor device according to claim 19, in, The semiconductor device further includes: Lower source / drain contacts are located below the lower source / drain pattern and connected to the lower source / drain pattern; and The lower insulating structure is located between the active pattern and the gate pattern, and In this configuration, between the lower source / drain contact and the gate pattern, a lower insulating structure extends upward in a third direction, and the stacked and non-stacked portions of the gate spacer extend in a second direction, such that the gate pattern does not contact the lower source / drain contact.

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