Stacked semiconductor device

Abstract

There is provided a semiconductor device including: a first source / drain pattern at a first level; a second source / drain pattern at a second level vertically different from the first level; and a first contact structure on the first source / drain pattern, wherein a portion of the first source / drain pattern is in a first recess of the first contact structure.

Description

TECHNICAL FIELD

[0001] Apparatuses and methods consistent with the present disclosure relate to a stacked semiconductor device including a bottom isolation layer. BACKGROUND

[0002] In response to an increasing demand for integrated circuits with high device density and performance, stacked semiconductor devices have been introduced. A stacked semiconductor device can include a first transistor at a first level and a second transistor at a second level vertically above the first level, where each of the two transistors can be a fin field effect transistor (FinFET), a nanosheet transistor, a fork transistor, or any other type of transistor.

[0003] A FinFET has one or more horizontally arranged vertical fin structures as a channel structure, at least three surfaces of which are surrounded by a gate structure, a nanosheet transistor is characterized by one or more nanosheet layers as a channel structure vertically stacked or arranged on a substrate, and a gate structure surrounding all four surfaces of each nanosheet layer. The nanosheet transistor is referred to as a gate-all-around (GAA) transistor or a multi-bridge-channel field effect transistor (MBCFET). A fork transistor is a combination of two nanosheet transistors with an isolation wall therebetween. The nanosheet layer of each nanosheet transistor is formed on each side of the isolation wall and passes through the gate structure in parallel with the isolation wall.

[0004] In addition to the stacked semiconductor device, a backside power distribution network (BSPDN) for a semiconductor device has been introduced to address congestion of signal lines and power rails at a front side of the semiconductor device. The BSPDN can help to reduce contact resistance between circuit elements formed at the front side of the semiconductor device. Here, the front side refers to a side on which transistors are formed with respect to a top surface of a substrate, and the back side refers to a side opposite to the front side. The BSPDN is formed on the back side of the semiconductor device and can include a backside metal line (such as a buried power rail) and a backside contact structure formed on a bottom surface of a source / drain pattern of a field effect transistor (such as a nanosheet transistor or a FinFET). The backside metal line can connect the backside contact structure to a voltage source or another circuit element for signal routing.

[0005] However, the stacked semiconductor device with or without the BSPDN structure still needs to improve performance in various different ways.

[0006] The information disclosed in this Background section of the specification is for the purpose of generally presenting the context and background of the application. The information described is not prior art to the claimed application, as described in 35 U.S.C. § 102, and similarly it is not admitted to be prior art by virtue of 35 U.S.C. § 103 or any other provision in any patent statute or regulation. SUMMARY

[0007] The present disclosure provides a stacked semiconductor device in which source / drain patterns and corresponding contact structures are formed to increase corresponding channel stress to improve device performance.

[0008] According to an aspect of the present disclosure, a stacked semiconductor device can include a first source / drain pattern at a first level, a second source / drain pattern at a second level different from the first level in a vertical direction, and a first contact structure on the first source / drain pattern, wherein a portion of the first source / drain pattern is in a first recess of the first contact structure.

[0009] According to an aspect of the present disclosure, a stacked semiconductor device can include a first source / drain pattern at a first level, a second source / drain pattern at a second level different from the first level in a vertical direction, and a first contact structure on the first source / drain pattern, wherein a portion of the first contact structure is in a first recess on the first source / drain pattern.

[0010] According to an aspect of the present disclosure, a stacked semiconductor device can include a first source / drain pattern at a first level, and a second source / drain pattern at a second level different from the first level in a vertical direction, wherein a top surface or a bottom surface of the first source / drain pattern includes a recess. BRIEF DESCRIPTION OF DRAWINGS

[0011] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and compared to prior art.

[0012] Figure 1 and Figures 2A-2C A stacked semiconductor device according to one or more embodiments is illustrated, in which a source / drain contact structure has different structural characteristics at lower and upper levels when channel widths at the lower level of an n-type transistor and the upper level of a p-type transistor are different.

[0013] Figure 3 A stacked semiconductor device according to one or more other embodiments is illustrated, in which a source / drain contact structure has different structural characteristics at lower and upper levels when channel widths at the lower level of a p-type transistor and the upper level of an n-type transistor are different.

[0014] Figure 4 A stacked semiconductor device according to yet one or more other embodiments is illustrated, in which a source / drain contact structure has different structural characteristics at lower and upper levels when channel widths at the lower level of an n-type transistor and the upper level of a p-type transistor are the same.

[0015] Figure 5Stacked semiconductor devices according to yet one or more other embodiments are shown in which the source / drain contact structure has different structural characteristics at the lower level and the upper level when the channel width is the same at the lower level of the p-type transistor and the upper level of the n-type transistor.

[0016] Figure 6 is a schematic block diagram showing an electronic device including a stacked semiconductor device according to one or more embodiments in which the source / drain contact structure has different structural characteristics at the lower level and the upper level. DETAILED DESCRIPTION

[0017] All embodiments of the present disclosure described herein are example embodiments, and thus, the present disclosure is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description is not exclusive of one or more features associated with another example or another embodiment provided herein or not provided herein but consistent with the present disclosure. For example, even if matters described in a particular example or embodiment are not described in a different example or embodiment, the matters can be understood to be related or combined with the different example or embodiment unless otherwise mentioned in the description thereof. Also, it should be understood that all descriptions of principles, aspects, examples, and embodiments of the present disclosure are intended to encompass structural and functional equivalents. Also, these equivalents are to be understood as not only including currently known equivalents but also equivalents that are to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure, are to be understood as equivalents. For example, the channel layer, the sacrificial layer, and the isolation layer described herein can take different types or forms as long as the present disclosure can be applied thereto.

[0018] It will be understood that when an element, component, layer, pattern, structure, region, or the like (hereinafter “element”) is referred to as being “on”, “above”, “on top of”, “over”, “under”, “below”, “underneath”, “beneath”, “connected to”, or “coupled to” another element, it can be directly on, above, on top of, over, under, below, underneath, beneath, connected to, or coupled to the other element, as the case can be, or there can be one or more intermediate elements. In contrast, when an element is referred to as being “directly on”, “directly above”, “directly on top of”, “directly over”, “directly under”, “directly below”, “directly underneath”, “directly beneath”, “directly connected to”, or “directly coupled to” another element, there are no intermediate elements. Like reference numbers refer to like elements throughout the present disclosure.

[0019] For ease of description, spatial relationship terms, such as “above”, “over”, “on”, “up”, “down”, “below”, “beneath”, “under”, “left”, “right”, “lower”, “upper”, “top”, “bottom”, “vertical”, “horizontal”, and the like, can be used herein to describe the relationship of one element to another element as illustrated in the figures. It will be understood that the spatial relationship terms are intended to encompass different orientations of the semiconductor device in use or operation, other than the orientation depicted in the figures. For example, if the semiconductor device in the figures is turned over, elements described as “below” or “under” other elements would then be oriented “above” the other elements. The terms “below” can encompass both the up and down orientations. The semiconductor device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein are interpreted accordingly. As another example, when a device or structure includes “left” and “right” elements, the “left” element and “right” element can be “right” and “left” elements, respectively, when the device or structure is oriented differently. Thus, the “left” and “right” elements of a structure can also be referred to herein as the “first” and “second” elements of the structure, respectively, as long as their structural relationship is clearly understood from the context of the description.

[0020] It will be understood that, although the terms“first,”“second,”“third,”“fourth,”“fifth,”“sixth,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element described in the context of one embodiment can also be later described as a second element in the context of another embodiment or in the context of one or more claims without departing from the teachings of this disclosure.

[0021] As used herein, such as in the phrase“at least one of,” when preceding the list of two or more elements, the phrase modifies those elements as a whole. For example, the phrase“at least one of a, b, and c” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0022] In the description herein, degree terms such as“substantially” or“approximately” can be used. In one or more examples, the term“substantially” can be understood to mean within ±10% of a value when a parameter X can be substantially the same as a parameter Y. In one or more examples, the term“approximately” can be understood to be within ±10% of a value when a parameter is about X. However, when the term“same” is used to compare a parameter of two or more elements, the term can encompass parameters that are“substantially the same.”

[0023] It will be understood that when the term“contact” is used to describe two metallic elements (e.g., a metal line and a via structure), a barrier metal layer such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN), but not limited thereto, can be formed therebetween. A barrier metal layer can also be formed between a metal line or a via structure and an isolation structure such as a dielectric layer. The purpose of forming a barrier metal layer includes improving adhesion properties and preventing metal diffusion into the isolation structure. Further, it will be understood that when a metal contact structure is described as being formed on or contacting a surface of a source / drain pattern, a silicide layer such as cobalt silicide (CoSi2), nickel silicide (NiSi2), titanium silicide (TiSi2), or tungsten silicide (WSi2), but not limited thereto, can be formed therebetween to improve the connection properties therebetween.

[0024] It will also be understood that even if a certain step or operation of making a device or structure is described later than another step or operation, the step or operation can be performed earlier than the other step or operation, unless the other step or operation is described as being performed after the step or operation.

[0025] Many embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments (and intermediate structures) of the embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the disclosure. Furthermore, the various regions of the figures can be exaggerated in size or relative size for the sake of clarity.

[0026] For the sake of brevity, conventional elements of a semiconductor device including a nanosheet transistor, structures or layers and materials forming the same can or can not be described in detail herein. For example, when a certain isolation layer or structure is not related to the novel features of the embodiments, the layer or structure of the semiconductor device and the materials forming the same can be omitted herein. Also, when the materials forming well-known structural elements of a semiconductor device are not related to the novel features of the embodiments, the description of the materials can be omitted herein. Herein, the term "isolation" relates to electrical insulation or separation between structures, layers, components or regions in the corresponding device or structure.

[0027] Figure 1 and Figures 2A-2C A stacked semiconductor device according to one or more embodiments is shown, in which a source / drain contact structure has different structural characteristics at lower and upper levels of n-type transistors when the channel width at the lower level and the upper level of p-type transistors is different.

[0028] Figure 1 is a plan view of a stacked semiconductor device 10, Figures 2A-2C are cross-sectional views taken along lines I-I', II-II' and III-III', respectively Figure 1 of the stacked semiconductor device 10 shown. It is to be understood herein that the Figure 1 are provided to show the positional relationship between the gate structure and the source / drain pattern, and therefore, for the sake of brevity, some Figure 1 structural elements such as interlayer isolation structures, contact structures, etc. are omitted in Figures 2A-2C

[0029] As shown in Figure 1 , a first direction D1 is a channel length direction in which a current flows between two source / drain patterns connected to each other by a channel structure, a second direction D2 is a channel width direction or a cell height direction that horizontally intersects the first direction D1, and a third direction D3 is a channel thickness direction that perpendicularly intersects the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 are referred to as horizontal directions, and the third direction D3 is referred to as a vertical direction.​

[0030] Referring to Figure 1 and Figures 2A-2C , the stacked semiconductor device 10 can include a first channel stack 10A, a second channel stack 10B, and a third channel stack 10C, each of which includes a lower channel structure formed of a plurality of lower channel layers 110 and an upper channel structure formed of a plurality of upper channel layers 120 vertically above the lower channel structure. The lower channel structure can be formed at a lower level on a base layer 101, and the upper channel structure can be formed at an upper level above the lower level. These channel layers 110 and 120 can be epitaxially grown from the base layer 101, which can be a silicon-based substrate. An intermediate isolation layer 125 can be formed between two channel structures, which isolates the two channel structures from each other. In addition, a bottom isolation layer 105 can be formed on a top surface of the base layer 101 to extend in a first direction D1 to isolate the base layer 101 from an active structure of the stacked semiconductor device 10 including the channel stacks 10A-10C.

[0031] The lower channel layers 110 can connect the lower source / drain patterns 135 on both sides thereof to each other such that a current can flow therebetween under the control of the lower gate structures 150L surrounding the lower channel layers 110. Similarly, the upper channel layers 120 can connect the upper source / drain patterns 145 on both sides thereof to each other such that a current can flow therebetween under the control of the upper gate structures 150U surrounding the upper channel layers 120. The lower gate structures 150L and the upper gate structures 150U form gate structures 150 of the stacked semiconductor device 10. The lower source / drain patterns 135 can be epitaxially grown from the lower channel layers 110 of the lower channel structures in the channel stacks 10A-10C, and the upper source / drain patterns 145 can be epitaxially grown from the upper channel layers 120 of the upper channel structures in the channel stacks 10A-10C. The gate structures 150 can be formed by replacing dummy gate structures and a plurality of sacrificial layers in the process of manufacturing the stacked semiconductor device 10.

[0032] Thus, in the stacked semiconductor device 10, the lower channel layers 110 along with the lower source / drain patterns 135 on both sides thereof and the lower gate structures 150L surrounding these lower channel layers 110 can form lower transistors T1 (which are nanosheet transistors) at the lower level. In addition, the upper channel layers 120 along with the upper source / drain patterns 145 on both sides thereof and the upper gate structures 150U surrounding these upper channel layers 120 can form upper transistors T2 (which are also nanosheet transistors) at the upper level.

[0033] The base layer 101 as a substrate can be formed of silicon (Si). Additionally or alternatively, it can include other materials such as silicon germanium (SiGe), silicon carbide (SiC), but is not limited thereto. The lower source / drain pattern 135 and the upper source / drain pattern 145 can each be formed of silicon (Si) or silicon germanium (SiGe). For example, the lower source / drain pattern 135 can be formed of Si, while the upper source / drain pattern 145 can be formed of SiGe. Further, the lower source / drain pattern 135 can be doped with an n-type impurity such as phosphorus (P), arsenic (As), antimony (Sb), etc., while the upper source / drain pattern 145 can be doped with an impurity such as boron (B), gallium (Ga), indium (In), etc. In this example, the lower transistor T1 can form an n-type field effect transistor, and the upper transistor T2 can form a p-type field effect transistor. Here, as an example, Figure 1 and Figures 2A-2C The stacked semiconductor device 10 shown in FIG. 1 is formed of an n-type lower transistor T1 and a p-type upper transistor T2. The materials forming the source / drain patterns 135 and 145 will be described in more detail later.

[0034] The lower gate structure 150L of the lower transistor T1 can include a gate dielectric layer GD, a lower work function metal layer LF, and a gate electrode GE, and the upper gate structure 150U can include a gate dielectric layer GD, an upper work function metal layer UF, and a gate electrode GE.

[0035] The gate dielectric layer GD can include an interface layer and a high-k dielectric layer formed on the interface layer. The interface layer can be formed on each of the channel layers 110 and 120 to protect the channel layers 110 and 120 and to facilitate growth of the high-k dielectric layer thereon, and the high-k dielectric layer can be formed on the interface layer to allow increased gate capacitance without associated current leakage from the gate structure 150. For these purposes, the interface layer can be formed of an oxide material such as silicon oxide (SiO or SiO2) and / or silicon oxynitride (SiON), but is not limited thereto, and the high-k dielectric layer can be formed of a high-k material such as hafnium oxide (HfO2), hafnium silicate (HfSiO4), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), yttrium oxide (Y2O3), etc.

[0036] A lower work function metal layer LF can be formed on the gate dielectric layer GD surrounding the lower channel layer 110 to control the gate threshold voltage of the lower transistor Tl, and an upper work function metal layer UF can be formed on the gate dielectric layer GD surrounding the upper channel layer 120 to control the gate threshold voltage of the upper transistor T2. Each of the work function metal layers LF and UF can be formed of a metal such as Ti, Ta, Al, W, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, and / or a combination thereof, but is not limited thereto. However, the lower work function metal layer LF of the lower transistor Tl and the upper work function metal layer UF of the upper transistor T2 can be formed of different materials when the two transistors have different polarity types (i.e., n-type and p-type), respectively. For example, since the lower transistor Tl is n-type and the upper transistor T2 is p-type, the lower work function metal layer LF can be formed of Al or TiC, and the upper work function metal layer UF can be formed of TiN.

[0037] Although the two transistors Tl and T2 have different work function metal layers LF and UF, respectively, a same gate electrode GE can surround the two work function metal layers LF and UF to form the two transistors Tl and T2 as a complementary metal-oxide-semiconductor (CMOS) device, such as an inverter circuit. The gate electrode GE can be formed of a metal such as Cu, W, Al, Ru, Mo, Co, etc. or a metal alloy thereof. However, the present disclosure is not limited thereto, and a gate isolation layer or structure can be formed to separate the gate structure 150 into two gate structures for the respective two transistors Tl and T2. For example, the gate electrode on the lower work function metal layer LF can be isolated from the gate electrode on the upper work function metal layer UF.

[0038] An interlayer isolation structure 170 can be formed to surround the source / drain patterns 135 and 145 to isolate these semiconductor structures from each other and from other circuit elements. The interlayer isolation structure 170 can be formed of a low-k dielectric material such as silicon oxide (e.g., SiO2).

[0039] A gate spacer 119 can be formed on the left and right side surfaces of the upper portion of the gate structure 150 disposed on the uppermost upper channel layer 120 in each of the channel stacks 10A-10C, respectively. For example, the gate spacer 119 can be formed on the left and right side surfaces of the gate dielectric layer included in the upper portion of the gate structure 150 in each of the channel stacks 10A-10C, respectively. Thus, the gate spacer 119 can also laterally face the upper source / drain pattern 145 and / or the portion of the interlayer isolation structure 170 formed vertically above the upper source / drain pattern 145.

[0040] Gate spacer 119 can be used to protect a dummy gate structure formed of polycrystalline silicon (p-Si) or amorphous silicon (a-Si) from the effects of various processes performed in the fabrication of the 3D stacked semiconductor device 10, and is retained after the dummy gate structure is replaced by gate structure 150 to prevent current leakage from it to other circuit elements. Gate spacer 119 can be formed of silicon nitride (e.g., SiN or Si3N4), SiBCN, SiCN, SiOC, SiOCN, silicon oxide (e.g., SiO2), etc., and is not limited thereto.

[0041] The inner spacer 103 may be formed between the lower source / drain pattern 135 and the lower work function metal layer LF, and between the upper source / drain pattern 145 and the upper work function metal layer UF, to isolate these structural elements from each other. The inner spacer 103 may be formed of silicon nitride (e.g., SiN or Si3N4), but is not limited thereto.

[0042] In such Figure 1 and Figure 2B In the stacked semiconductor device 10 shown, the upper channel structure including the upper channel layer 120 may have a smaller width in the second direction D2 than the lower channel structure including the lower channel layer 110, and the upper channel layer 120 may only partially overlap with the lower channel layer 110 in the third direction D3. For example, the left surfaces of the channel layers 110 and 120 may be aligned or coplanar with each other in the third direction D3, while their right surfaces are not. Therefore, as Figure 2C As shown, the upper source / drain pattern 145 epitaxially grown from the upper channel layer 120 can also be formed to have a smaller width in the second direction D2 than the lower source / drain pattern 135 epitaxially grown from the lower channel layer 110, and the right side portion of the lower source / drain pattern 135 can not overlap with the upper source / drain pattern 145 in the third direction D3.

[0043] Due to this width difference between the lower source / drain pattern 135 and the upper source / drain pattern 145, a lower contact structure (or lower contact plug) 180 can be formed on a top surface TS1 of the lower source / drain pattern 135 that does not overlap the upper source / drain pattern 145 in the D3 direction. This lower contact structure 180 can extend vertically upward in the third direction D3 through a region in the interlayer isolation structure 170 where the upper source / drain pattern 145 is not formed to connect the lower source / drain pattern 135 to a voltage source or another circuit element for signal routing purposes. When the top surface TS1 of the lower source / drain pattern 135 that does not overlap the upper source / drain pattern 145 does not provide sufficient area for forming the lower contact structure 180, the lower contact structure 180 can also be formed on a right side surface SS1 of the lower source / drain pattern 135. In contrast, an upper contact structure (or upper contact plug) 190 can be formed on a top surface TS2 of the upper source / drain pattern 145 to connect the upper source / drain pattern 145 to a voltage source or another circuit element for signal routing purposes.

[0044] The foregoing features of the channel structure and the source / drain pattern can be provided to address the increasing demand for high device density in semiconductor devices including the stacked semiconductor device 10.

[0045] The upper channel structure forming the upper transistor T2 can have a greater number of channel layers than the lower channel structure forming the lower transistor T1, such that the two transistors can have the same or substantially the same effective channel width (W eff For example, the upper channel structure can have three channel layers, while the lower channel structure has two channel layers, as shown in Figure 2A and Figure 2B .

[0046] The different channel widths and different numbers of channel layers can facilitate optimization of the stacked semiconductor device not only in terms of area gain of high-density semiconductor devices, but also in terms of device performance such as current speed, workload distribution, power efficiency, contact resistance, thermal control, structural stability, etc.

[0047] Device performance of the stacked semiconductor device 10 can also be improved by controlling the stress (or strain) applied to the channel layers 110 and 120 by the source / drain patterns 135 and 145. For example, the source / drain patterns 135 and 145 can be configured to apply channel stress to the channel layers 110 and 120 to increase carrier (hole or electron) mobility, thereby increasing drive current through the channel layers 110 and 120.

[0048] For this purpose, the n-type lower source / drain pattern 135 can be formed of silicon (Si) and / or silicon carbide (SiC), while the p-type upper source / drain pattern 145 can be formed of silicon germanium (SiGe). Since SiGe has a larger lattice constant or size than Si or SiC, the p-type upper source / drain pattern 145 including SiGe can apply compressive stress (or compressive strain) to the upper channel layer 120 to improve hole mobility therein, while the n-type lower source / drain pattern 135 including Si and / or SiC can apply tensile stress (or tensile strain) to the lower channel layer 110 to improve electron mobility therethrough. Furthermore, p-type impurities or dopants (such as boron (B), gallium (Ga), indium (In), etc.) in the upper source / drain pattern 145 of SiGe can enhance the compressive stress in the upper channel layer 120, and n-type impurities or dopants (such as phosphorus (P), arsenic (As), antimony (Sb), etc.) in the lower source / drain pattern 135 can enhance the tensile stress in the lower channel layer 110.

[0049] Meanwhile, the formation of the lower contact structure 180 and the upper contact structure 190 can also affect the channel stress control performed by the source / drain patterns 135 and 145. The contact structures 180 and 190 can be formed of metals (such as Cu, W, Al, Ru, Mo, Co, etc.) or their metal alloys.

[0050] like Figure 2C As shown, the lower contact structure 180 can be formed such that the lower portion of the lower contact structure 180 is formed in a recess RS, which is formed on or across the top surface TS1 and right surface SS1 of the lower source / drain pattern 135, which does not perpendicularly overlap with the upper source / drain pattern 145. The recess RS on the lower source / drain pattern 135 can be formed by etching the top surface TS1 and right surface SS1 of the lower source / drain pattern 135 through the isolation structure 170. Therefore, the lower contact structure 180 can be inserted into or penetrate the top surface TS1 and right surface SS1 of the lower source / drain pattern 135. By forming the lower source / drain pattern 135 and the lower contact structure 180 in this manner, the volume of the lower source / drain pattern 135 can be reduced to increase the tensile stress applied to the lower channel layer 110. This is because the smaller volume of the lower source / drain pattern 135 of Si and / or SiC results in a more concentrated mechanical force applied to the lower channel layer 110, thereby increasing the tensile stress on the lower channel layer 110.

[0051] Similarly, Figure 2CAs shown, the upper contact structure 190 can be formed such that a lower portion of the upper contact structure 190 wraps an upper portion of the upper source / drain pattern 145, the upper portion of the upper source / drain pattern 145 including at least a portion of the top surface TS2 and / or at least a portion of the side surface SS2, such that a volume of the upper source / drain pattern 145 is not lost or reduced. Thus, the upper portion of the upper source / drain pattern 145 can take the form of a recess RC formed on a bottom surface of the upper contact structure 190. By forming the upper source / drain pattern 145 and the upper contact structure 190 in this manner, a volume of the upper source / drain pattern 145 can not be lost or can be maintained to increase the compressive stress applied to the upper channel layer 120, as a greater volume of the upper source / drain pattern 145 of SiGe having a relatively larger lattice constant or size provides a greater mechanical force, thereby increasing the compressive stress on the upper channel layer 120. Further, the upper source / drain pattern 145 can have a greater height than the lower source / drain pattern 135.

[0052] In the above-described embodiments, when the stacked semiconductor device is formed of an n-type lower source / drain pattern of Si and / or SiC and a p-type upper source / drain pattern of SiGe, improvement in device performance in terms of channel stress is achieved, further, the lower source / drain pattern has a greater width based on a lower channel structure having a greater width and a smaller number of channel layers, and the upper source / drain pattern has a smaller width based on an upper channel structure having a smaller width and a greater number of channel layers. However, the present disclosure is not limited thereto, as described below.

[0053] Figure 3 A stacked semiconductor device according to one or more other embodiments is shown, in which a source / drain contact structure has different structural characteristics at a lower level and an upper level when a channel width is different at the lower level and the upper level of a p-type transistor and an n-type transistor.

[0054] Referring to FIG. 1, a stacked semiconductor device 10 according to an embodiment of the present disclosure is shown, in which a lower transistor T1 and an upper transistor T2 are formed in a stacked structure. Figure 2C Figure 3 , the stacked semiconductor device 20 can have the same structural elements as those included in the stacked semiconductor device 10 of Figure 1 and Figures 2A-2C . Hereinafter, only different aspects of the stacked semiconductor device 20 are described, and repetitive descriptions thereof can be omitted.

[0055] ​In the stacked semiconductor device 20, the lower transistor T1 can be formed of a p-type lower source / drain pattern 235, and the upper transistor T2 can be formed of an n-type upper source / drain pattern 245. Accordingly, the lower source / drain pattern 235 can be formed of SiGe having a p-type impurity, and the upper source / drain pattern 245 can be formed of Si and / or SiC having an n-type impurity. Further, the lower source / drain pattern 235 can be formed to apply a compressive stress to the lower channel layer 110, and the upper source / drain pattern 245 can be formed to apply a tensile stress to the upper channel layer 120.

[0056] Further, as Figure 3 indicated, the lower contact structure 280 can be formed such that a lower portion of the lower contact structure 280 wraps a portion of the lower source / drain pattern 235 including at least a portion of the top surface TS1 and / or at least a portion of the side surface SS1 that does not vertically overlap with the upper source / drain pattern 245, such that the volume of the lower source / drain pattern 235 is not lost or reduced by the lower contact structure 280. Accordingly, a portion (e.g., an upper right portion) of the lower source / drain pattern 235 can take the form of a recess RC formed on a bottom surface of the lower contact structure 280. By forming the lower source / drain pattern 235 and the lower contact structure 280 in this way, the compressive stress applied to the lower channel layer 110 can be increased.

[0057] In contrast, as Figure 3 indicated, the upper contact structure 290 can be formed such that a lower portion of the upper contact structure 290 is formed in a recess RS formed on at least the top surface TS2 of the upper source / drain pattern 245. Accordingly, the upper contact structure 290 can take the form of being inserted or penetrating into the top surface TS2 of the upper source / drain pattern 245. By forming the upper source / drain pattern 245 and the upper contact structure 290 in this way, the tensile stress applied to the upper channel layer 120 can be increased.

[0058] Accordingly, based on the formation of the source / drain patterns and the contact structures, a stacked semiconductor device formed of a p-type lower source / drain pattern having a larger width and an n-type upper source / drain pattern having a smaller width can also have improved device performance in terms of channel stress.

[0059] Figure 4 A stacked semiconductor device according to yet another or more other embodiments is shown, in which a source / drain contact structure has different structural characteristics at a lower level of an n-type transistor and an upper level of a p-type transistor when the channel width at the lower level and the upper level is the same.

[0060] Referring to the Figure 2C corresponding Figure 4, except that the lower source / drain pattern 335 and the upper source / drain pattern 345 have the same or substantially the same width in the second direction D2, the stacked semiconductor device 30 can have the same structural elements as those included in the stacked semiconductor device 10 of Figure 1 and Figures 2A-2C . Hereinafter, only different aspects of the stacked semiconductor device 30 are described, and repetitive descriptions thereof can be omitted.

[0061] The same or substantially the same source / drain pattern width of the lower transistor T1 and the upper transistor T2 in the stacked semiconductor device 30 can be obtained by forming the lower channel layer 110 and the upper channel layer 120 to have the same or substantially the same width and the same number of channel layers, because the lower source / drain pattern 335 and the upper source / drain pattern 345 are epitaxially grown from the lower channel layer 110 and the upper channel layer 120, respectively, as previously described with respect to the stacked semiconductor device 10.

[0062] When the lower source / drain pattern 335 and the upper source / drain pattern 345 vertically above thereof have the same or substantially the same width, a lower contact structure for the lower source / drain pattern 335 can not be formed on a top surface of the lower source / drain pattern 335 as in the stacked semiconductor device 10, unless an additional space is provided for the stacked semiconductor device 30 and the lower contact structure formed in the additional space is bent to contact the top surface of the lower source / drain pattern 335. However, the lower contact structure can be formed as a backside contact structure 380 on a backside of the stacked semiconductor device 30, as shown in Figure 4 The backside contact structure 380 can be formed to penetrate the base layer 101 and the bottom isolation layer 105 to contact a bottom surface BS1 of the lower source / drain pattern 335. Since the lower source / drain pattern 335 is n-type formed of Si and / or SiC having n-type impurities, the lower source / drain pattern 335 and the backside contact structure 380 can be formed such that a recess RS is formed on the bottom surface BS1 of the lower source / drain pattern 335 to reduce a volume of the lower source / drain pattern 335, and an upper portion of the backside contact structure 380 is formed in the recess RS. Accordingly, a tensile stress applied to the lower channel layer 110 can be increased.

[0063] In contrast, the upper contact structure 390 can be formed such that the lower portion of the upper contact structure 390 encloses the upper portion of the upper source / drain pattern 245, the upper portion of which includes at least a portion of the top surface TS2 and / or at least a portion of the side surface SS2, such that the volume of the upper source / drain pattern 345 is not lost or reduced due to the upper contact structure 390. Therefore, a portion of the upper source / drain pattern 345 (e.g., the upper portion) can be formed in a recess RC formed on the bottom surface of the upper contact structure 390. By forming the upper source / drain pattern 345 and the upper contact structure 390 in this manner, the compressive stress applied to the upper channel layer 120 can be increased.

[0064] Therefore, based on the formation of source / drain patterns and contact structures, stacked semiconductor devices formed by n-type lower source / drain patterns and p-type upper source / drain patterns with the same or substantially the same width can also have improved device performance in terms of channel stress.

[0065] Figure 5 A stacked semiconductor device according to yet another or one other embodiment is shown, wherein the source / drain contact structure has different structural characteristics at the lower and upper levels when the channel width is the same at the lower level of the p-type transistor and the upper level of the n-type transistor.

[0066] Reference corresponds to Figure 4 of Figure 5 Except that the polarities of the lower transistor T1 and the upper transistor T2 are opposite in the stacked semiconductor device 40, the stacked semiconductor device 40 can have the same polarity as the upper transistor T2. Figure 4 The stacked semiconductor device 30 includes the same structural elements. In the following description, only the different aspects of the stacked semiconductor device 30 are described, and repeated descriptions may be omitted.

[0067] In the stacked semiconductor device 40, since the lower source / drain pattern 435 is a p-type formed from SiGe with p-type impurities, the lower source / drain pattern 435 and the back-side contact structure 480 can be formed such that the upper portion of the back-side contact structure 480 encloses the lower portion of the lower source / drain pattern 435, including at least a portion of the bottom surface BS1 and / or at least a portion of the side surface SS1, so that the volume of the lower source / drain pattern 435 is not lost or reduced due to the back-side contact structure 480. Therefore, a portion of the lower source / drain pattern 435 (e.g., the lower portion) can take the form of a recess RC formed on the top surface of the back-side contact structure 480. By forming the lower source / drain pattern 435 and the back-side contact structure 480 in this way, the compressive stress applied to the lower channel layer 110 can be increased.

[0068] In contrast, since the upper source / drain pattern 445 is n-type formed of Si and / or SiC having an n-type impurity, the upper source / drain pattern 445 and the upper contact structure 490 can be formed so that a recess RS is formed on a top surface TS2 of the upper source / drain pattern 445 to reduce a volume of the upper source / drain pattern 445, and a lower portion of the upper contact structure 490 is formed in the recess RS. Accordingly, a tensile stress on the upper channel layer 120 can be increased.

[0069] Accordingly, based on the formation of the source / drain pattern and the contact structure, a stacked semiconductor device formed of a p-type lower source / drain pattern and an n-type upper source / drain pattern having the same or substantially the same width can also have improved device performance in terms of channel stress.

[0070] In the above embodiments, when each contact structure is formed on a surface of a source / drain pattern, a silicide layer can be formed therebetween to improve device performance, as previously described.

[0071] In the above embodiments, each of the lower transistor T1 and the upper transistor T2 is described as a nanosheet transistor. However, the present disclosure is not limited thereto. According to one or more other embodiments, these transistors T1 and T2 can each be a different type of field effect transistor, such as a FinFET or a fork transistor.

[0072] Figure 6 is a schematic block diagram illustrating an electronic device including a stacked semiconductor device according to one or more embodiments, the stacked semiconductor device including different source / drain contact structures. The stacked semiconductor device included in the electronic device can be or correspond to Figure 1 、 Figures 2A-2C 、 Figure 3 、 Figure 4 and Figure 5 the stacked semiconductor device 10, 20, 30, or 40 illustrated in FIGS. 1 to 3.

[0073] Referring to Figure 6 , the SoC 1000 can be an integrated circuit in which components of a computing system or other electronic system are integrated. As an example of the SoC 1000, an application processor (AP) can include at least one processor and components for various functions. The SoC 1000 can include a core 1011 (e.g., a processor), a digital signal processor (DSP) 1012, a graphic processing unit (GPU) 1013, an embedded memory 1014, a communication interface 1015, and a memory interface 1016. The components of the SoC 1000 can communicate with each other through a bus.

[0074] The core 1011 can process instructions and control operations of components included in the SoC 1000. For example, the core 1011 can process a series of instructions to run an operating system and execute an application on the operating system. The DSP 1012 can generate useful data by processing digital signals, for example, provided from the communication interface 1015. The GPU 1013 can generate data of an image output by a display device from image data provided from the embedded memory 1014 or the memory interface 1016, or can encode the image data.

[0075] The embedded memory 1014 can store data necessary for the core 1011, the DSP 1012, and the GPU 1013 to operate. The communication interface 1015 can provide an interface for a communication network or one-to-one communication. The memory interface 1016 can provide an interface for an external memory of the SoC 1000, such as a dynamic random access memory (RAM) (DRAM), a flash memory, or the like.

[0076] At least one of the core 1011, the DSP 1012, the GPU 1013, and / or the embedded memory 1014 can include at least one of the stacked semiconductor devices 10, 20, 30, and 40 shown in FIGS. 1 to 4. Figure 1 、 Figures 2A-2C 、 Figure 3 、 Figure 4 and Figure 5 .

[0077] The foregoing is a detailed description of example implementations, and should not be interpreted as limiting the disclosure. Although several example implementations have been described, those skilled in the art will readily understand that many modifications can be made to the above implementations without substantially departing from the disclosure.

Claims

1. A stacked semiconductor device, comprising: The first source / drain pattern at the first level; The second source / drain pattern at a second level that is perpendicular to the first level; as well as The first contact structure on the first source / drain pattern A portion of the first source / drain pattern is located in the first recess of the first contact structure.

2. The stacked semiconductor device of claim 1, further comprising a second contact structure on the second source / drain pattern, A portion of the second contact structure is located in a second recess on the second source / drain pattern.

3. The stacked semiconductor device of claim 2, wherein the first source / drain pattern is p-type and the second source / drain pattern is n-type.

4. The stacked semiconductor device of claim 3, wherein the first source / drain pattern is vertically below the second source / drain pattern.

5. The stacked semiconductor device of claim 3, wherein the first source / drain pattern is vertically above the second source / drain pattern.

6. The stacked semiconductor device of claim 5, wherein the first source / drain pattern has a wider width than the second source / drain pattern.

7. The stacked semiconductor device of claim 5, wherein the first source / drain pattern has a greater height than the second source / drain pattern.

8. The stacked semiconductor device of claim 4, wherein the first source / drain pattern has a wider width than the second source / drain pattern.

9. The stacked semiconductor device of claim 2, wherein the second recess is on the top surface of the second source / drain pattern.

10. The stacked semiconductor device of claim 9, wherein the second recess is also on the side surface of the second source / drain pattern.

11. The stacked semiconductor device of claim 2, wherein the second recess is on the bottom surface of the second source / drain pattern.

12. The stacked semiconductor device of claim 11, wherein the first contact structure is on the top surface of the first source / drain pattern.

13. A stacked semiconductor device, comprising: The first source / drain pattern at the first level; The second source / drain pattern at a second level that is perpendicular to the first level; as well as The first contact structure on the first source / drain pattern A portion of the first contact structure is located in a first recess on the first source / drain pattern.

14. The stacked semiconductor device of claim 13, wherein the first recess is on at least one of the top surface and side surface of the first source / drain pattern.

15. The stacked semiconductor device of claim 13, wherein the first source / drain pattern and the second source / drain pattern have different widths in the channel width direction.

16. The stacked semiconductor device of claim 13, wherein the first source / drain pattern and the second source / drain pattern have substantially equal widths in the channel width direction.

17. The stacked semiconductor device of claim 13, wherein the first recess is on the bottom surface of the first source / drain pattern.

18. A stacked semiconductor device, comprising: The first source / drain pattern at the first level; as well as The second source / drain pattern at a second level that is perpendicular to the first level. The top or bottom surface of the first source / drain pattern includes a recess.

19. The stacked semiconductor device of claim 18, wherein the first source / drain pattern is n-type.

20. The stacked semiconductor device of claim 18, wherein the top or bottom surface of the second source / drain pattern does not include a recess.

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