Wafer-level graphene-silicon three-terminal phototransistor and preparation method thereof

Abstract

The invention discloses a wafer-level graphene-silicon three-terminal phototransistor and a preparation method thereof, an emitter of the transistor is a silicon substrate covered with a silicon oxide layer, a silicon window is etched in the silicon oxide layer, and the silicon substrate is a doped silicon substrate; the base electrode comprises single-layer graphene located in a silicon window area, the doping mode of the single-layer graphene is opposite to that of the silicon substrate, the single-layer graphene and the silicon substrate form a shallow Schottky junction, base electrode graphene extends to the position of the metal electrode corresponding to the base electrode on the surface of the silicon oxide from the silicon window, and a tunnel layer is arranged between the metal electrode and the base electrode graphene; the collector electrode comprises collector electrode single-layer graphene which is isolated on the base electrode graphene through a tunnel layer, the collector electrode single-layer graphene extends to a metal electrode position corresponding to the collector electrode on the surface of the silicon oxide, and the base electrode graphene, the tunnel layer and the collector electrode graphene form a tunnel junction. According to the invention, the rectification characteristic is enhanced by utilizing the barrier difference of the graphene-silicon Schottky junction and the graphene-graphene-silicon Schottky junction, and large scale and low cost can be realized.

Description

Technical Field

[0001] This invention relates to semiconductor technology, and more particularly to a wafer-level graphene-silicon three-terminal phototransistor and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, the size scaling of silicon-based transistors has approached its physical limits, making it difficult to meet the demands of next-generation integrated circuits for high performance, high density, and low power consumption. Two-dimensional (2D) materials, due to their unique electrical and optical properties, have moved from materials-level research to product-level applications, becoming an important direction for replacing traditional silicon-based materials. Among them, graphene, with its high conductivity and ultra-wide operating bandwidth, occupies a key position in the low-dimensional semiconductor field, and the maturity of roll-to-roll production and wafer-level mass production technologies has met the basic requirements for commercialization.

[0003] Existing vertical transistors based on 2D material heterojunctions employ the following core approach: using vertically stacked 2D material heterojunctions as the core structure, and utilizing interlayer tunneling effects to achieve current regulation; relying on a fully 2D material system to construct the source, drain, and gate terminals, or achieving carrier injection through the combination of 2D materials and metal electrodes; the fabrication process is mainly based on small-area laboratory-level fabrication, relying on precision photolithography and transfer technology, and has not achieved wafer-level compatibility with silicon-based CMOS for large-scale production.

[0004] Existing vertical graphene heterojunction phototransistors form photoresponse structures by stacking graphene with other 2D semiconductor materials (such as MoS2), but they have the following limitations: poor material compatibility, high cost of large-scale fabrication, and on / off ratios below 10. 4 The rectification characteristics are unstable and cannot be directly integrated into existing silicon-based chips.

[0005] In summary, various structures have been developed in the field of low-dimensional transistors, including field-effect tunneling low-dimensional transistors, vertical low-dimensional transistors, low-dimensional hot-electron transistors, and low-dimensional bipolar transistors. However, these technologies still face core challenges:

[0006] Large-scale fabrication is difficult: All-2D material three-terminal transistors are limited by the wafer-level uniform growth and transfer process of 2D materials, making it difficult to achieve low-cost, large-area mass production, and the batch-to-batch consistency is poor;

[0007] The inherent zero bandgap characteristic of graphene makes it difficult to directly use it as a transistor or logic device in large-scale low-dimensional integrated circuits. Although its performance can be controlled by layer number control, fluorination, nanopatterning, etc., there are problems such as the difficulty of material growth and performance balance (such as the contradiction between conductivity and bandgap control).

[0008] Insufficient performance indicators: On / off ratios are generally below 10. 4The subthreshold swing is greater than 300 mV / dec, the linearity (R²) of the rectification characteristics is less than 0.99, and the amplification factor is less than 10, which cannot meet the core requirements of logic circuits.

[0009] Incompatible with silicon-based processes: Existing structural designs do not take into account compatibility with silicon-based CMOS processes, making it difficult to integrate into existing semiconductor manufacturing processes and hindering industrial applications;

[0010] Poor reliability and stability: Under long-term operation, there is performance drift caused by current decay and interface charge accumulation. Under high bias voltage, tunnel layer breakdown is prone to occur, and the band adaptability of optical response is narrow.

[0011] Poor power consumption control: Some structures suffer from high power consumption and weak control capability due to improper selection of tunnel layer materials or unreasonable electrode design. Summary of the Invention

[0012] The purpose of this invention is to address the shortcomings of existing technologies by proposing a three-terminal phototransistor that can be fabricated at the wafer level, is low-cost, high-performance, highly reliable, and compatible with silicon-based CMOS processes.

[0013] The objective of this invention is achieved through the following technical solution: a wafer-level graphene-silicon three-terminal phototransistor, comprising: an emitter, a base, a collector, a tunnel layer, and a metal electrode;

[0014] The emitter is a silicon substrate covered with a silicon oxide layer, in which silicon windows are etched, and the silicon substrate is a doped silicon substrate;

[0015] The base includes: a single layer of graphene located in the silicon window region with the opposite doping mode to the silicon substrate, forming a shallow Schottky junction with the silicon substrate, the base graphene extending from the silicon window to the metal electrode position corresponding to the base on the silicon oxide surface, and a tunnel layer is provided between the metal electrode and the base graphene.

[0016] The current collector includes: a single layer of current collector graphene isolated on the base graphene by a tunnel layer, extending to the metal electrode position corresponding to the current collector on the silicon oxide surface, wherein the base graphene, the tunnel layer and the current collector graphene form a tunnel junction.

[0017] Furthermore, the metal electrode includes metal electrodes corresponding to the emitter, base, and collector, with the metal electrode corresponding to the emitter disposed on the silicon substrate; and the metal electrodes corresponding to the base and collector disposed at different positions on the silicon oxide layer.

[0018] Furthermore, the tunnel layer is an Al2O3 film obtained by atomic layer deposition, or HfO2 or ZrO2 that is compatible with the graphene interface.

[0019] Furthermore, the doping types of the silicon substrate and the base graphene include: a lightly doped n-type silicon substrate combined with p-doped graphene to form a shallow Schottky junction, or a p-type silicon substrate combined with n-doped graphene to form a Schottky junction.

[0020] Furthermore, the metal electrodes use Cr / Au as the emitter and collector electrodes, and Cr / Ag as the base electrode, with dimensions including: 20 nm / 70 nm for the Cr / Au electrode and 20 nm / 300 nm for the Cr / Ag electrode.

[0021] Furthermore, the metal electrode also includes Ti / Au and Ni / Au electrodes, which replace Cr / Ag and Cr / Au electrodes to ensure ohmic contact and stability between the electrode and graphene / silicon.

[0022] According to another aspect of the specification, a method for fabricating the transistor is also provided, comprising:

[0023] Electrodes and metal pads for emitter and collector electrodes were fabricated using lightly doped silicon wafers with a surface-grown thermally oxidized SiO2 layer, via photolithography and electron beam evaporation.

[0024] Photoresist is used for patterning, and an etching solution is used to selectively etch the SiO2 layer to form a silicon window;

[0025] Monolayer graphene was prepared by chemical vapor deposition and transferred to a substrate containing silicon windows using PMMA-assisted wet transfer technology. The graphene was then patterned by photolithography and excess graphene was etched using oxygen plasma to form a Schottky junction.

[0026] Tunnel dielectric films are grown by atomic layer deposition to cover the silicon window region and the metal pad region;

[0027] The second wet transfer CVD process transfers monolayer graphene to the surface of the tunneling medium film. After photolithography patterning, excess graphene is etched by oxygen plasma to form a graphene-tunneling medium-graphene tunnel junction.

[0028] Wet etching of the tunnel layer in the collector metal pad area reduces contact resistance;

[0029] The device was fabricated by depositing the base electrode using electron beam evaporation.

[0030] Furthermore, when the tunnel dielectric film is made of Al2O3, the Al2O3 layer in the collector metal pad area is wet-etched using an Al etching solution, and the Al etching solution has a ratio of H3PO4: HNO3: CH3COOH: H2O = 16: 1:1: 2.

[0031] Furthermore, the oxygen plasma etching of excess graphene used during the transfer of each graphene layer includes two etching processes. The first etching process involves treating the excess monolayer graphene with oxygen plasma at an O2 flow rate of 300 sccm and a power of 50 W for 90 seconds. The second etching process involves treating the excess monolayer graphene with an O2 flow rate of 300 sccm and a power of 30 W for 3 minutes.

[0032] Furthermore, the SiO2 layer is formed by thermal oxidation of the silicon wafer surface by 100±5 nanometers.

[0033] The beneficial effects of this invention are:

[0034] A vertically stacked graphene-silicon three-terminal structure is adopted, and the base graphene and the current collector graphene are isolated by an Al2O3 tunnel layer to form a synergistic effect of double Schottky junction and tunnel junction.

[0035] Based on the difference in growth quality of Al2O3 on graphene and metal surfaces, selective transmission of channel current is achieved. At the same time, the barrier difference between graphene-silicon and graphene-graphene-silicon Schottky junctions is utilized to enhance rectification characteristics. The device operating voltage is reduced (within ±5 V range), and the power consumption is more than 30% lower than that of existing vertical transistors.

[0036] Scalability and low cost: Achieves 4-inch wafer-level fabrication, relying on mature CVD graphene growth and wet transfer technology, with a cost lower than all-2D heterojunction devices; the on / off ratio, rectification characteristics, and amplification factor are all superior to existing low-dimensional transistors, solving the logic performance defects caused by the zero bandgap of traditional graphene devices;

[0037] Through two steps of graphene wet transfer, patterning, and ALD Al2O3 deposition, it is fully compatible with silicon-based CMOS technology, requiring no additional development of dedicated equipment and lowering the threshold for industrialization.

[0038] No performance degradation during long-term pulse testing, good stability of the tunnel layer under high bias voltage, and wide optical response band (covering visible light to infrared).

[0039] Multifunctional Integration: This structure utilizes the photoelectric properties of the graphene-silicon Schottky junction, enabling the device to function as both a photodetector and a detector. The base region forward channel controls the signal amplification of the emitter-collector channel, and the excellent Schottky junction ensures self-rectification, allowing it to replace the traditional "detector + amplifier" combination structure and simplifying circuit design. Attached Figure Description

[0040] Figure 1 A schematic diagram of a wafer-level graphene-silicon three-terminal phototransistor structure provided in an embodiment of the present invention;

[0041] Figure 2 A flowchart illustrating the overall transistor fabrication process provided in this embodiment of the invention;

[0042] Figure 3 A diagram illustrating the transistor's working mechanism provided in an embodiment of the present invention;

[0043] Figure 4 Photoelectric characteristics diagram of a graphene-silicon vertical phototransistor provided in an embodiment of the present invention;

[0044] Figure 5 Performance analysis of the graphene-silicon vertical phototransistor provided in the embodiments of the present invention;

[0045] Figure 6 Long-term stability test diagram provided for embodiments of the present invention;

[0046] Figure 7 A simplified preparation flowchart is provided for embodiments of the present invention. Detailed Implementation

[0047] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0048] like Figure 1 As shown, the present invention provides a wafer-level graphene-silicon three-terminal phototransistor, the device having a three-terminal vertical structure, the core of which includes:

[0049] Emitter: Lightly doped n-type Si substrate, with a 100±5 nm thermally oxidized SiO2 layer covering the surface;

[0050] Base: A monolayer of p-doped graphene located above the silicon window region formed by SiO2 etching, forming a shallow Schottky junction (Emit-Base junction) with n-type Si.

[0051] A p-type Si substrate can be used in conjunction with n-doped graphene to form an n-type graphene / p-type Si Schottky junction, which can also achieve rectification and tunneling control.

[0052] The existing p-doping process can be replaced by ion implantation, chemical doping, etc., as long as a stable Schottky junction between p-type graphene and n-type Si can be formed.

[0053] Collector: A single layer of graphene located above the base graphene, isolated from the base graphene by an Al2O3 tunnel layer, forming a graphene–Al2O3–graphene tunnel junction (Base-Collect junction).

[0054] Tunneling layer: A 7 nm thick Al2O3 film, grown by atomic layer deposition (ALD), located between the base graphene and the current collector graphene, and between the base graphene and the base metal electrode. Other high-k dielectric materials such as HfO2 and ZrO2 can be used to replace Al2O3, and the tunneling control function can still be achieved. The key lies in the interface compatibility between the dielectric layer and graphene.

[0055] Metal electrodes: emitter electrode (Cr / Au = 20 nm / 70 nm), base electrode (Cr / Au = 20 nm / 70 nm - Al₂O₃ = 7 nm - Cr / Ag = 20 nm / 300 nm), and collector electrode (Cr / Au = 20 nm / 70 nm). The Al₂O₃ layer in the collector region is removed by wet etching to reduce contact resistance. Ti / Au and Ni / Au materials can be used to replace Cr / Ag and Cr / Au electrodes; the key is to ensure ohmic contact and stability between the electrode and graphene / silicon.

[0056] The difference in growth quality of Al2O3 on graphene and metal surfaces is utilized: Al2O3 grown on metal surfaces is of higher quality, while Al2O3 grown on graphene surfaces forms a tunneling / resistive layer, enabling selective transmission of channel current.

[0057] The barrier difference between the graphene-silicon Schottky junction (barrier 0.74 eV) and the graphene-graphene-silicon Schottky junction (barrier 0.76 eV) enhances the self-rectification characteristics.

[0058] Vertical stacking design: The base and collector graphene are vertically stacked and isolated by an Al2O3 tunnel layer, which shortens the carrier transport path and improves the response speed.

[0059] Based on the transistors described above, such as Figure 2 As shown, the embodiment also provides a method for fabricating a wafer-level graphene-silicon three-terminal phototransistor, specifically including:

[0060] Step 1: Substrate preparation

[0061] like Figure 2 As shown in Figure a, a lightly doped n-type Si wafer was selected, and its surface underwent a 100±5 nm thermal oxidation treatment to form a silicon dioxide layer. AZ6130 was used as the photoresist, and Cr / Au (20 nm / 70 nm) was prepared by photolithography and electron beam evaporation. Collector and base electrodes were then fabricated. The emitter electrode was composed of a gallium-indium alloy.

[0062] Step 2: Silicon window etching

[0063] Patterning was performed using AZ6130 photoresist, and the SiO2 layer was selectively etched using an HF-based etching solution (HF:NH4F:H2O=30 mL:60 g:45 mL, HF concentration 48%) to form silicon windows, as shown below. Figure 2 b in the text.

[0064] Step 3: Base Graphene Transfer and Patterning

[0065] Monolayer graphene was prepared by chemical vapor deposition (CVD) and transferred to the surface of a substrate containing a silicon window using PMMA-assisted wet transfer technology (Figure 2c). Subsequently, AZ6130 was used as a photoresist for re-patterning. Excess graphene was etched using an Alpha Plasma AL18 system with oxygen plasma (O2 = 300 sccm, 50 W × 90 s + 30 W × 3 min). A second removal of excess graphene was then performed using the Alpha Plasma AL18 system under the following conditions: oxygen flow rate 300 mAg, power 30 W. This formed a p-doped graphene / n-type Si Schottky junction (Emit-Base junction) (Figure 2c). Figure 2 (d in the text)

[0066] Step 4: Deposition of Al2O3 tunnel layer

[0067] A 7 nm thick Al₂O₃ film was grown at 200 °C using a Lesker ALD150LX, covering the silicon window region (tunneling layer) and the metal pad region (resistive layer). (See attached image) Figure 2 (e in the text).

[0068] Step 5: Collector Graphene Transfer and Patterning

[0069] Second wet transfer CVD process to transfer monolayer graphene to the surface of Al2O3 film (with attached) Figure 2 (f) Then, AZ6130 is used as the photoresist for conventional photolithography. After photolithographic patterning, oxygen plasma is used to etch excess graphene, forming a graphene-Al2O3-graphene tunnel junction (Base-Collect junction) (see appendix). Figure 2 g in (the middle part).

[0070] The oxygen plasma etching of excess graphene in this step includes: treating the excess monolayer graphene with oxygen plasma for 90 seconds using an Alpha Plasma AL18 system at an O2 flow rate of 300 sccm and a power of 50 W to remove the excess monolayer graphene. Then, it is treated again with oxygen plasma for 3 minutes using the same AlphaPlasma AL18 system, but with an O2 flow rate of 300 sccm and a power of 30 W, to further remove the excess monolayer graphene.

[0071] Step 6: Al2O3 etching of the collector region

[0072] Wet etching of the Al2O3 layer in the collector metal pad area was performed using an Al etching solution (H3PO4: HNO3: CH3COOH: H2O = 80 mL: 5 mL: 5 mL: 10 mL) to reduce contact resistance. Figure 2 (h in the middle).

[0073] Step 7: Metal Electrode Preparation

[0074] Device fabrication was completed by depositing Cr / Ag (20 nm / 300 nm) base electrodes via electron beam evaporation (see attached image). Figure 2 (i) This technology can subsequently be used in fields such as photodetectors, logic gates, signal amplifiers, and integrated optoelectronic chips.

[0075] The graphene used in this embodiment is a 200×300 square millimeter copper-based monolayer chemical vapor deposition graphene, purchased from the National Graphene Innovation Center in Ningbo, Zhejiang Province, China.

[0076] For the wet transfer of graphene, the process involves: first, spin-coating a polymethyl methacrylate (PMMA) layer onto the graphene / copper / graphene layer at 4000 rpm for 60 seconds. After coating the top graphene with the PMMA layer, the graphene under the copper layer on the other side of the graphene is subjected to oxygen plasma treatment for 15 minutes using a Plasma Washer PT-5 system at an oxygen flow rate of 300 standard cubic centimeters per minute and a power of 60 watts. The copper etching solution formulation is 16 g: 50 mL: 45 mL (copper sulfate pentahydrate: hydrochloric acid: water), and the ammonium persulfate stabilizer formulation is 10 g: 100 mL (ammonium persulfate: water). The supporting copper layer is then etched using the etching solution. After complete copper etching, the graphene / PMMA is transferred three times to fresh deionized water to remove residues. The cleaned graphene / PMMA stack is then transferred onto the target sample, and excess deionized water is allowed to air dry for more than 8 hours. Further annealing at 100 degrees Celsius for 30 minutes enhances the adhesion between graphene and the substrate. PMMA is removed by immersing the graphene / PMMA stack in fresh acetone for 1 hour; this process is repeated at least three times.

[0077] like Figure 3 The diagram illustrates the mechanism analysis of the device in this embodiment: The device uses an emitter (Si substrate) grounded, and carrier transport is controlled by applying bias voltage to the base and collector. The core mechanism is as follows:

[0078] 1) Schottky junction rectification effect: The Schottky junction formed by p-doped graphene / n-type Si has an internal electric field direction from Si to graphene, realizing self-rectification of the Emit-Base and Emit-Collect channels;

[0079] 2) Tunneling control: Base bias (V EB Holes are injected, and some of these holes enter the collector through the graphene-Al2O3-graphene tunnel junction, partially offsetting the internal electric field of the Schottky junction and regulating the current of the Emit-Collect channel.

[0080] 3) Photoelectric response: Under laser irradiation, photogenerated carriers are generated in the Schottky junction region. The built-in electric field separates electrons (injected into the emitter) and holes (entering the collector through the tunnel junction), thereby realizing photocurrent amplification.

[0081] like Figure 4 , Figure 5 and Figure 6 The following are the test results of an embodiment of the present invention: On / Off Ratio: Maximum 15062.24;

[0082] Subthreshold swing (SS): Minimum 218.7274 mV・dec⁻¹;

[0083] Self-rectification determination coefficient (R) 2 ): Maximum 0.9998;

[0084] Amplification factor: β'=19.8 (common emitter), α'=0.95 (common base);

[0085] Optical response band: 532 nm (visible light) to 1064 nm (infrared);

[0086] Long-term stability: No current attenuation was observed during three 250-second pulse tests, and no significant breakdown was observed under high bias voltage.

[0087] Specifically, among them Figure 4 The graphene-silicon phototransistor exhibits photoelectric properties. In this diagram, 'a' represents the IV characteristics of the BE (base-emitter) junction, CE (collector-emitter) junction, and BC (base-collector) junction in the dark state. 'b' represents the I characteristics in the dark state. EC -V EC Output characteristic curve. V EB The voltage changes from -1 V to -5 V in 1 V increments. EC The voltage changes from -2 V to 6 V in 0.1 V increments. c represents I under 532 nm laser conditions (powers of 130 nm, 281 nm, and 490 nm). EC -V EC Output characteristic curve. V EB The voltage changes from -1 V to -5 V in 1 V increments. EC The voltage is varied from -2 V to 6 V in 0.1 V increments. d represents I under 1064 nm laser conditions (powers of 140 nanowatts, 10.97 microwatts, and 23.6 microwatts, respectively). EC -V EC Input characteristic curve. V EB The voltage changes from -1 V to -5 V in 1 V increments. EC The voltage changes from -2 V to 6 V in 0.1 V increments.

[0088] Figure 5 Performance analysis of a graphene-silicon vertical phototransistor. a represents the current (V). EC = 5 V) and current (V) EC The ratio of dV to 0V and the threshold voltage. b is the minimum dV. EC / d(log) 10 I ECV EC The variation range is from 0.2 V to 1 V. c is the linear self-rectifying parameter (Rc). 2 According to V EB The range of variation (from -1 V to -5 V) and V EC The range of variation (from 2 V to 5 V). d is based on I CE and I BC The amplification factor of the common-base amplifier circuit (α = β' / (1+β')) and the amplification factor of the common-emitter amplifier circuit (β' = I) are calculated proportionally. EC / I BC ). And V EB The range of variation is from -1 V to -3 V. These parameters are in V EB It is applicable in the range of -1 V to -5 V, with laser wavelengths of 532 nm and 1064 nm, and laser powers of 532 nm - 130 nmW (1), 281 nmW (2) and 490 nmW (3), 1064 nm - 140 nmW (1), 10.97 μW (2) and 23.6 μW (3).

[0089] Figure 6 For long-term stability testing. (a) I under dark conditions. EC -V EB Feature testing. V EB -t(s) represents an electrical pulse of -3 V (1 s) / -1 V (9 s). (b) I under dark conditions EB -V EB Feature testing. V EB -t(s) represents an electrical pulse of -3 V (1 s) / -1 V (9 s). (c) I under dark conditions EC -V EC Feature testing. V EC -t(s) represents an electrical pulse of 5 V (1 s) / 10 V (10 s).

[0090] Figure 7 shows the structure and characteristics of a two-dimensional graphene-silicon vertical phototransistor device. ai. Fabrication process of the device. j. Optical image of a 4-inch wafer-level phototransistor. kl. Optical image of the device. It encompasses the silicon window (k), the first patterned graphene (l), the aluminum oxide deposition (m), and the second patterned graphene (n). Scale bar is 100 micrometers.

[0091] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0092] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. This application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A wafer-level graphene-silicon three-terminal phototransistor, characterized in that, include: Emitter, base, collector, tunnel layer, and metal electrode; The emitter is a silicon substrate covered with a silicon oxide layer, in which silicon windows are etched, and the silicon substrate is a doped silicon substrate; The base includes: a single layer of graphene located in the silicon window region with the opposite doping mode to the silicon substrate, forming a shallow Schottky junction with the silicon substrate, the base graphene extending from the silicon window to the metal electrode position corresponding to the base on the silicon oxide surface, and a tunnel layer is provided between the metal electrode and the base graphene. The current collector includes: a single layer of current collector graphene isolated on the base graphene by a tunnel layer, extending to the metal electrode position corresponding to the current collector on the silicon oxide surface, wherein the base graphene, the tunnel layer and the current collector graphene form a tunnel junction.

2. The wafer-level graphene-silicon three-terminal phototransistor according to claim 1, characterized in that, The metal electrodes include metal electrodes corresponding to the emitter, base, and collector. The metal electrode corresponding to the emitter is disposed on the silicon substrate; the metal electrodes corresponding to the base and collector are disposed at different positions on the silicon oxide layer.

3. The wafer-level graphene-silicon three-terminal phototransistor according to claim 1, characterized in that, The tunnel layer is an Al2O3 film obtained by atomic layer deposition, or HfO2 or ZrO2 that is compatible with the graphene interface.

4. The wafer-level graphene-silicon three-terminal phototransistor according to claim 1, characterized in that, The doping types of the silicon substrate and the base graphene include: a lightly doped n-type silicon substrate combined with p-doped graphene to form a shallow Schottky junction, or a p-type silicon substrate combined with n-doped graphene to form a Schottky junction.

5. A wafer-level graphene-silicon three-terminal phototransistor according to claim 1, characterized in that, The metal electrodes use Cr / Au as the emitter and collector electrodes and Cr / Ag as the base electrode. The dimensions include: Cr / Au electrodes are 20 nm / 70 nm, and Cr / Ag electrodes are 20 nm / 300 nm.

6. A wafer-level graphene-silicon three-terminal phototransistor according to claim 5, characterized in that, The metal electrode also includes Ti / Au and Ni / Au electrodes, which replace Cr / Ag and Cr / Au electrodes to ensure ohmic contact and stability between the electrode and graphene / silicon.

7. A method for fabricating a transistor according to any one of claims 1-6, characterized in that, include: Electrodes and metal pads for emitter and collector electrodes were fabricated using lightly doped silicon wafers with a surface-grown thermally oxidized SiO2 layer, via photolithography and electron beam evaporation. Photoresist is used for patterning, and an etching solution is used to selectively etch the SiO2 layer to form a silicon window; Monolayer graphene was prepared by chemical vapor deposition and transferred to a substrate containing silicon windows using PMMA-assisted wet transfer technology. The graphene was then patterned by photolithography and excess graphene was etched using oxygen plasma to form a Schottky junction. Tunnel dielectric films are grown by atomic layer deposition to cover the silicon window region and the metal pad region; The second wet transfer CVD process transfers monolayer graphene to the surface of the tunneling medium film. After photolithography patterning, excess graphene is etched by oxygen plasma to form a graphene-tunneling medium-graphene tunnel junction. Wet etching of the tunnel layer in the collector metal pad area reduces contact resistance; The device was fabricated by depositing the base electrode using electron beam evaporation.

8. The preparation method according to claim 7, characterized in that, When the tunnel dielectric film is made of Al2O3, the Al2O3 layer in the collector metal pad area is etched by wet etching with Al etching solution. The Al etching solution has a ratio of H3PO4: HNO3:CH3COOH: H2O = 16: 1:1:

2.

9. The preparation method according to claim 7, characterized in that, The oxygen plasma etching of excess graphene used during the transfer of each graphene layer includes two etching processes. The first etching process involves treating the excess monolayer graphene with oxygen plasma at an O2 flow rate of 300 sccm and a power of 50 W for 90 seconds. The second etching process involves treating the excess monolayer graphene with an O2 flow rate of 300 sccm and a power of 30 W for 3 minutes.

10. The preparation method according to claim 7, characterized in that, The SiO2 layer is formed by thermal oxidation of the silicon wafer surface at a depth of 100±5 nanometers.

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