Display panel, preparation method thereof and display device

Abstract

The invention discloses a display panel and a preparation method thereof and a display device, the display panel comprises a substrate and a driving circuit layer which are sequentially arranged along a first direction, the driving circuit layer is provided with a cathode signal line in a display area of the display panel, and one side, far away from the substrate, of the driving circuit layer is provided with a hollow area in the display area; a cathode layer is arranged on one side, far away from the substrate, of the driving circuit layer, extends to the hollow area and is in lap joint with the driving circuit layer, so that the cathode layer is electrically connected with a cathode signal line of the driving circuit layer. In the display panel, the cathode layer and the driving circuit layer are in lap joint in the display area by utilizing the hollow area arranged on one side, far away from the substrate, of the driving circuit layer, so that the cathode layer is electrically connected with the cathode signal line of the driving circuit layer, the current density of the VSS routing at the lower fillet of the driving circuit layer is reduced, the burning risk is reduced, and the display quality is improved. And the resistance of the whole VSS wiring of the display panel can be reduced, so that the voltage drop is reduced, and the brightness uniformity of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel, its manufacturing method, and a display device. Background Technology

[0002] In organic light-emitting diode (OLED) panels, the cathode layer is typically overlapped with the ring-shaped metal trace of the driving circuit layer in the bezel area of ​​the display panel to form the overall VSS trace of the display panel. The overall VSS trace has a large resistance and a large voltage drop, resulting in poor brightness uniformity of the display panel. It also causes the current density of the driving circuit layer in the lower rounded corner VSS trace to still be too high, which can lead to burn-in problems and fail to meet the high brightness requirements of customers. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a display panel, a method for manufacturing the same, and a display device.

[0004] In a first aspect, a display panel is provided, comprising: a substrate and a driving circuit layer disposed sequentially along a first direction, wherein the driving circuit layer provides a cathode signal line in the display area of ​​the display panel, and a cutout area is provided in the display area on the side of the driving circuit layer away from the substrate;

[0005] A cathode layer is disposed on the side of the driving circuit layer away from the substrate. The cathode layer extends to the cutout area and overlaps with the driving circuit layer so that the cathode layer is electrically connected to the cathode signal line of the driving circuit layer.

[0006] In addition, the display panel of the present invention may also have the following additional technical features:

[0007] In some embodiments, the display panel further includes a metal isolation pillar disposed in the cutout area, and the cathode layer extends to the cutout area and is disconnected from the side of the metal isolation pillar.

[0008] In some embodiments, the metal isolation pillar overlaps with the drive circuit layer, and the metal isolation pillar is electrically connected to the cathode signal line of the drive circuit layer;

[0009] The cathode layer extends to the hollow area and overlaps with the metal isolation pillar, so that the cathode layer is electrically connected to the cathode signal line of the drive circuit layer through the metal isolation pillar.

[0010] In some embodiments, the metal isolation post includes a main body located at the bottom of the hollow area and limbs located at the two side edges of the main body. The limbs extend away from the main body so that the two sides of the main body and the limbs respectively form an undercut structure.

[0011] In some embodiments, the main body and the limb are integrally formed.

[0012] In some embodiments, the display panel further includes a light-emitting layer disposed between the driving circuit layer and the cathode layer, the light-emitting layer extending to the cutout area and being disconnected from the side of the metal isolation pillar.

[0013] In some embodiments, the display panel further includes a pixel definition layer disposed between the cathode layer and the driving circuit layer; the pixel definition layer includes a plurality of spaced pixel opening regions, the cutout region and the pixel opening regions are spaced apart along a second direction, the second direction being perpendicular to the first direction.

[0014] In some embodiments, an anode layer is disposed within the pixel opening region, and the anode layer is disposed between the cathode layer and the driving circuit layer.

[0015] In some embodiments, the metal isolation pillar is partially disposed on the same layer as the anode layer, and the remaining portion is disposed on the same layer as the drive circuit layer; or, the metal isolation pillar is disposed on the same layer as the drive circuit layer.

[0016] In some embodiments, the driving circuit layer includes at least one source / drain metal layer disposed between the substrate and the anode layer, wherein the cathode signal line is disposed in the display area by at least one source / drain metal layer.

[0017] In some embodiments, the cathode signal line includes a plurality of parallel first cathode signal lines, each of which is disposed within the source / drain metal layer.

[0018] In some embodiments, the cathode signal line further includes multiple parallel second cathode signal lines, the first cathode signal line and the second cathode signal lines are intersecting, and the first cathode signal line and the second cathode signal line are respectively disposed on different source and drain metal layers.

[0019] In some embodiments, the cutout area is located at the junction of the first cathode signal line and the second cathode signal line.

[0020] Secondly, a method for manufacturing a display panel is provided, comprising:

[0021] A driving circuit layer formed on a substrate;

[0022] A cathode signal line is provided in the display area of ​​the display panel in the driving circuit layer, and a cutout area is formed in the display area on the side of the driving circuit layer away from the substrate;

[0023] A cathode layer is formed on the side of the driving circuit layer away from the substrate. The cathode layer extends to the cutout area and overlaps with the driving circuit layer so that the cathode layer is electrically connected to the cathode signal line of the driving circuit layer.

[0024] Thirdly, a display device is provided, the display device comprising the display panel described in any embodiment of the present application, or the display panel obtained by the preparation method of the display panel described in any embodiment of the present application.

[0025] This application provides a display panel and its manufacturing method and display device. The display panel has a cutout area on one side of the driving circuit layer located in the display area of ​​the display panel, which allows the cathode layer to overlap with the driving circuit layer in the cutout area. This enables the cathode signal lines of the cathode layer and the driving circuit layer to be electrically connected in the display area, reducing the overall resistance of the VSS traces of the display panel, reducing voltage drop, and improving the brightness uniformity of the display panel. In addition, more current from the cathode layer can flow directly from the display area to the port, reducing the current density of the VSS traces at the rounded corners under the driving circuit layer, reducing the risk of burn-in, meeting the high brightness requirements of customers, and is suitable for display panels of various sizes. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 This is an exemplary structural diagram of an existing display panel;

[0028] Figure 2 An exemplary top view of the display panel provided in an embodiment of this application;

[0029] Figure 3 This is a first exemplary side view of a display panel provided in an embodiment of this application;

[0030] Figure 4 This is a second exemplary side view of the display panel provided in an embodiment of this application;

[0031] Figure 5 A third exemplary side view of the display panel provided in the embodiments of this application;

[0032] Figure 6 A fourth exemplary side view of the display panel provided in the embodiments of this application;

[0033] Figure 7 An exemplary structural diagram of the metal isolation column provided in the embodiments of this application;

[0034] Figure 8 for Figure 3 The flowchart of the fabrication method of the display panel is shown.

[0035] Figure 9 for Figure 4 The flowchart of the fabrication method of the display panel is shown.

[0036] Figure 10 for Figure 5 The flowchart of the fabrication method of the display panel is shown.

[0037] Figure 11 for Figure 6 The flowchart of the fabrication method of the display panel is shown.

[0038] Figure 12 This is an exemplary structural diagram of a display device provided in an embodiment of this application.

[0039] In the above image:

[0040] 10 Display panel; 101 Display area; 102 Bezel area; 11 Cathode layer; 12 Emitting layer; 13 Pixel definition layer; 14 Anode layer; 15 Metal isolation pillar; 151 Main body; 152 Limbs;

[0041] 16 Substrate; 17 First source / drain metal layer; 18 First planarization layer; 19 Second source / drain metal layer; 20 Second planarization layer; 21 Third source / drain metal layer; 22 Third planarization layer; 23 Cathode signal line; 231 First cathode signal line; 232 Second cathode signal line; 24 Circular metal trace; 25 Mask;

[0042] 100 Display device. Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0046] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0047] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0048] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0049] Exemplary embodiments are described herein with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes.

[0050] In existing OLED panel structures, the anode signal lines (VDD traces) of the anode layer 14 can typically form a mesh structure in the display area 101 to reduce resistance; the cathode layer 11 is an EV vapor deposition material, and currently only a limited area is designed in the bezel area 102 outside the display area 101 (AA area) to overlap with the backplate metal of the driving circuit layer. Figure 1 This is an exemplary structural diagram of an existing OLED display panel 10. The driving circuit layer has a ring-shaped metal trace 24 only in the bezel area 102. This ring-shaped metal trace 24 is introduced from the Power IC, enters the bezel area 102 from the left and right sides of the display panel 10, and overlaps with the cathode layer 11 in the bezel area 102 to form the overall VSS trace of the display panel 10, finally transmitting the VSS signal to the pixel circuit of the display area 101. Therefore, the driving circuit layer only overlaps with the cathode layer 11 in the bezel area 102, the resistance of the overlap area is relatively large, and the resistance of the overall VSS trace of the display panel 10 is also relatively large, resulting in a large voltage drop and poor brightness uniformity of the display panel 10. At the same time, as the bezel of the display panel 10 is extremely narrowed, the VSS trace in the lower bezel area 102 is also extremely narrowed, resulting in excessive current density of the VSS trace in the lower rounded corner of the display area 101 of the display panel 10, which is prone to burn-in under high brightness conditions. Especially for large-size products, the current is already relatively large, making burn-in problems more likely. Among them, the lower rounded corner VSS trace refers to the VSS trace corresponding to the connection between the ring metal trace 24 in the drive circuit layer and the signal output terminal of the drive circuit.

[0051] To solve the above-mentioned technical problems, the first aspect of the embodiments of this application is as follows: Figures 2 to 6 As shown, a display panel 10 is provided, including: a substrate 16 and a driving circuit layer arranged sequentially along a first direction, wherein the driving circuit layer provides a cathode signal line 23 in the display area 101 of the display panel 10, and a cutout area is provided in the display area 101 on the side of the driving circuit layer away from the substrate 16.

[0052] A cathode layer 11 is disposed on the side of the driving circuit layer away from the substrate 16. The cathode layer 11 extends to the cutout area and overlaps with the driving circuit layer so that the cathode layer 11 is electrically connected to the cathode signal line 23 of the driving circuit layer.

[0053] Specifically, the display panel 10 includes a display area 101 (AA area) and a border area 102 located around the display area 101. The display area 101 is the pixel structure area of ​​the display panel 10. The border area 102 is located outside the display area 101 and a driving circuit, such as a driving circuit GOA, is provided in the border area 102.

[0054] The display panel 10 includes a substrate 16 and a driving circuit layer arranged sequentially along a first direction. The driving circuit layer provides cathode signal lines 23 in the display area 101 of the display panel 10, which can reduce the overall VSS trace resistance of the display panel 10, thereby reducing the voltage drop (IR drop) and improving the brightness uniformity of the display panel 10.

[0055] A cutout area is formed in the display area 101 of the display panel 10 on the side of the driving circuit layer away from the substrate 16. A cathode layer 11 is formed on the same side of the driving circuit layer away from the substrate 16. The cathode layer 11 extends along a second direction to the cutout area and overlaps with the driving circuit layer therein, electrically connecting the cathode layer 11 to the cathode signal line 23 within the driving circuit layer. This provides voltage to the cathode layer 11 of the display panel 10, causing the light-emitting layer 12 of the display panel 10 to emit light. This also reduces the overall VSS trace resistance of the display panel 10, thereby reducing the voltage drop (IR drop) and improving the brightness uniformity of the display panel 10. For the organic light-emitting display panel 10, the VSS signal line can be an ELVSS signal line. Figure 3 In this context, the z-direction is the first direction, the x-direction is the second direction, and the second direction is perpendicular to the first direction.

[0056] In the display panel 10 provided in this application embodiment, a cutout area is provided in the display area 101 of the display panel 10 on the side of the driving circuit layer away from the substrate 16, so that the cathode layer 11 can overlap with the driving circuit layer in the cutout area, thereby realizing the electrical connection between the cathode layer 11 and the cathode signal line 23 in the driving circuit layer in the display area 101 of the display panel 10. This allows more current from the cathode layer 11 to flow directly from the display area 101 to the Port, reducing the current density of the VSS signal line at the rounded corner of the driving circuit layer, reducing the risk of burn-in, and reducing the overall resistance of the VSS traces of the display panel 10, thereby reducing the voltage drop and improving the brightness uniformity of the display panel 10. This is suitable for display panels 10 of various sizes.

[0057] In some implementations, such as Figures 2 to 7 As shown, the display panel 10 also includes a metal isolation pillar 15, which is disposed in the hollow area. The cathode layer 11 extends to the hollow area and is disconnected from the side of the metal isolation pillar 15.

[0058] Specifically, the cathode layer 11 is formed on the side of the driving circuit layer away from the substrate 16. Due to the metal isolation pillar 15 structure provided in the cutout area, the cathode layer 11 will extend along the second direction to the cutout area and be disconnected on the side of the metal isolation pillar 15 during the formation process, and a disconnected common layer will be formed on the side of the metal isolation pillar 15 away from the driving circuit layer.

[0059] In some implementations, such as Figures 2 to 7 As shown, the metal isolation pillar 15 overlaps with the driving circuit layer, and the metal isolation pillar 15 is electrically connected to the cathode signal line 23 of the driving circuit layer;

[0060] The cathode layer 11 extends to the hollow area and overlaps with the metal isolation pillar 15, so that the cathode layer 11 is electrically connected to the cathode signal line 23 of the driving circuit layer through the metal isolation pillar 15.

[0061] Specifically, the driving circuit layer has metal isolation pillars 15 in the cutout area. The bottom of the metal isolation pillars 15 covers the driving circuit layer, increasing the contact area between the metal isolation pillars 15 and the driving circuit layer, and improving the electrical connection performance between the cathode signal lines 23 in the driving circuit layer and the metal isolation pillars 15. The cathode layer 11 extends to the cutout area, and the cathode layer 11 overlaps with the side of the cutout area and the metal isolation pillars 15, so that the cathode layer 11 is indirectly electrically connected to the cathode signal lines 23 of the driving circuit layer through the metal isolation pillars 15. This further reduces the resistance of the overall VSS traces of the display panel 10, reduces the voltage drop, and improves the brightness uniformity of the display panel 10.

[0062] Furthermore, although the metal isolation pillar 15 will cause the cathode layer 11 material to break at the position of the metal isolation pillar 15 during the evaporation process, the good ductility of the cathode layer 11 material allows the cathode layer 11 to extend into the hollow area and overlap with the metal isolation pillar 15, ensuring the integrity of signal transmission within the cathode layer 11.

[0063] The cathode layer 11 is preferably made of a material with a low work function to facilitate electron injection into the organic layer, while also possessing good light transmittance and conductivity. Specific examples of cathode layer 11 materials include, but are not limited to, metals, metal oxides, and metal alloys such as aluminum (Al), silver (Ag), gold (Au), magnesium (Mg), indium tin oxide (ITO), calcium / magnesium (Ca / Mg), calcium / silver (Ca / Ag), and barium / silver (Ba / Ag).

[0064] In some implementations, such as Figures 2 to 7 As shown, the metal isolation column 15 includes a main body 151 located at the bottom of the hollow area, and limbs 152 located at the two side edges of the main body 151. The limbs 152 extend away from the main body 151, so that the two sides of the main body 151 and the limbs 152 respectively form an undercut structure.

[0065] Specifically, the metal isolation pillar 15 includes a main body 151 and two limbs 152 located on both sides of the main body 151. One side of the main body 151 is located close to the drive circuit layer, and two limbs 152 are located on the edge of the other side of the main body 151. The limbs 152 are parallel to the main body 151 and extend away from the main body 151, so that the bottom end of the limbs 152 forms an undercut structure with the side of the main body 151. This facilitates the cathode layer 11 to extend to the undercut structure in the hollow area to achieve the overlap between the cathode layer 11 and the drive circuit layer, thereby enabling the cathode layer 11 to be directly electrically connected to the cathode signal line 23 of the drive circuit layer. Furthermore, the cathode layer 11 extends to the hollow area and overlaps with the main body 151 of the metal isolation pillar 15. The main body 151 is electrically connected to the cathode signal line 23 of the drive circuit layer, so that the cathode layer 11 is electrically connected to the cathode signal line 23 of the drive circuit layer through the metal isolation pillar 15.

[0066] In some embodiments, the main body 151 and the limb 152 are integrally formed.

[0067] Specifically, the main body 151 and the limb 152 are integrally formed from the same metal material, which is convenient to process and low in cost, making the manufacturing process of the metal isolation column 15 simple.

[0068] In some implementations, such as Figures 2 to 6 As shown, the display panel 10 also includes a light-emitting layer 12, which is disposed between the driving circuit layer and the cathode layer 11. The light-emitting layer 12 extends to the hollow area and is disconnected from the side of the metal isolation pillar 15.

[0069] Specifically, a light-emitting layer 12 is disposed between the driving circuit layer and the cathode layer 11. Due to the difference in ductility between the material of the light-emitting layer 12 (EL material) and the material of the cathode layer 11, the ductility of the cathode layer 11 material is superior to that of the light-emitting layer 12 material. This causes the light-emitting layer 12 to extend along the second direction to the hollow area and break off at the side of the metal isolation pillar 15 (i.e., the light-emitting layer 12 and the metal isolation pillar 15 do not overlap), and a broken common layer is formed on the side of the metal isolation pillar 15 away from the driving circuit layer. The material of the light-emitting layer 12 is a conventional material in the art, and will not be described in detail in this application.

[0070] In some implementations, such as Figures 2 to 6 As shown, the display panel 10 further includes a pixel definition layer 13, which is disposed between the cathode layer 11 and the driving circuit layer; the pixel definition layer 13 includes a plurality of spaced pixel opening areas, the cutout area and the pixel opening areas are spaced apart along a second direction, and the second direction is perpendicular to the first direction.

[0071] Specifically, the pixel definition layer 13 is disposed between the cathode layer 11 and the driving circuit layer. Further, the pixel definition layer 13 is disposed between the light-emitting layer 12 and the driving circuit layer. For example, the pixel definition layer 13 is formed on the side of the driving circuit layer away from the substrate 16, the light-emitting layer 12 is formed on the side of the pixel definition layer 13 away from the driving circuit layer, and the cathode layer 11 is formed on the side of the light-emitting layer 12 away from the pixel definition layer 13. The pixel definition layer 13 has multiple spaced pixel opening regions along a second direction. The cutout regions and pixel opening regions are spaced apart along the second direction, meaning the cutout regions avoid the pixel opening regions, thus preventing the cathode signal lines from affecting the light-emitting performance of the display panel 10. It can be understood that the pixel definition layer 13 is disconnected from the side of the metal isolation pillar 15, and a disconnected common layer is formed on the side of the metal isolation pillar 15 away from the driving circuit layer.

[0072] In some implementations, such as Figures 2 to 6 As shown, an anode layer 14 is disposed within the pixel opening area, and the anode layer 14 is disposed between the cathode layer 11 and the driving circuit layer.

[0073] Specifically, an anode layer 14 is disposed in the opening area of ​​the pixel definition layer 13, wherein the anode layer 14 is disposed between the cathode layer 11 and the driving circuit layer, and further, the anode layer 14 is disposed between the driving circuit layer and the light-emitting layer 12. For example, the pixel definition layer 13 is formed on the side of the driving circuit layer away from the substrate 16, and a plurality of spaced-apart pixel opening areas are formed in the pixel definition layer 13. An anode layer 14 is disposed in each pixel opening area, and a light-emitting layer 12 is formed on the side of the anode layer 14 away from the driving circuit layer. The light-emitting layer 12 covers the pixel definition layer 13 and the anode layer 14, and a cathode layer 11 is formed on the side of the light-emitting layer 12 away from the pixel definition layer 13.

[0074] The anode layer 14 is made of a high work function electrode material, such as transparent oxide ITO or IZO; it can also be a composite electrode formed by ITO / Ag / ITO, Ag / IZO, CNT / ITO, CNT / IZO, GO / ITO, GO / IZO, etc.

[0075] In some implementations, such as Figures 2 to 6 As shown, the driving circuit layer includes at least one source / drain metal layer disposed between the substrate 16 and the anode layer 14, and the cathode signal line 23 is disposed in the display area 101 by at least one source / drain metal layer.

[0076] Specifically, the substrate 16 can be a flexible substrate, such as a PI (polyimide) substrate 16. The driving circuit layer includes at least one source / drain metal layer disposed on the substrate 16. Each source / drain metal layer is disposed between the substrate 16 and the anode layer 14. At least one of the multiple source / drain metal layers has a cathode signal line 23 arranged in the display area 101. The cathode signal line 23 is electrically connected to the driving circuit of the driving circuit layer, reducing the resistance and power consumption of the overall VSS trace of the display panel 10, thereby reducing the voltage drop and improving the brightness uniformity of the display panel 10. The driving circuit layer has a ring-shaped metal trace 24 arranged in the bezel area 102 of the display panel 10. The cathode signal line 23 in the display area 101 of the driving circuit layer is electrically connected to the ring-shaped metal trace 24 to reduce the resistance of the overall VSS trace of the display panel 10.

[0077] Those skilled in the art can set the number of source and drain metal layers according to actual needs, such as 1, 2, 3, 4, etc. For example, the driving circuit layer includes a first source and drain metal layer 17 (SD1) disposed on the substrate 16, a second source and drain metal layer 19 (SD2) disposed on the side of the first source and drain metal layer 17 away from the substrate 16, and a third source and drain metal layer 21 (SD3) disposed on the second source and drain metal layer 19 away from the first source and drain metal layer 17, etc.

[0078] In some implementations, such as Figures 2 to 6 As shown, the driving circuit layer further includes at least one planarization layer, the number of which is the same as the number of source / drain metal layers, and each planarization layer is disposed on the side of the corresponding source / drain metal layer away from the substrate 16.

[0079] Specifically, the driver circuit layer also includes a planarization layer. For example, such as... Figure 3 As shown, the driving circuit layer includes a first source / drain metal layer 17 (SD1) disposed on the substrate 16. A first planarization layer 18 is formed on the side of the first source / drain metal layer 17 away from the substrate 16. A second source / drain metal layer 19 is formed on the side of the first planarization layer 18 away from the first source / drain metal layer 17. A second planarization layer 20 is formed on the side of the second source / drain metal layer 19 away from the first source / drain metal layer 17. This example illustrates the structure of the driving circuit layer with two source / drain metal layers and two planarization layers. The design principle is the same for driving circuit layers with three or more source / drain metal layers and planarization layers, and will not be repeated in the embodiments of this application.

[0080] In some implementations, such as Figure 2 As shown, the cathode signal line 23 includes multiple parallel first cathode signal lines 231, which are disposed within the source / drain metal layer.

[0081] Specifically, the source / drain metal layer provides multiple parallel first cathode signal lines 231 in the display area 101 of the display panel 10. The two ends of each first cathode signal line 231 are electrically connected to a ring-shaped metal trace 24 in the bezel area 102 of the source / drain metal layer, thereby reducing the overall VSS trace resistance of the display panel 10, decreasing voltage drop, and improving the brightness uniformity of the display panel 10. The first cathode signals can extend within the source / drain metal layer along a second direction or a third direction. The second direction and the third direction intersect and lie on the same plane, preferably perpendicular to each other. The first direction is perpendicular to the plane where the second and third directions intersect. Figure 2 The y-direction in the equation is the third direction.

[0082] In some implementations, such as Figure 2 As shown, the cathode signal line 23 also includes multiple parallel second cathode signal lines 232. The first cathode signal line 231 and the second cathode signal line 232 are intersected and disposed on different source and drain metal layers.

[0083] Specifically, multiple parallel second cathode signal lines 232 are electrically connected to the ring-shaped metal trace 24 of the driving circuit layer in the bezel area 102 to reduce the overall VSS trace resistance of the display panel 10, reduce voltage drop, and improve the brightness uniformity of the display panel 10. The first cathode signal line 231 and the second cathode signal line 232 intersect in the plane of the display panel 10, preferably perpendicularly. The first cathode signal line 231 and the second cathode signal line 232 are located in different source / drain metal layers, and the cutout area is located at the horizontal and vertical overlap of the first cathode signal line 231 and the second cathode signal line 232. In this example, by arranging multiple first cathode signal lines 231 along a second direction (e.g., horizontal) and multiple second cathode signal lines 232 along a third direction (e.g., vertical) within the driving circuit layer, a mesh-like SIP trace structure (including the horizontal first cathode signal lines 231 and the vertical second cathode signal lines 232) is formed in the display area 101. The mesh-like SIP trace structure is electrically connected to the annular metal trace 24 of the driving circuit layer in the frame area 102. This further reduces the overall VSS trace resistance of the display panel 10. Furthermore, the SIP traces overlap with the cathode layer 11 in the display area 101, achieving true VSS In Panel, reducing the VSS resistance of the display panel 10 in the display area 101, reducing the current density at the lower rounded corners, reducing the risk of VSS trace burn-in, and achieving higher brightness.

[0084] For example, such as Figure 3As shown, the driving circuit layer includes a first source / drain metal layer 17 and a second source / drain metal layer 19 sequentially disposed on the substrate 16. The second source / drain metal layer 19 is located between the anode layer 14 and the first source / drain metal layer 17. The first source / drain metal layer 17 contains a plurality of parallel first cathode signal lines 231. The second source / drain metal layer 19 contains a plurality of parallel second cathode signal lines 232. The first cathode signal lines 231 and the second cathode signal lines 232 are arranged vertically and overlap at the intersection of the horizontal and vertical axes to form a mesh structure of SIP traces. The cutout area is disposed at the intersection of the horizontal and vertical axes.

[0085] For example, such as Figure 4 As shown, the driving circuit layer includes a first source / drain metal layer 17 sequentially disposed on the substrate 16. Figure 4 (Not shown) A second source / drain metal layer 19 and a third source / drain metal layer 21, the third source / drain metal layer 21 being located between the anode layer 14 and the second source / drain metal layer 19. The second source / drain metal layer 19 contains a plurality of parallel first cathode signal lines 231; the third source / drain metal layer 21 contains a plurality of parallel second cathode signal lines 232. The first cathode signal lines 231 and the second cathode signal lines 232 are vertically arranged at the intersection of the horizontal and vertical axes to form a mesh structure of SIP wiring, and the cutout area is located at the intersection of the horizontal and vertical axes.

[0086] In some embodiments, a portion of the metal isolation pillar 15 is disposed in the same layer as the anode layer 14, and the remaining portion is disposed in the same layer as the drive circuit layer; or, the metal isolation pillar 15 is disposed in the same layer as the drive circuit layer.

[0087] Specifically, there are several ways to position the metal isolation pillar 15, as follows:

[0088] For example, a portion of the metal isolation pillar 15 is disposed on the same layer as the anode layer 14, and the remaining portion is disposed on the same layer as the driving circuit layer. For instance, the limb portion 152 of the metal isolation pillar 15 is disposed on the same layer as the anode layer, and the main body portion 151 is disposed on the same layer as the driving circuit layer. The metal isolation pillar 15 can be made of the same type of metal material as the anode layer 15. When this metal material is deposited on the side of the driving circuit layer away from the substrate 16, the metal material forms the anode layer 14 between the pixel opening areas of the pixel definition layer 13, and forms the metal isolation pillar 15 in the cutout area. Specifically:

[0089] For example, such as Figure 3As shown, a first source / drain metal layer 17 is disposed on a substrate 16 as a driving circuit layer. A first planarization layer 18 is disposed on the side of the first source / drain metal layer 17 away from the substrate 16. A second source / drain metal layer 19 is disposed on the side of the first planarization layer 18 away from the first source / drain metal layer 17. A second planarization layer 20 is disposed on the side of the second source / drain metal layer 19 away from the first source / drain metal layer 17. The first source / drain metal layer 17 has multiple parallel first cathode signal lines 231 disposed in the display area 101. The second source / drain metal layer 19 has multiple parallel second cathode signal lines 232 disposed in the display area 101. The first cathode signal lines 231 and the second cathode signal lines 232 overlap at the intersection of the horizontal and vertical axes. A cutout area is provided on the side of the second planarization layer 20 away from the first planarization layer 18 at the junction of the first cathode signal line 231 and the second cathode signal line 232. A pixel definition layer 13 is formed on the side of the second planarization layer 20 away from the first planarization layer 18. A plurality of pixel opening areas are provided at intervals along the second direction in the pixel definition layer 13. When the second planarization layer 20 deposits metal material on the side away from the first planarization layer 18, an anode layer 14 is formed in the pixel opening area, and a metal isolation pillar 15 is formed in the cutout area. The main body 151 of the metal isolation pillar 15 overlaps the surface of the second source / drain metal layer 19 and is electrically connected to the second cathode signal line 232 in the second source / drain metal layer 19. The limb 151 of the metal isolation pillar 15 is disposed in the same layer as the anode layer 14.

[0090] For example, such as Figure 4 As shown, the driving circuit layer includes a second source / drain metal layer 19 disposed on the substrate 16. A second planarization layer 20 is disposed on the side of the second source / drain metal layer 19 away from the substrate 16. A third source / drain metal layer 21 is disposed on the side of the second planarization layer 20 away from the second source / drain metal layer 19. A third planarization layer 22 is disposed on the side of the third source / drain metal layer 21 away from the second source / drain metal layer 19. The second source / drain metal layer 19 has multiple parallel first cathode signal lines 231 disposed in the display area 101. The third source / drain metal layer 21 has multiple parallel second cathode signal lines 232 disposed in the display area 101. The first cathode signal lines 231 and the second cathode signal lines 232 overlap at the intersection of the horizontal and vertical axes. A cutout area is provided on the side of the third planarization layer 22 away from the second planarization layer 20 at the junction of the first cathode signal line 231 and the second cathode signal line 232. A pixel definition layer 13 is formed on the side of the third planarization layer 22 away from the second planarization layer 20. Multiple pixel opening areas are provided at intervals along the second direction in the pixel definition layer 13. When the third planarization layer 22 deposits metal material on the side away from the second planarization layer 20, an anode layer 14 is formed in the pixel opening area, and a metal isolation pillar 15 is formed in the cutout area. The main body 151 of the metal isolation pillar 15 overlaps the surface of the third source / drain metal layer 21 and is electrically connected to the second cathode signal line 232 in the third source / drain metal layer 21. The limb 152 of the metal isolation pillar 15 is disposed in the same layer as the anode layer 14.

[0091] For example, the metal isolation pillar 15 is set on the same layer as the drive circuit layer, and the metal isolation pillar 15 and the drive circuit layer use the same type of metal material, specifically:

[0092] For example, such as Figure 5 As shown, the driving circuit layer includes a first source / drain metal layer 17 disposed on the substrate, and a plurality of parallel first cathode signal lines 231 disposed in the first source / drain metal layer 17; a first planarization layer 18 is disposed on the side of the first source / drain metal layer 17 away from the substrate 16, and a cutout area is disposed in the display area 101 on the side of the first planarization layer 18 away from the first source / drain metal layer 17; a metal isolation pillar 15 is formed on the side of the first planarization layer 18 away from the substrate 16 and located in the cutout area; the main body 151 of the metal isolation pillar 15 covers the surface of the first source / drain metal layer 17 so that the main body 151 is electrically connected to the first cathode signal lines 231 in the first source / drain metal layer 17; and the limbs 152 of the metal isolation pillar 15 cover the first planarization layer 18.

[0093] like Figure 6 As shown, the driving circuit layer includes a second source / drain metal layer 19 disposed on the substrate 16, and a plurality of parallel first cathode signal lines 231 disposed in the second source / drain metal layer 19; a second planarization layer 20 is disposed on the side of the second source / drain metal layer 19 away from the substrate 16, and a cutout area is disposed in the display area 101 on the side of the second planarization layer 20 away from the second source / drain metal layer 19; a metal isolation pillar 15 is formed on the side of the second planarization layer 20 away from the substrate 16 and located in the cutout area; the main body portion 151 of the metal isolation pillar 15 covers the surface of the second source / drain metal layer 19 so that the main body portion 151 is electrically connected to the first cathode signal lines 231 in the second source / drain metal layer 17; and the limb portion 152 of the metal isolation pillar 15 covers the second planarization layer 20.

[0094] Secondly, a method for manufacturing a display panel is provided, comprising:

[0095] A driving circuit layer formed on substrate 16;

[0096] A cathode signal line 23 is provided in the display area 101 of the display panel 10, and a cutout area is formed in the display area 101 on the side of the driving circuit layer away from the substrate 16.

[0097] A cathode layer 11 is formed on the side of the driving circuit layer away from the substrate 16. The cathode layer 11 extends to the cutout area and overlaps with the driving circuit layer so that the cathode layer 11 is electrically connected to the cathode signal line 23 of the driving circuit layer.

[0098] Specifically, by setting a cutout area in the display area 101 of the display panel 10 on the side of the driving circuit layer away from the substrate 16, the cathode layer 11 can overlap with the driving circuit layer in the cutout area, thereby achieving electrical connection between the cathode layer 11 and the cathode signal line 23 in the driving circuit layer in the display area 101 of the display panel 10. This allows more current from the cathode layer 11 to flow directly from the display area 101 to the port, reducing the current density of the VSS signal line at the rounded corners under the driving circuit layer, reducing the risk of burn-in, and also reducing the overall VSS resistance of the display panel 10, thereby reducing voltage drop and improving the brightness uniformity of the display panel 10. It is understood that the specific technical features and effects of the display panel manufacturing method are consistent with the technical features and effects of the display panel 10 provided in any embodiment of this application, and will not be repeated here.

[0099] The following specific embodiments illustrate the method for manufacturing the display panel of this application:

[0100] Example 1

[0101] A method for manufacturing a display panel, such as Figure 8 As shown, it includes:

[0102] S210: A first metal material is deposited on the substrate 16, and the first metal material is patterned to obtain a first source / drain metal layer 17. The first source / drain metal layer 17 has multiple parallel first cathode signal lines 231 arranged in the display area 101, and a ring-shaped metal trace 24 arranged in the frame area 102. The multiple first cathode signal lines 231 and the ring-shaped metal trace 24 are connected in parallel and electrically connected to the output terminal of the driving circuit. A first planarization layer 18 is formed by deposition on the side of the first source / drain metal layer 17 away from the substrate 16, and the first planarization layer 18 covers the first source / drain metal layer 17.

[0103] S220: A second metal material is deposited on the side of the first planarization layer 18 away from the substrate 16, and the second metal material is patterned to obtain a second source / drain metal layer 19; wherein, the second source / drain metal layer 19 has multiple parallel second cathode signal lines 232 arranged in the display area 101, and a ring metal trace 24 arranged in the frame area 102, the multiple second cathode signal lines 232 and the ring metal trace 24 are connected in parallel and electrically connected to the output terminal of the driving circuit, and the multiple second cathode signal lines 232 and the multiple first cathode signal lines 231 overlap at the horizontal and vertical intersections to form cathode signal lines.

[0104] S230: A second planarization layer 20 is formed by deposition on the side of the second source / drain metal layer 19 away from the first source / drain metal layer 17. The second planarization layer 20 is patterned to form a hollow area, wherein the hollow area is located at the horizontal and vertical overlap of the first cathode signal line 231 and the second cathode signal line 232.

[0105] S240: A third metal material is deposited on the side of the second planarization layer 20 away from the first planarization layer 18. The third metal material forms an anode layer 14 in the pixel opening area of ​​the pixel definition layer 13 and a metal isolation pillar 15 in the hollow area. The main body 151 of the metal isolation pillar 15 covers the second source / drain metal layer 19 and is electrically connected to the second cathode signal line 232 in the second source / drain metal layer 19. The limb 152 of the metal isolation pillar 15 covers the surface of the second planarization layer 20.

[0106] S250: The second planarization layer 20 is patterned by first coating photoresist, then patterning the photoresist through a mask 25, finally developing to remove the photoresist, and etching away the second planarization layer 20 between the two sides of the main body 151 and the bottom of the limb 152 to form an undercut structure.

[0107] S260: A pixel definition layer 13 is formed on the side of the anode layer 14 away from the second planarization layer 20. The pixel definition layer 13 includes a plurality of pixel opening regions spaced apart along the second direction. A light-emitting layer 12 is formed on the side of the pixel definition layer 13 away from the anode layer 14. The light-emitting layer 12 extends along the second direction to the hollow area and is disconnected on the side of the metal isolation pillar 15. A cathode layer 11 is formed on the side of the light-emitting layer 12 away from the pixel definition layer 13 by vapor deposition. The cathode layer 11 extends along the second direction to the hollow area and is disconnected on the side of the metal isolation pillar 15. The cathode layer 11 overlaps with the second source / drain metal layer 19 to achieve direct electrical connection between the cathode layer 11 and the second cathode signal line 232. Furthermore, the cathode layer 11 can also overlap with the main body 151 of the metal isolation pillar 15 to indirectly connect the second cathode signal line 232 of the second source / drain metal layer 19 through the metal isolation pillar 15.

[0108] Example 2

[0109] A method for manufacturing a display panel, such as Figure 9 As shown, it includes:

[0110] S210: A first metal material is deposited on the substrate 16, and the first metal material is patterned to obtain a first source / drain metal layer 17; a first planarization layer 18 is formed on the side of the first source / drain metal layer 17 away from the substrate 16 by deposition, and the first planarization layer 18 covers the first source / drain metal layer 17.

[0111] S220: A second metal material is deposited on the side of the first planarization layer 18 away from the substrate 16, and the second metal material is patterned to obtain a second source / drain metal layer 19; wherein, the second source / drain metal layer 19 has multiple parallel first cathode signal lines 231 arranged in the display area 101, and a ring metal trace 24 arranged in the frame area 102, and the multiple first cathode signal lines 231 and the ring metal trace 24 are connected in parallel and electrically connected to the output terminal of the driving circuit.

[0112] S230: A second planarization layer 20 is formed by deposition on the side of the second source / drain metal layer 19 away from the first source / drain metal layer 17. A third metal material is deposited on the side of the second planarization layer 20 away from the first planarization layer 18. The third metal material is patterned to obtain a third source / drain metal layer 21. The third source / drain metal layer 21 has multiple parallel second cathode signal lines 232 in the display area 101 and a ring-shaped metal trace 24 in the frame area 102. The multiple second cathode signal lines 232 are connected in parallel with the ring-shaped metal trace 24 and are electrically connected to the output terminal of the driving circuit. The multiple second cathode signal lines 232 and multiple first cathode signal lines 231 overlap at the intersection to form cathode signal lines.

[0113] S240: A third planarization layer 22 is formed by deposition on the side of the third source / drain metal layer 21 away from the second source / drain metal layer 19. The third planarization layer 22 is patterned to form a hollow area, wherein the hollow area is located at the horizontal and vertical overlap of the first cathode signal line 231 and the second cathode signal line 232.

[0114] S250: A fourth metal material is deposited on the side of the third planarization layer 22 away from the second planarization layer 20. The fourth metal material forms an anode layer 14 in the pixel opening area of ​​the pixel definition layer 13 and forms a metal isolation pillar 15 in the hollow area. The main body 151 of the metal isolation pillar 15 covers the third source / drain metal layer 21 and is electrically connected to the second cathode signal line 232 in the third source / drain metal layer 21. The limb 152 of the metal isolation pillar 15 covers the surface of the third planarization layer 22.

[0115] S260: The third planarization layer 22 is patterned by first coating photoresist, then patterning the photoresist through a mask 25, finally developing to remove the photoresist, and etching away the third planarization layer 22 between the two sides of the main body 151 and the bottom of the limb 152 to form an undercut structure.

[0116] S270: A pixel definition layer 13 is formed on the side of the anode layer 14 away from the third planarization layer 22. The pixel definition layer 13 includes a plurality of pixel opening regions spaced apart along the second direction. A light-emitting layer 12 is formed on the side of the pixel definition layer 13 away from the anode layer 14. The light-emitting layer 12 extends along the second direction to the hollow area and is disconnected on the side of the metal isolation pillar 15. The cathode layer 11 overlaps with the third source / drain metal layer 21 to achieve direct electrical connection between the cathode layer 11 and the second cathode signal line 232. Furthermore, the cathode layer 11 can also overlap with the main body 151 of the metal isolation pillar 15 to indirectly connect the second cathode signal line 232 of the third source / drain metal layer 21 through the metal isolation pillar 15.

[0117] Example 3

[0118] A method for manufacturing a display panel, such as Figure 10 As shown, it includes:

[0119] S210: A first metal material is deposited on the substrate 16, and the first metal material is patterned to obtain a first source / drain metal layer 17. The first source / drain metal layer 17 has multiple parallel first cathode signal lines 231 arranged in the display area 101, and a ring-shaped metal trace 24 arranged in the frame area 102. The multiple first cathode signal lines 231 and the ring-shaped metal trace 24 are connected in parallel and electrically connected to the output terminal of the driving circuit. A first planarization layer 18 is formed by deposition on the side of the first source / drain metal layer 17 away from the substrate 16, and the first planarization layer 18 covers the first source / drain metal layer 17.

[0120] S220: The first planarization layer 18 is patterned to form a cutout area. A second metal material is deposited on the side of the first planarization layer 18 away from the substrate 16. The second metal material is deposited in the cutout area to form a metal isolation pillar 15. The main body 151 of the metal isolation pillar 15 covers the first source / drain metal layer 17 and is electrically connected to the first cathode signal line 231 in the first source / drain metal layer 17. The limbs 152 of the metal isolation pillar 15 cover the surface of the first planarization layer 18. A second planarization layer 20 is formed on the side of the first planarization layer 18 away from the substrate 16 by deposition.

[0121] S230: The second planarization layer 20 and the first planarization layer 18 are patterned by first coating photoresist, then patterning the photoresist through a mask 25, and finally developing to remove the photoresist. The second planarization layer 20 and the first planarization layer 18 on the side and bottom of the metal isolation pillar 15 are etched away to form an undercut structure.

[0122] S240: An anode layer 14 is formed on the side of the second planarization layer 20 away from the first planarization layer 18. The anode layer 14 is disposed in the pixel opening area of ​​the pixel definition layer 13 and is disconnected on the side of the metal isolation pillar 15, and a disconnected common layer is formed above the metal isolation pillar 15.

[0123] S250: A pixel definition layer 13 is formed on the side of the anode layer 14 away from the second planarization layer 20. The pixel definition layer 13 includes a plurality of pixel opening regions spaced apart along the second direction. The pixel definition layer 13 is disconnected from the side of the metal isolation pillar 15. A light-emitting layer 12 is formed on the side of the pixel definition layer 13 away from the anode layer 14. The light-emitting layer 12 extends along the second direction to the hollow area and is disconnected from the side of the metal isolation pillar 15. A cathode layer 11 is formed on the side of the light-emitting layer 12 away from the pixel definition layer 13 by vapor deposition. The cathode layer 11 extends to the hollow area and is disconnected from the side of the metal isolation pillar 15. The cathode layer 11 overlaps with the first source / drain metal layer 17 in the hollow area to achieve direct electrical connection between the cathode layer 11 and the second cathode signal line 232. Furthermore, the cathode layer 11 can also overlap with the main body 151 of the metal isolation pillar 15 to indirectly connect with the first cathode signal line 231 of the first source / drain metal layer 17 through the metal isolation pillar 15.

[0124] Example 4

[0125] A method for manufacturing a display panel, such as Figure 11 As shown, it includes:

[0126] S210: A first metal material is deposited on the substrate 16, and the first metal material is patterned to obtain a first source / drain metal layer 17; a first planarization layer 18 is formed on the side of the first source / drain metal layer 17 away from the substrate 16 by deposition, and the first planarization layer 18 covers the first source / drain metal layer 17.

[0127] S220: A second metal material is deposited on the side of the first planarization layer 18 away from the substrate 16, and the second metal material is patterned to obtain a second source / drain metal layer 19; wherein, the second source / drain metal layer 19 has multiple parallel first cathode signal lines 231 arranged in the display area 101, and a ring metal trace 24 arranged in the frame area 102, and the multiple first cathode signal lines 231 and the ring metal trace 24 are connected in parallel and electrically connected to the output terminal of the driving circuit.

[0128] S230: A second planarization layer 20 is formed by deposition on the side of the second source / drain metal layer 19 away from the first source / drain metal layer 17. The second planarization layer 20 is patterned to form a hollow area. A third metal material is deposited on the side of the second planarization layer 20 away from the first planarization layer 18. The third metal material is deposited in the hollow area to form a metal isolation pillar 15. The main body 151 of the metal isolation pillar 15 covers the second source / drain metal layer 19 and is electrically connected to the first cathode signal line 231 in the second source / drain metal layer 19. The limb 152 of the metal isolation pillar 15 covers the surface of the second planarization layer 20. A third planarization layer 22 is formed by deposition on the side of the second planarization layer 20 away from the first planarization layer 18.

[0129] S240: The third planarization layer 22 and the second planarization layer 20 are patterned. First, photoresist is coated, then the photoresist is patterned through a mask 25, and finally the photoresist is removed by development. The third planarization layer 22 and the second planarization layer 20 on the side and bottom of the metal isolation pillar 15 are etched away to form an undercut structure.

[0130] S240: An anode layer 14 is formed on the side of the third planarization layer 22 away from the second planarization layer 20. The anode layer 14 is disposed in the pixel opening area of ​​the pixel definition layer 13 and is disconnected on the side of the metal isolation pillar 15, and a disconnected common layer is formed above the metal isolation pillar 15.

[0131] S250: A pixel definition layer 13 is formed on the side of the anode layer 14 away from the third planarization layer 22. The pixel definition layer 13 includes a plurality of pixel opening regions spaced apart along the second direction. The pixel definition layer 13 is disconnected from the side of the metal isolation pillar 15. A light-emitting layer 12 is formed on the side of the pixel definition layer 13 away from the anode layer 14. The light-emitting layer 12 extends along the second direction to the hollow area and is disconnected from the side of the metal isolation pillar 15. A cathode layer 11 is formed on the side of the light-emitting layer 12 away from the pixel definition layer 13 by vapor deposition. The cathode layer 11 extends to the hollow area and is disconnected from the side of the metal isolation pillar 15. The cathode layer 11 overlaps with the second source / drain metal layer 19 in the hollow area to achieve direct electrical connection between the cathode layer 11 and the first cathode signal line 231. Furthermore, the cathode layer 11 can also overlap with the main body 151 of the metal isolation pillar 15 to indirectly connect the first cathode signal line 231 of the second source / drain metal layer 19 through the metal isolation pillar 15.

[0132] In this embodiment, the patterning process includes photoresist coating, exposure, development, etching, and other processes. In embodiments 1 to 4, a laser method can also be used to remove the material of the light-emitting layer 12 so that the light-emitting layer 12 is disconnected on the side of the metal isolation pillar 15.

[0133] The lower rounded corner VSS current density of the display panel 10 provided in this application embodiment can be reduced by 40% to 60%, which greatly reduces the risk of burns under high brightness conditions, and the voltage drop (VSS IR Drop) is reduced by 30% to 50%, thereby reducing power consumption and improving brightness uniformity.

[0134] Thirdly, such as Figure 12 As shown, a display device 100 is provided, which includes the display panel 10 described in any embodiment of this application, or the display panel 10 obtained by the preparation method of the display panel described in any embodiment of this application.

[0135] Some embodiments of this application provide a display device 100, which includes a display panel 10 as described above. It may also include other components, such as a circuit for providing electrical signals to the display panel 10 to drive the display panel 10 to emit light. This circuit may be called a control circuit and may include a circuit board and / or an IC (Integrated Circuit) electrically connected to the display panel 10.

[0136] In some embodiments, the display device 100 can be a lighting device, in which case the display device 100 serves as a light source to achieve the lighting function. For example, the display device 100 can be a backlight module in a liquid crystal display device 100, a lamp for internal or external lighting, or various signal lights, etc.

[0137] In other embodiments, the display device 100 may be a display panel 100, in which case the display panel 10 is a display substrate 16 used to display images (i.e., screens). The display device 100 may include a monitor or a product containing a monitor. The monitor may be a flat panel display (FPD), a microdisplay, etc. Based on whether the user can see the back of the monitor, the monitor may be a transparent monitor or an opaque monitor. Based on whether the monitor can be bent or rolled, the monitor may be a flexible monitor or a regular monitor (which may be called a rigid monitor).

[0138] Examples of products that include displays include: computer monitors, televisions, billboards, laser printers with display capabilities, telephones, mobile phones, personal digital assistants (PDAs), laptops, digital cameras, portable camcorders, viewfinders, vehicles, large-area walls, theater screens, or stadium signs, etc.

[0139] The technical features and beneficial effects of the above-described display device 100 are the same as those of the display panel 10 provided in the above-described embodiments of this disclosure, and will not be repeated here.

[0140] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A display panel (10), characterized in that, The display panel (10) includes a substrate (16) and a driving circuit layer arranged sequentially along a first direction. The driving circuit layer provides cathode signal lines (23) in the display area (101) of the display panel (10). The side of the driving circuit layer away from the substrate (16) provides a cutout area in the display area (101). A cathode layer (11) is disposed on the side of the driving circuit layer away from the substrate (16). The cathode layer (11) extends to the cutout area and overlaps with the driving circuit layer so that the cathode layer (11) is electrically connected to the cathode signal line (23) of the driving circuit layer.

2. The display panel (10) according to claim 1, characterized in that, The display panel (10) also includes a metal isolation pillar (15), which is disposed in the hollow area. The cathode layer (11) extends to the hollow area and is disconnected from the side of the metal isolation pillar (15).

3. The display panel (10) according to claim 2, characterized in that, The metal isolation pillar (15) overlaps with the driving circuit layer, and the metal isolation pillar (15) is electrically connected to the cathode signal line (23) of the driving circuit layer; The cathode layer (11) extends to the hollow area and overlaps with the metal isolation pillar (15) so that the cathode layer (11) is electrically connected to the cathode signal line (23) of the drive circuit layer through the metal isolation pillar (15).

4. The display panel (10) according to claim 2 or 3, characterized in that, The metal isolation column (15) includes a main body (151) located at the bottom of the hollow area, and limbs (152) located at the two side edges of the main body (151). The limbs (152) extend away from the main body (151) so that the two sides of the main body (151) and the limbs (152) respectively form an undercut structure.

5. The display panel (10) according to claim 4, characterized in that, The main body (151) and the limb (152) are integrally formed.

6. The display panel (10) according to claim 2 or 3, characterized in that, The display panel (10) further includes a light-emitting layer (12), which is disposed between the driving circuit layer and the cathode layer (11). The light-emitting layer (12) extends to the hollow area and is disconnected from the side of the metal isolation pillar (15).

7. The display panel (10) according to claim 2 or 3, characterized in that, The display panel (10) further includes a pixel definition layer (13), which is disposed between the cathode layer (11) and the driving circuit layer. The pixel definition layer (13) includes a plurality of pixel opening areas that are spaced apart. The cutout area and the pixel opening area are spaced apart along a second direction, which is perpendicular to the first direction.

8. The display panel (10) according to claim 7, characterized in that, An anode layer (14) is disposed within the pixel opening area, and the anode layer (14) is disposed between the cathode layer (11) and the driving circuit layer.

9. The display panel (10) according to claim 8, characterized in that, The metal isolation pillar (15) is partially disposed on the same layer as the anode layer (14), and the remaining part is disposed on the same layer as the drive circuit layer; or, the metal isolation pillar (15) is disposed on the same layer as the drive circuit layer.

10. The display panel (10) according to claim 8 or 9, characterized in that, The driving circuit layer includes at least one source / drain metal layer disposed between the substrate (16) and the anode layer, and the cathode signal line (23) is disposed in the display area (101) by at least one source / drain metal layer.

11. The display panel (10) according to claim 10, characterized in that, The cathode signal line (23) includes multiple parallel first cathode signal lines (231), each of which is disposed within the source / drain metal layer.

12. The display panel (10) according to claim 11, characterized in that, The cathode signal line (23) also includes multiple parallel second cathode signal lines (232), the first cathode signal line (231) and the second cathode signal line (232) are intersected, and the first cathode signal line (231) and the second cathode signal line (232) are respectively disposed on different source and drain metal layers.

13. The display panel (10) according to claim 12, characterized in that, The hollow area is located at the junction of the first cathode signal line and the second cathode signal line.

14. A method for manufacturing a display panel, characterized in that, include: A driving circuit layer formed on the substrate (16); A cathode signal line (23) is provided in the display area (101) of the display panel (10) by the driving circuit layer, and a cutout area is formed in the display area (101) on the side of the driving circuit layer away from the substrate (16). A cathode layer (11) is formed on the side of the driving circuit layer away from the substrate (16). The cathode layer (11) extends to the cutout area and overlaps with the driving circuit layer so that the cathode layer (11) is electrically connected to the cathode signal line (23) of the driving circuit layer.

15. A display device (100), characterized in that, The display device (100) includes the display panel (10) according to any one of claims 1-13, or the display panel (10) obtained by the method of preparing the display panel according to claim 14.

Images