Semiconductor structure and manufacturing method thereof

Abstract

A method of fabricating a semiconductor structure is provided. The method comprises the following steps: providing a wafer substrate; a lower conductive layer is formed on the wafer substrate. A barrier layer is formed on the lower conductive layer. An amorphous layer is formed on the barrier layer, wherein an edge portion of the amorphous layer is thicker than a center portion of the amorphous layer. A sacrificial layer is formed on the amorphous layer, wherein the sacrificial layer has a concave shape toward the wafer substrate. An ignition layer is formed on the amorphous layer, while the sacrificial layer and an edge portion of a portion of the amorphous layer are removed. An upper conductive layer is formed on the firing layer. By this method, the sacrificial layer protects the amorphous layer from over etching, thereby avoiding an increase in edge resistance. Therefore, the performance of the semiconductor structure can be improved.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor structure and a method of manufacturing the same. BACKGROUND

[0002] In recent decades, as electronic products have been advancing, the demand for storage capacity has been increasing. To increase the storage capacity of a storage device, such as a DRAM device, more storage cells need to be integrated therein. As the integration level increases, it becomes particularly important to reduce the resistance of the conductive structure.

[0003] In a high bias voltage tungsten process for forming a conductive layer, a portion of an underlying layer can be removed, causing an increase in edge resistance, which results in a deterioration of parasitic capacitance. SUMMARY

[0004] According to one aspect of the present invention, a method of manufacturing a semiconductor structure is provided. The method includes the following steps. A wafer substrate is provided. A lower conductive layer is formed on the wafer substrate. A barrier layer is formed on the lower conductive layer. An amorphous layer is formed on the barrier layer, wherein an edge portion of the amorphous layer is thicker than a center portion of the amorphous layer. A sacrificial layer is formed on the amorphous layer, wherein the sacrificial layer has a concave shape toward the wafer substrate. A fire layer is formed on the amorphous layer while removing the sacrificial layer and an edge portion of the amorphous layer, wherein the center portion of the amorphous layer is thicker than the edge portion. An upper conductive layer is formed on the fire layer, wherein an edge portion of the upper conductive layer is thicker than a center portion of the upper conductive layer.

[0005] According to some embodiments of the present invention, the method further includes forming an ohmic layer on the lower conductive layer before forming the barrier layer, wherein the ohmic layer comprises titanium and the barrier layer comprises tungsten nitride.

[0006] According to some embodiments of the present invention, the method further includes forming a hard mask layer on the upper conductive layer.

[0007] According to some embodiments of the present invention, the sacrificial layer, the fire layer and the upper conductive layer are formed by a first sputtering process, a second sputtering process and a third sputtering process, respectively.

[0008] According to some embodiments of the present invention, the first sputtering process is performed using a first power and a first bias.

[0009] According to some embodiments of the present invention, the second sputtering process is performed using a second power and a second bias, wherein the second power is less than the first power and the second bias is higher than the first bias.

[0010] According to some embodiments of the present invention, the third sputtering process is performed using a third power and a third bias, wherein the third power is greater than the second power and the third bias is lower than the second bias.

[0011] According to some embodiments of the application, the sacrificial layer, the ignition layer and the upper conductive layer comprise the same material.

[0012] According to some embodiments of the application, the sacrificial layer, the ignition layer and the upper conductive layer comprise tungsten.

[0013] According to some embodiments of the application, the lower conductive layer comprises polysilicon.

[0014] According to some embodiments of the application, the average thickness of the sacrificial layer is in the range of 0.5 nm to 1.5 nm.

[0015] According to some embodiments of the application, the average thickness of the amorphous layer after forming the ignition layer is in the range of 3.2 nm to 4 nm.

[0016] According to an aspect of the application, there is provided a semiconductor structure. The semiconductor structure comprises a wafer substrate, a lower conductive layer, an ohmic layer, a barrier layer, an amorphous layer, an ignition layer, an upper conductive layer and a hard mask layer. The lower conductive layer is on the wafer substrate. The ohmic layer is on the lower conductive layer. The barrier layer is on the ohmic layer. The amorphous layer is on the barrier layer, wherein a top surface of the amorphous layer is convex and extends away from the wafer substrate. The ignition layer is on the amorphous layer, wherein a top surface of the ignition layer is convex and extends away from the wafer substrate. The upper conductive layer is on the ignition layer, wherein a top surface of the upper conductive layer is concave and extends towards the wafer substrate. The hard mask layer is on the upper conductive layer.

[0017] According to some embodiments of the application, the ohmic layer comprises titanium and the barrier layer comprises tungsten nitride.

[0018] According to some embodiments of the application, the barrier layer, the amorphous layer, the ignition layer and the upper conductive layer comprise the same material.

[0019] It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the subject application as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0020] The subject application can be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, in which: Figure 1 is a cross-sectional schematic view of a semiconductor structure according to some embodiments.

[0021] Figure 2 is a cross-sectional schematic view of a semiconductor structure after forming an ohmic layer and a barrier layer according to some embodiments.

[0022] Figure 3is a cross-sectional schematic view of a semiconductor structure after forming an amorphous layer on a barrier layer according to some embodiments.

[0023] Figure 4 is a cross-sectional schematic view of a semiconductor structure after forming a sacrificial layer on the amorphous layer according to some embodiments.

[0024] Figure 5 is a cross-sectional schematic view of a semiconductor structure after forming an ignition layer according to some embodiments.

[0025] Figure 6 is a cross-sectional schematic view of a semiconductor structure after forming an upper conductive layer on the amorphous layer according to some embodiments.

[0026] Figure 7 is a cross-sectional schematic view of a semiconductor structure after forming a hard mask layer according to some embodiments.

[0027] Figure 8 is a cross-sectional schematic view of a semiconductor structure after forming a trench according to some embodiments. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same or like reference numbers will be used in the drawings and the description to refer to the same or like parts. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the application. It will be apparent, however, to one skilled in the art that the application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the application.

[0029] It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific embodiments or examples of components and configurations are described herein in detail to provide a thorough understanding of the application. It will be apparent, however, that these are simply examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features, such that the first and second features do not form direct contact. In addition, the present application can be repeated in various examples with reference numerals and / or letters having different but similar meanings. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0030] In addition, for the purpose of convenience and brevity, the application can be described in the description with spatially relative terms as "below", "under", "lower", "above", "upper", and the like, which can be used to describe the relationship between one element or feature and one or more other elements or features as illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation, and the device can be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0031] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there can be intermediate components or layers.

[0032] Figures 1 to 8 This is a schematic diagram illustrating various intermediate stages in the formation process of a semiconductor structure 100 according to some embodiments. The semiconductor structure 100 can be applied to or as part of an integrated circuit (IC), such as logic circuits, resistors, capacitors, inductors, memory (e.g., dynamic random access memory (DRAM)), etc. It should be understood that, for the sake of simplicity, Figures 1 to 8 Some elements of the semiconductor structure 100 are not shown in the diagram, and additional elements may be included in other embodiments of the semiconductor structure 100.

[0033] refer to Figure 1 In some embodiments, the wafer substrate 110 may be a semiconductor substrate, such as a host semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. In some embodiments, the wafer substrate 110 may be doped (e.g., containing p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the wafer substrate 110 may include silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors, or combinations thereof. The wafer substrate 110 may also be formed of other materials, such as sapphire, indium tin oxide, etc.

[0034] like Figure 1 As shown, a lower conductive layer 120 is formed on a wafer substrate 110. In some embodiments, the lower conductive layer 120 includes a suitable conductive material; for example, the lower conductive layer 120 may include polycrystalline silicon. In some embodiments, the lower conductive layer 120 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.

[0035] Referring to Figure 2 An ohmic layer 130 is formed on the lower conductive layer 120, and a barrier layer 140 is formed on the ohmic layer 130. In some embodiments, the ohmic layer 130 includes a suitable low contact resistance material, for example, the ohmic layer 130 can include titanium. In some embodiments, the thickness T130 of the ohmic layer 130 can be in the range of 2 nanometers (nm) ± 10%. In some embodiments, the ohmic layer 130 can be formed using a suitable deposition process, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0036] In some embodiments, the barrier layer 140 includes a suitable material capable of preventing diffusion, for example, the barrier layer 140 can include tungsten nitride (WN). In some embodiments, the thickness T140 of the barrier layer 140 can be in the range of 4 nm ± 10%. In some embodiments, the barrier layer 140 can be formed using a suitable deposition process, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0037] Referring to Figure 3 An amorphous layer 150 is formed on the barrier layer 140. Specifically, after the amorphous layer 150 is formed, the edge portion 150E of the amorphous layer 150 is thicker than the center portion 150C of the amorphous layer 150. In other words, the amorphous layer 150 has a shape that is slightly concave toward the wafer substrate 110. In some embodiments, the amorphous layer 150 includes a suitable low contact resistance material, for example, the amorphous layer 150 can include tungsten silicide (WSi). In some embodiments, the amorphous layer 150 can be formed using a suitable deposition process, for example, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0038] Referring to Figure 4 A sacrificial layer 160 is formed on the amorphous layer 150. Specifically, after the sacrificial layer 160 is formed, the edge portion 160E of the sacrificial layer 160 is thicker than the center portion 160C of the sacrificial layer 160. In other words, the sacrificial layer 160 has a shape that is slightly concave toward the wafer substrate 110. In some embodiments, the average thickness T160 of the sacrificial layer 160 can be in the range of 0.5 nm to 1.5 nm. The average thickness T160 can be the average of the thickness T160E at the edge portion 160E and the thickness T160C at the center portion 160C. In some embodiments, the sacrificial layer 160 can include tungsten. In some embodiments, the sacrificial layer 160 can be formed using a suitable deposition process, for example, physical vapor deposition (PVD). For example, the sacrificial layer 160 is formed using a sputtering process with a power of 500 W and a bias voltage of -300 V, where the bias voltage is applied on the wafer substrate side.

[0039] Referring to Figure 5 The ignition layer 170 is formed while the sacrificial layer 160 is removed. The ignition layer 170 has a slightly convex shape and extends away from the wafer substrate 110. In some embodiments, the ignition layer 170 can include tungsten. In some embodiments, the ignition layer 170 can be formed using a suitable deposition process, such as physical vapor deposition (PVD). For example, the ignition layer 170 is formed using a sputtering process with a power of 300 W and a bias of -1050 V, where the bias is applied to the wafer substrate side. When forming the ignition layer 170, a high bias is applied, thereby removing a portion of the sacrificial layer 160 and the amorphous layer 150. The sacrificial layer 160 protects the amorphous layer 150 from over-etching, thereby enhancing the performance of the semiconductor structure 100.

[0040] Specifically, the edge portion 150E of the amorphous layer 150 is removed when forming the ignition layer 170. After forming the ignition layer 170, the center portion 150C of the amorphous layer 150 is thicker than the edge portion 150E. In other words, the amorphous layer 150 has a slightly convex shape and extends away from the wafer substrate 110. In some embodiments, the average thickness T150 of the amorphous layer 150 can be in the range of 3.2 nm to 4 nm. The average thickness T150 of the amorphous layer 150 can be the average of the thickness T150E at the edge portion 150E and the thickness T150C at the center portion 150C.

[0041] Referring to Figure 6 The upper conductive layer 180 is formed on the ignition layer 170. The ignition layer 170 serves as a seed layer, which facilitates the deposition of the upper conductive layer 180. Specifically, after forming the upper conductive layer 180, the edge portion 180E of the upper conductive layer 180 is thicker than the center portion 180C of the upper conductive layer 180. In other words, the top surface 180T of the upper conductive layer 180 is slightly concave towards the wafer substrate 110. In some embodiments, the upper conductive layer 180 can include tungsten. In some embodiments, the average thickness T180 of the upper conductive layer 180 can be in the range of 24 nm ± 10%. The average thickness T180 of the upper conductive layer 180 can be the average of the thickness T180E at the edge portion 180E and the thickness T180C at the center portion 180C.

[0042] In some embodiments, the upper conductive layer 180 can be formed using a suitable deposition process, such as physical vapor deposition (PVD). For example, the upper conductive layer 180 is formed using a sputtering process with a power of 900 W and a bias of -360 V, where the bias is applied to the wafer substrate side. By applying a higher power and a lower bias, the upper conductive layer 180 can be stably formed while preventing damage to the underlying layers.

[0043] In summary, the sacrificial layer 160, the ignition layer 170, and the upper conductive layer 180 can be formed by a first sputtering process, a second sputtering process, and a third sputtering process, respectively. In some embodiments, the first sputtering process, the second sputtering process, and the third sputtering process can be performed in the same chamber. The first sputtering process is performed with a first power and a first bias. The second sputtering process is performed with a second power and a second bias, where the second power is less than the first power and the second bias is higher than the first bias. The third sputtering process is performed with a third power and a third bias, where the third power is greater than the second power and the third bias is lower than the second bias.

[0044] Referring to Figure 7 A hard mask layer 190 is formed on the upper conductive layer 180. In some embodiments, the hard mask layer 190 can be formed by an appropriate deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. In some embodiments, the hard mask layer 190 comprises an appropriate dielectric material, for example, the hard mask layer 190 can comprise silicon nitride (SiN).

[0045] As shown, the amorphous layer 150, the ignition layer 170, and the upper conductive layer 180 in the active region R1 have good uniformity. In subsequent processes, the upper conductive layer 180 and the lower conductive layer 120 in the active region R1 can serve as conductive layers of a gate structure, a gate contact, and / or a bit line structure. The gate structure, the gate contact, and / or the bit line structure can be formed in the trench 200.

[0046] Referring to Figure 7 and Figure 8 The semiconductor structure 100 comprises a wafer substrate 110, a lower conductive layer 120, an ohmic layer 130, a barrier layer 140, an amorphous layer 150, an ignition layer 170, an upper conductive layer 180, and a hard mask layer 190. The lower conductive layer 120 is on the wafer substrate 110. The ohmic layer 130 is on the lower conductive layer 120. The barrier layer 140 is on the ohmic layer 130. The amorphous layer 150 is on the barrier layer 140, where a top surface 150T of the amorphous layer 150 has a convex shape extending away from the wafer substrate 110. The ignition layer 170 is on the amorphous layer 150, where a top surface 150T has a convex shape extending away from the wafer substrate 110. A top surface 170T of the ignition layer 170 has a convex shape extending away from the wafer substrate 110. The upper conductive layer 180 is on the ignition layer 170, where a top surface 180T of the upper conductive layer 180 has a concave shape facing the wafer substrate 110. The hard mask layer 190 is on the upper conductive layer 180. The semiconductor structure 100 has an active region R1 and an edge region R2 surrounding the active region R1. The trench 200 is in the active region R1.

[0047] The present application provides a method for manufacturing a semiconductor structure. By the method provided by the present application, the amorphous layer is protected from over-etching by the sacrificial layer, thereby avoiding the increase of edge resistance. Therefore, the performance of the semiconductor structure can be improved.

[0048] While the application has been described in considerable detail with reference to certain embodiments thereof, other embodiments will be apparent to those skilled in the art. The spirit and scope of the application should, therefore, be limited only by the appended claims.

[0049] It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the present application without departing from the scope or spirit of the application. In light of the foregoing, it is the intent that the present application be covered by all of the following claims.

[0050] SYMBOL DESCRIPTION 100: semiconductor structure 110: wafer substrate 120: lower conductive layer 130: ohmic layer 140: barrier layer 150: amorphous layer 150C: center portion 150E: edge portion 150T: top surface 160: sacrificial layer 160C: center portion 160E: edge portion 170: fire layer 170T: top surface 180: upper conductive layer 180C: center portion 180E: edge portion 180T: top surface 190: hard mask layer 200: trench R1: active region R2: edge region T130: thickness T140: thickness T150: average thickness T150C: thickness T150E: thickness T160: average thickness T160C: thickness T160E: thickness T180: average thickness T180C: thickness T180E: thickness.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide wafer substrates; A lower conductive layer is formed on the wafer substrate; A barrier layer is formed on the lower conductive layer; An amorphous layer is formed on the barrier layer, wherein the edge portion of the amorphous layer is thicker than the center portion of the amorphous layer. A sacrificial layer is formed on the amorphous layer, wherein the sacrificial layer has a concave shape facing the wafer substrate; An ignition layer is formed on the amorphous layer, while the sacrificial layer and a portion of the edge portion of the amorphous layer are removed, wherein the central portion of the amorphous layer is thicker than the edge portion. as well as An upper conductive layer is formed on the ignition layer, wherein the edge portion of the upper conductive layer is thicker than the center portion of the upper conductive layer.

2. The method according to claim 1, characterized in that, Further includes: Prior to forming the barrier layer, an ohmic layer is formed on the lower conductive layer, wherein the ohmic layer comprises titanium and the barrier layer comprises tungsten nitride.

3. The method according to claim 1, characterized in that, Further includes: A hard masking layer is formed on the conductive layer.

4. The method according to claim 1, characterized in that, The sacrificial layer, the ignition layer, and the upper conductive layer are formed by the first sputtering process, the second sputtering process, and the third sputtering process, respectively.

5. The method according to claim 4, characterized in that, The first sputtering process is performed using a first power and a first bias voltage.

6. The method according to claim 5, characterized in that, The second sputtering process is performed using a second power and a second bias voltage, wherein the second power is less than the first power and the second bias voltage is higher than the first bias voltage.

7. The method according to claim 6, characterized in that, The third sputtering process is performed using a third power and a third bias voltage, wherein the third power is greater than the second power and the third bias voltage is lower than the second bias voltage.

8. The method according to claim 1, characterized in that, The sacrificial layer, the ignition layer, and the upper conductive layer are made of the same material.

9. The method according to claim 8, characterized in that, The sacrificial layer, the ignition layer, and the upper conductive layer comprise tungsten.

10. The method according to claim 1, characterized in that, The underlying conductive layer comprises polycrystalline silicon.

11. The method according to claim 1, characterized in that, The average thickness of the sacrificial layer ranges from 0.5 nanometers to 1.5 nanometers.

12. The method according to claim 1, characterized in that, After the ignition layer is formed, the average thickness of the amorphous layer is in the range of 3.2 nanometers to 4 nanometers.

13. A semiconductor structure, characterized in that, include Wafer substrate; The lower conductive layer is located on the wafer substrate; An ohmic layer is located on top of the underlying conductive layer; A barrier layer is located on the ohmic layer; An amorphous layer is located on the barrier layer, wherein the top surface of the amorphous layer is convex and extends away from the wafer substrate; An ignition layer is located on the amorphous layer, wherein the top surface of the ignition layer is convex and extends away from the wafer substrate; An upper conductive layer is located on the ignition layer, wherein the top surface of the upper conductive layer is recessed and extends toward the wafer substrate; as well as A hard masking layer is located on the upper conductive layer.

14. The semiconductor structure according to claim 13, characterized in that, The ohmic layer comprises titanium, and the barrier layer comprises tungsten nitride.

15. The semiconductor structure according to claim 13, characterized in that, The barrier layer, the amorphous layer, the ignition layer, and the upper conductive layer all consist of the same material.

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