Heat dissipation structure for multi-power device accumulation environment

Abstract

The invention provides a heat dissipation structure for a multi-power device accumulation environment, and relates to the technical field of heat dissipation structures, the heat dissipation structure comprises a semiconductor substrate, a heat conduction elastic composite mechanism, a heat conduction elastic composite mechanism and a heat dissipation elastic composite mechanism, the semiconductor substrate is provided with a high-power-consumption semiconductor and a low-power-consumption semiconductor, and the heat conduction elastic composite mechanism is arranged at the lower ends of the high-power-consumption semiconductor and the low-power-consumption semiconductor. The heat-conducting elastic composite mechanism is used for transmitting heat generated by the heat-conducting elastic composite mechanism and the graphene and damping the semiconductor substrate, so that the impact of external vibration and thermal expansion difference on the semiconductor substrate and device welding spots is effectively relieved, and on one hand, a synergistic system is formed by the hydrogenated butadiene-acrylonitrile rubber of the heat-conducting elastic composite mechanism, the graphene and the nickel-plated copper fibers; hydrogenated nitrile rubber can specifically absorb thermal expansion stress generated by heating difference of a high-power-consumption semiconductor and a low-power-consumption semiconductor by means of excellent elastic deformation capacity, and meanwhile, vibration acceleration transmitted by an external environment is effectively attenuated, so that cracking damage of a semiconductor substrate and a device welding spot due to long-term stress concentration is fundamentally avoided.

Description

Technical Field

[0001] This invention belongs to the field of heat dissipation structure technology, and more specifically, relates to a heat dissipation structure for environments with high power device accumulation. Background Technology

[0002] Multi-power devices are a type of electronic device made with semiconductor materials as the core basis. The controllability of semiconductor conductivity is the fundamental premise for multi-power devices to realize core functions such as power conversion, signal amplification, and energy transmission. Multi-power devices are specific products that cover different power levels, such as high power and low power, by performing specific structural design and performance regulation of semiconductor materials according to the power requirements of different application scenarios.

[0003] Current heat dissipation structures used in environments with high power device accumulation have been found to have at least the following technical problems: First, it is difficult to balance heat transfer and mechanical protection. In existing heat dissipation solutions, heat-conducting components (such as metal thermal pads and ordinary graphite sheets) mostly focus on heat conduction efficiency, but ignore the differences in thermal expansion between multiple devices and the problem of external vibration and impact: high-power devices and low-power devices heat up at different rates when they are working, which can easily lead to thermal stress deformation between the substrate and the heat dissipation structure. Vibrations during equipment operation (such as vehicle electrical control and industrial equipment) will further aggravate this stress, causing the solder joints between semiconductor devices and the substrate to crack due to long-term stress concentration.

[0004] Secondly, the heat dissipation is not targeted enough and the assembly accuracy is poor. Most current heat dissipation structures adopt a uniform design, either using a single cold plate to dissipate heat for the entire substrate without zoning optimization for the thermal load differences between high-power and low-power devices. This causes heat from high-power areas to diffuse to low-power areas through the cold plate, causing the temperature of low-power devices to rise abnormally. Alternatively, the heat insulation layer is poorly designed and cannot accurately match the device layout. Furthermore, the assembly of the semiconductor substrate and the heat dissipation structure relies on traditional bolt fixing or manual alignment, which can easily create tiny gaps at the contact interface due to assembly deviations. These gaps will cause a sharp increase in contact thermal resistance, significantly reducing heat dissipation efficiency. Ultimately, this results in a dual problem of heat accumulation in high-power areas and high-temperature interference in low-power areas.

[0005] Third, thermal coupling interference cannot be effectively blocked. Because high-power and low-power semiconductors are arranged close together on the same substrate, the existing structure lacks the design to build a precise thermal isolation barrier in the heat dissipation path: the high temperature generated by the high-power device is not only directly conducted to the low-power area through the substrate, but also forms lateral thermal crosstalk through heat dissipation components (such as cold plates and heat dissipation fins), resulting in thermal coupling effect between the two. The high-power device cannot conduct heat in a directional manner, and the temperature continues to rise, causing performance degradation or even thermal runaway; the low-power device suffers from signal drift and response delay due to the high ambient temperature. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a heat dissipation structure for environments with a high concentration of multi-power devices. This structure solves the problems that traditional heat dissipation structures struggle to balance efficient heat transfer with shock absorption and electrical safety, lack differentiated heat dissipation for high- and low-power devices, and are prone to increased thermal resistance due to assembly deviations, and are unable to effectively block thermal coupling interference between high- and low-power semiconductors in such environments.

[0007] A heat dissipation structure for environments with high power device accumulation includes: a semiconductor substrate on which high-power semiconductors and low-power semiconductors are disposed; a thermally conductive elastic composite mechanism disposed at the lower end of the high-power semiconductors and low-power semiconductors for transferring the heat generated by both and damping the semiconductor substrate, effectively mitigating the impact of external vibrations and thermal expansion differences on the semiconductor substrate and device solder joints; a heat dissipation mechanism disposed at the lower end of the semiconductor substrate for efficient heat dissipation of the semiconductor substrate, quickly dissipating accumulated heat to avoid local heat accumulation; and a heat separation mechanism built into the heat dissipation mechanism for blocking heat transfer between the high-power semiconductors and low-power semiconductors, thereby avoiding thermal coupling, maintaining reasonable operating temperatures for both high-power and low-power semiconductors, preventing performance degradation or shortened lifespan due to mutual heat interference, and ultimately improving system reliability and energy efficiency.

[0008] Preferably, the thermally conductive elastic composite structure includes hydrogenated nitrile rubber, which is disposed at the lower end of the semiconductor substrate and contains graphene. The graphene also contains nickel-plated copper fibers. The graphene completely covers the back side of the semiconductor substrate and is located at the solder joints of the high-power semiconductor and the low-power semiconductor. The hydrogenated nitrile rubber, with its excellent elastic deformation capability, can absorb the thermal expansion differences between different devices and external vibration impacts, attenuating vibration acceleration and effectively preventing solder joint cracking due to stress concentration. Simultaneously, it possesses high insulation properties, eliminating the risk of electrical short circuits caused by contact between different devices. The graphene and nickel-plated copper fibers synergistically form a highly thermally conductive path, significantly improving heat conduction efficiency and reducing contact thermal resistance, achieving rapid heat dissipation from the high-power semiconductor and temperature stability of the low-power semiconductor. Furthermore, the full back-side coverage of the graphene and the precise alignment design of the solder joints further adapt the thermal distribution characteristics of the devices, ensuring targeted and uniform heat transfer.

[0009] Preferably, the heat dissipation mechanism includes a copper cold plate, on which a porous heat insulation layer is fixedly mounted. The porous heat insulation layer has high-power heat dissipation areas and low-power heat dissipation areas. Two positioning pins are fixedly mounted on the porous heat insulation layer, and two positioning grooves that mate with the positioning pins are formed on the semiconductor substrate. The copper cold plate, with its high thermal conductivity, can quickly dissipate heat transferred to its surface, achieving efficient heat diffusion. The porous heat insulation layer, through its partitioned design, precisely adapts to the thermal characteristics differences of high- and low-power devices, laying the foundation for subsequent differentiated heat dissipation and thermal isolation. The matching of the two positioning pins and the positioning grooves ensures precise assembly of the semiconductor substrate and the porous heat insulation layer, avoiding gaps at the heat dissipation interface that could lead to increased thermal resistance. It also prevents electrical contact problems caused by assembly deviations. Through partitioned thermal management and precise assembly design, the structural reliability requirements of multi-power semiconductor accumulation environments are fully met.

[0010] Preferably, the heat separation mechanism includes a laser-fused dense layer and a high-porosity thermally conductive copper layer. The laser-fused dense layer and the high-porosity thermally conductive copper layer can be adapted and installed according to the positional changes of the high-power semiconductor and the low-power semiconductor. The laser-fused dense layer is disposed in the high-power heat dissipation area of ​​the porous heat insulation layer, and the high-porosity thermally conductive copper layer is disposed in the low-power heat dissipation area of ​​the porous heat insulation layer. The low-porosity solid-phase framework of the laser-fused dense layer can construct a continuous vertical heat conduction path, ensuring the directional and rapid conduction of high-power heat and meeting the high-density heat load removal requirements of high-power devices. The porosity of the high-porosity thermally conductive copper is ≥70%, and its special pore structure can effectively block lateral thermal crosstalk while ensuring efficient heat removal from low-power devices. The adjustable position characteristics of both can achieve precise alignment with the hot spots of the device, further improving the targeting and effectiveness of the heat conduction path and avoiding the increase in local thermal resistance caused by positional deviation. Ultimately, the temperature difference between the high-power and low-power areas is controlled within 8°C, significantly improving the thermal coupling isolation efficiency. Moreover, the differentiated structural design takes into account both thermal management performance and structural lightweighting, while improving compatibility with different device layout schemes, and fully adapting to the high-efficiency heat dissipation and thermal isolation requirements of multi-power semiconductor accumulation environments.

[0011] Compared with the prior art, the present invention has the following beneficial effects: In this invention, a synergistic system formed by hydrogenated nitrile butadiene rubber (NBR) with a thermally conductive elastic composite structure, graphene, and nickel-plated copper fibers has several advantages. First, the NBR, with its excellent elastic deformation capability, can specifically absorb the thermal expansion stress caused by the difference in heating between high-power and low-power semiconductors, while effectively attenuating the vibration acceleration transmitted from the external environment. This fundamentally prevents cracking and damage to the semiconductor substrate and device solder joints due to long-term stress concentration. Second, the graphene not only completely covers the back of the semiconductor substrate to form a comprehensive thermally conductive substrate, but also precisely aligns with the solder joint positions of high- and low-power semiconductors. Together with the internally embedded nickel-plated copper fibers, it constructs a highly thermally conductive path, significantly reducing contact thermal resistance during heat transfer and achieving rapid heat dissipation from high-power semiconductors and temperature stability for low-power semiconductors. Furthermore, the inherent high insulation properties of the NBR can eliminate the risk of electrical short circuits caused by contact between different power devices, ultimately improving the thermal reliability, mechanical stability, and electrical safety of the multi-power semiconductor stacking system simultaneously.

[0012] In this invention, through the combined design of a copper cold plate, a porous heat insulation layer, and positioning pins and slots in the heat dissipation mechanism, firstly, the copper cold plate, relying on its excellent high thermal conductivity, can quickly receive and diffuse the accumulated heat transferred from above, forming an efficient heat flow diffusion channel and preventing heat accumulation in local areas; secondly, the porous heat insulation layer does not adopt a uniform structure, but is specially designed with high-power heat dissipation areas and low-power heat dissipation areas, precisely adapting to the thermal characteristic differences of the two devices, providing a structural basis for subsequent differentiated heat dissipation and heat isolation; at the same time, the two positioning pins fixed on the porous heat insulation layer form a precise fit with the matching positioning slots opened on the semiconductor substrate, which can ensure the positional accuracy of the semiconductor substrate and the porous heat insulation layer during assembly, preventing gaps in the heat dissipation interface due to assembly deviation (thus avoiding increased contact thermal resistance and affecting heat dissipation efficiency), and also avoiding the problem of poor electrical contact between devices caused by positional misalignment, comprehensively meeting the dual requirements of efficient heat dissipation and structural reliability in the environment of multi-power device accumulation.

[0013] In this invention, the differential layout of the laser-fused dense layer and the highly porous thermally conductive copper of the heat separation mechanism, combined with the adaptability of both that can be adjusted according to the device position, achieves precise blocking of heat transfer between high- and low-power semiconductors. The laser-fused dense layer is specifically positioned within the high-power heat dissipation zone of the porous thermal insulation layer. Its low-porosity solid-phase framework constructs a continuous vertical heat conduction path, ensuring that the high-density heat load generated by the high-power semiconductor can be quickly and directionally conducted to the copper cold plate, meeting the high-intensity heat dissipation requirements of high-power devices. Meanwhile, high-porosity thermally conductive copper (porosity ≥70%) is installed in the low-power heat dissipation zone. Through its special pore structure, it cuts off the lateral heat transfer path, ensuring effective heat dissipation from the low-power semiconductor while preventing heat from the high-power area from crossing over to the low-power area. Furthermore, the installation positions of both can be flexibly adjusted according to the actual layout of the high-power and low-power semiconductors on the substrate, achieving precise alignment with the hot spots of the device. Ultimately, the temperature difference between the high-power and low-power areas is strictly controlled within 8°C, significantly reducing the impact of thermal coupling on device performance and effectively avoiding problems such as decreased device processing speed, response delay, or shortened lifespan caused by high-temperature mutual interference.

[0014] In this invention, the design of completely covering the back of a semiconductor substrate with graphene and precisely aligning it with the solder joints of high- and low-power semiconductors fully adapts to the thermal distribution characteristics of multi-power devices on the substrate. On one hand, the full back-side coverage design of graphene transforms the back of the semiconductor substrate into a heat conduction surface without dead angles, avoiding heat transfer blind spots caused by partial uncovering, and ensuring that heat from any area on the substrate can be conducted to the heat dissipation structure below in a timely manner. On the other hand, the precise alignment design of graphene with the solder joints allows it to directly act on the core source of heat generation, reducing the path length of heat transfer from the solder joints to the graphene layer and reducing heat loss during the process. This dual design of full coverage and precise alignment not only ensures the overall uniformity of heat transfer but also enhances targeted heat conduction in high-power solder joint areas, further improving the timeliness of heat dissipation from high-power semiconductors, while preventing abnormal temperature fluctuations in low-power semiconductors due to high-temperature conduction from the surrounding environment, thus maintaining the stability of the temperature field of the entire system.

[0015] In this invention, a multi-dimensional performance balance and optimization are achieved through the modular design of the overall structure and the functional synergy of the thermally conductive elastic composite mechanism, the heat dissipation mechanism, and the heat isolation mechanism. From a structural design perspective, each mechanism can be independently produced, assembled, and maintained, which not only reduces the processing difficulty and cost during production but also facilitates component replacement during subsequent equipment maintenance. From a functional synergy perspective, the heat transfer and vibration damping functions of the thermally conductive elastic composite mechanism provide a stable heat input foundation and structural protection for the heat dissipation mechanism. The zoned heat dissipation design of the heat dissipation mechanism creates conditions for the efficient operation of the heat isolation mechanism, and the thermal isolation function of the heat isolation mechanism, in turn, ensures the differentiated heat dissipation effect of the heat dissipation mechanism. The three form a complete thermal management closed loop of heat transfer, efficient heat dissipation, and thermal isolation protection. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall structure of the present invention; Figure 2 This is a schematic diagram of the porous heat insulation layer of the present invention; Figure 3 This is a schematic diagram of the semiconductor substrate structure of the present invention; Figure 4 This is a schematic diagram of the high-power semiconductor structure of the present invention; Figure 5 This is a schematic diagram of the graphene structure of the present invention; Figure 6 This is a schematic diagram of the structure of the copper cold plate of the present invention; Figure 7 This is a schematic diagram of the high-porosity thermally conductive copper structure of the present invention; Figure 8 This is a schematic diagram of the high-power heat dissipation area of ​​the present invention; Figure 9 This is the present invention. Figure 2 An enlarged schematic diagram of the structure at point A.

[0017] In the figure, the correspondence between the component names and the attached drawing numbers is as follows: 1. Porous heat insulation layer; 2. Positioning pin; 3. Semiconductor substrate; 4. Positioning groove; 5. High power consumption heat dissipation area; 6. Low power consumption heat dissipation area; 7. Copper cold plate; 8. Laser-welded dense layer; 9. High-porosity thermally conductive copper; 10. Locking screw; 11. High power consumption semiconductor; 12. Graphene; 13. Nickel-plated copper fiber; 14. Hydrogenated nitrile rubber; 15. Low power consumption semiconductor. Detailed Implementation

[0018] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention. Please see Figure 1 - Figure 9This invention provides a heat dissipation structure for environments with high power device accumulation, including a semiconductor substrate 3, a high-power semiconductor 11 and a low-power semiconductor 15 mounted on the semiconductor substrate 3, a thermally conductive elastic composite mechanism disposed at the lower end of the high-power semiconductor 11 and the low-power semiconductor 15, a heat dissipation mechanism assembled at the lower end of the semiconductor substrate 3, and a heat separation mechanism built into the heat dissipation mechanism to prevent heat transfer between the high-power and low-power semiconductors 15. The thermally conductive elastic composite mechanism has both heat transfer and shock absorption protection functions, the heat dissipation mechanism is responsible for improving the overall heat dissipation efficiency, and the heat separation mechanism can block thermal coupling, so that the high-power and low-power semiconductors maintain a reasonable operating temperature, avoid local overheating, performance degradation or shortened lifespan, thereby improving system reliability and energy efficiency.

[0019] refer to Figure 3 - Figure 5 As shown, the thermally conductive elastic composite mechanism includes a hydrogenated nitrile rubber 14 disposed at the lower end of the semiconductor substrate 3. Graphene 12 is embedded in the hydrogenated nitrile rubber 14. The graphene 12 completely covers the back side of the semiconductor substrate 3 and precisely corresponds to the solder joint positions of the high-power semiconductor 11 and the low-power semiconductor 15. Nickel-plated copper fibers 13 are also disposed inside the graphene 12, which are specifically used to transfer the heat generated by the high-power semiconductor 11 and the low-power semiconductor 15.

[0020] Specifically, hydrogenated nitrile rubber 14 has excellent elastic deformation capability, which can effectively absorb the thermal expansion difference between different devices and the vibration impact transmitted from the outside, and attenuate the vibration acceleration, thereby avoiding cracking of the solder joint between the semiconductor substrate 3 and the device due to stress concentration. Graphene 12 and nickel-plated copper fiber 13 work together to form a highly efficient thermal conductivity path, which can significantly improve the heat conduction efficiency and reduce the contact thermal resistance, realize the rapid heat dissipation of high power semiconductor 11, and at the same time ensure the temperature stability of low power semiconductor 15.

[0021] It should be noted that hydrogenated nitrile rubber 14 also has high insulation properties, which can avoid the risk of electrical short circuits caused by contact between different devices. Graphene 12 adopts a planar full-coverage design, which can accurately adapt to the distribution pattern of solder joints, and ultimately achieve simultaneous improvement in thermal reliability, mechanical stability and electrical safety of multi-power semiconductor accumulation system.

[0022] refer to Figure 7 - Figure 9 As shown, the heat dissipation mechanism includes a copper cold plate 7, on which a porous heat insulation layer 1 is fixedly installed. On the porous heat insulation layer 1, high-power heat dissipation area 5 and low-power heat dissipation area 6 are respectively opened at the positions corresponding to the high-power semiconductor 11 and the low-power semiconductor 15. Two positioning pins 2 are also fixedly installed on the porous heat insulation layer 1. Two positioning grooves 4 adapted to the positioning pins 2 are opened on the semiconductor substrate 3.

[0023] Specifically, the copper cold plate 7, with its high thermal conductivity, can quickly conduct heat transferred to its surface, achieving efficient heat diffusion. The precise cooperation between the two positioning pins 2 and the positioning groove 4 can ensure the assembly accuracy of the semiconductor substrate 3 and the porous heat insulation layer 1, avoid gaps at the heat dissipation interface, and prevent poor electrical contact caused by assembly deviations.

[0024] This heat dissipation mechanism, through its zoned thermal management design, adapts to the differences in thermal characteristics of different power devices. Combined with a precision assembly structure, it can fully meet the requirements for efficient heat dissipation, thermal coupling isolation, and structural reliability in environments with a high concentration of multi-power semiconductors.

[0025] refer to Figure 6 - Figure 7 As shown, the heat separation mechanism includes a laser-fused dense layer 8 and a high-porosity thermally conductive copper 9. The laser-fused dense layer 8 is assembled in the high-power heat dissipation area 5 of the porous heat insulation layer 1, and the high-porosity thermally conductive copper 9 is assembled in the low-power heat dissipation area 6 of the porous heat insulation layer 1. The laser-fused dense layer 8 and the high-porosity thermally conductive copper 9 can be adapted and installed according to the actual position changes of the high-power semiconductor 11 and the low-power semiconductor 15. The position adjustable feature enables it to achieve precise alignment with the hot spot area of ​​the device, further improving the targeting and effectiveness of the heat conduction path.

[0026] Specifically, the copper cold plate 7 is based on high thermal conductivity to achieve rapid heat diffusion. The porous heat insulation layer 1 is designed to adapt to the thermal characteristics differences of high and low power devices. The laser-welded dense layer 8 forms a continuous heat conduction path in the high power heat dissipation area 5. Its low porosity solid phase skeleton can ensure the vertical conduction of high power heat, significantly improve heat conduction efficiency, and meet the high-density heat load requirements of high power devices.

[0027] The high-porosity thermally conductive copper 9 blocks lateral thermal crosstalk in the low-power heat dissipation area 6 through its own porous structure (porosity ≥ 70%), while ensuring that the heat generated by the low-power device is effectively dissipated. This design, which dynamically adapts to the device position, further improves the matching degree of the heat conduction path and avoids the problem of increased local thermal resistance caused by positional offset.

[0028] It should be noted that this heat separation mechanism can control the temperature difference between the high and low power consumption areas within 8°C, which greatly improves the thermal coupling isolation efficiency. The differentiated design of laser welding and high porosity structure not only takes into account thermal management performance and structural lightweight, but also improves the compatibility with different device layout schemes, and fully adapts to the high-efficiency heat dissipation and thermal isolation requirements of multi-power semiconductor accumulation environment.

[0029] A locking screw 10 is provided between the copper cold plate 7, the porous heat insulation layer 1, and the semiconductor substrate 3. The locking screw 10 is threadedly connected to the copper cold plate 7, thereby fixing the semiconductor substrate 3 and the porous heat insulation layer 1.

[0030] Within this device: Porous insulation layer 1: Installed and fixed above and to the copper cold plate 7, it is a heat insulation component with a porous structure. Its core function is to block lateral heat crosstalk, while achieving zoned heat dissipation adaptation through the preset high-power heat dissipation zone 5 and low-power heat dissipation zone 6. This not only prevents heat from the high and low power areas from interfering with each other through the insulation layer, but also provides a precise mounting carrier for the subsequent heat separation mechanism, thus taking into account both heat insulation and structural zoning functions.

[0031] Semiconductor substrate 3: The device support base of the entire heat dissipation structure is a flat plate component made of semiconductor material. Its front side is used to fix the high-power semiconductor 11 and the low-power semiconductor 15, and its back side is in direct contact with the thermally conductive elastic composite mechanism. Its core function is to provide mounting support for the two types of power devices. At the same time, it serves as an intermediate carrier for heat transfer, conducting the heat generated by the device to the thermally conductive and heat dissipation components on the back side. It is the core carrier for the integration of multiple power devices.

[0032] High-power heat dissipation area 5: A specific area opened on the porous heat insulation layer 1, the position of which corresponds exactly to the high-power semiconductor 11 on the semiconductor substrate 3. A laser-welded dense layer 8 is installed inside this area. Its core function is to provide a dedicated heat dissipation channel for the high-power semiconductor 11. Because the high-power device generates a lot of heat and has a high heat flux density, this area uses the high thermal conductivity of the laser-welded dense layer 8 to quickly and directionally conduct the heat generated by the high-power semiconductor 11 to the copper cold plate 7, meeting the requirements for dissipating high-density heat load.

[0033] Low-power heat dissipation area 6: It is located on the porous heat insulation layer 1 in parallel with the high-power heat dissipation area 5, and its position corresponds to the low-power semiconductor 15 on the semiconductor substrate 3. High-porosity thermally conductive copper 9 is installed inside the area. Its core function is to block thermal crosstalk while dissipating the heat of low-power devices: Low-power devices generate little heat but are sensitive to temperature. This area uses the low lateral thermal conductivity of the high-porosity thermally conductive copper 9 with a porosity of ≥70% to dissipate the heat of the low-power semiconductor 15 and prevent the heat of the high-power heat dissipation area 5 from interfering with the low-power devices through the lateral path, thus maintaining the temperature stability of the low-power devices.

[0034] Copper cold plate 7: A copper flat plate component located at the bottom of the heat dissipation structure, fixedly connected to the porous heat insulation layer 1. Because copper has excellent thermal conductivity, its core function is to act as a heat dissipation core: receiving heat transferred from the high and low power consumption heat dissipation areas 6, and quickly dissipating the locally accumulated heat to the entire surface of the cold plate through its own large-area conduction characteristics, avoiding heat accumulation in a single area, and providing a foundation for subsequent system-level heat dissipation such as matching fans and water cooling.

[0035] Laser-welded dense layer 8: Installed inside the high-power heat dissipation area 5, between the porous heat insulation layer 1 and the copper cold plate 7, this dense metal layer is made by laser welding and has a low porosity and near-solid structure. Its core function is to build a high thermal conductivity path: by utilizing the vertical high thermal conductivity of the dense structure, the heat transferred from the high-power semiconductor 11 to this area is efficiently and directionally conducted to the copper cold plate 7. There are no pores to hinder heat transfer, which meets the core requirement of rapid heat dissipation of high-power devices.

[0036] High-porosity thermally conductive copper 9: A porous copper component installed inside the low-power heat dissipation area 6 with a porosity of ≥70%. Its core function is to conduct heat and provide thermal insulation. On the one hand, its copper material ensures the effective removal of heat from the low-power semiconductor 15 to meet the low heat load requirements. On the other hand, the high-porosity structure can cut off the lateral heat transfer path and prevent the heat from the high-power heat dissipation area 5 from crosstalking to the low-power area through this component, thus achieving the dual function of conducting low-power heat and insulating high-power heat.

[0037] High-power semiconductor 11: High-power devices such as power chips and processors installed on the front side of semiconductor substrate 3 are characterized by high heat generation and high heat flux density, making them one of the main heat sources of the heat dissipation structure. The large amount of heat generated during operation needs to be transferred through semiconductor substrate 3 to the heat conduction and heat dissipation components on the back side. If the heat cannot be dissipated in time, performance degradation such as efficiency reduction or thermal runaway may occur. Therefore, a heat dissipation path with high thermal conductivity is required, such as high-power heat dissipation area 5 and laser-welded dense layer 8.

[0038] Graphene 12: A high thermal conductivity material layer embedded inside hydrogenated nitrile rubber 14, possessing extremely high thermal conductivity. Its structural design has two key features: first, it completely covers the back of the semiconductor substrate 3; second, it precisely aligns with the solder joints of the semiconductor. Its core function is to build an efficient heat transfer bridge: quickly conduct the heat generated by the semiconductor substrate 3 and the device solder joints to the heat dissipation mechanism below. At the same time, through full coverage and solder joint alignment design, it ensures that heat transfer has no blind spots and no delay, reducing contact thermal resistance.

[0039] Nickel-plated copper fiber 13: A metal fiber material distributed inside graphene 12. The surface is plated with nickel to improve oxidation resistance and conductivity, and the core is copper to ensure thermal conductivity. Its core function is to work synergistically with graphene 12 to enhance thermal conductivity: Through the fibrous structure, a three-dimensional thermal conductive network is formed in the graphene 12 layer, which makes up for the thermal conductivity shortcomings of a single graphene 12 layer in local areas, and further reduces the thermal resistance in the heat transfer process. Especially for the concentrated heat of high power semiconductor 11, it achieves faster heat dissipation and more uniform heat transfer.

[0040] Hydrogenated nitrile rubber 14: An elastic rubber component located between the back of the semiconductor substrate 3 and the porous heat insulation layer 1, internally encapsulating graphene 12 and nickel-plated copper fibers 13. Its core functions are shock absorption and protection, electrical insulation, and heat conduction carrier. First, it absorbs the thermal expansion difference between high- and low-power devices and external vibration impacts through elastic deformation, avoiding stress cracking of solder joints. Second, its high insulation prevents electrical short circuits caused by contact between different devices. Third, it serves as the encapsulation carrier for graphene 12 and nickel-plated copper fibers 13, ensuring the structural stability of the heat-conducting material and the integrity of the heat transfer path.

[0041] Low-power semiconductor 15: Low-power devices such as signal chips and sensors mounted on the front side of semiconductor substrate 3 are characterized by low heat generation, but are sensitive to temperature and need to maintain a narrow operating temperature range. They do not require high-load heat dissipation, but need to avoid heat interference from high-power semiconductor 11. Therefore, through the design of low-power heat dissipation area 6 and high-porosity thermally conductive copper 9, they can dissipate a small amount of their own heat while blocking thermal crosstalk in high-power areas, ensuring stable operating temperature and avoiding signal drift or shortened lifespan due to high temperature.

[0042] Working principle: In the first step, the heat generated by the high-power semiconductor 11 and the low-power semiconductor 15 during operation is first transferred to the thermally conductive elastic composite mechanism at the lower end through the semiconductor substrate 3. The hydrogenated nitrile rubber 14 absorbs the difference in thermal expansion and vibration impact by elastic deformation, protecting the solder joint from cracking. The high thermal conductivity path composed of graphene 12 and nickel-plated copper fiber 13 quickly conducts the heat out and transfers it to the porous heat insulation layer 1 of the heat dissipation mechanism.

[0043] In the second step, the semiconductor substrate 3 is precisely assembled with the porous heat insulation layer 1 through the cooperation of the positioning pin 2 and the positioning groove 4, ensuring that there is no gap in the heat dissipation interface. The high power heat dissipation area 5 and the low power heat dissipation area 6 of the porous heat insulation layer 1 correspond to the two types of devices respectively. The laser-welded dense layer 8 of the heat separation mechanism forms an efficient vertical heat conduction path in the high power area, which quickly transfers high-density heat to the copper cold plate 7 for diffusion. The high-porosity thermally conductive copper 9 blocks lateral thermal crosstalk in the low power area, while dissipating low-power heat.

[0044] In the third step, the copper cold plate 7 will quickly dissipate the absorbed heat to achieve overall heat dissipation. Throughout the process, the thermally conductive elastic composite mechanism ensures mechanical stability and electrical safety. The heat dissipation mechanism and the heat separation mechanism work together to achieve efficient heat dissipation and thermal coupling isolation, keeping the temperature difference between the high and low power consumption areas within 8°C, thus meeting the thermal management and structural reliability requirements of multi-power semiconductor accumulation environments.

[0045] The embodiments of the present invention are given for illustrative and descriptive purposes only, and are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of the invention, and to enable those skilled in the art to understand the invention and to design various embodiments with various modifications suitable for a particular purpose.

Claims

1. A heat dissipation structure for a multi-power device accumulation environment, characterized by, The application relates to a semiconductor substrate (3) provided with a high-power semiconductor (11) and a low-power semiconductor (15), a heat-conducting elastic composite mechanism arranged at the lower end of the high-power semiconductor (11) and the low-power semiconductor (15) and used for transferring heat generated by the two and damping the semiconductor substrate (3), a heat-dissipating mechanism arranged at the lower end of the semiconductor substrate (3) and used for dissipating heat of the semiconductor substrate (3), and a heat-separation mechanism arranged in the heat-dissipating mechanism and used for blocking heat transfer between the high-power semiconductor (11) and the low-power semiconductor (15). The heat-conducting elastic composite mechanism comprises hydrogenated nitrile rubber (14) arranged at the lower end of the semiconductor substrate (3) and internally provided with graphene (12) internally provided with nickel-plated copper fibers (13). The graphene (12) completely covers the back surface of the semiconductor substrate (3). The graphene (12) is located at the welding points of the high-power semiconductor (11) and the low-power semiconductor (15). The heat-dissipating mechanism comprises a copper cold plate (7) fixedly provided with a porous heat-insulating layer (1).

2. The heat sink structure for a multi-power device accumulation environment according to claim 1, wherein, The porous heat-insulating layer (1) is provided with a high-power heat-dissipating area (5) and a low-power heat-dissipating area (6).

3. The heat sink structure for a multi-power device accumulation environment according to claim 2, wherein, The porous heat-insulating layer (1) is fixedly provided with two positioning pins (2).

4. The heat sink structure for a multi-power device accumulation environment according to claim 3, wherein, The semiconductor substrate (3) is provided with two positioning grooves (4) matched with the positioning pins (2).

5. The heat sink structure for a multi-power device accumulation environment according to claim 4, wherein, The heat-separation mechanism comprises a laser fusion dense layer (8) and high-porosity heat-conducting copper (9), and the laser fusion dense layer (8) and the high-porosity heat-conducting copper (9) can be adaptively installed according to the position change of the high-power semiconductor (11) and the low-power semiconductor (15).

6. The heat sink structure for a multi-power device accumulation environment according to claim 5, wherein, The laser fusion dense layer (8) is arranged in the high-power heat-dissipating area (5) of the porous heat-insulating layer (1), and the high-porosity heat-conducting copper (9) is arranged in the low-power heat-dissipating area (6) of the porous heat-insulating layer (1).

7. The heat sink structure for a multi-power device accumulation environment according to claim 6, wherein, ​ 8. The heat sink structure for a multi-power device accumulation environment according to claim 7, wherein, ​ 9. The heat sink structure for a multi-power device accumulation environment according to claim 8, wherein, ​ 10. The heat sink structure for a multi-power device accumulation environment according to claim 9, wherein, ​

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