Packaging substrate structure and manufacturing method thereof

Abstract

The invention provides a package substrate structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, forming a through hole penetrating through the substrate, and forming a seed metal layer covering the lower surface of the substrate and an inner wall at a preset distance upward from the opening of the through hole in the lower surface of the substrate; forming a conductive adhesive layer on the lower surface of the seed metal layer, wherein the conductive adhesive layer blocks the bottom opening of the through hole; sequentially forming a pre-plating layer at least covering and blocking the exposed surface of the conductive adhesive layer at the bottom opening of the through hole and an electroplated layer filling the through hole in the through hole, wherein the pre-plating layer and the electroplated layer form a filling conductive layer; and removing the conductive adhesive layer, and respectively forming a circuit layer and at least one layer of wiring structure which are stacked in sequence on the lower surface and the upper surface of the substrate after the filling conductive layer is formed. According to the packaging substrate structure and the manufacturing method thereof, high-quality filling of the through hole with the large depth-to-width ratio is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a packaging substrate structure and a manufacturing method thereof. BACKGROUND

[0002] Through glass via (TGV) is a vertical electrical interconnection through glass substrate, corresponding to through silicon via (TSV) technology, which can be used as a new technology to replace organic board via interconnection. TGV has excellent electrical performance, optical performance and good mechanical stability, and has great application potential in advanced packaging and passive device manufacturing fields. Therefore, TGV is considered as a key technology for the next generation of advanced packaging. However, TGV also faces great challenges, such as hole forming technology, which is difficult to meet the requirements of high precision, verticality, hole shape, high aspect ratio (depth / diameter of via) while ensuring that the glass surface and hole wall cannot have cracks, because these defects will affect the subsequent process and reliability.

[0003] Therefore, TGV hole filling technology is a technical difficulty that limits the application of glass via. In order to achieve smaller volume, faster transmission speed and lower signal loss, high aspect ratio TGV hole filling is required. At present, via hole filling with a high aspect ratio of 5:1 cannot meet market demand. If TGV via hole filling with a high aspect ratio of 10:1 or even 20:1 can be achieved, it will have a more competitive advantage in the market. However, via hole filling with a larger aspect ratio has the problems of smaller hole diameter, deeper hole depth, longer electroplating time, thicker copper thickness on the glass surface, higher cost, etc.

[0004] Therefore, there is an urgent need for a packaging substrate structure and a manufacturing method thereof capable of realizing glass via filling with a higher aspect ratio. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a packaging substrate structure and a manufacturing method thereof, which can solve the problem of difficult glass via filling with a high aspect ratio in the prior art.

[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a manufacturing method of a packaging substrate structure, comprising the following steps:

[0007] providing a substrate, forming a via hole penetrating through the substrate, and forming a seed metal layer covering the lower surface of the substrate and the inner wall of the via hole opening from the lower surface of the substrate to a predetermined distance upward;

[0008] forming a conductive adhesive layer on the lower surface of the seed metal layer, the conductive adhesive layer sealing the bottom opening of the via hole;

[0009] a pre-plating layer covering at least the exposed surface of the conductive adhesive layer and a plating layer filling the through hole are formed in sequence inside the through hole, and the pre-plating layer and the plating layer constitute a filling conductive layer;

[0010] The conductive adhesive layer is removed, and a circuit layer and at least one wiring structure are formed in sequence on the lower surface and the upper surface of the substrate after the filling conductive layer is formed.

[0011] Optionally, the method for forming the through hole comprises laser-induced deep etching.

[0012] Optionally, the high aspect ratio of the through hole is 10-20:1.

[0013] Optionally, the method for forming the conductive adhesive layer on the lower surface of the seed metal layer comprises dispensing or spraying.

[0014] Optionally, the method for forming the pre-plating layer comprises physical vapor deposition or chemical vapor deposition.

[0015] Optionally, after the conductive adhesive layer is removed, before the circuit layer is formed, a buffer metal layer is formed on the upper surface of the substrate after the filling conductive layer is formed, a conductive metal layer is formed on the surface of the seed metal layer and the buffer metal layer away from the surface of the substrate, and the conductive metal layer is thinned.

[0016] Optionally, the method for thinning the conductive metal layer comprises chemical mechanical polishing or chemical thinning.

[0017] Optionally, the formation of the circuit layer comprises the following steps: a patterned first shielding layer is formed on the surface of the thinned conductive metal layer, a circuit material layer covering the exposed surface of the conductive metal layer is formed based on the patterned first shielding layer, the patterned first shielding layer is removed, a first opening exposing the conductive metal layer at the bottom is formed in the circuit material layer, and the conductive metal layer, the seed metal layer and the buffer metal layer at the bottom of the first opening are removed in sequence to obtain the circuit layer.

[0018] Optionally, the formation of the wiring structure comprises the following steps: an insulating layer covering the exposed surface of the circuit layer and the substrate is formed, a through hole exposing the circuit layer on the surface of the filling conductive layer at the bottom is formed in the insulating layer from the surface of the insulating layer away from the substrate, and a metal wiring layer filling the through hole and located on the surface of the insulating layer away from the substrate is formed to obtain the wiring structure.

[0019] Optionally, forming the metal wiring layer comprises the following steps: forming a chemical plating layer covering the inner wall and bottom of the through hole and the surface of the insulating layer away from the substrate, forming a patterned second shielding layer on the surface of the chemical plating layer, forming a metal connection layer filling the through hole and located on the surface of the chemical plating layer based on the patterned second shielding layer, removing the patterned second shielding layer, forming a second opening in the metal connection layer exposing the chemical plating layer, removing the chemical plating layer located at the bottom of the second opening to obtain the metal wiring layer.

[0020] The application further provides a packaging substrate structure prepared by the method.

[0021] As described above, the packaging substrate structure and the manufacturing method thereof have the following beneficial effects: by using the bottom-up method, the filling conductive layer filling the through hole is formed in the through hole on the upper surface of the conductive adhesive layer, the filling conductive layer is composed of the pre-plating layer and the electroplating layer, the filling conductive layer formed has uniform quality and no convex and concave is generated, high-quality filling of the through hole with a large aspect ratio is achieved, and by forming the pre-plating layer at the bottom of the through hole, electroplating of the surface of the substrate can be effectively inhibited, and in the subsequent process of forming the electroplating layer, the electroplating current can be maximally applied to the through hole, so that the deposition speed in the through hole is increased, the electroplating time is reduced, the thickness of the electroplating layer after electroplating is reduced, and high-quality filling of the through hole with a large aspect ratio is ensured; in addition, before forming the filling conductive layer filling the through hole, the seed metal layer covering the lower surface of the substrate and the inner wall of the through hole upward from the opening of the through hole to a preset distance is formed, which helps to achieve uniform electroplating of the inner wall of the through hole, ensures uniform filling of the entire through hole, improves the quality and electrical conductivity of the through hole filling, avoids the occurrence of hollow or incomplete filling, and the good adhesion between the seed metal layer and the inner wall of the through hole helps to enhance the mechanical stability of the filling conductive layer and reduce the possibility of peeling or breaking in the process after removing the conductive adhesive layer; by forming the conductive adhesive layer on the lower surface of the seed metal layer, not only can the conductive adhesive layer provide support for the subsequent formation of the pre-plating layer and the electroplating layer filling the through hole, but also can provide a conductive condition for the subsequent formation of the pre-plating layer and the electroplating layer filling the through hole, and damage to the substrate can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 The figure shows a manufacturing process schematic diagram of the packaging substrate structure of the application.

[0023] Figure 2A structural schematic diagram of a substrate shown as a structure after forming a via in a method of fabricating a package substrate structure of the present application.

[0024] Figure 3 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0025] Figure 4 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0026] Figure 5 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0027] Figure 6 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0028] Figure 7 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0029] Figure 8 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0030] Figure 9 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0031] Figure 10 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0032] Figure 11 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0033] Figure 12 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0034] Figure 13 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0035] Figure 14 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0036] Figure 15 A structural schematic diagram of a substrate shown as a structure after forming a seed metal layer in a method of fabricating a package substrate structure of the present application.

[0037] Figure 16 A structure schematic diagram after forming the insulating layer in the manufacturing method of the packaging substrate structure of the present application.

[0038] Figure 17 A structure schematic diagram after forming the through hole in the manufacturing method of the packaging substrate structure of the present application.

[0039] Figure 18 A structure schematic diagram after forming the chemical plating layer in the manufacturing method of the packaging substrate structure of the present application.

[0040] Figure 19 A structure schematic diagram after forming the second shielding layer in the manufacturing method of the packaging substrate structure of the present application.

[0041] Figure 20 A structure schematic diagram after patterning the second shielding layer in the manufacturing method of the packaging substrate structure of the present application.

[0042] Figure 21 A structure schematic diagram after forming the metal wiring layer in the manufacturing method of the packaging substrate structure of the present application.

[0043] Figure 22 A structure schematic diagram after removing the second shielding layer in the manufacturing method of the packaging substrate structure of the present application.

[0044] Figure 23 A structure schematic diagram after forming the metal wiring layer in the manufacturing method of the packaging substrate structure of the present application.

[0045] Element number explanation

[0046] 1 substrate

[0047] 2 through hole

[0048] 3 seed metal layer

[0049] 4 conductive adhesive layer

[0050] 5 filled conductive layer

[0051] 51 pre-plating layer

[0052] 52 electroplating layer

[0053] 6 wiring layer

[0054] 61 wiring material layer

[0055] 611 first opening

[0056] 7 conductive metal layer

[0057] 8 wiring structure

[0058] 81 insulating layer

[0059] 82 through hole

[0060] 83 metal wiring layer

[0061] 831 electroless plating layer

[0062] 832 metal connection layer

[0063] 833 second opening

[0064] 9 first shielding layer

[0065] 10 buffer metal layer

[0066] 1a second shielding layer DETAILED DESCRIPTION

[0067] The present application will be described in detail by specific embodiments, and other advantages and effects of the present application can be easily understood by those skilled in the art from the contents disclosed in the specification.

[0068] Reference will now be made to the drawings, wherein: Figures 1 to 23 It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to the specification are only used to illustrate the contents disclosed in the specification, to be understood and read by those skilled in the art, and do not define the limiting conditions for the implementation of the present application, and therefore do not have technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" used in the specification are only for the convenience of clear description, and are not used to limit the scope of the implementation of the present application. The change or adjustment of the relative relationship, without substantially changing the technical content, is also considered as the implementation scope of the present application.

[0069] Embodiment 1

[0070] Figure 1 As shown in the flowchart of the manufacturing process of the packaging substrate structure, the present application provides a manufacturing method of a packaging substrate structure, comprising the following steps:

[0071] S1: providing a substrate, forming a through hole through the substrate, and forming a seed metal layer covering the lower surface of the substrate and the inner wall of the through hole opening from the lower surface of the substrate to a predetermined distance upward;

[0072] S2: forming a conductive adhesive layer on the lower surface of the seed metal layer, and the conductive adhesive layer seals the opening of the bottom surface of the through hole;

[0073] S3: sequentially forming a pre-plating layer covering the exposed surface of the conductive adhesive layer and an electroplating layer filling the through hole, the pre-plating layer and the electroplating layer forming a filled conductive layer;

[0074] S4: removing the conductive adhesive layer, and forming a circuit layer and at least one wiring structure sequentially stacked on the lower surface and the upper surface of the substrate after forming the filled conductive layer.

[0075] Specifically, referring to Figures 2-4 , step S1 is performed to provide a substrate 1, a through hole 2 penetrating the substrate 1 is formed, and a seed metal layer 3 covering the lower surface of the substrate 1 and the inner wall of the through hole 2 upward from the opening of the through hole 2 on the lower surface of the substrate 1 to a predetermined distance is formed.

[0076] Specifically, Figure 2 , as shown in the structural schematic diagram of the substrate 1, the thickness of the substrate 1 ranges from 0.2 mm to 1.6 mm.

[0077] Specifically, the lateral cross-sectional dimension of the substrate 1 is greater than 70 mm x 70 mm.

[0078] Specifically, the substrate 1 is a glass substrate with high heat resistance, extremely low loss factor and relatively high Young's modulus, and the substrate also has the characteristics of unlimited width, low cost, strong mechanical stability and excellent high-frequency electrical performance.

[0079] As an example, Figure 3 , as shown in the structural schematic diagram after forming the through hole 2, the method for forming the through hole 2 includes laser-induced deep etching or other suitable methods.

[0080] Specifically, the aperture size of the through hole 2 is greater than 10 μm.

[0081] Specifically, the method for forming the through hole 2 by laser-induced deep etching includes the following steps: providing a laser emitting device, starting the laser emitting device to irradiate a predetermined position of the substrate 1, generating a denatured area on the substrate 1, and then placing the substrate 1 after generating the denatured area into an etching solution system to etch the denatured area, so as to obtain the through hole 2 penetrating the substrate 1.

[0082] Specifically, the etching solution system used for forming the through hole 2 by laser-induced deep etching includes one of a hydrofluoric acid system or an alkaline system.

[0083] Specifically, the laser used for forming the through hole 1 by laser-induced deep etching includes one of a nanosecond laser, a picosecond laser, a femtosecond laser or other suitable types of lasers.

[0084] Specifically, the laser-induced deep etching is to use a pulsed laser to act on the substrate to generate a continuous denatured region on the substrate 1. Compared with the non-denatured region on the substrate 1, the substrate in the denatured region has a faster etching rate in the etching solution system, thereby forming a through hole 2 penetrating through the substrate 1.

[0085] Specifically, the laser-induced deep etching is used to form the through hole 2. Due to the anisotropy of etching, the perpendicularity and morphology of the through hole can be adjusted by adjusting the parameters of the laser emitting device. The hole forming rate is fast, and the formed through hole 2 is uniform in quality, good in consistency and free of cracks.

[0086] As an example, the high aspect ratio of the through hole 2 is 10-20:1. In the embodiment, the high aspect ratio of the through hole 2 is 20:1.

[0087] Specifically, the seed metal layer 3 is composed of a titanium metal layer (not shown) and a copper metal layer (not shown) stacked in sequence.

[0088] Specifically, Figure 4 As shown, the structure after forming the seed metal layer 3 is shown. The seed metal layer 3 is formed by the following steps: providing a vacuum coating equipment, vacuumizing the vacuum coating equipment, using plasma etching to form a titanium metal layer and a copper metal layer on the lower surface of the substrate 1 and the inner wall surface of the through hole 2 from the opening at the bottom of the through hole 2 in a predetermined distance, to obtain the seed metal layer 3.

[0089] Specifically, the method for forming the seed metal layer 3 includes one of vacuum evaporation, sputtering, arc plasma coating, ion plating and molecular beam epitaxy or other suitable methods.

[0090] Specifically, the vacuum coating equipment includes one of vacuum evaporation coating machine, vacuum sputtering coating machine, vacuum ion coating machine or other suitable vacuum coating equipment.

[0091] Specifically, the temperature range for vacuumizing the vacuum coating equipment is 60-150℃, and the processing time range is 30-3000s.

[0092] Specifically, the gas used in the plasma etching is at least one of oxygen, carbon tetrafluoride and argon.

[0093] Specifically, the power range used in the plasma etching is 500-5000W, and the processing time range is 1-8min.

[0094] Specifically, the thickness of the copper metal layer is greater than that of the titanium metal layer.

[0095] Specifically, the thickness of the titanium metal layer is greater than 50nm, and the thickness deviation is less than 5%.

[0096] Specifically, before forming the filling conductive layer 5, the seed metal layer 3 is formed to cover the lower surface of the substrate 1 and the inner wall of the via 2 upward from the opening of the lower surface of the substrate 1 by a predetermined distance, which helps to realize uniform electroplating of the inner wall of the via 2, ensures uniform filling of the entire via 2, improves the quality and electrical conductivity of the via filling, avoids the occurrence of voids or incomplete filling, and the good adhesion between the seed metal layer 3 and the inner wall of the via 2 helps to enhance the mechanical stability of the filling conductive layer 5 and reduce the possibility of peeling or breaking in the process after removing the conductive adhesive layer 4.

[0097] Specifically, referring to Figure 5 , step S2 is performed to form a conductive adhesive layer 4 on the lower surface of the seed metal layer 3, and the conductive adhesive layer 4 seals the opening of the bottom surface of the via 2.

[0098] Specifically, the conductive adhesive layer 4 is composed of two parts: a matrix (not shown) and a conductive filler (not shown), wherein the matrix includes one of epoxy resin, phenolic resin, polyimide, and polyurethane, and the conductive filler includes one of carbon, metal, and metal oxide.

[0099] As an example, Figure 5 , a structure schematic diagram after forming the conductive adhesive layer 4 is shown, and the method for forming the conductive adhesive layer 4 on the lower surface of the seed metal layer 3 includes dispensing, spraying, or other suitable methods.

[0100] Specifically, the conductive adhesive layer 4 is formed on the lower surface of the seed metal layer 3, which provides conductive conditions for the subsequent formation of the pre-plating layer 5a and the electroplating layer 5b filling the via 2, and in addition, the conductive adhesive layer 4 also provides support for the subsequent formation of the pre-plating layer 51 and the electroplating layer 52 filling the via 2, avoiding damage to the substrate 1.

[0101] Specifically, referring to Figures 6-7 , step S3 is performed to form, inside the via 2, a pre-plating layer 51 and an electroplating layer 52 filling the via 2 in sequence, the pre-plating layer 51 covers at least the exposed surface of the conductive adhesive layer 4 sealing the opening of the bottom surface of the via 2, and the pre-plating layer 51 and the electroplating layer 52 constitute the filling conductive layer 5.

[0102] Specifically, the material of the pre-plating layer 51 includes copper or other suitable materials.

[0103] Specifically, Figure 6 , a structure schematic diagram after forming the pre-plating layer 51 is shown, and the method for forming the pre-plating layer 51 includes physical vapor deposition, chemical vapor deposition, or other suitable methods.

[0104] Specifically, the thickness and shape of the pre-plating layer 51 can be selected according to actual conditions without limitation, provided that the performance of the packaging substrate structure is met.

[0105] Specifically,Figure 7 The diagram shown is a structural schematic after the electroplated layer 52 is formed. The method for forming the electroplated layer 52 includes electroplating or other suitable methods.

[0106] Specifically, by forming a pre-plating layer 51 at the bottom of the through hole 2, the electroplating on the surface of the substrate 1 can be effectively suppressed. At the same time, during the subsequent formation of the electroplating layer 52, the electroplating current can be maximized to act inside 2, thereby increasing the deposition rate inside the through hole 2, reducing the electroplating time, reducing the thickness of the electroplated layer 52 after electroplating, achieving the filling of the through hole 2 with a large aspect ratio, and ensuring that the quality of the formed electroplated layer 52 is uniform, without voids or gaps.

[0107] Specifically, by adopting a bottom-up method, a pre-plating layer 51 and an electroplating layer 52 are sequentially formed inside the through hole 2 on the upper surface of the conductive adhesive layer 4 to form a filling conductive layer 5 that fills the through hole 2. The formed filling conductive layer 5 has uniform quality and no bumps or grooves, thus achieving high-quality filling of the through hole 2 with a large aspect ratio.

[0108] For details, please refer to Figures 8-23 In step S4, the conductive adhesive layer 4 is removed, and a circuit layer 6 and at least one wiring structure 8 are formed sequentially on the lower and upper surfaces of the substrate 1 after the conductive filling layer 5 is formed.

[0109] As an example, Figures 8-10 The diagrams shown are schematic diagrams of the structure after the seed metal layer 3 covering the upper surface of the substrate 1 and filling the upper surface of the conductive layer 5 is formed, the structure after the conductive metal layer 7 is formed, and the structure after the conductive metal layer 7 is thinned. After removing the conductive adhesive layer 4 and before forming the circuit layer 6, a buffer metal layer 10 is formed on the upper surface of the substrate 1 after the conductive layer 5 is formed, and a conductive metal layer 7 is formed on the surface of the seed metal layer 3 and the buffer metal layer 10 away from the substrate 1. The conductive metal layer 7 is then thinned.

[0110] Specifically, the method for forming the buffer metal layer 10 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0111] Specifically, while meeting the performance requirements of the packaging substrate structure, the thickness, material, and shape of the buffer metal layer 10 can be selected according to the actual situation, and are not limited here.

[0112] Specifically, the conductive metal layer 7 is made of copper or other suitable conductive materials.

[0113] Specifically, the method for forming the conductive metal layer 7 includes one of vacuum ion plating, horizontal copper plating, and horizontal plating.

[0114] Specifically, the initial conductive metal layer 7 has a thickness greater than 25 μm.

[0115] Specifically, the method for thinning the conductive metal layer 7 includes chemical mechanical grinding, chemical thinning or other suitable methods. In the present embodiment, the method for thinning the conductive metal layer 7 is chemical mechanical grinding.

[0116] Specifically, the conductive metal layer 7 after thinning has a thickness less than 15 μm.

[0117] Specifically, the method for thinning the conductive metal layer 7 by chemical mechanical grinding includes the following steps: providing a chemical mechanical grinding device, placing the substrate 1 with the conductive metal layer 7 formed thereon on the chemical mechanical grinding device, and adding a polishing liquid to the contact surface between the conductive metal layer 7 and the chemical mechanical grinding device, then grinding the conductive metal layer 7, and monitoring the thickness of the conductive metal layer 7 during the grinding process until the thickness of the conductive metal layer 7 after thinning is less than 15 μm.

[0118] Specifically, the chemical mechanical grinding is realized by the physical grinding action of nano-sized particles and the chemical corrosion action of the polishing liquid, and the surface of the conductive metal layer 7 after chemical mechanical grinding is flat without protrusions or grooves.

[0119] Specifically, the polishing liquid used for thinning the conductive metal layer 7 by chemical mechanical grinding includes abrasive particles, oxidizing agents, complexing agents, surfactants, abrasives, pH adjusters, corrosion inhibitors or other suitable polishing liquids.

[0120] Specifically, Figures 11-15 As shown, the structure schematic diagrams after forming the first shielding layer 9, patterning the first shielding layer 9, forming the circuit material layer 61, removing the first shielding layer 9 and forming the circuit layer 6 are shown respectively. Forming the circuit layer 6 includes the following steps: forming the patterned first shielding layer 9 on the surface of the thinned conductive metal layer 7, forming the circuit material layer 61 covering the exposed surface of the conductive metal layer 7 based on the patterned first shielding layer 9, forming the first opening 611 in the circuit material layer 61 with the bottom surface of the conductive metal layer 7 exposed, and sequentially removing the patterned first shielding layer 9, the conductive metal layer 7, the seed metal layer 3 and the buffer metal layer 10 at the bottom of the first opening 611 to obtain the circuit layer 6.

[0121] Specifically, forming the patterned first shielding layer 9 includes the following steps: forming the first shielding layer 9 on the surface of the thinned conductive metal layer 7, and sequentially exposing and developing the first shielding layer 9 to obtain the patterned first shielding layer 9.

[0122] Specifically, the first shielding layer 9 is made of polyethylene film (PE), photoresist film and polyester film (PET), which is a kind of high polymer material that can block electroplating and etching, and can be polymerized by ultraviolet irradiation.

[0123] Specifically, the exposure machine used for exposing the first shielding layer 9 includes at least one of G-line, I-line and H-line.

[0124] Specifically, the light source used for exposing the first shielding layer 9 includes one of halogen lamp, high-pressure mercury lamp and iodine gallium lamp.

[0125] Specifically, the developing solution used for developing the first shielding layer 9 includes one of sodium hydroxide, sodium carbonate and sodium bicarbonate.

[0126] Specifically, the method for forming the circuit material layer 61 includes electroplating or other suitable methods.

[0127] Specifically, the method for removing the patterned first shielding layer 9 includes chemical solution removal or other suitable removal methods.

[0128] Specifically, the chemical solution used for removing the patterned first shielding layer 9 includes strong alkali solution or other suitable solutions.

[0129] Specifically, the method for removing the conductive metal layer 7, the buffer metal layer 10 and the seed metal layer 3 at the bottom of the first opening 611 includes chemical solution removal or other suitable methods.

[0130] Specifically, the chemical solution used for removing the conductive metal layer 7, the buffer metal layer 10 and the seed metal layer 3 at the bottom of the first opening 611 includes at least one of NaOH, NaHCO3, Na2CO3, HCl, H3PO4 and H2O2.

[0131] As an example, Figures 16-23 As shown, the formation of the wiring structure 8 includes the following steps: forming the insulating layer 81 covering the circuit layer 6 and the exposed surface of the substrate, forming the through hole 82 in the insulating layer 81, which is open from the surface of the insulating layer 81 away from the substrate 1 and exposes the circuit layer 6 on the surface of the conductive layer 5 at the bottom, forming the metal wiring layer 83 filling the through hole 82 and located on the surface of the insulating layer 81 away from the substrate 1, to obtain the wiring structure 8.

[0132] Specifically, the method for forming the insulating layer 81 includes lamination or other suitable methods.

[0133] Specifically, the insulating layer 81 includes an ABF film or other suitable insulating layer.

[0134] Specifically, the ABF film is used as the insulating layer 81, which has low thermal expansion coefficient, low dielectric loss, easy to process fine lines, good mechanical properties, good durability, and other characteristics.

[0135] Specifically, the method for forming the through hole 82 includes laser drilling or other suitable methods.

[0136] Specifically, the laser drilling device used for forming the through hole 82 by laser drilling includes one of a UV laser drilling machine, a CO2 laser drilling machine, and an ultrafast laser drilling machine.

[0137] Specifically, the laser used by the laser drilling device includes one of a continuous laser, a quasi-continuous laser, a nanosecond laser, a picosecond laser, and a femtosecond laser.

[0138] As an example, forming the metal wiring layer 83 includes the following steps: forming a chemical plating layer 831 covering the inner wall and bottom of the through hole 82 and the surface of the insulating layer 81, forming a patterned second shielding layer 1a on the surface of the chemical plating layer 831, forming a metal connection layer 832 filling the through hole 82 and located on the surface of the chemical plating layer 831 based on the patterned second shielding layer 1a, removing the patterned second shielding layer 1a, forming a second opening 833 exposing the chemical plating layer 831 in the metal connection layer 832, removing the chemical plating layer 831 at the bottom of the second opening 833, to obtain the metal wiring layer 83.

[0139] Specifically, the material of the chemical plating layer 831 includes copper or other suitable materials.

[0140] Specifically, the thickness of the chemical plating layer 831 ranges from 5 μm to 15 μm.

[0141] Specifically, the method for forming the chemical plating layer 831 includes chemical plating or other suitable methods.

[0142] Specifically, the main components of the plating solution used for forming the chemical plating layer 831 by chemical plating include copper sulfate, potassium sodium tartrate, sodium hydroxide, formaldehyde, ethylenediaminetetraacetic acid, triethanolamine, sodium carbonate, and deionized water.

[0143] Specifically, the chemical plating layer 831 formed by chemical plating has a back light level of no less than 9 levels, and the board surface has no serious oxidation, fiber filaments, finger marks, etc., and the board surface is shiny and uniform.

[0144] Specifically, the forming of the patterned second shielding layer 1a comprises sequentially exposing and developing the second shielding layer 1a.

[0145] Specifically, the method for forming the metal wiring layer 832 comprises electroplating or other suitable methods.

[0146] Specifically, the number of layers and the line width spacing of the formed wiring structure 8 can be selected according to actual conditions without limitation in the case of meeting the performance of the packaging substrate structure. In the embodiment, the line width spacing of the metal wiring layer 83 in the formed wiring structure 8 is 8 / 8 μm.

[0147] The manufacturing method of the packaging substrate structure of the embodiment, by adopting the bottom-up method, sequentially forms the filling conductive layer 5 filling the via 2 on the inner surface of the via 2 on the upper surface of the conductive adhesive layer 4, the filling conductive layer 5 is composed of a pre-plating layer 51 and an electroplating layer 52, the formed filling conductive layer 5 is uniform in quality without bumps and grooves, realizing high-quality filling of the via 2 with a large high aspect ratio, and by forming the pre-plating layer 51 at the bottom of the via 2, the surface plating of the substrate 1 can be effectively inhibited, and in the subsequent process of forming the electroplating layer 52, the electroplating current can be maximized to act on the via 2, thereby increasing the deposition speed in the via 2, reducing the electroplating time, reducing the thickness of the electroplating layer 52 after electroplating, and ensuring the high-quality filling of the via 2 with a high aspect ratio. In addition, before forming the filling conductive layer 5 filling the via 2, the seed metal layer 3 covering the lower surface of the substrate 1 and the inner wall of the via 2 opening upward from the lower surface of the substrate 1 is formed to a predetermined distance, which helps to realize uniform plating of the inner wall of the via 2, ensures uniform filling of the entire via 2, improves the quality and electrical conductivity of the via 2 filling, avoids the occurrence of voids or incomplete filling, and the good adhesion between the seed metal layer 3 and the inner wall of the via 2 helps to enhance the mechanical stability of the filling conductive layer 5 and reduce the possibility of peeling or breaking in the process after removing the conductive adhesive layer 4. The conductive adhesive layer 4 formed on the lower surface of the seed metal layer 3 provides support for the subsequent formation of the pre-plating layer 51 and the electroplating layer 52 filling the via 2, and the formed conductive adhesive layer 4 can also provide a conductive condition for the subsequent formation of the pre-plating layer 51 and the electroplating layer 52 filling the via 2, avoiding damage to the substrate 1.

[0148] Embodiment two

[0149] The embodiment provides a packaging substrate structure, and the packaging substrate structure is prepared by the packaging substrate structure manufacturing method in the embodiment one, and the packaging substrate structure comprises a substrate 1, a through hole 2, a seed metal layer 3, a filled conductive layer 5, a circuit layer 6 and at least one wiring structure 8, wherein the through hole 2 penetrates the substrate 1, the seed metal layer 3 covers the lower surface of the substrate 1 and the inner wall of the through hole 2 at a preset distance upwards from the opening of the through hole 2 on the lower surface of the substrate 1, the filled conductive layer 5 comprises a pre-plating layer 51 and an electroplating layer 52 which are sequentially stacked, and the circuit layer 6 and the wiring structure 8 are sequentially stacked on the lower surface and the upper surface of the substrate 1 after the filled conductive layer 5 is formed.

[0150] Specifically, the packaging substrate structure further comprises a buffer metal layer 10, and the buffer metal layer 10 is located on the upper surface of the substrate 1 after the filled conductive layer 5 is formed.

[0151] Specifically, the packaging substrate structure further comprises a conductive metal layer 7, and the conductive metal layer 7 is located on the surfaces of the buffer metal layer 10 and the seed metal layer 6 away from the substrate 1, and the circuit layer 6 is located on the surface of the conductive metal layer 7 away from the substrate 1.

[0152] Specifically, the wiring structure 8 comprises an insulating layer 81, a through hole 82 and a metal wiring layer 83, the insulating layer 81 covers the exposed surfaces of the substrate 1 and the circuit layer 8, the through hole 82 is open on the surface of the insulating layer 82 away from the substrate 1 and exposes the circuit layer 6 at the bottom, and the metal wiring layer 83 is respectively located in the through hole 82 and on the surface of the insulating layer 81 away from the substrate 1, and the metal wiring layer 83 comprises a chemical plating layer 831 and a metal connecting layer 832 which are sequentially stacked.

[0153] Specifically, the circuit layer 6 and the wiring structure 8 which are sequentially stacked on the upper and lower surfaces of the substrate 1 are electrically connected through the filled conductive layer 5.

[0154] Specifically, the through hole 2 is filled by the filled conductive layer 5, the formed filled conductive layer 5 is uniform in quality and does not have protrusions and recesses, high-quality filling of the through hole 2 with a large high-depth-width ratio is achieved, and the yield of the packaging substrate structure is improved.

[0155] The packaging substrate structure in the embodiment fills the through hole 2 by the filled conductive layer 5, the formed filled conductive layer 5 is uniform in quality and does not have protrusions and recesses, high-quality filling of the through hole 2 with a large high-depth-width ratio is achieved, and the yield of the packaging substrate structure is improved.

[0156] In summary, the package substrate structure and the manufacturing method thereof adopt the bottom-up method to sequentially form the filling conductive layer in the via inside the upper surface of the conductive adhesive layer, the filling conductive layer is composed of a pre-plating layer and a plating layer, the filling conductive layer formed is uniform in quality without bumps and grooves, high-quality filling of the via with a large aspect ratio is achieved, the pre-plating layer formed at the bottom of the via can effectively inhibit the plating of the substrate surface, and in the subsequent process of forming the plating layer, the plating current can be maximally applied to the via, so as to increase the deposition speed in the via, reduce the plating time, reduce the thickness of the plating layer after plating, and ensure high-quality filling of the via with a large aspect ratio. In addition, before forming the filling conductive layer filling the via, a seed metal layer covering the lower surface of the substrate and the inner wall of the via opening upward from the lower surface of the substrate is formed, which helps to realize uniform plating of the inner wall of the via, ensures uniform filling of the entire via, improves the quality and electrical conductivity of the via filling, avoids the occurrence of hollow or incomplete filling, and the good adhesion between the seed metal layer and the inner wall of the via helps to enhance the mechanical stability of the filling conductive layer and reduce the possibility of peeling or breaking in the process after removing the conductive adhesive layer. The conductive adhesive layer formed at the lower surface of the seed metal layer provides support for the subsequent formation of the pre-plating layer and the plating layer filling the via, and the conductive adhesive layer formed can also provide a conductive condition for the subsequent formation of the pre-plating layer and the plating layer filling the via, avoiding damage to the substrate. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0157] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a packaging substrate structure, characterized in that, Includes the following steps: A substrate is provided, through-holes are formed through the substrate, and a seed metal layer is formed covering the lower surface of the substrate and the inner wall at a predetermined distance upward from the opening of the through-hole on the lower surface of the substrate. A conductive adhesive layer is formed on the lower surface of the seed metal layer, and the conductive adhesive layer seals the bottom opening of the through hole. Inside the through hole, a pre-plating layer that covers at least the exposed surface of the conductive adhesive layer that seals the bottom opening of the through hole and an electroplating layer that fills the through hole are formed sequentially, the pre-plating layer and the electroplating layer constituting a conductive filling layer; After removing the conductive adhesive layer, a circuit layer and at least one wiring structure are formed sequentially on the lower and upper surfaces of the substrate after the conductive filling layer is formed.

2. The method for fabricating the packaging substrate structure according to claim 1, characterized in that: The method for forming the via includes laser-induced depth etching.

3. The method for fabricating the packaging substrate structure according to claim 1, characterized in that: The aspect ratio of the through hole is 10 to 20:

1.

4. The method for fabricating the packaging substrate structure according to claim 1, characterized in that: Methods for forming a conductive adhesive layer on the lower surface of the seed metal layer include dispensing and spraying.

5. The method for fabricating the packaging substrate structure according to claim 1, characterized in that: The methods for forming the pre-coating include physical vapor deposition and chemical vapor deposition.

6. The method for manufacturing the packaging substrate structure according to claim 1, characterized in that: After removing the conductive adhesive layer and before forming the circuit layer, a buffer metal layer is formed on the upper surface of the substrate after the conductive filling layer is formed, and a conductive metal layer is formed on the surface of the seed metal layer and the buffer metal layer away from the substrate, and then the conductive metal layer is thinned.

7. The method for manufacturing the packaging substrate structure according to claim 6, characterized in that: Methods for thinning the conductive metal layer include chemical mechanical polishing and chemical thinning.

8. The method for fabricating the packaging substrate structure according to claim 6, characterized in that, The formation of the circuit layer includes the following steps: forming a patterned first masking layer on the surface of the thinned conductive metal layer; forming a circuit material layer covering the exposed surface of the conductive metal layer based on the patterned first masking layer; removing the patterned first masking layer; forming a first opening with its bottom surface exposed to the conductive metal layer in the circuit material layer; and sequentially removing the conductive metal layer, the seed metal layer, and the buffer metal layer located at the bottom of the first opening to obtain the circuit layer.

9. The method for fabricating the packaging substrate structure according to claim 8, characterized in that, The wiring structure is formed by the following steps: forming an insulating layer covering the exposed surfaces of the circuit layer and the substrate; opening an opening from the surface of the insulating layer away from the substrate; forming a through hole in the insulating layer with the bottom exposed on the surface of the conductive filling layer; and forming a metal wiring layer inside the through hole and on the surface of the insulating layer away from the substrate, to obtain the wiring structure.

10. The method for fabricating the packaging substrate structure according to claim 9, characterized in that, Forming the metal wiring layer includes the following steps: forming a chemical plating layer covering the inner wall and bottom of the through hole and the surface of the insulating layer away from the substrate; forming a patterned second masking layer on the surface of the chemical plating layer; forming a metal interconnect layer based on the patterned second masking layer that fills the through hole and is located on the surface of the chemical plating layer; removing the patterned second masking layer; forming a second opening in the metal interconnect layer that exposes the chemical plating layer; and removing the chemical plating layer located at the bottom of the second opening to obtain the metal wiring layer.

11. A packaging substrate structure, characterized in that, The packaging substrate structure is manufactured using the method described in any one of claims 1 to 10.

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