Double-layer TSV pinboard packaging structure and preparation method thereof

Abstract

The invention discloses a double-layer TSV pinboard packaging structure and a preparation method thereof. The method comprises the following steps: etching a TSV hole in a first silicon wafer; preparing a Cu seed layer in the TSV hole; electroplating Cu in the TSV hole from bottom to top, and performing solid filling on the TSV hole to form a TSV copper column; reducing the thickness of the first silicon wafer, and exposing part of the TSV copper column; sequentially preparing a first bonding film layer, a buffer layer and a second bonding film layer in the bonding area to obtain a lower-layer adapter plate; etching a deep cavity on the second silicon wafer; electroplating a first bonding film layer in the deep cavity and the bonding area to obtain an upper-layer adapter plate; corroding off a non-bonding region of the upper-layer adapter plate; and completing bonding packaging of the upper-layer adapter plate and the lower-layer adapter plate through flip-chip bonding. According to the invention, not only can thermal diffusion between the bonding film layers be slowed down before packaging and high packaging strength be maintained, but also during alignment bonding, the bonding film layers of the double-layer adapter plate can be in close contact, and the problem of poor packaging airtightness of the adapter plate is solved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor microelectronic packaging technology, and specifically relates to a double-layer TSV adapter board packaging structure and its preparation method. Background Technology

[0002] In recent years, as microwave systems have become increasingly miniaturized, there are also demands for smaller size and higher integration of packaged devices. Packaging technology is also developing towards three-dimensional stacked interconnection. Packaging technology based on TSV adapter boards is also facing new development needs and its applications are becoming more widespread.

[0003] TSV-based interconnect technology utilizes techniques such as TSV etching, TSV plating, RDL wiring, CMP thinning and polishing, and metal bonding to achieve vertical and horizontal transmission of radio frequency signals. It offers advantages such as high integration, small size, and good electrical performance. However, the high integration of the interconnect board, coupled with its complex internal circuitry, numerous chip mounting points, and multiple subsequent assembly processes, along with its complex application scenarios, places higher demands on packaging strength and hermeticity.

[0004] The packaging technology based on double-layer adapter boards has made significant progress, but the following problems still exist: (1) TSV copper pillars are exposed by CMP thinning and polishing. Due to the difference in uniformity of thinning and polishing, the exposed height of TSV copper pillars in the center area of ​​the silicon wafer is significantly different from that in the edge area. Furthermore, the packaging bonding metal film layer is electroplated in the packaging area, which further increases the height of the TSV copper pillars in the packaging area. This causes the bonding film layer of the upper adapter board to contact the TSV copper pillar of the lower adapter board first during packaging bonding, resulting in the bonding film layers of the upper and lower adapter boards not being able to make close contact and poor bonding strength. (2) In the traditional production process, the two bonding film layers are directly electroplated to achieve high-strength bonding. However, in the actual production process, the adapter board will experience high temperature. It will also have to withstand high temperature during subsequent chip mounting, wire bonding, and testing. This causes the two metal film layers of the lower adapter board to have a diffusion reaction before packaging, making it impossible to bond and package with the upper adapter board. Summary of the Invention

[0005] The purpose of this invention is to provide a double-layer TSV adapter board packaging structure and its preparation method, which can not only slow down the heat diffusion between the bonding film layers before packaging and maintain high packaging strength, but also ensure that the bonding film layers of the double-layer adapter board can make close contact during alignment and bonding, thus solving the problem of poor airtightness of the adapter board packaging.

[0006] To achieve the above objectives, one aspect of the present invention provides a method for fabricating a dual-layer TSV adapter board packaging structure, comprising: Step S1: TSV holes are etched on the first silicon wafer. Step S2: A Cu seed layer is prepared in the TSV pores by magnetron sputtering; Step S3: Electroplating Cu into the TSV hole from bottom to top by electrochemical electroplating to solidify the TSV hole and form a TSV copper pillar. Step S4: Reduce the thickness of the first silicon wafer by chemical mechanical polishing and expose part of the TSV copper pillars; Step S5: The first bonding film layer, the buffer layer and the second bonding film layer are sequentially prepared in the bonding area by electrochemical electroplating to obtain the lower layer adapter plate; Step S6: A deep cavity is etched on the second silicon wafer by deep cavity etching; a first bonding film layer is electroplated on the deep cavity and bonding area by electrochemical electroplating to obtain the upper layer adapter plate; the non-bonded area of ​​the upper layer adapter plate is etched away, wherein the width of the non-bonded area of ​​the lower layer adapter plate is greater than the width of the non-bonded area of ​​the upper layer adapter plate, and the width of the first bonding film layer of the upper layer adapter plate is greater than the width of the second bonding film layer of the lower layer adapter plate. Step S7: The upper and lower adapter boards are bonded and packaged by flip bonding.

[0007] Another aspect of the present invention provides a dual-layer TSV adapter board packaging structure, which is prepared by the above method.

[0008] According to the above-described aspects of the dual-layer TSV adapter board packaging structure and its preparation method, not only can the heat diffusion between the bonding film layers be slowed down before packaging to maintain high packaging strength, but also the bonding film layers of the dual-layer adapter board can be in close contact during alignment and bonding, solving the problem of poor airtightness of the adapter board packaging and effectively improving the packaging yield. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort: Figure 1 A schematic diagram illustrating the fabrication of TSV holes in the lower adapter board according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the electroplating filling of TSV holes in the lower adapter plate according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the lower adapter plate being thinned and polished to expose the TSV copper pillar in an embodiment of the present invention; Figure 4 This is a schematic diagram of the electroplated bonding film layer of the lower adapter plate according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the etching of a deep cavity on the upper adapter plate according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the electroplated bonding film layer of the upper adapter plate according to an embodiment of the present invention; Figure 7 This is a side view schematic diagram of the dual-layer TSV adapter board packaging structure according to an embodiment of the present invention. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0011] The present invention provides a method for preparing a dual-layer TSV adapter board packaging structure, comprising the following steps: Step S1: Using the TSV etching method, TSV holes 7 are etched on the first silicon wafer, such as... Figure 1 As shown; Step S2: A Cu seed layer is prepared in the TSV hole 7 using magnetron sputtering. Step S3: Using electrochemical electroplating, Cu is electroplated from bottom to top inside the TSV holes to solidify the TSV holes and form TSV copper pillars 3, as shown. Figure 2 As shown; Step S4: Using chemical mechanical polishing, the thickness of the first silicon wafer is reduced, exposing part of the TSV copper pillar 3, such as... Figure 3 As shown; Step S5: Using electrochemical electroplating, a first bonding film layer 4, a buffer layer 5, and a second bonding film layer 6 are sequentially prepared in the bonding region to obtain the lower adapter plate 1, as shown below. Figure 4 As shown; Step S6, fabricating an upper-layer adapter board on the second silicon wafer, including: etching a deep cavity 8 on the silicon wafer using a deep cavity etching method, such as... Figure 5 As shown; using an electrochemical electroplating method, the first bonding film layer 4 is electroplated in the deep cavity and bonding region to obtain the upper adapter plate, as shown. Figure 6 As shown; the non-bonded areas of the upper adapter plate are etched away using a metal etching method; Step S7: Using flip-chip bonding, the upper adapter board 2 and the lower adapter board 1 are bonded and packaged to obtain the following... Figure 7 The dual-layer TSV adapter board packaging structure is shown.

[0012] The buffer layer is located between the first bonding film layer and the second bonding film layer, and the thickness of the buffer layer is A, which ranges from 0.01 to 8 μm. Both the bonding film layer and the buffer layer of the lower adapter board avoid the TSV copper pillars, and the width B of the avoidance area (the distance from the bonding area of ​​the lower adapter board to the TSV copper pillars) ranges from 1 to 60 μm.

[0013] The unbonded region of the lower adapter board includes the TSV copper pillars and the area avoided by the bonding film layer. The width of the unbonded region of the lower adapter board is greater than the width of the unbonded region of the upper adapter board, thus the width of the first bonding film layer of the upper adapter board is greater than the width of the second bonding film layer of the lower adapter board. The difference between the width C of the unbonded region of the lower adapter board and the width D of the unbonded region of the upper adapter board is E, where E = CD, and the value of E ranges from 10 to 35 μm.

[0014] The first and second bonding layers are respectively one of the Cu / Sn, Au / Sn, Au / In, Pb / Sn, In / Sn bonding layer systems. The buffer layer is made of one or more of Ti, Ni, W, Ta, TaN, and TiN. The height of the TSV copper pillar exposed above the surface of the first silicon wafer is H, and the value of H ranges from 0.1 to 5 μm.

[0015] In one specific embodiment, the method for preparing the dual-layer TSV adapter board packaging structure of the present invention includes the following steps: Step S1: Take a silicon wafer (first silicon wafer) and use deep reactive ion etching technology to etch TSV deep holes on the silicon wafer. The depth of the TSV holes is 200~400μm.

[0016] In step S2, an insulating layer with a thickness of 1-4 μm is prepared on the silicon wafer surface and the inner wall of the TSV deep hole using thermal oxidation technology. A seed layer of Cu is then sputtered onto the surface of the insulating layer using magnetron sputtering technology.

[0017] Step S3: Using electrochemical electroplating technology, copper is electroplated on the silicon wafer surface and inside the TSV holes. The deep TSV holes need to be electroplated from bottom to top, and the copper needs to fill the TSV holes completely.

[0018] Step S4: Chemical mechanical polishing (CMP) is used to remove the copper from the silicon wafer surface and expose the TSV copper pillars. The height of the TSV copper pillars exposed on the silicon wafer surface is 0.1~5μm.

[0019] Step S5: Using electrochemical electroplating technology, the first bonding film layer, the buffer layer, and the second bonding film layer are sequentially electroplated on the packaging area of ​​the silicon wafer surface, thereby obtaining the lower layer adapter board packaging structure.

[0020] Step S6: Take another silicon wafer (second silicon wafer), use deep reactive ion etching technology to etch a deep cavity on the silicon wafer, the cavity depth is 300~500μm; use electrochemical electroplating technology to electroplat the first bonding film layer on the packaging area on the surface of the silicon wafer; use metal etching method to etch away the non-bonded area of ​​the upper transition board, thereby obtaining the upper transition board packaging structure.

[0021] Step S7: Using flip-chip bonding, the upper and lower adapter boards are bonded and packaged.

[0022] In summary, the fabrication method of the dual-layer TSV adapter plate packaging structure according to the embodiments of the present invention firstly fabricates TSV copper pillars on a silicon wafer; then thins the silicon wafer to expose a portion of the TSV copper pillars; next, a first bonding film layer, a buffer layer, and a second bonding film layer are sequentially fabricated in the packaging area to obtain the lower adapter plate; a deep cavity is etched on another silicon wafer, and then the first bonding film layer is fabricated to obtain the upper adapter plate.

[0023] The method for preparing the dual-layer TSV adapter board packaging structure according to the embodiments of the present invention has the following beneficial effects: 1. In this invention, a buffer layer is provided between the first and second bonding film layers of the lower adapter plate. When the adapter plate is subjected to high temperature, the buffer layer can slow down the interdiffusion reaction of the two bonding film layers, so that the two bonding film layers can maintain their original state before encapsulation. By applying a higher temperature during the final bonding and encapsulation, the bonding film layers can break through the constraint of the buffer layer and achieve interdiffusion between the film layers, thus ensuring high bonding strength. 2. The present invention avoids the TSV copper pillars by using the bonding film layer and buffer layer of the lower adapter plate, so that the TSV copper pillars will not increase in height during the preparation of the bonding film layer. This ensures that the bonding film blocks of the upper and lower adapter plates can be in close contact and react fully during the bonding process, thus ensuring good airtightness. 3. By setting the width of the non-bonded area of ​​the lower adapter plate to be greater than the width of the non-bonded area of ​​the upper adapter plate, the width of the upper first bonded film layer is greater than the width of the lower second bonded film layer. This allows the second bonded film layer to react fully. Furthermore, the upper adapter plate also has a non-bonded area, so that when the second bonded film layer is consumed by the reaction, the upper adapter plate will not touch the TSV copper pillar, preventing the TSV copper pillar from pushing up the upper adapter plate and ensuring complete reaction, thereby further improving sealing performance and sealing yield.

[0024] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a double-layer TSV adapter board packaging structure, characterized in that, include: Step S1: TSV holes are etched on the first silicon wafer. Step S2: A Cu seed layer is prepared in the TSV pores by magnetron sputtering; Step S3: Electroplating Cu into the TSV hole from bottom to top by electrochemical electroplating to solidify the TSV hole and form a TSV copper pillar. Step S4: Reduce the thickness of the first silicon wafer by chemical mechanical polishing and expose part of the TSV copper pillars; Step S5: The first bonding film layer, the buffer layer and the second bonding film layer are sequentially prepared in the bonding area by electrochemical electroplating to obtain the lower layer adapter plate; Step S6: A deep cavity is etched on the second silicon wafer by deep cavity etching; a first bonding film layer is electroplated on the deep cavity and bonding area by electrochemical electroplating to obtain the upper layer adapter plate; the non-bonded area of ​​the upper layer adapter plate is etched away, wherein the width of the non-bonded area of ​​the lower layer adapter plate is greater than the width of the non-bonded area of ​​the upper layer adapter plate, and the width of the first bonding film layer of the upper layer adapter plate is greater than the width of the second bonding film layer of the lower layer adapter plate. Step S7: The upper and lower adapter boards are bonded and packaged by flip bonding.

2. The method according to claim 1, characterized in that, The buffer layer is located between the first bonding film layer and the second bonding film layer, and the thickness of the buffer layer is 0.01~8μm.

3. The method according to claim 1 or 2, characterized in that, The first bonding film layer, buffer layer and second bonding film layer of the lower adapter board all avoid the TSV copper pillars, and the width of the avoidance area is 1~60μm.

4. The method according to claim 3, characterized in that, The non-bonded area of ​​the lower adapter board includes TSV copper pillars and a avoidance area. The difference between the width of the non-bonded area of ​​the lower adapter board and the width of the non-bonded area of ​​the upper adapter board is 10~35μm.

5. The method according to claim 1 or 2, characterized in that, The first bonded film layer and the second bonded film layer are respectively one of Cu / Sn, Au / Sn, Au / In, Pb / Sn and In / Sn.

6. The method according to claim 1 or 2, characterized in that, The material of the buffer layer is one or more of Ti, Ni, W, Ta, TaN, and TiN.

7. The method according to claim 1 or 2, characterized in that, The height of the TSV copper pillar exposed above the surface of the first silicon wafer is 0.1~5μm.

8. The method according to claim 1 or 2, characterized in that, The depth of the TSV holes is 200~400μm, and the thickness of the insulating layer is 1~4μm.

9. The method according to claim 1 or 2, characterized in that, In step S3, copper is electroplated on the surface of the first silicon wafer and inside the TSV holes using electrochemical electroplating technology; in step S4, copper is removed from the surface of the first silicon wafer by chemical mechanical polishing technology, exposing the TSV copper pillars.

10. A dual-layer TSV adapter board packaging structure, characterized in that, It is prepared by the method according to any one of claims 1-9.

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