Power module packaging structure based on double-sided cooling and full-symmetric layout

Abstract

The invention relates to a power module packaging structure based on double-sided cooling and full-symmetric layout. The double-sided cooling packaging structure solves the problem that a double-sided cooling packaging structure in the prior art cannot cooperatively realize low parasitic inductance, efficient and uniform heat dissipation and high mechanical reliability. The power module comprises a power module body, an upper substrate and a lower substrate are arranged on the upper side and the lower side of the power module body respectively, upper bridge arm power chip sets are arranged at the four corners of the upper substrate and the lower substrate in the circumferential direction, lower bridge arm power chip sets are arranged between the upper bridge arm power chip sets, and DC terminals and AC terminals are arranged on the upper substrate and the lower substrate in the circumferential direction. A plurality of module vertical interconnection copper columns are arranged between the upper layer substrate and the lower layer substrate, and an upper substrate bridging copper bridge is arranged between the upper layer substrate and the lower layer substrate. The power module has the advantages that the overall reliability and the switching performance of the module are improved, the switching loss is reduced, the parasitic inductance of the direct-current bus side is effectively reduced, the fatigue failure of the solder layer is delayed, and the thermal cycle life of the power module is prolonged.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and more specifically to a power module packaging structure based on double-sided cooling and a fully symmetrical layout. Background Technology

[0002] As power electronic devices evolve towards higher power density and higher integration, effective thermal management and electrical performance have become crucial for improving system reliability. Double-sided cooling packaging technology, by simultaneously dissipating heat on both the top and bottom surfaces of the chip and utilizing planar interconnects instead of traditional wire bonding, demonstrates significant advantages in reducing module thermal resistance and parasitic inductance, and improving current capability.

[0003] However, existing double-sided cooling structures still have significant limitations in terms of synergistic performance optimization: In terms of electrical performance, existing designs struggle to balance low parasitic inductance with current sharing among chips. Some structures, while reducing loop inductance, introduce uneven parasitic inductance across branches, leading to current imbalance in parallel chips; while overly complex layouts introduce new parasitic parameters, which in turn limit switching performance.

[0004] In terms of thermal management performance, internal interconnects and material stacking are prone to thermal coupling, which not only leads to excessively high chip surface temperatures but also makes it easier to generate local hot spots. Hot spots significantly accelerate chip performance degradation and the aging and failure of packaging materials, posing a primary threat to system reliability. Furthermore, existing research mostly focuses on material selection and generally lacks analysis and optimization of the thermal-mechanical coupling mechanism of material layers under process feasibility constraints, making it difficult to achieve optimal performance.

[0005] In summary, existing technologies cannot simultaneously achieve the goals of low parasitic inductance, efficient and uniform heat dissipation, and high mechanical reliability. Their structures often compromise on one aspect while neglecting another, resulting in complex designs or a lack of systematic optimization, which restricts further improvements in the overall performance and reliability of the module. Therefore, it is crucial to provide a novel bifacially cooled power module that can simultaneously achieve excellent electrical performance, thermal management efficiency, and reliability. Summary of the Invention

[0006] The purpose of this invention is to address the above-mentioned problems by providing a power module packaging structure based on double-sided cooling and a fully symmetrical layout.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a power module packaging structure based on double-sided cooling and a fully symmetrical layout, comprising a power module body, an upper substrate and a lower substrate respectively disposed on the upper and lower sides of the power module body, upper bridge arm power chip groups disposed at the four corners of the upper and lower substrates, and lower bridge arm power chip groups disposed between the upper bridge arm power chip groups, and DC terminals and AC terminals symmetrically arranged in the circumferential direction of the upper and lower substrates, a plurality of module vertical interconnection copper pillars disposed between the upper and lower substrates, and an upper substrate bridging copper bridge for connecting the upper substrate first wiring area and the upper substrate third wiring area of ​​the upper substrate disposed between the upper and lower substrates.

[0008] In the power module packaging structure based on double-sided cooling and fully symmetrical layout described above, an upper Cu layer is provided on the upper substrate, and a lower Cu layer is provided on the lower substrate.

[0009] In the power module packaging structure based on double-sided cooling and fully symmetrical layout described above, the upper substrate has a first wiring area, a second wiring area, and a third wiring area on the lower Cu layer.

[0010] In the power module packaging structure based on double-sided cooling and fully symmetrical layout described above, the upper surface of the lower substrate is provided with an upper Cu layer, and the lower surface of the lower substrate is provided with a lower Cu layer.

[0011] In the power module packaging structure based on double-sided cooling and fully symmetrical layout described above, the CU layer on the lower substrate has a first wiring area, a second wiring area, and a third wiring area.

[0012] In the aforementioned power module packaging structure based on double-sided cooling and a fully symmetrical layout, the DC terminals include a first DC- terminal disposed on one side of the outer wall of the upper substrate and connected to the first wiring area of ​​the upper substrate, and a second DC- terminal disposed on the other side of the outer wall of the upper substrate in a left-right symmetrical arrangement with the first DC- terminal, the second DC- terminal being connected to the third wiring area of ​​the upper substrate; a first DC+ terminal disposed on one side of the outer wall of the lower substrate and connected to the first wiring area of ​​the lower substrate, and a second DC+ terminal disposed on one side of the outer wall of the lower substrate and connected to the first wiring area of ​​the lower substrate, the first DC- terminal and the first DC+ terminal being vertically symmetrically arranged, the second DC- terminal and the second DC+ terminal being vertically symmetrically arranged.

[0013] In the power module packaging structure based on double-sided cooling and fully symmetrical layout described above, the AC terminal includes a first AC output terminal disposed at one end of the lower Cu layer of the upper substrate and connected to the second wiring area of ​​the upper substrate, and a second AC output terminal disposed at the other end of the lower Cu layer of the upper substrate and connected to the second wiring area of ​​the upper substrate and symmetrically disposed with the first AC output terminal.

[0014] In the power module packaging structure based on double-sided cooling and fully symmetrical layout described above, the upper bridge arm power chip group includes an upper bridge arm first solder layer located at the bottom. The upper end of the upper bridge arm first solder layer is sequentially provided with an upper bridge arm first buffer layer, an upper bridge arm second solder layer, an upper bridge arm MOSFET chip, an upper bridge arm third solder layer, an upper bridge arm second buffer layer, and an upper bridge arm fourth solder layer. The upper bridge arm first solder layer is connected to the upper CU layer of the lower substrate, and the upper bridge arm fourth solder layer is connected to the lower Cu layer of the upper substrate.

[0015] In the aforementioned power module packaging structure based on double-sided cooling and a fully symmetrical layout, the lower bridge arm power chip group includes a first solder layer disposed on the lower bridge arm, a first buffer layer, a second solder layer, a MOSFET chip, a third solder layer, a second buffer layer, and a fourth solder layer disposed at the lower end of the first solder layer. The first solder layer is connected to the lower Cu layer of the upper substrate, and the fourth solder layer is connected to the upper Cu layer of the lower substrate.

[0016] In the power module packaging structure based on double-sided cooling and fully symmetrical layout described above, the two ends of the upper substrate bridging copper bridge are electrically connected to the first wiring area and the third wiring area of ​​the upper substrate, respectively; the module vertical interconnect copper pillar is vertically electrically connected to the first wiring area of ​​the upper substrate and the second wiring area or the third wiring area of ​​the lower substrate; or, the module vertical interconnect copper pillar is vertically electrically connected to the third wiring area of ​​the upper substrate and the third wiring area or the second wiring area of ​​the lower substrate.

[0017] Compared with existing technologies, the advantages of this solution are: 1. Fully Symmetrical Parallel Layout and Parameter Matching: The physical layout exhibits strict geometric central symmetry. Specifically, the upper bridge arm MOSFET chips, connected between the DC positive terminal (DC+) and the AC output terminal (AC), are distributed in the corner areas of the module, while the lower bridge arm MOSFET chips, connected between the AC output terminal (AC) and the DC negative terminal (DC-), are centrally located in the module's center. This layout ensures that all parallel upper and lower bridge arm branches have highly symmetrical current paths in physical space, guaranteeing a natural match between the parasitic inductance and resistance of each branch. This fundamentally suppresses dynamic and static current sharing problems caused by parameter mismatch, effectively reduces thermal coupling between branches, and ultimately achieves a balanced distribution of chip junction temperature, improving the overall reliability of the module.

[0018] 2. Flux Cancellation Design for Power Circuit Inductors: By optimizing the direction and spatial relationship of adjacent current paths, the magnetic flux generated by currents flowing through different circuits is made to be opposite in direction, forming a significant negative mutual inductance effect in the inductor matrix. This flux cancellation mechanism can significantly reduce the equivalent series parasitic inductance of the power circuit, thereby suppressing voltage overshoot and ringing during switching, improving switching performance, and reducing switching losses.

[0019] 3. Low inductance design of DC terminals: The positive and negative DC power supply terminals are arranged in close parallel, and a two-terminal configuration is preferred. This design utilizes the mutual cancellation of the magnetic fields generated by the reverse current between adjacent terminals to effectively reduce the parasitic inductance on the DC bus side.

[0020] 4. Chip Dual-Side Stress Buffer Design: Molybdenum (Mo) buffer layers are set on both the top and bottom sides of each power chip. This dual-side buffer structure is used to effectively absorb and buffer the mechanical stress generated during thermal cycling due to the huge thermal expansion coefficient (CTE) mismatch between the chip, such as SiC, and the directly bonded copper (DBC) layer. This significantly reduces the plastic strain of the solder layer, thereby delaying solder layer fatigue failure and extending the thermal cycle life of the power module. Attached Figure Description

[0021] Figure 1 This is a three-dimensional perspective view of the present invention; Figure 2 This is a top view of the present invention; Figure 3 This is a front view of the present invention; Figure 4 This is a schematic diagram of the upper substrate and lower Cu layer structure in this invention; Figure 5 This is a schematic diagram of the Cu layer structure on the lower substrate in this invention; Figure 6 This is an enlarged view of the upper bridge arm power chipset and lower bridge arm power chipset structure in this invention; Figure 7 This is a schematic cross-sectional view of a partial structure in this invention; Figure 8 This invention demonstrates the current path and flow direction diagram of the magnetic flux cancellation effect; Figure 9 This is a temperature distribution curve of the substrate surface along a specific measurement path of the power module body under double-sided cooling conditions in this invention. Figure 10 This is a comparison diagram of the plastic strain of each solder layer under thermal cycling for the double-sided and single-sided buffer layers in this invention. In the figure: power module body 100, upper substrate 11, lower substrate 12, upper Cu layer 21 on the upper substrate, lower Cu layer 22 on the upper substrate, first wiring area 22a on the upper substrate, second wiring area 22b on the upper substrate, third wiring area 22c on the upper substrate, upper Cu layer 23 on the lower substrate, first wiring area 23a on the lower substrate, second wiring area 23b on the lower substrate, third wiring area 23c on the lower substrate, lower Cu layer 24 on the lower substrate, first DC- terminal 31a, second DC- terminal 31b, first DC+ terminal 32a, second DC+ terminal 32b, first AC output terminal 33a, second AC output terminal 33b, Upper bridge arm power chipset 40, First solder layer 41, Upper bridge arm first buffer layer 42, Upper bridge arm second solder layer 43, Upper bridge arm MOSFET chip 44, Upper bridge arm third solder layer 45, Upper bridge arm second buffer layer 46, Upper bridge arm fourth solder layer 47, Lower bridge arm power chipset 50, Lower bridge arm first solder layer 51, Lower bridge arm first buffer layer 52, Lower bridge arm second solder layer 53, Lower bridge arm MOSFET chip 54, Lower bridge arm third solder layer 55, Lower bridge arm second buffer layer 56, Lower bridge arm fourth solder layer 57, Upper substrate bridging copper bridge 61, Module vertical interconnect copper pillar 62. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0023] like Figure 1-10 As shown, the power module packaging structure based on double-sided cooling and a fully symmetrical layout includes a power module body 100. An upper substrate 11 and a lower substrate 12 are respectively arranged on the upper and lower sides of the power module body 100. Upper bridge arm power chip groups 40 are arranged at the four corners of the upper substrate 11 and the lower substrate 12, and a lower bridge arm power chip group 50 is arranged between the upper bridge arm power chip groups 40. DC terminals and AC terminals are symmetrically arranged on the upper substrate 11 and the lower substrate 12. Several module vertical interconnection copper pillars 62 are arranged between the upper substrate 11 and the lower substrate 12. An upper substrate bridging copper bridge 61 for connecting the upper substrate first wiring area 22a and the upper substrate third wiring area 22c of the upper substrate 11 is arranged between the upper substrate 11 and the lower substrate 12.

[0024] The upper bridge power chipset 40 is distributed at the four corners, while the lower bridge power chipset 50 is concentrated in the center. Each input and output port consists of two symmetrically distributed DC and AC terminals. This parallel terminal configuration helps to reduce the parasitic inductance of the terminals. The module adopts a double-sided cooling design, with an upper substrate (11) and a lower substrate (12), which significantly increases and optimizes the heat dissipation area and heat dissipation path of the power module.

[0025] like Figure 2As shown, this package structure is 45mm long and 34mm wide, which is smaller than the area of ​​traditional power modules on the market, and has a higher power density under the same operating conditions.

[0026] It should be noted that this structure primarily focuses on optimizing the power circuit and heat dissipation layout to improve current sharing and temperature balance in parallel power modules. Therefore, detailed modeling of the chip's gate control structure is not performed; only the source-drain conduction condition of the power circuit is discussed. This structure, through a fully symmetrical layout, double-sided cooling, and staggered chip arrangement, collaboratively solves problems such as poor current sharing, thermal imbalance, large parasitic inductance, and low heat dissipation efficiency in traditional modules.

[0027] The upper substrate 11 has an upper Cu layer 21 and a lower Cu layer 22.

[0028] The upper Cu layer 21 on the upper substrate is a heat dissipation layer for heat dissipation; the lower Cu layer 22 on the upper substrate is a wiring layer for wiring.

[0029] Furthermore, the lower Cu layer 22 of the upper substrate has a first wiring region 22a, a second wiring region 22b, and a third wiring region 22c, respectively.

[0030] The first wiring area 22a of the upper substrate is used to connect the first DC-terminal 31a, the second wiring area 22b of the upper substrate is used to connect the first AC output terminal 33a and the second AC output terminal 33b, and the third wiring area 22c of the upper substrate is used to connect the second DC-terminal 31b.

[0031] Specifically, the upper surface of the lower substrate 12 is provided with an upper Cu layer 23, and the lower surface of the lower substrate 12 is provided with a lower Cu layer 24.

[0032] The upper Cu layer 23 on the lower substrate is a wiring layer used for arranging circuits, and the lower Cu layer 24 on the lower substrate is a heat dissipation layer used for heat dissipation.

[0033] Furthermore, the CU layer 23 on the lower substrate has a first wiring region 23a, a second wiring region 23b, and a third wiring region 23c.

[0034] The first wiring area 23a of the lower substrate is connected to the first DC+ terminal 32a and the second DC+ terminal 32b respectively, and the second wiring area 23b and the third wiring area 23c of the lower substrate are connected to the module vertical interconnect copper pillars 62 respectively.

[0035] More specifically, the DC terminals include a first DC-terminal 31a disposed on one side of the outer wall of the upper substrate 11 and connected to the first wiring area 22a of the upper substrate, and a second DC-terminal 31b disposed on the other side of the outer wall of the upper substrate 11 and symmetrically disposed with respect to the first DC-terminal 31a. The second DC-terminal 31b is connected to the third wiring area 22c of the upper substrate. A first DC+ terminal 32a disposed on one side of the outer wall of the lower substrate and connected to the first wiring area 23a of the lower substrate, and a second DC+ terminal 32b disposed on one side of the outer wall of the lower substrate 12 and connected to the first wiring area 23a of the lower substrate. The first DC-terminal 31a and the first DC+ terminal 32a are symmetrically disposed vertically, and the second DC-terminal 31b and the second DC+ terminal 32b are symmetrically disposed vertically.

[0036] In detail, the AC terminal includes a first AC output terminal 33a disposed at one end of the lower Cu layer 22 of the upper substrate and connected to the second wiring area 22b of the upper substrate, and a second AC output terminal 33b disposed at the other end of the lower Cu layer 22 of the upper substrate and connected to the second wiring area 22b of the upper substrate and symmetrically disposed with the first AC output terminal 33a.

[0037] Current flows in from the DC positive terminal (first DC+ terminal 32a, second DC+ terminal 32b), flows through the power chipset 40 which serves as the upper bridge arm, and then flows out from the AC output terminal (first AC output terminal 33a, second AC output terminal 33b). It then flows through the power chipset 50 which serves as the lower bridge arm, and finally flows out from the DC negative terminal (first DC- terminal 31a, second DC- terminal 31b).

[0038] Preferably, the upper bridge arm power chipset 40 includes an upper bridge arm first solder layer 41 located at the bottom. The upper end of the upper bridge arm first solder layer 41 is sequentially provided with an upper bridge arm first buffer layer 42, an upper bridge arm second solder layer 43, an upper bridge arm MOSFET chip 44, an upper bridge arm third solder layer 45, an upper bridge arm second buffer layer 46, and an upper bridge arm fourth solder layer 47. The upper bridge arm first solder layer 41 is connected to the upper Cu layer 23 of the lower substrate, and the upper bridge arm fourth solder layer 47 is connected to the lower Cu layer 22 of the upper substrate.

[0039] As can be seen, the lower bridge arm power chip group 50 includes a first solder layer 51 disposed on the lower bridge arm. A first buffer layer 52, a second solder layer 53, a MOSFET chip 54, a third solder layer 55, a second buffer layer 56, and a fourth solder layer 57 are disposed at the lower end of the first solder layer 51. The first solder layer 51 is connected to the lower Cu layer 22 of the upper substrate, and the fourth solder layer 57 is connected to the upper Cu layer 23 of the lower substrate.

[0040] After the current flows in from the DC+ port, it first passes through the first wiring area 23a of the CU layer 23 on the lower substrate, and then sequentially passes through the first solder layer 41, the first buffer layer 42, the second solder layer 43, the MOSFET chip 44, the third solder layer 45, the second buffer layer 46, and the fourth solder layer 47 of the upper bridge arm, reaching the second wiring area 22b of the lower Cu layer 22 on the upper substrate. After that, it flows sequentially through the first solder layer 51, the first buffer layer 52, the second solder layer 53, the MOSFET chip 54, the third solder layer 55, the second buffer layer 56, and the fourth solder layer 57 of the lower power chip group 50, reaching the second wiring area 23b or the third wiring area 23c of the CU layer 23 on the lower substrate.

[0041] In addition, the two ends of the upper substrate bridging copper bridge 61 are electrically connected to the first wiring area 22a and the third wiring area 22c of the upper substrate, respectively; the module vertical interconnect copper pillar 62 is vertically electrically connected to the first wiring area 22a of the upper substrate and the second wiring area 23b or the third wiring area 23c of the lower substrate; or, the module vertical interconnect copper pillar 62 is vertically electrically connected to the third wiring area 22c of the upper substrate and the third wiring area 23c or the second wiring area 23b of the lower substrate.

[0042] The module vertical interconnect copper pillar 62 realizes the vertical electrical connection between the second wiring area 23b or the third wiring area 23c of the CU layer 23 on the lower substrate and the first wiring area 22a or the third wiring area 22c of the Cu layer 21 on the upper substrate.

[0043] There are four such vertical interconnect copper pillars 62, which constitute the key vertical channels of the three-dimensional current path inside the power module body 100.

[0044] Four modules vertically interconnected copper pillars 62 are located in Figure 4 Below the upper substrate first wiring region 22a and upper substrate third wiring region 22c of the upper substrate lower Cu layer 22, there is a connection between the upper substrate first wiring region 22a and upper substrate third wiring region 22c of the upper substrate lower Cu layer 22 and the lower substrate second wiring region 23b and lower substrate third wiring region 23c of the lower substrate upper Cu layer 23, and finally the current flows out from the first DC-terminal 31a and the second DC-terminal 31b.

[0045] The upper substrate bridging copper bridge 61 is located below the lower Cu layer 22 of the upper substrate and is used to connect the first wiring area 22a of the lower Cu layer 22 of the upper substrate and the third wiring area 22c of the upper substrate.

[0046] Figure 8The figure shows the current flow process when a half-bridge unit is turned on. As can be seen from the figure, there are multiple opposite paths for the current flow. These opposite current paths provide negative coupling inductance, which helps to reduce the overall parasitic inductance.

[0047] Parasitic inductance simulation of a half-bridge unit of the design module was performed using 3D electromagnetic simulation software. The simulation results are shown in Table 1 below. In Table 1, L_D refers to the parasitic inductance from the DC+ terminal to the upper bridge arm MOSFET chip 44, L_O refers to the parasitic inductance at both ends of the AC port, and L_s refers to the parasitic inductance from the lower bridge arm MOSFET chip 54 to the DC- port.

[0048] The results show that multiple negative coupling paths exist in the power module circuit, such as the obvious negative mutual inductance terms in the inductance matrix, like those between D–S and O–S, demonstrating the flux cancellation effect between current paths. This multi-point distributed negative coupling significantly reduces the equivalent parasitic inductance of a single half-bridge, which helps suppress voltage spikes, improve the module's switching performance, and enhance the system's electromagnetic compatibility.

[0049] Table 1. Parasitic inductance matrix of a single half-bridge: Inductor nH 100MHZ [[ L D ]]> [[ L O ]]> [[ L S ]]> total [[ L D ]]> 0.66 0.04 -0.36 0.34 [[ L O ]]> 0.04 1.58 -1.08 0.54 [[ L S ]]> -0.36 -1.08 5.61 4.17 The "Total" column in Table 1 (0.34nH, 0.54nH, 4.17nH) represents the equivalent series parasitic inductance of each branch (LD, LO, LS) at a frequency of 100MHz, after considering mutual inductance coupling with other branches. Therefore, the total equivalent parasitic inductance of the power circuit of this half-bridge unit is the sum of the equivalent inductances of each branch, that is: ; Therefore, the total parasitic inductance of the four-and-a-half-bridge module is: ; However, due to the positive coupling between the four half-bridge modules, the total parasitic inductance of the four half-bridge modules obtained from the actual simulation is 1.47nH, which is still at an extremely low level, proving the effectiveness of the design.

[0050] The DC positive and negative power supply terminals of the structure are arranged in a closely parallel manner, and preferably in a two-terminal configuration, such as... Figure 3 As shown, 31a and 31b are DC- terminals, and 32a and 32b are DC+ terminals. This design utilizes the mutual cancellation of the magnetic fields generated by the reverse current between adjacent terminals, effectively reducing the parasitic inductance on the DC bus side. Simultaneously, this design preferentially uses a two-terminal configuration, extending one terminal to form a parallel loop, effectively reducing the overall circuit parasitic inductance. According to electromagnetic simulation software, the total parasitic inductance of the two-terminal power module structure is 1.99nH, while the parasitic inductance of the single-terminal power module is as high as 3.83nH, twice that of the two-terminal structure, proving that the parallel terminals effectively reduce the total parasitic inductance.

[0051] Thermal simulation was performed to evaluate the double-sided heat dissipation performance of the module. The simulation was set with a power consumption of 50W per chip and enhanced cooling conditions based on a double-sided liquid cooler. The convective heat transfer coefficients of both the upper and lower substrate surfaces were set to 5000W / (m²•K). Figure 9 The temperature distribution curves shown indicate that the temperature distribution between each upper bridge arm chip and between each lower bridge arm chip is highly consistent, successfully improving the local overheating problem caused by thermal coupling through symmetrical layout.

[0052] In terms of mechanical reliability, such as Figure 10 As shown, the viscoplastic strain of double-sided and single-sided buffer layer structures under the same thermal cycling conditions was compared. The results show that the double-sided molybdenum (Mo) buffer layer structure can better absorb the stress caused by the thermal expansion mismatch between the SiC chip and the Cu layer, significantly reducing the plastic strain of the solder layer, thereby improving the reliability and service life of the solder layer.

Claims

1. A power module packaging structure based on double-sided cooling and a fully symmetrical layout, comprising a power module body (100), wherein an upper substrate (11) and a lower substrate (12) are respectively disposed on the upper and lower sides of the power module body (100), characterized in that, The upper substrate (11) and the lower substrate (12) are provided with upper bridge arm power chip groups (40) at the four corners of the circumference, and lower bridge arm power chip groups (50) are provided between the upper bridge arm power chip groups (40). The upper substrate (11) and the lower substrate (12) are provided with DC terminals and AC terminals arranged symmetrically in the circumference. A number of module vertical interconnect copper pillars (62) are provided between the upper substrate (11) and the lower substrate (12). The upper substrate (11) and the lower substrate (12) are provided with an upper substrate bridging copper bridge (61) for connecting the upper substrate first wiring area (22a) and the upper substrate third wiring area (22c) of the upper substrate (11).

2. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 1, characterized in that, The upper substrate (11) is provided with an upper Cu layer (21) and the lower substrate (11) is provided with a lower Cu layer (22).

3. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 2, characterized in that, The upper substrate lower Cu layer (22) has an upper substrate first wiring region (22a), an upper substrate second wiring region (22b) and an upper substrate third wiring region (22c).

4. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 4, characterized in that, The lower substrate (12) has an upper Cu layer (23) on its upper surface and a lower Cu layer (24) on its lower surface.

5. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 4, characterized in that, The CU layer (23) on the lower substrate has a first wiring region (23a), a second wiring region (23b), and a third wiring region (23c).

6. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 5, characterized in that, The DC terminals include a first DC-terminal (31a) disposed on one side of the outer wall of the upper substrate (11) and connected to the first wiring area (22a) of the upper substrate; a second DC-terminal (31b) disposed on the other side of the outer wall of the upper substrate (11) and arranged symmetrically with respect to the first DC-terminal (31a); the second DC-terminal (31b) is connected to the third wiring area (22c) of the upper substrate; a first DC+ terminal (32a) disposed on one side of the outer wall of the lower substrate (12) and connected to the first wiring area (23a) of the lower substrate; a second DC+ terminal (32b) disposed on one side of the outer wall of the lower substrate (12) and connected to the first wiring area (23a) of the lower substrate; the first DC-terminal (31a) and the first DC+ terminal (32a) are arranged symmetrically with respect to each other; the second DC-terminal (31b) and the second DC+ terminal (32b) are arranged symmetrically with respect to each other.

7. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 6, characterized in that, The AC terminal includes a first AC output terminal (33a) disposed at one end of the lower Cu layer (22) of the upper substrate and connected to the second wiring area (22b) of the upper substrate, and a second AC output terminal (33b) disposed at the other end of the lower Cu layer (22) of the upper substrate and connected to the second wiring area (22b) of the upper substrate and symmetrically disposed with the first AC output terminal (33a).

8. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 4, characterized in that, The upper bridge power chip group (40) includes an upper bridge first solder layer (41) located at the bottom. The upper bridge first solder layer (41) is provided with an upper bridge first buffer layer (42), an upper bridge second solder layer (43), an upper bridge MOSFET chip (44), an upper bridge third solder layer (45), an upper bridge second buffer layer (46), and an upper bridge fourth solder layer (47) in sequence. The upper bridge first solder layer (41) is connected to the upper CU layer (23) of the lower substrate, and the upper bridge fourth solder layer (47) is connected to the lower Cu layer (22) of the upper substrate.

9. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 8, characterized in that, The lower arm power chip assembly (50) includes a first solder layer (51) disposed on the lower arm. The lower end of the first solder layer (51) of the lower arm is provided with a first buffer layer (52), a second solder layer (53), a MOSFET chip (54), a third solder layer (55), a second buffer layer (56), and a fourth solder layer (57). The first solder layer (51) of the lower arm is connected to the lower Cu layer (22) of the upper substrate, and the fourth solder layer (57) of the lower arm is connected to the upper Cu layer (23) of the lower substrate.

10. The power module packaging structure based on double-sided cooling and fully symmetrical layout according to claim 8, characterized in that, The upper substrate bridging copper bridge (61) is electrically connected at both ends to the upper substrate first wiring area (22a) and the upper substrate third wiring area (22c); the module vertical interconnect copper pillar (62) is vertically electrically connected to the upper substrate first wiring area (22a) and the lower substrate second wiring area (23b) or the lower substrate third wiring area (23c); or, the module vertical interconnect copper pillar (62) is vertically electrically connected to the upper substrate third wiring area (22c) and the lower substrate third wiring area (23c) or the lower substrate second wiring area (23b).

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