Substrate structure and manufacturing method thereof

Abstract

The invention provides a substrate structure and a manufacturing method thereof. The substrate structure comprises a core substrate, a sputtering metal layer, an electroless plating metal layer and a conductive material layer. The core substrate is provided with an upper surface, a lower surface and at least one through hole penetrating from the upper surface to the lower surface. The sputtering metal layer is arranged on the upper surface and the lower surface of the core substrate and a part of the inner wall of the at least one through hole. The electroless plating metal layer is arranged on the sputtering metal layer and the remaining part of the inner wall of the at least one through hole. The conductive material layer is disposed on the electroless metal layer and fills the at least one through hole. At least one first conductive circuit located on the upper surface, at least one second conductive circuit located on the lower surface and at least one conductive through hole located in the at least one through hole and electrically connected with the at least one first conductive circuit and the at least one second conductive circuit are defined.

Description

Technical Field

[0001] This invention relates to a substrate structure and its manufacturing method, and more particularly to a substrate structure and its manufacturing method that can improve structural reliability. Background Technology

[0002] Generally, due to adhesion issues between inorganic substrates and metal layers, metal layers are deposited on inorganic substrates using dry deposition methods (such as physical vapor deposition (PVD) or chemical vapor deposition (CVD)). However, dry deposition is expensive, and for blind vias and through-holes with high aspect ratios, it often suffers from insufficient step coverage, thus increasing process defects and reducing product reliability. Summary of the Invention

[0003] This invention relates to a substrate structure that has better structural reliability.

[0004] The present invention also relates to a method for manufacturing a substrate structure, for manufacturing the aforementioned substrate structure.

[0005] According to an embodiment of the present invention, the substrate structure includes a core substrate, a sputtered metal layer, an electroless metal layer, and a conductive material layer. The core substrate has an upper surface and a lower surface opposite to each other, and at least one through-hole extending from the upper surface to the lower surface. The sputtered metal layer is disposed on the upper surface, the lower surface, and a portion of the inner wall of the at least one through-hole of the core substrate. The electroless metal layer is disposed on the sputtered metal layer and on the remaining portion of the inner wall of the at least one through-hole. The conductive material layer is disposed on the electroless metal layer and fills the at least one through-hole, defining at least one first conductive circuit located on the upper surface, at least one second conductive circuit located on the lower surface, and at least one conductive via located within the at least one through-hole and electrically connecting the at least one first conductive circuit and the at least one second conductive circuit.

[0006] In the substrate structure according to an embodiment of the present invention, the substrate structure further includes an adhesion promoting layer, which directly covers the upper surface, the lower surface and the inner wall of at least one through hole of the core substrate, wherein the sputtered metal layer is located between the adhesion promoting layer and the electroplated metal layer.

[0007] In the substrate structure according to an embodiment of the present invention, the material of the adhesion promoting layer includes oxides or nitrides.

[0008] In the substrate structure according to an embodiment of the present invention, the oxides mentioned above include silicon oxide, aluminum oxide, or titanium oxide.

[0009] In the substrate structure according to an embodiment of the present invention, the nitride described above includes silicon nitride.

[0010] In the substrate structure according to an embodiment of the present invention, the thickness of the adhesion promoting layer is between 0.01 nanometers and 100 nanometers.

[0011] In the substrate structure according to an embodiment of the present invention, the core substrate described above includes an insulating substrate.

[0012] In the substrate structure according to an embodiment of the present invention, the insulating substrate described above includes an inorganic substrate.

[0013] In the substrate structure according to an embodiment of the present invention, the material of the inorganic substrate includes glass or ceramic.

[0014] In the substrate structure according to an embodiment of the present invention, the surface roughness of the core substrate is between 1 nanometer and 50 nanometers.

[0015] In the substrate structure according to an embodiment of the present invention, the thickness of the core substrate is between 50 micrometers and 1000 micrometers.

[0016] In the substrate structure according to an embodiment of the present invention, the diameter of the at least one via is between 10 micrometers and 200 micrometers.

[0017] In the substrate structure according to an embodiment of the present invention, the thickness of the electroless metal layer is less than 1 micrometer.

[0018] In the substrate structure according to an embodiment of the present invention, the material of the electroless metal layer includes nickel-phosphorus, copper, silver, or a combination of the above materials.

[0019] In the substrate structure according to an embodiment of the present invention, the material of the sputtered metal layer includes a titanium-copper alloy.

[0020] In the substrate structure according to an embodiment of the present invention, the substrate structure further includes at least one add-on structure disposed on at least one of the upper surface and the lower surface of the core substrate. The at least one add-on structure includes at least one insulating layer, at least one conductive blind via, and at least one circuit. The at least one insulating layer covers at least one of at least one first conductive circuit and at least one second conductive circuit. The at least one circuit is located on the at least one insulating layer. The at least one conductive blind via is located within the at least one insulating layer and electrically connects the at least one circuit and at least one of the at least one first conductive circuit and at least one of the at least one second conductive circuit.

[0021] According to an embodiment of the present invention, a method for fabricating a substrate structure includes the following steps: A core substrate is provided. The core substrate has an upper surface and a lower surface opposite to each other, and at least one through-hole extending from the upper surface to the lower surface. A dry process is performed on the core substrate to form a sputtered metal layer on the upper surface, the lower surface, and a portion of the inner wall of the at least one through-hole. A wet process is performed on the core substrate to form an electroless metal layer on the sputtered metal layer and the remaining portion of the inner wall of the at least one through-hole. A conductive material layer is formed on the electroless metal layer and fills the at least one through-hole, and at least one conductive via is defined within the at least one through-hole. The conductive material, the electroless metal layer, and the sputtered metal layer are patterned, and at least one first conductive circuit is defined on the upper surface of the core substrate and at least one second conductive circuit is defined on the lower surface of the core substrate, wherein the at least one conductive via electrically connects the at least one first conductive circuit and the at least one second conductive circuit.

[0022] In the method for manufacturing a substrate structure according to an embodiment of the present invention, an adhesion promotion layer is formed before the core substrate is subjected to a dry process to directly cover the upper surface, the lower surface and the inner wall of at least one through hole of the core substrate.

[0023] In the method for fabricating a substrate structure according to an embodiment of the present invention, the material of the adhesion promoting layer includes oxides or nitrides.

[0024] In the method for fabricating a substrate structure according to an embodiment of the present invention, the method further includes patterning a conductive material, an electroless metal layer, and sputtering a metal layer, and then forming at least one add-on structure on at least one of the upper surface and lower surface of the core substrate. The at least one add-on structure includes at least one insulating layer, at least one conductive blind via, and at least one circuit. The at least one insulating layer covers at least one of at least one first conductive circuit and at least one of at least one second conductive circuit. The at least one circuit is located on the at least one insulating layer. The at least one conductive blind via is located within the at least one insulating layer and electrically connects the at least one circuit and at least one of the at least one first conductive circuit and at least one of the at least one second conductive circuit.

[0025] Based on the above, in the substrate structure and manufacturing method of the present invention, a sputtered metal layer is first formed on the upper surface, lower surface and a portion of the inner wall of the through hole of the core substrate by a dry process. Then, a wet process is performed to form an electroless metal layer on the sputtered metal layer and the remaining portion of the inner wall of the through hole. This solves the problem of low step coverage faced by the prior art in the dry deposition process, and enables the substrate structure of the present invention to have better structural reliability. Attached Figure Description

[0026] Figures 1A to 1D This is a cross-sectional schematic diagram of a method for manufacturing a substrate structure according to an embodiment of the present invention;

[0027] Figure 2 This is a cross-sectional schematic diagram of a substrate structure according to an embodiment of the present invention;

[0028] Figures 3A to 3D This is a cross-sectional schematic diagram of partial steps in a method for manufacturing a substrate structure according to another embodiment of the present invention.

[0029] Figure 4 This is a cross-sectional schematic diagram of a substrate structure according to another embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures

[0031] 100a, 100b, 100c, 100d: Substrate structure;

[0032] 110: Core substrate;

[0033] 111: Upper surface;

[0034] 112: Through hole;

[0035] 113: Lower surface;

[0036] 115: Inner wall;

[0037] 120, 120': Sputtered metal layer;

[0038] 130, 130': No electroplated metal layer;

[0039] 140, 140': Conductive material layer;

[0040] 150a, 150b: Add-on structure;

[0041] 152a, 152b: Insulation layer;

[0042] 154a, 154b: Conductive blind vias;

[0043] 156a, 156b: Lines;

[0044] 160: Adhesion promoting layer;

[0045] C1, C1': First conductive circuit;

[0046] C2, C2': Second conductive circuit;

[0047] CT, CT': Conductive via;

[0048] D: Diameter;

[0049] P: part;

[0050] R: Remaining portion;

[0051] T1, T2: Thickness. Detailed Implementation

[0052] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0053] The embodiments of the present invention can be understood in conjunction with the accompanying drawings, which are also considered part of the disclosure. It should be understood that the drawings of the present invention are not drawn to scale; in fact, the dimensions of the components may be arbitrarily enlarged or reduced to clearly illustrate the features of the present invention.

[0054] Figures 1A to 1D This is a cross-sectional schematic diagram of a method for manufacturing a substrate structure according to an embodiment of the present invention. Regarding the method for manufacturing the substrate structure according to this embodiment, please first refer to... Figure 1A A core substrate 110 is provided. The core substrate 110 has an upper surface 111 and a lower surface 113 opposite to each other, and at least one through-hole (two through-holes 112 are schematically shown) extending from the upper surface 111 to the lower surface 113. In one embodiment, the core substrate 110 is, for example, an insulating substrate. In one embodiment, the aforementioned insulating substrate may be, for example, an inorganic substrate, and the material of the inorganic substrate may be, for example, glass or ceramic, but is not limited thereto. In this embodiment, the surface roughness (e.g., Sa) of the core substrate 110 is, for example, between 1 nanometer and 50 nanometers. Preferably, the surface roughness of the core substrate 110 is less than 10 nanometers. It should be noted that Sa is the extension of Ra (arithmetic mean height of a line) to the surface, which represents the difference in height at each point compared to the arithmetic mean of the surface in absolute value, and this parameter is generally used to evaluate surface roughness. The thickness T1 of the core substrate 110 is, for example, between 50 micrometers and 1000 micrometers, preferably between 100 micrometers and 800 micrometers. In one embodiment, the via 112 may be a glass via (TGV). In one embodiment, the diameter D of the via 112 is, for example, between 10 micrometers and 200 micrometers, preferably between 100 micrometers and 200 micrometers.

[0055] Next, please refer to Figure 1B A dry process is performed on the core substrate 110 to form a sputtered metal layer 120 on the upper surface 111, the lower surface 113, the surrounding surface connecting the upper surface 111 and the lower surface 113, and a portion P of the inner wall 115 of the through hole 112. Here, the sputtered metal layer 120 only covers a portion P of the inner wall 115, while the remaining portion R of the inner wall 115 is not covered by the sputtered metal layer 120. In one embodiment, the material of the sputtered metal layer 120 is, for example, a titanium-copper alloy, but is not limited thereto.

[0056] Next, please refer to Figure 1C A wet process is performed on the core substrate 110 to form an electroless metal layer 130 on the sputtered metal layer 120 and the remaining portion R of the inner wall 115 of the through-hole 112. That is, in this embodiment, the inner wall 115 of the through-hole 112 is directly covered by the sputtered metal layer 120 and the electroless metal layer 130. The thickness T2 of the electroless metal layer 130 is, for example, less than 1 micrometer. In one embodiment, the material of the electroless metal layer 130 includes nickel-phosphorus, copper, silver, or a combination of the above materials.

[0057] Next, please refer to the following: Figure 1C and Figure 1D Using the unplated metal layer 130 as a seed layer, a conductive material layer 140 is formed on the unplated metal layer 130 by electroplating and fills the via 112. At least one conductive via is defined in the via 112 (two conductive vias CT are schematically shown).

[0058] Finally, please refer to... Figure 1D The substrate 110 comprises a patterned conductive material 140, an electroless metal layer 130, and a sputtered metal layer 120. At least one first conductive circuit (schematically showing three first conductive circuits C1) is defined on the upper surface 111 of the core substrate 110, and at least one second conductive circuit (schematically showing three second conductive circuits C2) is defined on the lower surface 113 of the core substrate 110. Conductive vias CT electrically connect the first conductive circuits C1 and the second conductive circuits C2. Thus, the fabrication of the substrate structure 100a is complete.

[0059] Structurally, please refer to [the relevant documentation / reference]. Figure 1D The substrate structure 100a of this embodiment includes a core substrate 110, a sputtered metal layer 120, an electroless metal layer 130, and a conductive material layer 140. The core substrate 110 has an upper surface 111 and a lower surface 113 opposite to each other, and a through hole 112 extending from the upper surface 111 to the lower surface 113. The sputtered metal layer 120 is disposed on the upper surface 111, the lower surface 113, and a portion P of the inner wall 115 of the through hole 112 of the core substrate 110. The electroless metal layer 130 is disposed on the sputtered metal layer 120 and the remaining portion R of the inner wall 115 of the through hole 112. A conductive material layer 140 is disposed on an electroless metal layer 130 and fills the through hole 112, thereby defining a first conductive circuit C1 located on the upper surface 111, a second conductive circuit C2 located on the lower surface 113, and a conductive through hole CT located in the through hole 112 and electrically connecting the first conductive circuit C1 and the second conductive circuit C2.

[0060] In short, this embodiment first uses a dry process to form a sputtered metal layer 120 on the upper surface 111, lower surface 113, and a portion P of the inner wall 115 of the through hole 112 on the core substrate 110. Then, a wet process is performed to form an electroless metal layer 130 on the sputtered metal layer 120 and the remaining portion R of the inner wall 115 of the through hole 112. This solves the problem of low step coverage faced by the prior art in the dry deposition process, and enables the substrate structure 100a of this embodiment to have better structural reliability.

[0061] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals representing the same or similar components, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0062] Figure 2 This is a cross-sectional schematic diagram of a substrate structure according to an embodiment of the present invention. Please also refer to... Figure 1D and Figure 2 The substrate structure 100b of this embodiment is similar to the substrate structure 100a described above, except that the main difference is that in this embodiment, after the patterned conductive material 140, the electroless metal layer 130, and the sputtered metal layer 120, at least one add-on structure (schematically showing two add-on structures 150a and 150b) is formed on at least one of the upper surface 111 and the lower surface 113 of the core substrate 110 (schematically formed on the upper surface 111 and the lower surface 113, respectively). The add-on structure 150a includes at least one insulating layer (schematically showing one insulating layer 152a), at least one conductive blind via (schematically showing two conductive blind vias 154a), and at least one circuit (schematically showing two circuits 156a). The insulating layer 152a covers the first conductive circuit C1, and the circuit 156a is located on the insulating layer 152a. The conductive blind vias 154a are located within the insulating layer 152a and electrically connect the circuit 156a and the first conductive circuit C1. Similarly, the add-on structure 150b includes at least one insulating layer (schematically shown as one insulating layer 152b), at least one conductive blind via (schematically shown as two conductive blind vias 154b), and at least one circuit (schematically shown as two circuits 156b). The insulating layer 152b covers the second conductive circuit C2, while the circuit 156b is located on the insulating layer 152b, and the conductive blind via 154b is located within the insulating layer 152b and electrically connects the circuit 156b and the second conductive circuit C2. The addition of the add-on structures 150a and 150b creates a fan-out structure, thereby increasing the applicability of the substrate structure 100b.

[0063] Figures 3A to 3CThis is a cross-sectional schematic diagram showing partial steps of a method for manufacturing a substrate structure according to another embodiment of the present invention. Please also refer to... Figure 1B and Figure 3A The fabrication method of the substrate structure 100c in this embodiment is similar to the fabrication method of the substrate structure 100a described above, except that the main difference lies in: Figure 1A After the step of providing the core substrate 110, and in Figure 1B Before the dry processing step of the core substrate 110, an adhesion promoting layer 160 is formed to directly cover the upper surface 111, lower surface 113, surrounding surface connecting the upper surface 111 and lower surface 113, and inner wall 115 of the through hole 112 of the core substrate 110. Here, the adhesion promoting layer 160 completely covers the upper surface 111, lower surface 113, surrounding surface, and inner wall 115 of the through hole 112 of the core substrate 110. In one embodiment, the material of the adhesion promoting layer 160 is, for example, an oxide or a nitride, wherein the oxide is, for example, titanium oxide (TiO2). X (such as titanium monoxide (TiO) or titanium dioxide (TiO2)), silicon dioxide (SiO) X (e.g., silicon dioxide (SiO2)) or aluminum oxide (Al2O3), while nitrides are, for example, silicon nitride (SiN). X (e.g., silicon nitride (Si3N4)). In this embodiment, the thickness T2 of the adhesion promoting layer 160 is, for example, between 0.01 nanometers and 100 nanometers, wherein the adhesion promoting layer 160 can increase the adhesion between the core substrate 110 and the subsequently formed metal layer.

[0064] Next, please refer to Figure 3B A dry process is performed on the core substrate 110 to form a sputtered metal layer 120' on the upper surface 111, the lower surface 113, and a portion P of the inner wall 115 of the through-hole 112. Here, the sputtered metal layer 120' directly covers the adhesion promoting layer 160 and only indirectly covers a portion P of the inner wall 115, while the remaining portion R of the inner wall 115 is not indirectly covered by the sputtered metal layer 120'. In one embodiment, the material of the sputtered metal layer 120' is, for example, a titanium-copper alloy, but is not limited thereto.

[0065] Next, please refer to Figure 3C A wet process is performed on the core substrate 110 to form an electroless metal layer 130' on the sputtered metal layer 120' and the remaining portion R of the inner wall 115 of the through hole 112. That is, in this embodiment, the inner wall 115 of the through hole 112 is indirectly covered by the sputtered metal layer 120' and the electroless metal layer 130'. In one embodiment, the electroless metal layer 130' is made of nickel-phosphorus, copper, silver, or a combination of the above materials.

[0066] Next, please refer to the following: Figure 3C and Figure 3D Using an electroless metal layer 130' as a seed layer, a conductive material layer 140' is formed on the electroless metal layer 130' by electroplating and fills the via 112, and at least one conductive via is defined in the via 112 (two conductive vias CT' are schematically shown).

[0067] Finally, please refer to... Figure 3D The substrate 110 comprises a patterned conductive material 140', an electroless metal layer 130', and a sputtered metal layer 120'. At least one first conductive circuit (schematically three first conductive circuits C1') is defined on the upper surface 111 of the core substrate 110, and at least one second conductive circuit (schematically three second conductive circuits C2') is defined on the lower surface 113 of the core substrate 110. Conductive vias CT' electrically connect the first conductive circuit C1' and the second conductive circuit C2'. This completes the fabrication of the substrate structure 100c.

[0068] In terms of structure, please also refer to Figure 1D as well as Figure 3D The substrate structure 100c of this embodiment is similar to the substrate structure 100a described above, except that the main difference is that in this embodiment, the substrate structure 100c further includes an adhesion promoting layer 160, which directly covers the upper surface 111, the lower surface 113, and the inner wall 115 of the through hole 112 of the core substrate 110, wherein the sputtered metal layer 120' is located between the adhesion promoting layer 160 and the electroplated metal layer 130'.

[0069] In short, this embodiment first forms an adhesion-enhancing layer 160 to increase the adhesion between the core substrate 110 and the subsequent metal layers (i.e., sputtered metal layer 120' and electroless metal layer 130'). Then, the sputtered metal layer 120' is formed sequentially through a dry process, and the electroless metal layer 130' is formed on the inner wall 115 of the via 112 through a wet process. This solves the problem of low step coverage faced by the prior art in the dry deposition process, and enables the substrate structure 100c of this embodiment to have better structural reliability.

[0070] Figure 4 This is a cross-sectional schematic diagram of a substrate structure according to another embodiment of the present invention. Please also refer to... Figure 3D and Figure 4The substrate structure 100d in this embodiment is similar to the substrate structure 100c described above, except that the main difference is that in this embodiment, after patterning the conductive material 140', the electroless metal layer 130', and the sputtered metal layer 120', at least one add-on structure (schematically showing two add-on structures 150a and 150b) is formed on at least one of the upper surface 111 and lower surface 113 of the core substrate 110 (schematically formed on the upper surface 111 and lower surface 113, respectively). The add-on structure 150a includes at least one insulating layer (schematically showing one insulating layer 152a), at least one conductive blind via (schematically showing two conductive blind vias 154a), and at least one circuit (schematically showing two circuits 156a). The insulating layer 152a covers the first conductive circuit C1, and the circuit 156a is located on the insulating layer 152a. The conductive blind vias 154a are located within the insulating layer 152a and electrically connect the circuit 156a and the first conductive circuit C1. Similarly, the add-on structure 150b includes at least one insulating layer (schematically shown as one insulating layer 152b), at least one conductive blind via (schematically shown as two conductive blind vias 154b), and at least one circuit (schematically shown as two circuits 156b). The insulating layer 152b covers the second conductive circuit C2, while the circuit 156b is located on the insulating layer 152b, and the conductive blind via 154b is located within the insulating layer 152b and electrically connects the circuit 156b and the second conductive circuit C2. The addition of the add-on structures 150a and 150b creates a fan-out structure, thereby increasing the applicability of the substrate structure 100d.

[0071] In summary, the substrate structure and its fabrication method of the present invention first use a dry process to form a sputtered metal layer on the upper and lower surfaces of the core substrate and a portion of the inner wall of the via. Then, a wet process is performed to form an electroless metal layer on the sputtered metal layer and the remaining portion of the inner wall of the via. This solves the problem of low step coverage faced by the prior art in the dry deposition process, and enables the substrate structure of the present invention to have better structural reliability.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A substrate structure, characterized in that, include: The core substrate has an upper surface and a lower surface opposite to each other and at least one through hole extending from the upper surface to the lower surface; A sputtered metal layer is disposed on the upper surface, the lower surface, and a portion of the inner wall of the at least one through hole of the core substrate; An electroplated metal layer is disposed on the sputtered metal layer and on the remaining portion of the inner wall of the at least one through hole; as well as A conductive material layer is disposed on the electroless metal layer and fills the at least one via, thereby defining at least one first conductive circuit located on the upper surface, at least one second conductive circuit located on the lower surface, and at least one conductive via located in the at least one via and electrically connecting the at least one first conductive circuit and the at least one second conductive circuit.

2. The substrate structure according to claim 1, characterized in that, Also includes: An adhesion promoting layer is directly applied to the upper surface, the lower surface, and the inner wall of the at least one through-hole of the core substrate, wherein the sputtered metal layer is located between the adhesion promoting layer and the electroplated metal layer.

3. The substrate structure according to claim 2, characterized in that, The material of the adhesion-promoting layer includes oxides or nitrides.

4. The substrate structure according to claim 3, characterized in that, The oxides include silicon oxide, aluminum oxide, or titanium oxide.

5. The substrate structure according to claim 3, characterized in that, The nitride includes silicon nitride.

6. The substrate structure according to claim 2, characterized in that, The thickness of the adhesion-promoting layer is between 0.01 nanometers and 100 nanometers.

7. The substrate structure according to claim 1, characterized in that, The core substrate includes an insulating substrate.

8. The substrate structure according to claim 7, characterized in that, The insulating substrate includes an inorganic substrate.

9. The substrate structure according to claim 8, characterized in that, The inorganic substrate is made of glass or ceramic.

10. The substrate structure according to claim 1, characterized in that, The surface roughness of the core substrate is between 1 nanometer and 50 nanometers.

11. The substrate structure according to claim 1, characterized in that, The thickness of the core substrate is between 50 micrometers and 1000 micrometers.

12. The substrate structure according to claim 1, characterized in that, The diameter of the at least one through hole is between 10 micrometers and 200 micrometers.

13. The substrate structure according to claim 1, characterized in that, The thickness of the electroless metal layer is less than 1 micrometer.

14. The substrate structure according to claim 1, characterized in that, The material of the electroless metal layer includes nickel-phosphorus, copper, silver, or a combination of the above materials.

15. The substrate structure according to claim 1, characterized in that, The material of the sputtered metal layer includes a titanium-copper alloy.

16. The substrate structure according to claim 1, characterized in that, Also includes: At least one add-on structure is disposed on at least one of the upper surface and the lower surface of the core substrate. The at least one add-on structure includes at least one insulating layer, at least one conductive blind via, and at least one circuit. The at least one insulating layer covers at least one of the at least one first conductive circuit and at least one second conductive circuit. The at least one circuit is located on the at least one insulating layer. The at least one conductive blind via is located within the at least one insulating layer and electrically connects the at least one circuit and at least one of the at least one first conductive circuit and at least one second conductive circuit.

17. A method for manufacturing a substrate structure, characterized in that, include: A core substrate is provided, the core substrate having an upper surface and a lower surface opposite to each other and at least one through hole extending from the upper surface to the lower surface; A dry process is performed on the core substrate to form a sputtered metal layer on the upper surface, the lower surface, and a portion of the inner wall of the at least one through hole of the core substrate. A wet process is performed on the core substrate to form an electroless metal layer on the sputtered metal layer and on the remaining portion of the inner wall of the at least one through hole; as well as A conductive material layer is formed on the electroless metal layer and fills the at least one via, and at least one conductive via is defined within the at least one via; as well as The conductive material, the electroless metal layer, and the sputtered metal layer are patterned, and at least one first conductive circuit is defined on the upper surface of the core substrate and at least one second conductive circuit is defined on the lower surface of the core substrate, wherein the at least one conductive via electrically connects the at least one first conductive circuit and the at least one second conductive circuit.

18. The method for fabricating a substrate structure according to claim 17, characterized in that, Also includes: Before performing the dry process on the core substrate, an adhesion promoting layer is formed to directly cover the upper surface, the lower surface, and the inner wall of the at least one through hole of the core substrate.

19. The method for fabricating a substrate structure according to claim 18, characterized in that, The material of the adhesion-promoting layer includes oxides or nitrides.

20. The method for manufacturing a substrate structure according to claim 17, characterized in that, Also includes: After patterning the conductive material, the electroless metal layer, and the sputtered metal layer, at least one add-on structure is formed on at least one of the upper surface and the lower surface of the core substrate. The at least one add-on structure includes at least one insulating layer, at least one conductive blind via, and at least one circuit. The at least one insulating layer covers at least one of the at least one first conductive circuit and at least one second conductive circuit, while the at least one circuit is located on the at least one insulating layer. The at least one conductive blind via is located within the at least one insulating layer and electrically connects the at least one circuit and at least one of the at least one first conductive circuit and at least one of the at least two second conductive circuits.

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