Die-to-die attachment between terminals

Abstract

An integrated circuit (IC) package concept includes attaching an auxiliary die to a main die between terminals of the main die. The auxiliary die may include one or more capacitors and / or inductors and active circuitry (including, for example, vertical FETs). In some embodiments, more than one secondary IC may be attached (directly or indirectly) to the primary IC. Such a multi-IC stack configuration reduces parasitic capacitance and / or inductance compared to conventional side-by-side arrangements, and thus enables higher frequency operation. In power converters, the higher operating frequencies typically enable the circuitry to make a beneficial trade-off between reducing capacitance and / or inductance requirements, if present, and typically improve the energy transfer capability of the power converter.

Description

Technical Field

[0001] This invention relates to three-dimensional integrated circuit packaging structures. Background Technology

[0002] The electronics industry continues to add electronic functionality and performance to a wide variety of products, including (by way of example) personal electronics (such as “smart” watches and fitness wearables), personal computers, tablets, wireless network components, televisions, cable system “set-top boxes,” radar systems, and cellular phones. There is also a trend toward packaging such added functionality and / or performance into smaller sizes. The two-dimensional (2-D) planar form factor, or “footprint,” of circuit modules and circuit boards is a constraint on reducing the size of electronic products.

[0003] Reducing the size of circuit modules and circuit boards is often hampered by the need to accommodate relatively large passive components such as capacitors and inductors. For example, power converters, especially charge pump power converters, may require physically large capacitors and inductors.

[0004] Therefore, many capacitors and inductors are discrete components mounted directly on the surface of or within a module substrate or printed circuit board (PCB) near the packaged IC chip. The module substrate is then typically electrically connected in sequence to other structures, such as the PCB, that can house multiple module substrates and other components. It should be apparent that mounting capacitors and inductors to the module substrate consumes planar area, thus limiting the reduction in module substrate size. Furthermore, placing capacitors and inductors at a distance from the packaged IC increases undesirable impedance, parasitic capacitance, and inductance, a problem that worsens with increasing operating frequency.

[0005] Several technologies exist for forming “on-chip” capacitors and inductors that are fully integrated with CMOS IC chips. For example, on-chip capacitors can be fabricated using MIM (metal-insulator-metal), MOM (metal-oxide-semiconductor), and MOS (metal-oxide-semiconductor) processes. However, many applications require high capacitance density, which is not achievable for IC dies with dimensions of at most a few square millimeters. For instance, current MIM, MOM, and MOS on-chip capacitor technologies offer capacitance densities that can be measured at a maximum of a few picofarads per square millimeter (pF / mm²). 2 Unless expensive and time-consuming (months of factory manufacturing time) multilayer stacks are used (and even then, the capacitance density remains relatively low). In contrast, in many applications, especially power converters, capacitance density needs to be measured in microfarads per square millimeter (μF / mm²). 2That is, approximately 1,000,000 times the capacitance that an on-chip capacitor can provide. A similar problem applies to on-chip inductors. For example, on-chip planar spiral inductors offer limited inductance due to the limited number of possible turns and have a low quality (Q) factor, while requiring a relatively large amount of silicon surface area. Summary of the Invention Technical issues

[0006] Achieving high capacitance and inductance values ​​using current on-chip technology requires very large IC dies, which runs counter to modern design goals. Therefore, circuit designs requiring high capacitance and / or inductance values ​​typically use discrete capacitors (e.g., silicon capacitors) and inductors as described above, consuming planar area of ​​the mounting structure (e.g., module substrate or PCB). Discrete capacitors and inductors are typically packaged as surface mount devices (SMDs) for easy handling during PCB manufacturing.

[0007] Therefore, there is a need in the art for an IC packaging solution that offers significantly higher capacitance and / or inductance densities than existing on-chip solutions, while reducing the planar area consumed by the mounting structure. This invention addresses this need. Solution to the problem

[0008] This invention includes an IC packaging concept that includes attaching an auxiliary die to a main IC between terminals of a main IC. The auxiliary die may include one or more capacitors and / or inductors, as well as active circuitry (including, for example, a vertical FET). In some embodiments, more than one auxiliary IC may be attached (directly or indirectly) to the main IC.

[0009] Compared to conventional side-by-side arrangements, this multi-IC stacking configuration reduces parasitic capacitance and / or inductance, and thus enables higher frequency operation. In power converters, higher operating frequencies typically allow the circuit to make beneficial trade-offs between reducing capacitance and / or inductance requirements (if any), and higher operating frequencies generally improve the power converter's power delivery capability.

[0010] The present invention includes a multi-integrated circuit (IC) stack, including a main IC configured with a main terminal array; and a first auxiliary IC configured with a first auxiliary terminal array, wherein the first auxiliary IC is electrically connected to the main IC through at least one terminal of the first auxiliary terminal array, wherein the first auxiliary IC is located in a gap region of the main IC where there are no terminals in the main terminal array.

[0011] The present invention also includes a method of manufacturing a multi-integrated circuit (IC) stack, comprising: configuring a main terminal array for a main IC; configuring a first auxiliary terminal array for a first auxiliary IC; positioning the first auxiliary IC in a gap region of the main IC where there are no terminals within the main terminal array; and electrically connecting the first auxiliary IC to the main IC via at least one terminal of the first auxiliary terminal array. Details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will become apparent from the specification, drawings, and claims. Attached Figure Description

[0012] Figure 1A This is a cross-sectional view of a standard existing technology MOSFET. Figure 1B This is a cross-sectional view of a standard existing technology MOSFET formed through the SLT process. Figure 2A This is a bottom plan view of a pre-existing packaged IC, which includes an IC with a terminal array configured in the form of solder bumps, solder balls, copper pillars, etc. Figure 2B yes Figure 2A Cross-sectional view along line AA. Figure 3A This is a bottom plan view of the multi-IC stack according to the present invention. Figure 3B yes Figure 3A Cross-sectional view along line BB. Figure 3C It is a cross-sectional view of a multi-IC stack including auxiliary ICs with RDL. Figure 4 It is a bottom plan view of a multi-IC stack with multiple rectangular auxiliary ICs of different sizes located between the terminals of the main IC. Figure 5A This is a bottom plan view of a multi-IC stack with two rectangular auxiliary ICs located between the terminals of the main IC. Figure 5B It is a bottom plan view of a multi-IC stack with two rectangular auxiliary ICs located between the terminals of the main IC, the auxiliary ICs being rotated at an angle of approximately 45° relative to the grid pattern of the main terminal array. Figure 6 It is a bottom plan view of a multi-IC stack with two rectangular auxiliary ICs located between different groups of terminals of the main IC, the auxiliary ICs being rotated at an angle of approximately 33° relative to the grid pattern of the main terminal array. Figure 7 It is a bottom plan view of a multi-IC stack with auxiliary ICs located between a set of terminals of the main IC. Figure 8AThis is a bottom plan view of a first example multi-IC stack, including sub-stacks consisting of multiple auxiliary ICs. Figure 8B yes Figure 8A A cross-sectional view along the CC line in the first embodiment. Figure 8C yes Figure 8A The second embodiment is a cross-sectional view along the CC line. Figure 9A This is a bottom plan view of a second example multi-IC stack, which includes sub-stacks consisting of multiple auxiliary ICs. Figure 9B yes Figure 9A Cross-sectional view along line DD. Figure 10 This is a schematic diagram of a three-level DC-DC buck converter circuit in the prior art. Figure 11 It has partial representation Figure 10 The schematic diagram of the circuit is a bottom plan view of the first multi-IC stack covered by the circuit. Figure 12 It has partial representation Figure 10 The schematic diagram of the circuit is a bottom plan view of the second multi-IC stack covered by the circuit. Figure 13 This is a top plan view of a substrate, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin film block). Figure 14 This is a process flow diagram illustrating a method for manufacturing multi-IC stacks. Detailed Implementation

[0013] The same reference numerals and symbols in the various figures indicate the same elements.

[0014] This invention includes an IC packaging concept that involves attaching an auxiliary die to a main IC between terminals of a main IC. The auxiliary die may include one or more capacitors and / or inductors, as well as active circuitry (including, for example, a vertical FET). In some embodiments, more than one auxiliary IC may be attached (directly or indirectly) to the main IC.

[0015] Compared to conventional side-by-side arrangements, this multi-IC stacking configuration reduces parasitic capacitance and / or inductance, and thus enables higher frequency operation. In power converters, higher operating frequencies typically allow the circuit to make beneficial trade-offs between reducing capacitance and / or inductance requirements (if any), and higher operating frequencies generally improve the power converter's power delivery capability.

[0016] It may be useful to review how metal-oxide-semiconductor field-effect transistor (MOSFET) circuit systems are manufactured. Figure 1A This is a cross-sectional view of a conventional MOSFET 100. Starting from a wafer substrate 102, such as silicon, a main circuit layer 104, typically made of doped silicon, is formed. For silicon-on-insulator (SOI) MOSFETs, an insulating buried oxide (BOX) layer (not shown) may be formed on the wafer substrate 102 prior to the formation of the main circuit layer 104.

[0017] On and / or within the main circuit layer 104, one or more MOSFET structures (not shown) are formed within the boundaries of a single IC die (not monolithically formed at this point). Each wafer substrate typically includes hundreds or thousands of non-monolithically formed dies.

[0018] A MOSFET structure typically includes a mask-formed channel, gate, source, drain, and isolation region. To date, IC manufacturing processes are generally considered to be front-end-of-line (FEOL) processes, where individual devices (transistors, capacitors, resistors, inductors, etc.) are patterned in or on the main circuit layer 104. FEOL typically covers everything up to (but not including) the deposition of the metal interconnect layers and can be viewed as the fabrication of the underlying die structure.

[0019] Following the final FEOL step, the wafer comprises multiple die regions, each containing isolated transistors without any interconnect conductors. Back-end-of-line (BEOL) processes are the second part of IC manufacturing, where individual devices within the die regions (transistors, capacitors, resistors, inductors, etc.) are interconnected with conductors forming part of or penetrating one or more metal interconnect layers. BEOL includes the fabrication of an upper structure 106, which includes, for example, vias, insulating layers (dielectrics), metallization layers, and electrical contacts (pads) 108 for die-to-package connections. In some applications, one or more through-substrate vias (TSVs) 110 may be fabricated, each TSV penetrating the wafer substrate 102 between the main circuit layer 104 and electrical connection points 112 (such as bonding pads).

[0020] Some BEOL manufacturing processes or post-BEOL manufacturing processes (e.g., as part of Outsourced Semiconductor Assembly and Test or "OSAT") support the fabrication of a redistribution layer (RDL). The redistribution layer is typically an additional patterned conductive layer (usually aluminum) on the IC die that allows the IC die's input / output (I / O) pads to be used for coupling to other locations on the die and / or another IC die and / or a dedicated package structure. The RDL can be formed on top of the "upper" BEOL upper structure of the IC die. In some cases (e.g., for single-layer transfer or "SLT" die structures), the RDL can be formed adjacent to the main circuitry layer containing the active MOSFET region after the wafer substrate has been removed and the main circuitry layer and upper structure have been reattached to the processed wafer.

[0021] For example, Figure 1B This is a cross-sectional view of a programmed, existing-technology MOSFET 120 manufactured using the SLT process. Similar to... Figure 1A The MOSFET 100 IC die is basically inverted (compared to...). Figure 1A The arrows in Figure 1B (The arrow in the diagram) allows the upper structure 106 to be bonded to the processing wafer 122. The initial substrate 102 is partially or completely removed, and the RDL 124 is formed adjacent to the main circuit layer 124.

[0022] Therefore, a MOSFET IC die is essentially formed from two parts: the “lower” FEOL lower layer structure and the “upper” BEOL upper layer structure of the main circuit layer 124. After the FEOL and BEOL processes, the wafer can undergo several additional processing steps, including dicing and testing, to form multiple IC dies.

[0023] One or more IC dies can be configured to be attached to a chip module substrate (e.g., a thin-film block or other chip carrier), which in turn can be configured to be attached to another structure such as a printed circuit board. For example, Figure 2A This is a bottom plan view of a prior art packaged IC 200, which includes an IC 202 configured with a terminal array 204 in the form of solder bumps, solder balls, copper pillars, etc. Figure 2B yes Figure 2AA cross-sectional view along line AA. Although a 3×3 square terminal array 204 is shown, this array can have other sizes and does not need to be square. A common example of such an array is a ball grid array (BGA), in which IC 202 has conductive (e.g., copper) pads configured on one side of the IC structure, and each pad initially has tiny solder balls adhered to it. The solder balls can be placed manually or by automated equipment and can be held in place with viscous flux. The packaged IC 200 can be placed on a PCB with conductive pads having a pattern that matches the solder balls. The assembly is then heated either in a reflow oven or by an infrared heater to melt the solder balls. Surface tension keeps the package aligned with the PCB at the correct spacing as the solder cools and solidifies, forming a solder joint between the device and the PCB.

[0024] Traditionally, packaged ICs 200 requiring large capacitors and / or inductors are placed on PCBs, adjacent to packaged capacitors or inductors. As mentioned above, mounting capacitors and inductors to the module substrate in such a "side-by-side" arrangement consumes planar area, thus limiting the reduction in the size of the module substrate.

[0025] One aspect of the invention involves attaching auxiliary dies to the main lead between the terminals of the main lead, wherein the auxiliary dies comprise one or more capacitors and / or inductors. Compared to conventional side-by-side arrangements, such a stacked configuration reduces parasitic capacitance and / or inductance, and thus enables higher frequency operation. In power converters, higher operating frequencies typically allow the circuit to make beneficial trade-offs between reduced capacitance and / or inductance requirements (if any), and higher operating frequencies improve the power converter's power delivery capability.

[0026] Figure 3A This is a bottom plan view of the multi-IC stack 300 according to the present invention. Figure 3B yes Figure 3A A cross-sectional view along line BB. The multi-IC stack 300 includes a main IC 302 configured with a main terminal array 304 in the form of solder bumps, solder balls, copper pillars, etc. For example, the main IC 302 may be a power converter or a radio frequency (RF) circuit. An auxiliary IC 308, such as a silicon capacitor, is electrically connected and / or thermally connected to the main IC 302 via an auxiliary terminal array 306. The auxiliary terminal array 306 may be formed in the same manner as the main terminal array 304, but in a smaller size, such that the "Z" height of the auxiliary terminal array 306 and the auxiliary IC 308 is smaller than the reflow "Z" height of the main terminal array 304.

[0027] The auxiliary IC 308 can be electrically and / or thermally connected to the main IC 302 via the auxiliary terminal array 306 and thereby indirectly connected to the PCB 310 via the main terminal array 304. In an alternative embodiment, the back side of the auxiliary IC 308 (the side facing away from the main IC 302) may include electrical contacts formed in the redistribution layer, enabling direct connection between the auxiliary IC 308 and the PCB. For example, Figure 3C This is a cross-sectional view of a multi-IC stack 320 including an auxiliary IC 308 having RDL 312. A portion of RDL 312 may be configured to be directly electrically and / or thermally connected to a PCB substrate (e.g., to dissipate heat from either or both of the main IC 302 and the auxiliary IC 308). In some embodiments, an additional terminal array 314 may be formed on RDL 312 and configured to be electrically and / or thermally connected to a PCB substrate (not shown to avoid clutter, but see...). Figure 3B Compared to PCB routing (which is typically around 50 μm to 100 μm in current processes), RDL routing's finer pitch (less than about 20 μm in current processes) provides greater flexibility in component placement and connectivity.

[0028] One limitation on the “Z” height of the auxiliary terminal array 306, the auxiliary IC 308 with RDL 312, and the optional additional terminal array 314 is that their total stack height should be the same as the “Z” height of the main terminal array 304 after reflow, so that the connection to the back side of the auxiliary IC 308 contacts the PCB substrate after the main terminal array 304 melts.

[0029] like Figure 3A As shown, the auxiliary IC 308 is positioned within the gap region of the main IC 302 where there are no terminals within the main terminal array 304. The preferred position of the auxiliary IC 308 is rotated at an angle of approximately 45° relative to the grid pattern of the main terminal array 304. However, other angles, as well as other shapes and numbers of auxiliary ICs 308, can be used. Maintaining the rotation angle between approximately 30° and 60° has several advantages, including that the size of the auxiliary IC 308 can generally be maximized while providing adequate spacing away from the main terminal array 304.

[0030] For example, Figure 4 This is a bottom plan view of a multi-IC stack 400 having multiple rectangular auxiliary ICs 308a to 308c of different sizes located between terminals 304 of the main IC 302; each of the auxiliary ICs 308a to 308c will have a corresponding auxiliary terminal array ( Figure 4 (Not shown in the image).

[0031] Figure 5AThis is a bottom plan view of a multi-IC stack 500 having two rectangular auxiliary ICs 308a to 308b located between terminals 304 of the main IC 302. Figure 5B It is a bottom plan view of a multi-IC stack 520 having two rectangular auxiliary ICs 308a to 308b located between terminals 304 of the main IC 302, the auxiliary ICs being rotated at an angle of approximately 45° relative to the grid pattern of the main terminal array 304.

[0032] Figure 6 It is a bottom plan view of a multi-IC stack 600 having two rectangular auxiliary ICs 308a to 308b located between different groups of terminals 304 of the main IC 302, the auxiliary ICs being rotated at an angle of approximately 33° relative to the grid pattern of the main terminal array 304.

[0033] Figure 7 This is a bottom plan view of a multi-IC stack 600 having an auxiliary IC 308 located between a set of terminals 304 of the main IC 302. The view shows that the auxiliary IC 308 may occupy only a relatively small portion of the attachment surface of the main IC 302, while the remaining portion of the attachment surface is available for the terminals 304.

[0034] Another aspect of the invention is that the multiple auxiliary ICs 308 can be stacked on top of each other, with optional direct electrical and / or thermal connections between the stacked components, and optionally, the "bottom" component of the stack has a redistribution layer and a terminal array configured to be electrically and / or thermally connected to a PCB substrate, etc.

[0035] For example, Figure 8A This is a bottom plan view of a first example multi-IC stack 800, which includes a sub-stack consisting of multiple auxiliary ICs 308a to 308b stacked adjacent to each other. Figure 8B yes Figure 8A A cross-sectional view along the CC line in the first embodiment. Figure 8C yes Figure 8A The second embodiment is a cross-sectional view along the CC line.

[0036] In the first embodiment, as described above, the first auxiliary IC 308a is attached to the main IC 302 in the gap region of the main IC 302 where there are no terminals within the main terminal array 304. Then, the second auxiliary IC 308b is attached to the first auxiliary IC 308a, as follows: Figure 4As shown in B. For example, the attachment of auxiliary ICs 308a and 308b can be achieved directly through die-to-die hybrid bonding, wherein the interconnect electrical connections are accomplished, for example, by TSV 802, RDL pads, or a combination of TSV and RDL pads. In some embodiments, the first auxiliary IC 308a and the second auxiliary IC 308b are first bonded together as a stack, and then the stack is attached as a unit to the main IC 302 via auxiliary terminal array 306.

[0037] In the second embodiment, as described above, the first auxiliary IC 308a is attached to the main IC 302 in the gap region of the main IC 302 where there are no terminals within the main terminal array 304. Then, the second auxiliary IC 308b is attached to the first auxiliary IC 308a via an intermediate terminal array 804 in the form of solder bumps, solder balls, copper pillars, etc. Figure 4 As shown in C. In some embodiments, the first auxiliary IC 308a and the second auxiliary IC 308b are first coupled together as a stack, and then the stack is attached to the main IC 302 as a unit.

[0038] Although Figure 8A The second auxiliary IC 308b is shown as smaller than the first auxiliary IC 308a, but the two auxiliary ICs may have the same size, or the second auxiliary IC 308b may be larger than the first auxiliary IC 308a.

[0039] As another example, Figure 9A This is a bottom plan view of a second example multi-IC stack 900, which includes a sub-stack consisting of multiple auxiliary ICs 308a to 308b. Figure 9B yes Figure 9A Cross-sectional view along line DD. As described above, the first auxiliary IC 308a is attached to the main IC 302 in the gap area of ​​the main IC 302 where there are no terminals within the main terminal array 304. Then, the second auxiliary IC 308b is attached to the main IC 302 through an intermediate terminal array 902 in the form of solder bumps, solder balls, copper pillars, etc. Figure 4 As shown in Figure C. In some embodiments, the second auxiliary IC 308b may include an RDL 904, and an additional terminal array 906 may be formed on the RDL 904 and configured to be electrically and / or thermally connected to a PCB substrate (not shown to avoid clutter, but see Figure C). Figure 3B ).

[0040] Figure 9BOne advantage of the configuration shown is that the first auxiliary IC 308a and the second auxiliary IC 308b can optionally be spaced apart by an air gap. Compared to a configuration in which the first auxiliary IC 308a and the second auxiliary IC 308b are in physical contact, the air gap can promote heat dissipation and help avoid any adverse effects (e.g., parasitic capacitance) between the first auxiliary IC 308a and the second auxiliary IC 308b. In an alternative embodiment, an intermediate terminal array (not shown, but see...) Figure 8C It can be used for electrical and / or thermal coupling of the first auxiliary IC 308a and the second auxiliary IC 308b. Figure 9B Another advantage of the configuration shown is that optical inspection of various terminal arrays is still possible.

[0041] The above embodiments allow for the attachment of an auxiliary IC 308 (or a stack of auxiliary ICs 308) to a main IC 302 during BEOL manufacturing processes or post-BEOL manufacturing processes (e.g., OSAT). One attachment method involves removing the auxiliary IC 308 from a carrier (e.g., tape) using a "pick and place" device and placing the auxiliary IC 308 onto the main IC 302, followed by a reflow process for permanent bonding.

[0042] Another attachment method involves using a "pick and place" device to remove the auxiliary IC 308 from the carrier and place it onto the main IC 302 mounted on the "reconstructed" wafer, followed by a reflow process for permanent bonding. The reconstructed wafer carries multiple monolithic IC dies (typically tested as "known good") remounted on the carrier substrate. For example, the carrier substrate (e.g., glass or silicon) may have an adhesive layer (e.g., epoxy compound) applied, and then filled with multiple known good IC dies using, for example, a "pick and place" device. Of course, which IC is mounted on the reconstructed wafer is relative; for example, multiple instances of the auxiliary IC 308 may be mounted on the substrate to form the reconstructed wafer, and then the main IC 302 may be "pick and place" onto the corresponding auxiliary IC 308.

[0043] The auxiliary IC 308 can be placed within the main terminal array 304 of the main IC 302 to reduce the potential impact of the auxiliary IC 308 on high-frequency (e.g., radio frequency) components within the main IC 302.

[0044] Embodiments of the present invention can be used in a variety of applications. As an example, a multi-IC stack including a main IC 302 with an active circuit system (e.g., a transistor switch) and at least one auxiliary IC 308 including one or more capacitors and / or one or more inductors may be particularly useful in compact power converters.

[0045] Figure 10 This is a schematic diagram of a prior art three-level DC-DC buck converter circuit 1000. The converter circuit 1000 shown includes a "flying" capacitor C1 connected at node A between switches Sw1 and Sw2, and at node B between switches Sw3 and Sw4. It also includes a capacitor connected at node C between switches Sw2 and Sw3, and a capacitor connected to the output terminal V. OUT_T The inductor L at node D. The output capacitor C. OUT Coupled between the reference potentials (e.g., circuit ground) at nodes D and E. In the example shown, at input terminal V IN_T Voltage V applied at point IN At the output terminal V OUT_T Converted to output voltage V OUT =1 / 2V IN Details of the operation of the converter circuit 1000 are set forth in U.S. Patent Application No. 17 / 560,767, entitled “Controlling Charge-Balance and Transients in a Multi-Level Power Converter,” filed December 23, 2021, which has been assigned to the assignee of this invention and is incorporated herein by reference.

[0046] Figure 11 It has partial representation Figure 10 The schematic diagram of the circuitry covers the bottom plan view of the first multi-IC stack 1100. Three terminals within the main terminal array 304 are configured to correspond to the input terminal V. IN_T Output terminal V OUT_T And circuit ground (GND). In the example shown, auxiliary IC 308 includes a flying capacitor C1 coupled between node A and node B within the main IC 302.

[0047] Figure 12 It has partial representation Figure 10 The schematic diagram of the circuitry covers the bottom plan view of the second multi-IC stack 1200. Three terminals within the main terminal array 304 are configured to correspond to the input terminal V. IN_T Output terminal V OUT_T And circuit ground (GND). In the example shown, auxiliary IC 308 includes a flying capacitor C1 coupled within the main IC 302 between nodes A and B, an inductor L coupled within the main IC 302 between nodes C and D, and an output capacitor C coupled within the main IC 302 between nodes D and E. OUTThe dashed line between the two instances of node D indicates the inductor L and capacitor C. OUT The connection can be made within the auxiliary IC 308, thus saving terminals within the auxiliary terminal array 306 (see [link]). Figure 3B And further reduce parasitic capacitors and / or inductance.

[0048] It should be understood that the auxiliary IC 308 may include more than two capacitors or one inductor, and therefore can support more than Figure 10 The divider converter circuit requires power converters with more flying capacitors (e.g., divider, boost, tripler, etc.).

[0049] It should also be understood that, Figure 11 and Figure 12 The auxiliary IC 308 in the example may include a stack of multiple auxiliary ICs 308, such as Figures 8A to 8C As shown in the diagram. Such a stacking enables larger capacitance and / or inductance values, and / or different allocations of capacitors and / or inductors to a particular auxiliary IC 308 within the stack.

[0050] The circuits and devices according to the invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules for ease of handling, manufacturing, and / or performance improvement. In particular, IC embodiments of the invention are frequently used in modules, where one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possible additional ICs) in a single package. Then, typically, the ICs and / or modules are often combined with other components on a printed circuit board to form part of an end product such as a cellular phone, laptop computer, or tablet computer, or to form a higher-level module that can be used in a wide variety of products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and components, such ICs are typically capable of implementing communication modes, typically wireless communication.

[0051] As an example of further integration of the present invention with other components, Figure 13This is a top plan view of a substrate 1300, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin-film block). In the illustrated example, substrate 1300 includes a plurality of ICs 1302a to 1302d having terminal pads 1304 interconnected via conductive vias and / or traces on and / or within substrate 1300 or on opposing (back) surfaces of substrate 1300 (surface conductive traces are not shown to avoid clutter, and not all terminal pads are marked). ICs 1302a to 1302d may include, for example, signal switches, active and / or passive filters, amplifiers (including one or more LNAs), and other circuitry. For example, ICs 1302c and 1302d may each include charge pumps CP1 and CP2, wherein each charge pump may include a multi-IC stack according to the invention. With suitable control circuitry, the outputs of charge pumps CP1 and CP2 (or more, CP1…CPn) may be coupled in parallel to provide a higher available power level.

[0052] The substrate 1300 may also include one or more passive devices 1306 embedded in, formed on, and / or attached to the substrate 1300. Although shown as a general rectangle, the passive device 1306 may be, for example, a filter, capacitor, inductor, transmission line, resistor, antenna element, transducer (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), battery, etc. The passive device 1306 is interconnected with other passive devices 1306 and / or individual ICs 1302a to 1302d via conductive traces on or in the substrate 1300. The front or rear surface of the substrate 1300 may be used as a location for forming other structures.

[0053] Multiple IC stack configurations can include various combinations of main IC / auxiliary ICs, including: processor / memory ICs, power FET / power FET ICs, power FET / gate driver ICs, and RF / antenna / filter ICs.

[0054] While the examples above focus on auxiliary IC 308 or a stack of auxiliary IC 308 including capacitors and / or inductors, it should be understood that the packaging concepts disclosed above are applicable to ICs including, for example, analog and / or digital transistor circuit systems, transmission lines, resistors, diodes, planar antenna elements, and transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, temperature sensors, humidity sensors, pressure sensors, etc.). For example, the transistor circuit system may include, for example, a vertical FET, wherein the source of the FET within the auxiliary IC 308 is close to the main IC 302, while the drain of the FET is close to the other side of the auxiliary IC 308.

[0055] Embodiments of the present invention are useful in various larger circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, radio frequency (RF) power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam steering systems, charge pump devices, RF switches, etc. Such functionality is useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0056] Radio system applications include wireless RF systems (including base stations, relay stations, and handheld transceivers) using a variety of technologies and protocols, including various types of Orthogonal Frequency Division Multiplexing (“OFDM”), Orthogonal Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Time Division Multiple Access (“TDMA”), Wideband Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G New Radio, 6G and WiFi (e.g., 802.11a, 802.11b, 802.11g, 802.11ac, 802.11ax, 802.11be) protocols, as well as other radio communication standards and protocols.

[0057] Another aspect of the invention includes a method for manufacturing a multi-integrated circuit (IC) stack. For example, Figure 14 This is a process flow diagram 1400 illustrating a method for manufacturing a multi-IC stack. The method includes: configuring a main terminal array for a main IC (block 1402); configuring a first auxiliary terminal array for a first auxiliary IC (block 1404); positioning the first auxiliary IC in a gap region of the main IC where there are no terminals in the main terminal array (block 1406); and electrically connecting the first auxiliary IC to the main IC via at least one terminal of the first auxiliary terminal array (block 1408).

[0058] Additional aspects of the above method may include one or more of the following: wherein the main terminal array is in a grid pattern, and the first auxiliary IC is rotated relative to the grid pattern of the main terminal array; wherein the main terminal array is in a grid pattern, and the first auxiliary IC is rotated relative to the grid pattern of the main terminal array at an angle of approximately 45°; configuring a second auxiliary terminal array for a second auxiliary IC, positioning the second auxiliary IC in a gap region of the main IC, and electrically connecting the second auxiliary IC to the main IC through at least one terminal of the second auxiliary terminal array; positioning the second auxiliary IC near the first auxiliary IC in a sub-stack configuration; electrically connecting the second auxiliary IC to the first auxiliary IC through one or more through-holes penetrating the substrate; The second auxiliary IC is electrically connected to the first auxiliary IC via an intermediate terminal array; the second auxiliary IC is electrically connected to the main IC via an intermediate terminal array; wherein the second auxiliary IC is spaced apart from the first auxiliary IC; wherein the first auxiliary IC includes a redistribution layer and further includes an additional terminal array providing connection to a corresponding portion of the redistribution layer; the main terminal array is configured to stack multiple ICs on other structures; wherein the first auxiliary IC includes at least one capacitor; wherein the first auxiliary IC includes at least one inductor; wherein the first auxiliary IC includes at least one transistor circuit, and / or wherein the first auxiliary IC includes at least one of a transmission line, a resistor, a diode, an antenna element, or a transducer.

[0059] As used in this disclosure, the term "MOSFET" includes any field-effect transistor (FET) having an insulated gate with conductivity that determines its voltage, and includes an insulated gate having a metallic or metalloid, insulator, and / or semiconductor structure. The terms "metal" or "metalloid" include at least one conductive material (such as aluminum, copper, or other metals, or highly doped polycrystalline silicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (such as silicon oxide or other dielectric materials), and "semiconductor" includes at least one semiconductor material.

[0060] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequencies of electromagnetic waves or the frequencies of alternating voltage or current in a circuit.

[0061] Regarding the accompanying drawings referenced in this disclosure, the dimensions of various elements are not drawn to scale; some dimensions may be significantly enlarged vertically and / or horizontally for clarity or emphasis. Furthermore, references to orientations and directions (e.g., “top,” “bottom,” “above,” “below,” “lateral,” “vertical,” “horizontal,” etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0062] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented using any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures), or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise stated above, embodiments of the present invention can be implemented using 2-D, 2.5-D, and 3-D structures with other transistor technologies such as bipolar junction transistors (BJTs), BiCMOS, LDMOS, BCD, GaAs HBTs, GaN HEMTs, GaAs pHEMTs, MESFETs, InP HBTs, InP HEMTs, FinFETs, GAAFETs, and SiC-based power device technologies. However, embodiments of the present invention are particularly useful when fabricated using SOI- or SOS-based processes, or when fabricated using processes with similar characteristics. Fabrication using SOI or SOS processes in CMOS enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., RF up to and exceeding 300 GHz). Monolithic IC implementations are particularly useful because parasitic capacitance can typically be kept low (or minimized, and kept consistent across all cells, thus allowing for compensation of parasitic capacitance) through careful design.

[0063] Voltage levels and / or voltage and / or logic signal polarities can be adjusted according to specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, "stacked" components (especially FETs) in series to handle higher voltages, and / or by using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or provide additional functionality without significantly altering its original function.

[0064] Several embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequentially independent and therefore may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0065] It should be understood that the foregoing description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all possible combinations of one or more of the processes, machines, manufactures, or material compositions set forth in the following claims. (Note that the bracket markings of the claim elements are for ease of reference to such elements and do not in themselves indicate a particular desired order or enumeration of the elements; furthermore, such markings may be repeated in dependent claims as references to additional elements and are not considered as a sequence of markings that initiates conflict.)

Claims

1. A multi-integrated circuit (IC) stack, comprising: (a) A main IC configured with a main terminal array; as well as (b) A first auxiliary IC configured with a first auxiliary terminal array, wherein the first auxiliary IC is electrically connected to the main IC via at least one terminal of the first auxiliary terminal array, wherein the first auxiliary IC is located in a gap region of the main IC where there are no terminals in the main terminal array.

2. The IC stack according to claim 1, wherein, The main terminal array is in the form of a grid pattern, and the first auxiliary IC rotates relative to the grid pattern of the main terminal array.

3. The IC stack according to claim 1, wherein, The main terminal array is in the form of a grid pattern, and the first auxiliary IC rotates between approximately 30° and approximately 60° relative to the grid pattern of the main terminal array.

4. The IC stack according to claim 1, further comprising a second auxiliary IC configured with a second auxiliary terminal array, wherein the second auxiliary IC is electrically connected to the main IC via at least one terminal of the second auxiliary terminal array, wherein, The second auxiliary IC is located in the gap area of ​​the main IC where there are no terminals in the main terminal array.

5. The IC stack according to claim 1, further comprising: The second auxiliary IC is located close to the first auxiliary IC in the sub-stack configuration.

6. The IC stack according to claim 5, wherein, The second auxiliary IC is electrically connected to the first auxiliary IC through one or more through-holes penetrating the substrate.

7. The IC stack according to claim 5, wherein, The second auxiliary IC is electrically connected to the first auxiliary IC via an intermediate terminal array.

8. The IC stack according to claim 5, wherein, The second auxiliary IC is electrically connected to the main IC via an intermediate terminal array.

9. The IC stack according to claim 5, wherein, The second auxiliary IC is spaced apart from the first auxiliary IC.

10. The IC stack according to claim 1, wherein, The first auxiliary IC includes a redistribution layer and further includes an additional terminal array connected to a corresponding portion of the redistribution layer.

11. The IC stack according to claim 1, wherein, The main terminal array is configured to mount the multi-IC stack on other structures.

12. The IC stack according to claim 1, wherein, The first auxiliary IC includes at least one capacitor.

13. The IC stack according to claim 1, wherein, The first auxiliary IC includes at least one inductor.

14. The IC stack according to claim 1, wherein, The first auxiliary IC includes at least one transistor circuit.

15. The IC stack according to claim 1, wherein, The first auxiliary IC includes at least one of a transmission line, a resistor, a diode, an antenna element, or a transducer.

16. A multi-integrated circuit (IC) stack, comprising: (a) A main IC configured with a main terminal array; as well as (b) A first auxiliary IC including at least one capacitor having a first terminal and a second terminal, and the first auxiliary IC being configured with an auxiliary terminal array, wherein at least one terminal of the capacitor is electrically connected to the main IC via at least one terminal of the auxiliary terminal array, wherein the first auxiliary IC is located in a gap region of the main IC where there are no terminals in the main terminal array.

17. The IC stack according to claim 16, wherein, The main terminal array is in the form of a grid pattern, and the first auxiliary IC rotates relative to the grid pattern of the main terminal array.

18. The IC stack according to claim 16, wherein, The main terminal array is in the form of a grid pattern, and the first auxiliary IC rotates between approximately 30° and approximately 60° relative to the grid pattern of the main terminal array.

19. The IC stack of claim 16, further comprising a second auxiliary IC configured with a second auxiliary terminal array, wherein the second auxiliary IC is electrically connected to the main IC via at least one terminal of the second auxiliary terminal array, wherein, The second auxiliary IC is located in the gap area of ​​the main IC where there are no terminals in the main terminal array.

20. The IC stack of claim 16, further comprising a second auxiliary IC located close to the first auxiliary IC in a sub-stack configuration.

21. The IC stack according to claim 20, wherein, The second auxiliary IC is electrically connected to the first auxiliary IC through one or more through-holes penetrating the substrate.

22. The IC stack according to claim 20, wherein, The second auxiliary IC is electrically connected to the first auxiliary IC via an intermediate terminal array.

23. The IC stack according to claim 20, wherein, The second auxiliary IC is electrically connected to the main IC via an intermediate terminal array.

24. The IC stack according to claim 20, wherein, The second auxiliary IC is spaced apart from the first auxiliary IC.

25. The IC stack according to claim 16, wherein, The first auxiliary IC includes a redistribution layer and further includes an additional terminal array connected to a corresponding portion of the redistribution layer.

26. The IC stack according to claim 16, wherein, The main terminal array is configured to mount the multi-IC stack on other structures.

27. The IC stack according to claim 16, wherein, The first auxiliary IC includes at least one inductor.

28. The IC stack according to claim 16, wherein, The first auxiliary IC includes at least one transistor circuit.

29. The IC stack according to claim 16, wherein, The first auxiliary IC includes at least one of a transmission line, a resistor, a diode, an antenna element, or a transducer.

30. A method for fabricating a stack of multiple integrated circuits (ICs), comprising: (a) Configure the main terminal array for the main IC; (b) Configure a first auxiliary terminal array for the first auxiliary IC; (c) Position the first auxiliary IC in the gap region of the main IC where there are no terminals in the main terminal array; as well as (d) The first auxiliary IC is electrically connected to the main IC via at least one terminal of the first auxiliary terminal array.

31. The method according to claim 30, wherein, The main terminal array is in the form of a grid pattern, and the first auxiliary IC rotates relative to the grid pattern of the main terminal array.

32. The method according to claim 30, wherein, The main terminal array is in the form of a grid pattern, and the first auxiliary IC rotates between approximately 30° and approximately 60° relative to the grid pattern of the main terminal array.

33. The method of claim 30, further comprising: (a) Configure a second auxiliary terminal array for the second auxiliary IC; (b) Position the second auxiliary IC within the gap region of the main IC; as well as (c) The second auxiliary IC is electrically connected to the main IC via at least one terminal of the second auxiliary terminal array.

34. The method of claim 30, further comprising: In a sub-stack configuration, the second auxiliary IC is positioned near the first auxiliary IC.

35. The method of claim 34, further comprising: The second auxiliary IC is electrically connected to the first auxiliary IC through one or more through-holes penetrating the substrate.

36. The method of claim 34, further comprising: The second auxiliary IC is electrically connected to the first auxiliary IC via an intermediate terminal array.

37. The method of claim 34, further comprising: The second auxiliary IC is electrically connected to the main IC via an intermediate terminal array.

38. The method according to claim 34, wherein, The second auxiliary IC is spaced apart from the first auxiliary IC.

39. The method according to claim 30, wherein, The first auxiliary IC includes a redistribution layer and further includes an additional terminal array providing connections to corresponding portions of the redistribution layer.

40. The method of claim 30, further comprising: Configure the main terminal array to mount the multi-IC stack on other structures.

41. The method according to claim 30, wherein, The first auxiliary IC includes at least one capacitor.

42. The method according to claim 30, wherein, The first auxiliary IC includes at least one inductor.

43. The method according to claim 30, wherein, The first auxiliary IC includes at least one transistor circuit.

44. The method of claim 30, wherein, The first auxiliary IC includes at least one of a transmission line, a resistor, a diode, an antenna element, or a transducer.

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