Method and system for automatically adjusting flatness of radar power beacon machine
By employing a digital domain adjustment method using a digital radio frequency storage (DRFM) unit and a two-dimensional power coefficient matrix, the problem of inconsistent gain of the radar power beacon at different frequencies and bandwidths was solved, enabling flatness adjustment of the radar at arbitrary frequencies and bandwidths and ensuring calibration accuracy.
Patent Information
- Application Number
- CN202511710343.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-02-17
AI Technical Summary
Existing radar power beacon receivers have inconsistent gains at different frequencies and bandwidths, leading to inaccurate radar calibration, especially under modulation methods such as linear frequency modulation, which cannot achieve broadband calibration.
The digital radio frequency storage (DRFM) unit, including an AD conversion chip, an FPGA chip, and a DA conversion chip, is used to achieve automatic adjustment of the flatness in the digital domain by using a preset flatness power coefficient table and a frequency-link combined two-dimensional power coefficient matrix.
It breaks through the limitations of analog device bandwidth and fluctuation number, and realizes flatness adjustment at arbitrary frequency and bandwidth, ensuring the calibration accuracy of radar in dynamic link scenarios.
Smart Images
Figure CN121541149A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of radar calibration technology, specifically relating to an automatic adjustment method for the flatness of a radar power beacon. Background Technology
[0002] A radar power beacon is a device that receives signals emitted by a radar, amplifies them, and then transmits them back to the radar. Its amplification gain is configurable and highly accurate. Its purpose is to simulate the echo situation when radar illuminates a target with a certain radar cross-section. After receiving this echo, the radar compares the measured gain with the gain set by the radar power beacon. Based on the comparison result, the radar power measurement is adjusted to ensure that the radar accurately measures the radar cross-section of incoming targets in actual combat.
[0003] Because radar power beacon receivers contain numerous analog components in their transmit and receive links, and these components exhibit varying gain and insertion loss responses at different frequencies, the gain of the radar power beacon itself across different frequency signals within the radar's instantaneous bandwidth is inconsistent (a phenomenon known in the industry as non-uniformity). Consequently, when calibrating a radar using a radar beacon, only single-point calibration can be performed. Modern radars frequently employ modulation methods such as linear frequency modulation, requiring the radar power beacon to be capable of simultaneous calibration across a certain bandwidth. If the radar power beacon itself is non-uniform, it's equivalent to adjusting the radar's "ruler" inaccurately, making radar calibration impossible.
[0004] To level the gain of radar power beacon receivers and reduce gain unevenness, the industry has made efforts in the following two directions.
[0005] 1. Adjust the flatness of each analog device on the radar power beacon receiver and transmitter link, or select devices with better flatness;
[0006] 2. Customize a notch filter based on the overall output flatness trend and connect it in series at the end of the link to achieve final adjustment of flatness.
[0007] The two methods mentioned above have the following problems and limitations.
[0008] 1. The flatness of each component is not always adjustable. Some components with non-adjustable flatness can still cause significant gain fluctuations. Although each component can be leveled, the impedance matching between the front and rear stages during the assembly of a single component is to some extent uncontrollable. Even a slight mismatch between the front and rear stages can have a significant impact on the flatness.
[0009] 2. Notch filters can only smooth out simple in-band undulations within a limited bandwidth. If there are multiple undulations within the band, or the bandwidth is too wide, or the beacon needs to switch local oscillators or attenuation settings to change the combination of link devices, the notch filter cannot adjust the flatness. Summary of the Invention
[0010] Purpose of the invention: The purpose of this invention is to provide an automatic adjustment method for the flatness of a radar power beacon that can maintain the flatness of the radar power beacon itself under any frequency and bandwidth conditions.
[0011] Technical solution: The present invention provides an automatic flatness adjustment method for radar power beacon, comprising a receiving link, a digital radio frequency storage (DRFM) unit, and a transmitting link. The DRFM unit includes an AD conversion chip, an FPGA chip, and a DA conversion chip. The FPGA chip has a preset flatness power coefficient table, which is a two-dimensional power coefficient matrix of "frequency-link combination".
[0012] The AD conversion chip converts the analog signal transmitted by the receiving link into a digital signal;
[0013] The FPGA chip traverses the flatness power coefficient table according to the frequency and link combination of the received digital signal and outputs the corresponding digital power compensation value.
[0014] The DA conversion chip adjusts the signal amplitude in 0.01dB steps based on the received digital power compensation value.
[0015] This technical solution is further defined as follows: the method for generating the flatness power coefficient table is as follows:
[0016] S2.1 Set the frequency converter local oscillator and attenuator to the i-th link combination;
[0017] S2.2 Scan all frequencies under the current local oscillator with a uniform input power, record the difference between the actual output gain and the target gain at each frequency point, and convert the difference into a compensation code value for storage;
[0018] S2.3 Repeat steps S2.1 and S2.2 until all link combinations are completed, forming a two-dimensional power coefficient matrix of "frequency-link combination".
[0019] Furthermore, the receiver attenuator has two settings, the transmitter attenuator has two settings, and the local oscillator has two settings. The beacon has eight types of local oscillator attenuation, and the link combinations are shown in the table below:
[0020] The resulting two-dimensional power coefficient matrix of the "frequency-link combination" is shown in the table below:
[0021] In the table above, a, b, c, d...x, y, z represent frequencies within the mid-frequency range.
[0022] Furthermore, the FPGA chip performs frequency mixing on the radio frequency signal to the intermediate frequency, and then performs flatness correction on the intermediate frequency signal in the digital domain.
[0023] Furthermore, the specific method for leveling the flatness is as follows:
[0024] First, the FPGA chip processes the digitized intermediate frequency signal to obtain its frequency, bandwidth, frequency modulation speed, and power information. The frequency information can determine the local oscillator level, and the preset gain information determines the receive attenuation level and the transmit attenuation level.
[0025] Then, based on the above information, the link combination and the signal frequency to be transmitted are determined. Subsequently, the corresponding power coefficient is found by traversing the preset flatness power coefficient table of the FPGA chip, and the signal power is increased or decreased according to the coefficient.
[0026] Beneficial effects: Compared with the prior art, the radar power beacon flatness automatic adjustment method provided by the present invention breaks through the bandwidth and fluctuation number limitations of analog devices (such as notch filters) through digital domain pre-calibration + real-time table lookup scheme, realizes flatness leveling of arbitrary bandwidth and arbitrary frequency, and solves the problem of unadjustable flatness in broadband, multi-fluctuation, and dynamic link scenarios. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of the link of a radar power beacon provided by the present invention;
[0028] Figure 2 This is a schematic diagram of the link of the DRFM unit of a radar power beacon provided by the present invention;
[0029] Figure 3 This is a circuit diagram of a radar power beacon provided by the present invention. Detailed Implementation
[0030] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the embodiments described.
[0031] Example 1:
[0032] A typical link diagram of a radar power beacon is shown below. Figure 1 As shown, its detailed circuit diagram is as follows: Figure 3 As shown, the system includes a receive link, a digital radio frequency (DRFM) storage unit, and a transmit link. The receive link precedes the DRFM unit, and the transmit link follows the DRFM unit. Except for the DRFM unit, each of the other components performs its respective function while increasing the link's unevenness.
[0033] This embodiment improves the digital radio frequency storage (DRFM) unit of the radar power beacon, and its link diagram is shown below. Figure 2 As shown, the system includes an AD converter chip, an FPGA chip, and a DA converter chip. The AD converter chip converts the analog signal from the receiving link into a digital signal, which is then processed by the FPGA chip. The FPGA chip performs frequency measurement and power factor adjustment on the signal, and sends the processed digital signal to the DA converter chip to convert it back into an analog signal, thus restoring the original radar signal. The power factor adjustment during this process changes the output power of the DA chip, thereby altering the output of the entire radar power beacon. Therefore, this process can be used to achieve gain leveling of the radar power beacon.
[0034] In the radar power beacon flatness automatic adjustment method provided in this embodiment, the FPGA chip has a pre-set flatness power coefficient table, which is a two-dimensional power coefficient matrix of "frequency-link combination". On the link, the switching of attenuators and frequency converter local oscillators is controlled by the DRFM unit. Therefore, it is only necessary to pre-create the power coefficient table for various attenuator and mixer combinations. The FPGA chip can find the corresponding power coefficient by looking up the table according to the two dimensions of frequency and the combination of attenuator and frequency converter local oscillator.
[0035] The specific adjustment steps for the automatic flatness adjustment method are as follows:
[0036] S1. The AD conversion chip converts the analog signal transmitted by the receiving link into a digital signal.
[0037] S2. The FPGA chip traverses the flatness power coefficient table according to the frequency and link combination of the received digital signal and outputs the corresponding digital power compensation value.
[0038] FPGA chips can store pre-calibrated power coefficient tables at different frequencies in their own memory. When needed, they can automatically look up and send the tables based on the frequency. As long as the corresponding coefficient exists at the frequency that needs adjustment, leveling can be achieved. Therefore, the number of in-band ripples does not pose any obstacle to this leveling method.
[0039] S3. The DA converter chip adjusts the signal amplitude in 0.01dB steps based on the received digital power compensation value. The power adjustment range of the DA chip can reach more than ten dB, the coefficient can be divided into 1024 parts, and its adjustment step can be refined to 0.01dB, which is far higher than the requirements for flatness adjustment.
[0040] The most important aspect of this method lies in the generation of the flatness power coefficient table. The detailed steps of the generation method are as follows:
[0041] S2.1 Set the frequency converter local oscillator and attenuator to the i-th link combination.
[0042] In this embodiment, the receiver attenuator has two settings, the transmitter attenuator has two settings, and the local oscillator has two settings. The beacon has eight types of local oscillator attenuation, and the link combinations are shown in Table 1.
[0043] Table 1
[0044] S2.2 Scan all frequencies under the current local oscillator with a uniform input power, record the difference between the actual output gain and the target gain at each frequency point, and convert the difference into a compensation code value for storage.
[0045] S2.3 Repeat steps S2.1 and S2.2 until all link combinations are completed, forming a two-dimensional power coefficient matrix of "frequency-link combination".
[0046] In the case of combination A of frequency converter local oscillator and attenuator, the power coefficient is uniformly set to 512. With uniform input power, all frequencies under the current local oscillator are output once with sufficiently fine frequency steps. The flatness of the output signal and input signal result, i.e. the flatness of the whole machine in combination A, is obtained. The flatness target value is determined based on the flatness condition.
[0047] Then, with a uniform input power, all frequencies under the current local oscillator are output in sufficiently fine frequency steps. However, this time, for each frequency signal output, the FPGA will use algorithms such as binary search to find the power coefficient that enables the gain to reach the flatness target value at the current frequency and record it to form a power coefficient table for combination A, which is then recorded in the storage area of the FPGA chip.
[0048] The above steps are repeated for combinations B, C, and so on, ultimately forming a two-dimensional coefficient matrix consisting of frequency, attenuator, and frequency converter local oscillator. When the radar power beacon outputs a signal, it automatically retrieves this matrix based on the frequency, attenuator attenuation value, and frequency converter local oscillator value, without manual intervention, thus achieving intelligent automatic flatness adjustment. The entire process of forming the coefficient matrix is automatically completed by the radar power beacon and related instruments under program control.
[0049] The resulting two-dimensional power coefficient matrix of the "frequency-link combination" is shown in Table 2:
[0050] Table 2
[0051] This embodiment focuses on a power beacon receiver for an ultra-wideband radar, operating in the 5GHz and 6GHz frequency bands. In a radar system, the power beacon receiver is used to simulate target reflection signals to assist in radar calibration. Traditional power beacon receivers have a signal gain of 43dB at 5GHz, but a gain as high as 46dB at 6GHz, a gain difference of 3dB, which leads to radar measurement errors.
[0052] When the radar power beacon unit outputs a signal, it can automatically find the matrix based on the frequency, attenuator attenuation value, and frequency converter local oscillator value without manual intervention, thus achieving intelligent automatic leveling of flatness.
[0053] The automatic adjustment method for radar power beacon flatness provided in this embodiment adopts a two-dimensional power coefficient matrix of "frequency-link combination" and combines the linkage control of FPGA chip and DA chip. The specific adjustment method is as follows:
[0054] 1. Power coefficient matrix generation
[0055] Link combinations are set up for the 5GHz and 6GHz frequencies respectively, and gain data is scanned and recorded. Taking combination A as an example, the 5GHz gain is 43dB and the 6GHz gain is 46dB. The 6GHz signal needs to be reduced by 3dB. This power difference is converted into a power coefficient (corresponding to the DA chip control code) and stored in the "Frequency-Link Combination" table.
[0056] To cover the entire operating frequency band, a frequency scan range is set, and the frequency step for each scan is determined. For example, between 5 GHz and 6 GHz, a frequency scan is performed in 10 MHz steps.
[0057] Set the standard input signal: Use a signal source to generate a standard power input signal and input it into the power beacon. For example, set the input signal power to 0dBm.
[0058] Traverse link combinations and frequency points: Test each link combination and each frequency point. For example, for combination A, measure the actual output gain at 5 GHz and 6 GHz frequencies respectively.
[0059] Measure the actual output gain: Use a power meter to measure the actual output gain of the power beacon at the current link combination and frequency point. For example, in combination A, the actual output gain at 5 GHz is measured to be 43 dB, and the actual output gain at 6 GHz is 46 dB.
[0060] Calculate the difference: Compare the actual output gain with the target gain and calculate the difference. The target gain can be set to the desired gain value at all frequency points, such as 43dB. For example, in combination A, the difference is 0dB (43-43) at 5GHz and +3dB (46-43) at 6GHz.
[0061] Convert to power factor: The calculated difference is converted into a corresponding power factor to control the output power of the DA chip. There is a correspondence between the power factor and the difference; for example, a difference of +3dB corresponds to a power factor that reduces the DA chip power by 3dB.
[0062] Convert to power factor: The calculated difference is converted into a corresponding power factor to control the output power of the DA chip. There is a correspondence between the power factor and the difference; for example, a difference of +3dB corresponds to a power factor that reduces the DA chip power by 3dB.
[0063] 2. The 5GHz and 6GHz signals emitted by the radar are received by the power beacon unit, preliminarily processed by the AD chip, and then sent to the FPGA chip. The FPGA chip performs frequency mixing processing on the radio frequency signal to the intermediate frequency (IF), and then performs flattening of the IF signal in the digital domain. The specific method for flattening is as follows:
[0064] First, the FPGA chip processes the digitized intermediate frequency signal to obtain its frequency (5GHz / 6GHz), bandwidth, frequency modulation speed, and power information. The frequency information can determine the local oscillator level, and combined with the preset gain information, the receive attenuation level and transmit attenuation level are determined to obtain the link combination A.
[0065] Then, based on the above information, the link combination and the frequency of the signal to be transmitted are determined (calculated by combining the original signal frequency, bandwidth, and frequency modulation speed). Then, the corresponding power coefficient is found by traversing the preset flatness power coefficient table of the FPGA chip. The signal power is increased or decreased according to the coefficient to achieve signal flatness correction.
[0066] The FPGA chip locates the power coefficient (corresponding to -3dB compensation) for 4GHz in combination A within the "frequency-link combination" matrix. This coefficient is then sent to the DA chip. Before restoring the signal to an analog signal, the DA chip reduces the 6GHz signal power by 3dB in 0.01dB steps. After adjustment, the 6GHz output gain decreases from 46dB to 43dB, matching the 5GHz gain, thus completing the leveling process.
[0067] If the link combination switches to another state (such as combination B) during operation, the FPGA automatically updates the power factor to ensure the leveling effect.
[0068] As described above, although the invention has been shown and described with reference to the specified preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims
1. A method for automatic adjustment of flatness of a radar power beaconer, comprising a receive chain, a digital radio frequency memory (DRFM) unit and a transmit chain, characterized in that, The digital radio frequency memory (DRFM) unit comprises an AD conversion chip, an FPGA chip and a DA conversion chip, the FPGA chip is preset with a flatness power coefficient table which is a two-dimensional power coefficient matrix of "frequency-link combination"; The AD conversion chip converts an analog signal transmitted by a receiving link into a digital signal; The FPGA chip traverses the flatness power coefficient table according to the frequency and link combination of the received digital signal and outputs a corresponding digital power compensation value; The DA conversion chip performs step adjustment of 0.01 dB on the signal amplitude according to the received digital power compensation value.
2. A method for automatic adjustment of flatness of a radar power beaconer according to claim 1, characterized in that, The generation method of the flatness power coefficient table is as follows: S2.1 sets a frequency conversion local oscillator and an attenuator to the i-th link combination; S2.2 scans all frequencies under the current local oscillator with a uniform input power, records the difference between the actual output gain and the target gain of each frequency point, and stores the difference converted into a compensation code value; S2.3 cyclically executes S2.1 and S2.2 until all link combinations are completed, forming a two-dimensional power coefficient matrix of "frequency-link combination".
3. A method for automatic adjustment of flatness of a radar power beaconer according to claim 2, characterized in that, The receiving attenuator has two positions, the transmitting attenuator has two positions, and the local oscillator has two positions, so that the beacon machine has eight local oscillator attenuations, and the link combinations are as shown in the following table: ； The two-dimensional power coefficient matrix of "frequency-link combination" formed is as shown in the following table: ； a, b, c, d...x, y, z in the above table are frequencies in the intermediate frequency range.
4. The method of claim 1, wherein, The FPGA chip performs mixing processing of the radio frequency signal to the intermediate frequency, and then performs flatness calibration of the intermediate frequency signal in the digital domain.
5. The method of claim 1, wherein, The specific method of the flatness calibration is as follows: Firstly, the FPGA chip processes the digitized intermediate frequency signal to obtain its frequency, bandwidth, frequency modulation speed and power information, wherein the frequency information can determine the local oscillator position, and the preset gain information can determine the receiving attenuator position and the transmitting attenuator position; Then, according to the above information, the link combination and the signal frequency to be transmitted currently are determined, and then the corresponding power coefficient is searched in the flatness power coefficient table preset in the FPGA chip, and the signal power is increased or decreased according to the coefficient.