Method for manufacturing a patch bar, optical waveguide network chip and optical quantum computer

Abstract

The application provides a preparation method of a patch strip, an optical waveguide network chip and an optical quantum computer, and relates to the technical field of optical communication. The preparation method comprises the following steps: sequentially forming a buried oxide layer and a waveguide layer on a first substrate, and making the waveguide layer form a plurality of nanotines arranged in an array; etching the buried oxide layer to form a plurality of first grooves in the buried oxide layer, and forming oxide columns between adjacent first grooves, wherein the nanotines are located on the oxide columns; bonding a second substrate to the waveguide layer through an adhesive, and making the adhesive away from the second substrate extend into the first grooves to form a first adhesive layer; making the adhesive close to the second substrate and not extending into the first grooves form a second adhesive layer; removing the first substrate and the buried oxide layer; removing the first adhesive layer, and making the second adhesive layer form a plurality of second grooves, and forming second adhesive columns between adjacent second grooves, wherein the nanotines are located in the second adhesive columns; and splitting the second substrate along the second grooves to obtain a plurality of patch strips. The nanotines are completely transferred to the second substrate, and reliable patching is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of optical communication, in particular to a patch strip preparation method, an optical waveguide network chip and an optical quantum computer. BACKGROUND

[0002] With the rapid development of optical quantum computing and other applications, there is an increasing demand for large-size optical waveguide network chips, especially when a higher number of optical qubits is implemented, it is urgent to develop super-large-size optical waveguide network technology. However, the existing electron beam lithography (EBL) technology and deep ultraviolet lithography (DUV) technology have certain limitations in directly manufacturing super-large-size optical waveguide networks. These traditional lithography technologies face challenges in precision and scale expansion, and it is difficult to meet the manufacturing needs of large-scale optical waveguide networks.

[0003] To solve this problem, one possible solution is to design optical waveguide networks in blocks, that is, to use DUV lithography technology to manufacture multiple copies of optical waveguide networks on a wafer; then, another wafer is used for the second DUV lithography to prepare another group of optical waveguide network copies. After completing the manufacturing of these copies, the corresponding optical waveguide network copies can be extracted from each wafer and spliced together through precise positioning, thereby forming a super-large-size optical waveguide network. Through this splicing method, a larger scale optical waveguide network design can be completed within a limited lithography area. In order to connect these optical waveguide network copies, connecting pieces (such as Nanoteeth structures) can be used to connect the block-designed optical waveguide network copies with low loss, and finally form a super-large-size optical waveguide network. However, if the Nanoteeth structure is manufactured in the conventional way, there will be some problems:

[0004] In the existing conventional silicon-on-insulator (SOI) preparation and thinning process, curling and peeling phenomena are prone to occur, which affects the stability of the Nanoteeth patch strip; when the silicon substrate is removed, only the buried oxide layer is left, which is prone to wave-like undulation and may cause the formation of cracks. The direction and length of the cracks are uncontrollable, and when the cracks pass through the Nanoteeth area, the silicon waveguide may be broken, which cannot meet the requirement of low transmission loss; and in the existing conventional cutting process, the composite structure cannot be directly mechanically cut, and it is difficult to divide multiple Nanoteeths prepared on a SOI wafer at the same time into actual Nanoteeth patch strips for connection, thereby affecting the production efficiency and preparation precision. SUMMARY

[0005] The embodiment of the application aims to provide a patch strip preparation method, an optical waveguide network chip and an optical quantum computer, which can solve the problems in the prior art, ensure high stability and high reliability in the bonding transfer process, realize low-loss connection of the optical waveguide network copy, and also ensure production efficiency and preparation accuracy.

[0006] In one aspect of the embodiment of the application, a patch strip preparation method is provided, which comprises the following steps.

[0007] A buried oxide layer and a waveguide layer are sequentially formed on a first substrate, and the waveguide layer is formed into a plurality of nanotines arranged in an array;

[0008] The buried oxide layer is etched to form a plurality of first grooves in the buried oxide layer, and an oxide column is formed between adjacent first grooves, and the nanotines are located on the oxide column;

[0009] The second substrate is bonded to the waveguide layer through an adhesive, the adhesive away from the second substrate extends into the first grooves to form a first adhesive layer, and the adhesive close to the second substrate and not extending into the first grooves forms a second adhesive layer;

[0010] The first substrate and the buried oxide layer are removed;

[0011] The first adhesive layer is removed, and the second adhesive layer is formed into a plurality of second grooves, a second adhesive column is formed between adjacent second grooves, and the nanotines are located in the second adhesive column;

[0012] The second substrate is cracked along the second grooves to obtain a plurality of patch strips.

[0013] Optionally, the buried oxide layer and the waveguide layer are sequentially formed on the first substrate, and the waveguide layer is formed into a plurality of nanotines arranged in an array, which comprises the following steps.

[0014] The buried oxide layer and the waveguide layer are sequentially formed on the first substrate;

[0015] The waveguide layer is photoetched to form a plurality of nanotines in the waveguide layer.

[0016] Optionally, the buried oxide layer is etched to form a plurality of first grooves in the buried oxide layer, and an oxide column is formed between adjacent first grooves, and the nanotines are located on the oxide column, which comprises the following steps.

[0017] The depth of the first groove along the first direction is at least greater than 1.5 um, the width of the first groove along the second direction is at least greater than 10 um, the etching period of the plurality of first grooves along the second direction is less than 1000 um, and the etching period along the third direction is less than 400 um; the first direction, the second direction and the third direction are perpendicular to each other.

[0018] Optionally, the first substrate and the buried oxide layer are removed, which comprises the following steps.

[0019] thinning the first substrate;

[0020] removing the remaining first substrate after thinning by a deep silicon etching process;

[0021] dry etching the buried oxide layer to form a plurality of arrayed first glue columns in the first glue layer, and the nanotines are located in the second glue layer and between adjacent first glue columns;

[0022] wet etching the remaining buried oxide layer to expose the nanotines.

[0023] Optionally, removing the first substrate and the buried oxide layer comprises:

[0024] thinning the first substrate;

[0025] removing the remaining first substrate after thinning by a deep silicon etching process;

[0026] attaching the second substrate to the third substrate, and wrapping the third substrate around the second substrate;

[0027] etching the buried oxide layer;

[0028] wet etching the remaining buried oxide layer to expose the nanotines.

[0029] Optionally, wet etching the remaining buried oxide layer to expose the nanotines comprises:

[0030] etching the remaining buried oxide layer with an ammonium fluoride solution.

[0031] Optionally, the first substrate is a silicon substrate, the buried oxide layer is a silicon dioxide layer, the waveguide layer is a silicon waveguide, and the second substrate is glass.

[0032] Optionally, in the thickness direction, the first substrate is 350-450 um, the buried oxide layer is 2-4 um, the waveguide layer is 210-230 nm, the second glue layer is 130-150 um, and the second substrate is 500-600 um.

[0033] In another aspect of the embodiments of the present application, a photonic waveguide network chip is provided, comprising: a plurality of photonic chips connected by the patch strip obtained by the patch strip preparation method.

[0034] In still another aspect of the embodiments of the present application, a photonic quantum computer is provided, comprising: a quantum light source, a detector, and the photonic chip of the photonic waveguide network chip.

[0035] The preparation method of the patch strip, the optical waveguide network chip and the optical quantum computer provided by the embodiment of the application completely transfer the nano-tooth array structure prepared on the waveguide layer to the second substrate through the adhesive, adopt the adhesive with appropriate adhesive force, enable the nano-tooth to be firmly bonded on the second substrate, avoid the curling and the adhesive falling off, and ensure the reliable connection of the nano-tooth; and the nano-tooth array structure and the second adhesive column form the interfitting state, form the physical mechanical interlocking, can effectively resist the shear force and the peeling force, and can also prevent the interface delamination and the curling; the tooth-shaped structure of the nano-tooth array can also disperse the concentrated stress in the bonding process to a larger area, avoid the local stress being too large to cause the material deformation, wrinkles or fragmentation; in addition, the second slot is arranged, the nano-tooth of the array is also dispersedly arranged, and the crack phenomenon caused by the concentrated arrangement of the nano-tooth is also avoided, and the structural integrity of the nano-tooth is ensured. Therefore, the arrangement of the nano-tooth array and the second slot in the application cooperates synergistically from the physical and material levels through the mechanical interlocking and the stress dispersion, realizes the high stability and the high reliability in the bonding transfer process; when the second slot is cracked, the problem of difficult cutting caused by the direct cutting of the adhesive can also be avoided, and the patch strip used for actual patching can be successfully separated from the nano-tooth array group, so that the convenient and reliable patching process is realized, and the separate optical waveguide is connected with low loss.

[0036] The prepared patch strip connects the photonic chip, and finally forms an optical waveguide network with a super large size, and completes the interconnection between the waveguides of the photonic chip.

[0037] When applied to an optical quantum computer, a quantum light source generates photons, and the photons are transmitted through the photonic chip of the optical waveguide network chip, and a detector converts the optical signal of the photonic chip into an electrical signal to realize the functions of transmission or display. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments of the application. It should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0039] Figure 1 is one of the process schematic diagrams of the preparation method of the patch strip provided by the embodiment of the application;

[0040] Figure 2 is the second process schematic diagram of the preparation method of the patch strip provided by the embodiment of the application;

[0041] Figure 3is the third schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0042] Figure 4 is the fourth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0043] Figure 5 is the fifth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0044] Figure 6 is the sixth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0045] Figure 7 is the seventh schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0046] Figure 8 is the eighth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0047] Figure 9 is the ninth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0048] Figure 10 is the tenth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0049] Figure 11 is the eleventh schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0050] Figure 12 is the twelfth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0051] Figure 13 is the thirteenth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0052] Figure 14 is the fourteenth schematic diagram of the preparation method of the patch strip provided in the embodiment;

[0053] Figure 15 is a sample diagram of the PDMS adhesive after the SOI is thinned and curled off;

[0054] Figure 16 is a diagram of the wrinkled and fragmented nanotooth array prepared without grooving;

[0055] Figure 17 is a diagram of the nanotooth array transferred after the grooving treatment of the preparation method of the patch strip provided in the embodiment;

[0056] Figure 18 is a photograph of the nanotooth array used for waveguide connection after the patch strip is pasted in the embodiment;

[0057] Figure 19 This is a schematic diagram of the optical waveguide network chip structure provided in this embodiment.

[0058] Icons: 100 - Patch strip; 10 - First substrate; 11 - Buried oxide layer; 12 - Waveguide layer; 120 - Nanotooth; 110 - First slot; 111 - Oxide pillar; 13 - Second substrate; 14 - Adhesive; 141 - First adhesive layer; 1410 - First adhesive pillar; 142 - Second adhesive layer; 1420 - Second slot; 1421 - Second adhesive pillar; 15 - Third substrate; F1 - First orientation; F2 - Second orientation. Detailed Implementation

[0059] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0060] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0061] It should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0062] This application provides a method for preparing a patch strip, the method comprising:

[0063] Step 200: A buried oxide layer 11 and a waveguide layer 12 are sequentially formed on the first substrate 10, and the waveguide layer 12 is arranged in an array of multiple nanotooths 120.

[0064] like Figure 1 As shown, a buried oxide layer 11 and a waveguide layer 12 are sequentially formed on the first substrate 10.

[0065] like Figure 2As shown, waveguide layer 12 is photolithographically patterned to form multiple nanotooth 120s on waveguide layer 12. For example, the first substrate 10 is an SOI (silicon-on-insulator) wafer, the buried oxide layer 11 is a silicon dioxide layer, and the waveguide layer 12 is a silicon (Si) layer. Nanoteeth (nanotooth 120) array Si waveguides are fabricated on the SOI wafer using positive photoresist EBL (electron beam lithography).

[0066] Combination Figure 19 As shown, the top view of the nanotooth 120 is a rhomboid structure that is wide in the middle and pointed at both ends. Of course, other similar shapes can also be used, as long as the two ends of the nanotooth 120 are pointed structures. When using this pointed structure to connect different photonic chips, the interlocking between the nanotooth 120 and the photonic chip is more reliable, which is beneficial to the reliability of the connection, so as to realize low-loss interconnection between different waveguides.

[0067] It should be noted that, in addition to SOI wafers, the first substrate 10 can also be other suitable optical waveguide materials such as LNOI (lithium niobate on insulator) and Si3N4 (silicon nitride).

[0068] In addition to EBL, other photolithography methods such as laser direct writing, contact exposure, and DUV (deep ultraviolet lithography) can also be used to fabricate nano-tooth 120. Furthermore, positive EBL photoresist can be replaced with various other photoresists such as negative photoresist to fabricate nano-tooth 120.

[0069] like Figure 3 As shown, positive adhesive contact exposure removes the large-area outer waveguide layer 12, leaving an array of nanotooth-shaped structures 120 on the top waveguide layer 12. The purpose of this step is to directly expose the soft adhesive of the subsequently formed Nanoteeth patch strip 100 on the surface to complete the bonding with the photonic chip.

[0070] The contact exposure in this step can also be replaced by other lithography methods such as laser direct writing or EBL.

[0071] Furthermore, without considering cost, the etching of waveguide layer 12 and the removal of the large-area top waveguide layer 12 can be performed in the same round of EBL, laser direct writing, contact exposure and other photolithography methods.

[0072] Step 201: Etch the buried oxide layer 11 to form a plurality of first slots 110 in the buried oxide layer 11, and form oxide pillars 111 between adjacent first slots 110, with nanotooth 120 located on the oxide pillars 111.

[0073] like Figure 4As shown, a negative photoresist contact etching process is used to etch a SiO2 buried oxide layer 11 with a thickness of approximately 3 micrometers (along the first direction F1). Multiple first slots 110 are formed within the buried oxide layer 11, and oxide pillars 111 capable of supporting nanotooth 120 are formed between adjacent first slots 110. The purpose of this step is to prevent the nanotooth 120 structure from breaking when the first substrate 10 is removed.

[0074] The depth of the first groove 110 along the first direction F1 should be at least greater than 1.5 micrometers, as deeper etching provides better protection for the nanotooth 120; the width of the first groove 110 along the second direction F2 should be at least greater than 10 micrometers, as wider etching also provides better protection for the nanotooth 120; the longitudinal (third direction) etching cycle of the first groove 110 should be less than 400 micrometers, and the transverse (second direction F2) etching cycle can be 100 micrometers to 1000 micrometers, as denser grooves provide better protection; the first direction F1, the second direction F2, and the third direction are perpendicular to each other; in specific fabrication, due to process error, the perpendicularity between the first direction F1, the second direction F2, and the third direction can be within a reasonable process error range.

[0075] In addition to the aforementioned negative photoresist contact exposure overlay, other similar photolithography methods can also be used to achieve the above-mentioned grooving effect, which will not be elaborated here.

[0076] For example, the etch depth of the buried oxide layer 11 is 3.3 micrometers, the etch width is 10 micrometers, the lateral etch cycle is 1000 micrometers, the longitudinal etch cycle is 100 micrometers, and the vertical etch method is adopted.

[0077] The oxide pillar 111 can have different shapes, such as trapezoidal, rectangular, etc. For example, the oxide pillar 111 is in... Figure 4 In the side view, it has a rectangular column shape. Rectangle has a significant advantage in resisting bending and torsional forces. Therefore, the rectangular oxide column 111 can better support the nanotooth 120, ensure the structural stability of the nanotooth 120 during the preparation process, and avoid phenomena such as breakage.

[0078] Correspondingly, a first groove 110 is formed between adjacent oxide pillars 111, and the shape of the first groove 110 corresponds to and matches the shape of the oxide pillar 111. The first groove 110 includes a horizontal and vertical grid structure. Different structures can be adopted for waveguides of different shapes (such as irregular, spiral, etc.), including irregular, spiral, and etching of all buried oxide layers 11 except for necessary areas.

[0079] Step 202: Bond the second substrate 13 to the waveguide layer 12 with adhesive 14. The adhesive 14 away from the second substrate 13 extends into the first groove 110 to form the first adhesive layer 141; the adhesive 14 that does not extend into the first groove 110 and is close to the second substrate 13 forms the second adhesive layer 142.

[0080] like Figure 5 As shown, for example, adhesive 14 may be a UV-curable adhesive; in some embodiments, NTT AT6001 is a UV-curable optical adhesive that can be used as adhesive 14 to bond the first substrate 10 to a second substrate 13 of appropriate thickness. The purpose of this step is to fix the waveguide layer 12 to the second substrate 13 together.

[0081] For example, the second substrate 13 is a glass substrate or other material, which is used to provide support for the waveguide layer 12 that is wrapped by NTT AT6001 after transfer. Transparent materials are easy to judge the bonding effect and easy to align, while opaque substrate materials can also be used.

[0082] During bonding, since the buried oxide layer 11 has a first groove 110, a portion of the adhesive 14 can extend into the first groove 110. The adhesive 14 extending into the first groove 110 is defined as the first adhesive layer 141, while the adhesive 14 not extending into the first groove 110 is defined as the second adhesive layer 142. The second adhesive layer 142 is close to the second substrate 13.

[0083] It should be noted that the adhesive 14 used here is generally a soft adhesive. Soft adhesives are soft polymer materials used in bonding processes to achieve flexible connections or functionalization between materials. They are flexible plastic materials that are soft at room temperature and do not require vulcanization. The NTT AT6001 in this application can also be replaced with other organic soft adhesives as adhesive 14. Adhesives with suitable adhesion and low shrinkage should be selected to reduce the chances of curling, wrinkling, and cracking, and to avoid the problem of difficulty in cutting the fragments later.

[0084] For example, an adhesive 14 with a viscosity of approximately 80 mPa·s to 300 mPa·s and a shrinkage rate of approximately 0.4% to 1.2% can be selected. An adhesive 14 with suitable viscosity has good flowability, which can reduce local accumulation and also provides strong adhesion, preventing curling. An adhesive 14 with low shrinkage can reduce internal stress after curing, thereby reducing the risk of wrinkling and breakage. In addition to the aforementioned UV soft adhesive and NTT AT6001, the adhesive 14 of this application can also be made of materials such as PU (polyurethane), TPE (thermoplastic elastomer), and TPU (thermoplastic polyurethane elastomer).

[0085] Step 203: Remove the first substrate 10 and the buried oxide layer 11.

[0086] like Figure 6 As shown, the first substrate 10 is thinned to approximately 100 micrometers by mechanical polishing or other thinning processes. The purpose of this step is to rapidly thin the first substrate 10, saving time for deep silicon etching.

[0087] like Figure 7 As shown, the remaining first substrate 10 is removed using deep silicon etching technology. The purpose of this step is to precisely remove the first substrate 10.

[0088] Without considering cost, deep silicon etching can be used to directly remove the first substrate 10, which is more than 100 micrometers in diameter, without the need for a thinning step.

[0089] like Figure 8 As shown, TMAH (tetramethylammonium hydroxide, a key chemical used in the developing process of photolithography, specifically as an alkaline aqueous developer) is used to remove any unetched silicon particles. The purpose of this step is to prevent the fabricated nanotooth 120 from being contaminated in subsequent processes, which would lead to increased losses.

[0090] like Figure 9 As shown, the remaining 3-micrometer-thick buried oxide layer 11 is dry-etched to remove approximately 2-micrometer-thick buried oxide layer 11, so that the first adhesive layer 141 forms multiple arrays of first adhesive pillars 1410, and the nanotooth 120 is located within the second adhesive layer 142 and between adjacent first adhesive pillars 1410.

[0091] The purpose of this step is to accelerate the removal of the buried oxide layer 11. The subsequent BOE (ammonium fluoride solution) has low corrosion efficiency for the transition state layer between silicon and silicon oxide. Prolonged immersion will cause the glass substrate used as the transfer substrate to also be corroded.

[0092] like Figure 10 As shown, the remaining buried oxide layer 11 is wet-etched to expose the nanotooth 120.

[0093] Specifically, BOE etching is used to remove the remaining buried oxide layer 11. The purpose of this step is to expose the surface of the soft adhesive, nano-tooth 120, for patch application. The nano-tooth 120 is exposed through the gap region between adjacent first adhesive pillars 1410.

[0094] In other embodiments, Figure 9 , Figure 10 The steps can also be replaced with Figure 13 , Figure 14 The second substrate 13 is attached to the third substrate 15, and the third substrate 15 completely covers the second substrate 13; then the buried oxide layer 11 is etched; the remaining buried oxide layer 11 is wet-etched to expose the nanotooth 120.

[0095] PDMS (polydimethylsiloxane, mainly used as the core material in soft lithography) can be used to attach the buried oxide layer 11, waveguide layer 12, adhesive 14, and glass surface of the glass substrate to the third substrate 15. Note that the glass substrate is completely encapsulated and protected by PDMS, which can prevent the glass substrate in the composite from being etched by BOE. After a sufficiently long soaking time, the buried oxide layer 11 can be completely removed.

[0096] It should be noted that PDMS can be replaced with other protective materials. Its purpose is to protect the glass substrate from contact with BOE, while the buried oxide layer 11 is exposed to contact with BOE.

[0097] Step 204: Remove the first adhesive layer 141 and form a plurality of second grooves 1420 in the second adhesive layer 142. Second adhesive pillars 1421 are formed between adjacent second grooves 1420, and nanotooth 120 is located in the second adhesive pillars 1421.

[0098] like Figure 11 As shown, laser processing removes the adhesive 14 material between the nanotooth 120, forming a second groove 1420 that extends to the surface of the second substrate 13. The purpose of this step is to directly expose the glass substrate to air for cutting. Compared to conventional removal methods, laser removal of the adhesive 14 material offers higher removal efficiency and precision.

[0099] Step 205: Split the second substrate 13 along the second slot 1420 to obtain multiple patch strips 100.

[0100] like Figure 12 As shown, the second substrate 13 is cut and cleaved to obtain patch strips 100. Laser cutting is used to obtain small patch strips 100 for patching. The patch strips 100 have nanotooth 120 and are supported by the second substrate 13.

[0101] For example, along the thickness direction (first direction F1), the first substrate 10 is 350um to 450um, the buried oxide layer 11 is 2um to 4um, the waveguide layer 12 is 210nm to 230nm, the second adhesive layer 142 is 130um to 150um, and the second substrate 13 is 500um to 600um.

[0102] In existing conventional silicon-on-insulator (SOI) fabrication and thinning processes, when using adhesives with low adhesion (such as PDMS) to fabricate Nanoteeth patches, if the silicon substrate is thinned to a certain thickness on the silicon dioxide buried oxide layer in SOI, curling can easily occur due to internal stress, causing the adhesive layer to detach and affecting the stability of the Nanoteeth patch. Figure 15 As shown.

[0103] Furthermore, in existing conventional SOI fabrication and thinning processes, when using adhesives with excessively strong bonding strength to fabricate Nanoteeth patches, wavy undulations can easily occur after the silicon substrate is removed, leaving only the buried oxide layer, potentially leading to crack formation. The direction and length of these cracks are uncontrollable, and when cracks traverse the Nanoteeth region, they can cause silicon waveguide breakage, failing to meet the requirements for low transmission loss. Figure 16 As shown.

[0104] On the other hand, UV adhesives shrink during the curing process, exhibiting a tendency to shrink after curing. When the silicon substrate is thick enough, its material strength is sufficient to effectively suppress this shrinkage. However, when the silicon substrate is thinned to a certain extent, its material strength is insufficient to resist the shrinkage of the UV adhesive, leading to wavy undulations on the adhesive surface and potentially causing cracks in the buried oxide layer 11, resulting in the breakage of the silicon waveguide. This phenomenon significantly affects quality control during the manufacturing process and the performance of the final product.

[0105] Using flexible soft adhesive materials for patching can also make them difficult to cut mechanically. Current cutting processes struggle to precisely cut them without damaging the structure, making it difficult to divide multiple Nanoteeth connectors fabricated simultaneously on an SOI wafer into usable Nanoteeth patch strips, thus impacting process efficiency and accuracy.

[0106] The above-mentioned problems can be solved by using the patch strip preparation method provided in this application embodiment. The patch strip preparation method provided in this application embodiment transfers the nanotooth 120 array structure prepared on the waveguide layer 12 completely onto the glass substrate using soft adhesive. Using an adhesive 14 with suitable adhesion, the nanotooth 120 can be firmly bonded to the glass substrate, avoiding curling and causing the adhesive 14 to fall off, thus ensuring the reliable connection of the nanotooth 120. Furthermore, the nanotooth 120 array structure and the second adhesive pillar 1421 form an interlocking state, forming a physical mechanical interlock, which can effectively resist shear force and peeling force, and also prevent interface delamination and curling. The tooth-shaped structure of the nanotooth 120 array can also disperse the concentrated stress during the bonding process to a larger area, avoiding excessive local stress that could cause material deformation, wrinkling, or breakage. In addition, the setting of the second slot 1420 also distributes the nanotooth 120 array, avoiding cracking caused by concentrated setting, and ensuring the structural integrity of the nanotooth 120. Therefore, the arrangement of the nanotooth 120 array in this application works synergistically from the physical and material levels through mechanical interlocking and stress dispersion, and the distribution of the nanotooth 120 through the second slot 1420 achieves high stability and high reliability in the bonding transfer process, thereby realizing a convenient and reliable patching process, and then connecting discrete optical waveguides with low loss.

[0107] Furthermore, the adhesive 14 with suitable adhesion can also avoid the problem of difficult cutting. In the final step of this application, when cutting the slit, the second substrate 13 is slit along the second groove 1420. The setting of the second groove 1420 avoids cutting the second adhesive layer 142 formed by NTT AT6001 material. At the same time, the laser cutting method can cut the second substrate 13 with precision without damaging the structure and with high cutting efficiency.

[0108] The aforementioned patch strip 100 connects the photonic chips, ultimately forming a large-scale optical waveguide network, completing the inter-waveguide interconnection of the photonic chips. For example, the photonic chip can be an LNOI photonic chip, or other photonic chips; this application does not specifically limit this. The patch strip fabrication method provided in this application embodiment can effectively avoid curling, wrinkling, and breakage. Figure 17 As shown, patch strips 100 for actual patching can be successfully separated from the nano-tooth 120 array group, and the cutting accuracy and cutting efficiency are both high.

[0109] Using the patch strip 100 and the alignment marks on the photonic chip, the patch strip 100 is attached to the interface of the adjacent chip of the photonic chip. A photograph of the completed patch installation is shown below. Figure 18 As shown, the seamless fit between the NTT AT6001 and the photonic chip can be seen through the transparent backplate glass, indicating a good bonding effect.

[0110] Reference Figure 19 As shown in the embodiments of this application, an optical waveguide network chip is also disclosed, including multiple photonic chips, which are connected by a patch strip 100 obtained by any of the patch strip preparation methods described above.

[0111] On the other hand, this application also provides an optical quantum computer, including a quantum light source, a detector, and a photonic chip of the aforementioned optical waveguide network chip.

[0112] In this system, quantum light sources generate photons, which are then transmitted through photonic chips in an optical waveguide network chip. A detector converts the optical signals from the photonic chips into electrical signals to achieve functions such as transmission or display.

[0113] The optical waveguide network chip and optical quantum computer have the same structure and beneficial effects as the patch strip fabrication method in the foregoing embodiments. The structure and beneficial effects of the patch strip fabrication method have been described in detail in the foregoing embodiments and will not be repeated here.

[0114] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for preparing a patch strip, characterized in that, include: A buried oxide layer and a waveguide layer are sequentially formed on a first substrate, and the waveguide layer is arranged in an array of multiple nanotooth-shaped structures. The buried oxide layer is etched to form a plurality of first slots within the buried oxide layer, and oxide pillars are formed between adjacent first slots, with the nanotooth located on the oxide pillars; A second substrate is bonded to the waveguide layer with an adhesive, and the adhesive extends into the first groove away from the second substrate to form a first adhesive layer; The adhesive that does not extend into the first groove but is close to the second substrate forms a second adhesive layer; Remove the first substrate and the buried oxide layer; Remove the first adhesive layer and form a plurality of second grooves in the second adhesive layer, and form second adhesive pillars between adjacent second grooves, with the nanotooth located within the second adhesive pillars; Multiple patch strips are obtained along the second substrate of the second slotted slit.

2. The method for preparing the patch strip according to claim 1, characterized in that, The step of sequentially forming a buried oxide layer and a waveguide layer on a first substrate, and forming multiple nanotooth arrays of the waveguide layer, includes: The buried oxide layer and the waveguide layer are sequentially formed on the first substrate; The waveguide layer is photolithographically etched to form a plurality of nanotooth-shaped structures on the waveguide layer.

3. The method for preparing the patch strip according to claim 1 or 2, characterized in that, The etching of the buried oxide layer to form a plurality of first slots within the buried oxide layer, with oxide pillars formed between adjacent first slots, and the nanotooth located on the oxide pillars, includes: The depth of the first groove along the first direction is at least greater than 1.5 μm, the width of the first groove along the second direction is at least greater than 10 μm, the etching period of the plurality of first grooves along the second direction is less than 1000 μm, and the etching period along the third direction is less than 400 μm; the first direction, the second direction and the third direction are perpendicular to each other.

4. The method for preparing the patch strip according to claim 3, characterized in that, The removal of the first substrate and the buried oxide layer includes: Thin the first substrate; The remaining first substrate after thinning is removed by deep silicon etching process; The buried oxide layer is dry etched to form a plurality of arrayed first adhesive pillars in the first adhesive layer. The nanotooth is located in the second adhesive layer and between adjacent first adhesive pillars. The remaining buried oxide layer is wet-etched to expose the nanotooth.

5. The method for preparing the patch strip according to claim 3, characterized in that, The removal of the first substrate and the buried oxide layer includes: Thin the first substrate; The remaining first substrate after thinning is removed by deep silicon etching process; The second substrate is attached to the third substrate, and the third substrate completely encloses the second substrate; Etch the buried oxide layer; The remaining buried oxide layer is wet-etched to expose the nanotooth.

6. The method for preparing the patch strip according to claim 4 or 5, characterized in that, The wet etching of the remaining buried oxide layer to expose the nanotooth includes: The remaining buried oxide layer was etched using an ammonium fluoride solution.

7. The method for preparing the patch strip according to claim 1, characterized in that, The first substrate is a silicon substrate, the buried oxide layer is a silicon dioxide layer, the waveguide layer is a silicon waveguide, and the second substrate is glass.

8. The method for preparing the patch strip according to claim 1 or 7, characterized in that, Along the thickness direction, the first substrate is 350um to 450um, the buried oxide layer is 2um to 4um, the waveguide layer is 210nm to 230nm, the second adhesive layer is 130um to 150um, and the second substrate is 500um to 600um.

9. An optical waveguide network chip, characterized in that, It includes multiple photonic chips, and the multiple photonic chips are connected by the patch strip obtained by the patch strip preparation method according to any one of claims 1 to 8.

10. An optical quantum computer, characterized in that, It includes a quantum light source, a detector, and a photonic chip as described in claim 9, which is a waveguide network chip.

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