SoC system control method and device, electronic equipment and readable storage medium

Abstract

The invention provides an SoC system control method and device, electronic equipment and a readable storage medium, and the method comprises the steps: controlling a CPU large core to generate a control instruction, and writing the control instruction into a register; the control register analyzes the control instruction, determines at least one target function module associated with the control instruction, generates a corresponding enable signal and sends the enable signal to a control circuit corresponding to each target function module; and aiming at the control circuit of each target function module, controlling the control circuit to receive and analyze the corresponding enable signal, generating control information and sending the control information to the corresponding target function module, so that each target function module is configured according to the control information and executes the control instruction. Therefore, the configuration time of the CPU for configuring the functional modules one by one through the on-chip internet can be reduced, and the control efficiency of the SoC system is further improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit control technology, and in particular to control methods, devices, electronic devices, and readable storage media for SoC systems. Background Technology

[0002] As integrated circuits integrate more and more functional modules, the entire SoC system becomes increasingly complex. Large SoC systems include multiple different functional modules. When the CPU core controls each functional module in the SoC system, it needs to transmit the corresponding configuration information to each functional module one by one through the on-chip interconnect network to complete the register configuration of each functional module. This results in a long data path to complete a control instruction and may also involve asynchronous circuits across clocks, which in turn leads to data processing delays and affects the control efficiency of the SoC system. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a control method, device, electronic device, and readable storage medium for a SoC system. Each functional module's subsystem has a control circuit, and a register connected to the CPU core is added to the SoC system. When the CPU core issues an instruction, it writes the control instruction into the connected register. After parsing the control instruction, the register generates an enable signal and sends it to each control circuit. After parsing the enable signal, the control circuit generates control information and sends it to the corresponding target functional module. This allows the control information to be sent to the corresponding target functional module, automatically completing the configuration and executing the control instruction. This reduces the configuration time required for the CPU to configure functional modules one by one via the on-chip interconnect network, thereby improving the control efficiency of the SoC system.

[0004] In a first aspect, embodiments of this application provide a control method for a SoC system, applied to an SoC system; the SoC system includes a CPU core, registers connected to the CPU core, and at least one functional module, each functional module having a corresponding control circuit within its subsystem; each control circuit is connected to the register; the control method includes: The CPU big core is controlled to generate control instructions, and the control instructions are written into the register; The register is controlled to analyze the control instruction, determine at least one target functional module associated with the control instruction, and generate a corresponding enable signal to be sent to the control circuit corresponding to each target functional module. For each target functional module, the control circuit receives and parses the corresponding enable signal, generates control information, and sends it to the corresponding target functional module so that each target functional module is configured according to the control information and executes the control command.

[0005] In one possible implementation, the control register analyzes the control instruction, determines at least one target functional module associated with the control instruction, and generates a corresponding enable signal to be sent to the control circuit corresponding to each target functional module, including: The register analyzes the control instruction to determine at least one target functional module associated with the control instruction and the corresponding operating mode of each target functional module; For each target functional module, a target number corresponding to the working mode is determined, and after generating a corresponding enable signal based on the target number, the enable signal is sent to the control circuit corresponding to each target functional module.

[0006] In one possible implementation, generating the corresponding enable signal based on the target sequence number includes: The target sequence number is converted into a binary sequence of a preset number of bits, and the binary sequence is determined as the enable signal.

[0007] In one possible implementation, generating the corresponding enable signal and sending it to the control circuit corresponding to each target functional module includes: Generate enable signals for each target functional module one by one, and send the corresponding control signals to each target functional module one by one; or, Simultaneously, enable signals are generated for each target functional module, and corresponding control signals are sent to each target functional module.

[0008] In one possible implementation, when the control instruction includes an initialization instruction, the control circuit for each target functional module controls itself to receive and parse the corresponding enable signal, generate control information, and send it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control instruction, including: For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, generates initialization control information, and sends it to the corresponding target functional module, so that each target functional module triggers its internal circuit to automatically complete the initialization configuration of the target functional module according to the configuration information.

[0009] In one possible implementation, when the control command includes a working mode switching command, the control circuit for each target functional module controls the control circuit to receive and parse the corresponding enable signal, generate control information, and send it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control command, including: For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, determines the corresponding target operating mode, and sends the target operating mode to the corresponding target functional module, so that each target functional module automatically switches to the target operating mode according to the configuration information of the target operating mode.

[0010] In one possible implementation, the SoC system further includes a small CPU core; before controlling the large CPU core to generate control instructions and writing the control instructions into the register, the control method further includes: The small CPU core loads the firmware and operating system program of the large CPU core from the off-chip flash memory, stores the firmware and operating system program in the on-chip random access memory, and controls the large CPU core to reset and release. The CPU big core reads the big core control instructions from the on-chip random access memory and executes the big core control instructions to complete the boot process for the CPU big core.

[0011] Secondly, embodiments of this application also provide a control device for a SoC system, applied to the SoC system; the SoC system includes a CPU core, registers connected to the CPU core, and at least one functional module, each functional module having a corresponding control circuit within its subsystem; each control circuit is connected to the register; the control device includes: The instruction writing module is used to control the CPU big core to generate control instructions and write the control instructions into the register; An enable signal sending module is used to control the register to analyze the control instruction, determine at least one target functional module associated with the control instruction, and generate a corresponding enable signal to send to the control circuit corresponding to each target functional module. The configuration module is used to control the control circuit of each target functional module to receive and parse the corresponding enable signal, generate control information and send it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control command.

[0012] Thirdly, embodiments of this application also provide an electronic device, including: a processor, a storage medium, and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the machine-readable instructions to perform the steps of the control method of the SoC system as described in any of the first aspects.

[0013] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the control method for the SoC system as described in any of the first aspects.

[0014] The control method, apparatus, electronic device, and readable storage medium for a SoC system provided in this application embodiment control the CPU big core to generate control instructions and write the control instructions into the registers. The control registers analyze the control instructions, determine at least one target functional module associated with the control instructions, and generate corresponding enable signals to be sent to the control circuits corresponding to each target functional module. For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, generates control information, and sends it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control instructions. In this way, a control circuit is set up inside the subsystem of each functional module, and a register connected to the CPU big core is added to the SoC system. When the CPU big core issues an instruction, it writes the control instruction into the connected register. After the register parses the control instruction, it generates an enable signal and sends it to each control circuit. After the control circuit parses the enable signal, it generates control information and sends it to the corresponding target functional module, so that the control information sent to the corresponding target functional module automatically completes the configuration and executes the control instructions. This can reduce the configuration time of the CPU configuring functional modules one by one through the on-chip interconnect network, thereby improving the control efficiency of the SoC system.

[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a control method for a SoC system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a SoC system in the prior art provided in the embodiments of this application; Figure 3 This is a schematic diagram of the SoC system provided in the embodiments of this application; Figure 4This is a schematic diagram of the structure of a control device for a SoC system provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0019] First, the applicable scenarios for this application will be introduced. This application can be applied to the field of integrated circuit control technology.

[0020] As integrated circuits integrate more and more functional modules, the entire SoC system becomes increasingly complex. Large SoC systems include multiple different functional modules. Specifically, before controlling the CPU's large core to start, it is necessary to control the CPU's small core to start. The specific startup process of the SoC system is as follows: SoC hardware circuit preparation, including stabilizing the system clock crystal and resetting / releasing; the CPU's small core reads instructions from the on-chip ROM and executes them, completing the CPU's small core startup; the CPU's small core controls the flash memory controller to load the firmware program from the external flash memory into the internal on-chip SRAM; the CPU's small core executes the program in the SRAM, completing the initialization of the on-chip interconnect network and the on-chip memory system DDR; after confirming the CPU's small core startup and completing the initialization of the on-chip memory system DDR, the CPU's small core loads the firmware program and operating system program of the CPU's large core from the external flash memory and stores them in the on-chip memory system DDR; the CPU's small core controls the CPU's large core to reset and release, reads control instructions from the DDR and executes them, completing the CPU's large core startup process; the CPU's small core controls the CPU's large core to reset and release, reads control instructions from the DDR and executes them. After the CPU big core completes its boot process, it begins to gradually load the firmware of functional modules such as the graphics processor, completing the boot process for these modules. The CPU big core then configures the registers of interfaces such as USB, initializing these IPs. Finally, it initializes other related components in the system. When the CPU big core controls the various functional modules in the SoC system, it needs to transmit the corresponding configuration information to each module individually via the on-chip interconnect network to complete the register configuration for each module. This results in a long data path for completing a control instruction and may also involve asynchronous circuits across clock cycles, leading to data processing delays and impacting the control efficiency of the SoC system.

[0021] Based on this, embodiments of this application provide a control method for a SoC system to reduce the configuration time of the CPU configuring functional modules one by one through the on-chip interconnect network, thereby improving the control efficiency of the SoC system.

[0022] Please see Figure 1 , Figure 1 This is a flowchart illustrating a control method for a SoC system provided in an embodiment of this application. Figure 1 As shown in the embodiments of this application, the control method for the SoC system includes: S101. Control the CPU big core to generate control instructions and write the control instructions into the register.

[0023] S102. The register is controlled to analyze the control instruction, determine at least one target functional module associated with the control instruction, and generate a corresponding enable signal to be sent to the control circuit corresponding to each target functional module.

[0024] S103. For each target functional module, the control circuit receives and parses the corresponding enable signal, generates control information, and sends it to the corresponding target functional module so that each target functional module is configured according to the control information and executes the control command.

[0025] The control method for the SoC system provided in this application embodiment includes a control circuit within the subsystem of each functional module and a register connected to the CPU core in the SoC system. When the CPU core issues an instruction, it writes the control instruction into the connected register. After parsing the control instruction, the register generates an enable signal and sends it to each control circuit. After parsing the enable signal, the control circuit generates control information and sends it to the corresponding target functional module. This allows the control information to be sent to the corresponding target functional module, which automatically completes the configuration and executes the control instruction. This reduces the configuration time of the CPU configuring each functional module through the on-chip interconnect network, thereby improving the control efficiency of the SoC system.

[0026] The exemplary steps of the embodiments of this application are described below: S101. Control the CPU big core to generate control instructions and write the control instructions into the register.

[0027] As integrated circuits incorporate more and more functional modules, the entire SoC (System-on-a-Chip) system becomes increasingly complex. Please refer to [link / reference]. Figure 2 , Figure 2 This is a schematic diagram of the structure of a SoC system in the prior art provided in the embodiments of this application, such as... Figure 2 As shown, a large SoC system includes a CPU big core, a CPU little core, on-chip read-only memory (ROM), off-chip flash memory (Flash), on-chip shared memory SRAM, PCIe interface, USB interface, Ethernet interface, audio subsystem, UFS interface, on-chip storage system DDR, graphics processing unit (GPU), embedded neural network processor (NPU), data processor (DPU), video processing unit (VPU), DMA controller, ISP interface, DP interface, and on-chip interconnect network. When the CPU big core controls the various functional modules in the SoC system, it needs to transmit the corresponding configuration information to each functional module one by one through the on-chip interconnect network to complete the register configuration of each functional module. This results in a long data path to complete a control instruction and may also involve asynchronous circuits across clocks, which in turn leads to data processing delays and affects the control efficiency of the SoC system.

[0028] Based on this, in the embodiments of this application, a control circuit is set inside the subsystem of each functional module, and a register connected to the CPU big core is added to the SoC system. When the CPU big core issues an instruction, it writes the control instruction into the connected register. After the register parses the control instruction, it generates an enable signal and sends it to each control circuit. After the control circuit parses the enable signal, it generates control information and sends it to the corresponding target functional module. This allows the control information to be sent to the corresponding target functional module to automatically complete the configuration and execute the control instruction. This can reduce the configuration time of the CPU configuring functional modules one by one through the on-chip interconnect network, thereby improving the control efficiency of the SoC system.

[0029] In one possible implementation, the SoC system includes CPU big cores and CPU little cores. Specifically, CPU big cores, also known as performance cores or P cores, focus on handling high-load, computationally intensive tasks, such as running large games, video rendering, or scientific computing. CPU big cores typically have higher clock frequencies and instructions per cycle to provide extreme single-threaded performance, but with relatively higher power consumption. Little cores, also known as energy-efficient cores or E cores, are responsible for lightweight, multi-threaded tasks, such as background programs (browser tabs, antivirus software) or system management. Little cores are smaller and consume less power, significantly improving energy efficiency and extending battery life. Before the CPU big core issues control commands, the CPU little cores need to be configured and started first, and then the startup process for the CPU big core is completed.

[0030] Specifically, before the step "the CPU big core generates control instructions and writes the control instructions into the register", the control method further includes: a1: The small CPU core loads the firmware and operating system program of the large CPU core from the off-chip flash memory, stores the firmware and operating system program in the on-chip random access memory, and controls the large CPU core to reset and release.

[0031] a2: The CPU big core reads the big core control instructions from the on-chip random access memory and executes the big core control instructions to complete the boot process for the CPU big core.

[0032] In one possible implementation, before controlling the CPU big core to start, it is necessary to control the CPU small core to start. Specifically, the SoC system startup process is as follows: SoC hardware circuit preparation work, including completing system clock crystal stabilization and reset release; the CPU small core reads instructions from the on-chip ROM and executes them to complete the startup of the CPU small core; the CPU small core controls the flash memory controller to load the firmware program from the external flash memory into the internal on-chip memory SRAM; the CPU small core executes the program in the SRAM to complete the initialization of the on-chip interconnect network and the on-chip memory system DDR.

[0033] Furthermore, after confirming the startup of the CPU small core and completing the initialization of the on-chip storage system DDR, the CPU small core loads the firmware and operating system programs of the CPU large core from the external flash memory, and stores the firmware and operating system programs in the on-chip storage system DDR; the CPU small core controls the CPU large core to reset and release, reads control instructions from DDR and executes control instructions to complete the startup process of the CPU large core.

[0034] In one possible implementation, after the CPU big core generates control instructions, it writes the control instructions into the nearest connected register. The register needs to analyze the control instructions, determine at least one target functional module involved in the current control instructions, and generate corresponding enable signals to be sent to the control circuit corresponding to each target functional module.

[0035] S102. The register is controlled to analyze the control instruction, determine at least one target functional module associated with the control instruction, and generate a corresponding enable signal to be sent to the control circuit corresponding to each target functional module.

[0036] In one possible implementation, after receiving the control instruction sent by the CPU big core, the register needs to analyze the control instruction, determine at least one target functional module involved in the control instruction, and determine the enable signal to be sent to each target functional module.

[0037] For example, if the control instruction sent by the current CPU core is to play a target video, then the target functional module that needs to execute the control instruction may include a video processing unit, etc. Therefore, it is necessary to identify the video processing unit as the target functional module and generate an enable signal for the video processing unit.

[0038] In one possible implementation, after receiving a control instruction, the register needs to determine the corresponding operating mode, and then determine the corresponding enable signal based on the corresponding operating mode.

[0039] Specifically, the step "register analyzes the control instruction, determines at least one target functional module associated with the control instruction, and generates a corresponding enable signal to be sent to the control circuit corresponding to each target functional module" includes: b1: The register analyzes the control instruction to determine at least one target functional module associated with the control instruction and the corresponding operating mode of each target functional module.

[0040] b2: For each target functional module, determine the target number corresponding to the working mode, and after generating the corresponding enable signal based on the target number, send the enable signal to the control circuit corresponding to each target functional module.

[0041] In this embodiment of the application, different working mode numbers can be predefined. After determining the working mode in the control command, the corresponding enable signal is set according to the target number corresponding to the working mode.

[0042] Here, the enable signal is a control signal used to enable or disable the working state of a device, module, or functional unit. In this embodiment, the enable signal can be a binary sequence of a preset number of bits, which represents the target sequence number of the working mode and thus transmits the corresponding working mode.

[0043] Specifically, the step "generating a corresponding enable signal based on the target sequence number" includes: c1: Convert the target sequence number into a binary sequence of a preset number of bits, and determine the binary sequence as the enable signal.

[0044] In one possible implementation, the preset number of bits can be 4 bits, corresponding to sixteen working modes, and the corresponding control circuit is also set to support the sixteen working modes of the corresponding functional module.

[0045] Specifically, the binary sequence corresponding to the sixteen working modes can be a binary sequence from 0000 to 1111, representing working modes 0-15.

[0046] For example, operating mode 1 can be set to initial startup configuration; operating mode 2 to normal operation mode; operating mode 3 to half-frequency operation mode, etc. When the control command is determined to be initial startup configuration, the target sequence number of the corresponding operating mode is determined to be 1, the generated binary sequence is 0001, and then 0001 is determined as the corresponding enable signal.

[0047] Furthermore, after the register determines the corresponding enable signal, the enable signal can be sent to the control circuit corresponding to each target functional module.

[0048] Specifically, the step "generating the corresponding enable signal and sending it to the control circuit corresponding to each target functional module" includes: d1: Generate enable signals for each target functional module one by one, and send the corresponding control signals to each target functional module one by one; or, d2: Simultaneously generate enable signals for each target functional module and send the corresponding control signals to each target functional module.

[0049] In one possible implementation, for the register, after parsing the control instruction and determining at least one target functional module involved in the control instruction, the register may determine the enable signal for each target functional module one by one, and then send the enable signal sequentially to the control circuit corresponding to the target functional module; alternatively, it may determine the enable signal for each target functional module simultaneously and send the enable signal for each target functional module to the control circuit corresponding to the target functional module simultaneously. The specific sending method can be determined according to the sending requirements and the register's data processing capabilities, and is not specifically limited here.

[0050] Furthermore, after the register sends the corresponding enable signal to the control circuit of the target function, the control circuit parses the enable signal, generates control information, and then controls each target function module.

[0051] S103. For each target functional module, the control circuit receives and parses the corresponding enable signal, generates control information, and sends it to the corresponding target functional module so that each target functional module is configured according to the control information and executes the control command.

[0052] In one possible implementation, after receiving the enable signal, the control circuit needs to compile the enable signal, determine the corresponding operating mode, and then generate control information to send to the corresponding target functional module for control.

[0053] For example, in the above example, the binary sequence of the enable signal 0001 is parsed to correspond to the working mode 1, that is, the initial startup configuration. The control circuit then generates initialization control information and sends it to the target functional module to complete the automatic initialization configuration.

[0054] Specifically, when the control instruction includes an initialization instruction, the step "for each target functional module's control circuit, controlling the control circuit to receive and parse the corresponding enable signal, generating control information and sending it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control instruction" includes: e1: For the control circuit of each target functional module, the control circuit receives and parses the corresponding enable signal, generates initialization control information, and sends it to the corresponding target functional module, so that each target functional module triggers its internal circuit to automatically complete the initialization configuration of the target functional module according to the configuration information.

[0055] In this embodiment of the application, when the control command includes an initialization command, the control circuit generates initialization control information and sends it to the target functional module. After receiving the initialization control information, each target functional module triggers its internal circuit to automatically complete the initialization configuration of the target functional module according to the configuration information, thereby completing the initialization control process.

[0056] In one possible implementation, when the control instructions include initialization instructions, the overall control flow of the SoC system can be as follows: upon initial startup, the CPU big core writes to the registers near it, and the registers are output through hardware connections and directly sent to the control circuits of each functional module. The control circuits of each functional module parse the received information to initialize the functional module, and automatically complete the initialization configuration of the functional module by triggering the internal circuit of the self-trigger.

[0057] In another possible implementation, during the operation of the SoC system, there may be a switching of operating modes. Here, the CPU can also send an operating mode switching instruction to complete the subsequent switching process.

[0058] For example, in the above example, the current SoC system is in normal operating mode, and the enable signal is a binary sequence of 0011. After parsing, the corresponding operating mode is operating mode 3, that is, operating mode with half frequency. The control circuit then generates operating mode switching control information with half frequency and sends it to the target functional module, thereby switching the operating mode.

[0059] Specifically, when the control command includes a working mode switching command, the step "for each target functional module's control circuit, control the control circuit to receive and parse the corresponding enable signal, generate control information and send it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control command" includes: f1: For the control circuit of each target functional module, control the control circuit to receive and parse the corresponding enable signal, determine the corresponding target working mode, and send the target working mode to the corresponding target functional module, so that each target functional module automatically switches to the target working mode according to the configuration information of the target working mode.

[0060] In this embodiment of the application, when the control command includes a working mode switching command, the control circuit generates working mode switching control information and sends it to the target functional module. After receiving the working mode switching control information, each target functional module automatically switches to the target working mode according to the configuration information of the target working mode.

[0061] In one possible implementation, when the control instruction includes a working mode switching instruction, the overall control flow of the SoC system can be as follows: when a functional module needs to switch working modes, the CPU big core writes to the registers near it, the registers are output through hardware connections, the control circuits of each functional module parse the value of the received register output, parse which working mode it is, and the control circuit module has the corresponding configuration to complete the mode switching of the target working mode, and automatically completes the configuration required for the mode switching of the functional module.

[0062] The control process of the SoC system in the embodiments of this disclosure will be illustrated below through specific examples: Please see Figure 3 , Figure 3 This is a schematic diagram of the SoC system provided in the embodiments of this application, such as... Figure 3As shown, the SoC system includes a CPU big core, a CPU little core, on-chip read-only memory (ROM), off-chip flash memory (Flash), on-chip shared memory (SRAM), a PCIe interface, a USB interface, an Ethernet interface, an audio subsystem, a UFS interface, an on-chip DDR memory system, a graphics processing unit (GPU), an embedded neural network processor (NPU), a data processor (DPU), a video processing unit (VPU), a DMA controller, an ISP interface, a DP interface, and an on-chip interconnect network. Registers are connected near the CPU big core. Control circuits are connected to the PCIe interface, USB interface, Ethernet interface, GMAC interface, audio subsystem, UFS interface, on-chip DDR memory system, GPU, NPU, DPU, VPU, DMA controller, ISP interface, DP interface, and on-chip interconnect network. These control circuits are hardware-connected to the registers. Based on the processing flow compatible with existing technologies, the additional registers and hardware-connected control circuits within each functional module subsystem enable each functional module to complete its initialization in parallel, independent of the CPU. By configuring each functional module serially, the overall initialization time is reduced. Previously, the CPU's large cores needed to traverse the on-chip network, crossing long distances or different clock domains. Now, by sending the initialization configuration to each functional module, only a single trigger signal needs to be output, and the configuration is handled by the functional module itself. This reduces the configuration time required for functional module switching. Furthermore, since the on-chip internet processes less data, the activity level of the on-chip network can be reduced, saving energy to some extent.

[0063] The control method for a SoC system provided in this application embodiment controls the CPU big core to generate control instructions and writes the control instructions into the register. The control register analyzes the control instructions, determines at least one target functional module associated with the control instructions, and generates corresponding enable signals to be sent to the control circuit corresponding to each target functional module. For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, generates control information, and sends it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control instructions. In this way, a control circuit is set up inside the subsystem of each functional module, and a register connected to the CPU big core is added to the SoC system. When the CPU big core issues an instruction, it writes the control instruction into the connected register. After the register parses the control instruction, it generates an enable signal and sends it to each control circuit. After the control circuit parses the enable signal, it generates control information and sends it to the corresponding target functional module, so that the control information sent to the corresponding target functional module automatically completes the configuration and executes the control instructions. This can reduce the configuration time of the CPU configuring functional modules one by one through the on-chip interconnect network, thereby improving the control efficiency of the SoC system.

[0064] Based on the same inventive concept, this application also provides a control device for a SoC system corresponding to the control method of the SoC system. Since the principle of the device in this application is similar to the control method of the SoC system described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0065] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a control device for a SoC system provided in an embodiment of this application. Figure 4 As shown, the control device 400 includes: Instruction writing module 410 is used to control the CPU big core to generate control instructions and write the control instructions into the register; The enable signal sending module 420 is used to control the register to analyze the control instruction, determine at least one target functional module associated with the control instruction, and generate a corresponding enable signal to send to the control circuit corresponding to each target functional module. The configuration module 430 is used to control the control circuit of each target functional module to receive and parse the corresponding enable signal, generate control information and send it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control command.

[0066] In one possible implementation, when the enable signal sending module 420 controls the register to analyze the control instruction, determine at least one target functional module associated with the control instruction, and generate a corresponding enable signal to send to the control circuit corresponding to each target functional module, the enable signal sending module 420 is configured to: The register analyzes the control instruction to determine at least one target functional module associated with the control instruction and the corresponding operating mode of each target functional module; For each target functional module, a target number corresponding to the working mode is determined, and after generating a corresponding enable signal based on the target number, the enable signal is sent to the control circuit corresponding to each target functional module.

[0067] In one possible implementation, when the enable signal sending module 420 is used to generate a corresponding enable signal based on the target sequence number, the enable signal sending module 420 is configured to: The target sequence number is converted into a binary sequence of a preset number of bits, and the binary sequence is determined as the enable signal.

[0068] In one possible implementation, when the enable signal sending module 420 generates a corresponding enable signal and sends it to the control circuit corresponding to each target functional module, the enable signal sending module 420 is used to: Generate enable signals for each target functional module one by one, and send the corresponding control signals to each target functional module one by one; or, Simultaneously, enable signals are generated for each target functional module, and corresponding control signals are sent to each target functional module.

[0069] In one possible implementation, when the control instruction includes an initialization instruction, the configuration module 430 controls the control circuit for each target functional module to receive and parse the corresponding enable signal, generate control information, and send it to the corresponding target functional module, so that each target functional module is configured according to the control information. When executing the control instruction, the configuration module 430 is used to: For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, generates initialization control information, and sends it to the corresponding target functional module, so that each target functional module triggers its internal circuit to automatically complete the initialization configuration of the target functional module according to the configuration information.

[0070] In one possible implementation, when the control command includes a working mode switching command, the configuration module 430 controls the control circuit for each target functional module to receive and parse the corresponding enable signal, generate control information, and send it to the corresponding target functional module, so that each target functional module is configured according to the control information. When executing the control command, the configuration module 430 is used to: For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, determines the corresponding target operating mode, and sends the target operating mode to the corresponding target functional module, so that each target functional module automatically switches to the target operating mode according to the configuration information of the target operating mode.

[0071] In one possible implementation, the SoC system further includes a small CPU core; the control device 400 further includes a large CPU core startup module (not shown in the figure), the large CPU core startup module being used for: The small CPU core loads the firmware and operating system program of the large CPU core from the off-chip flash memory, stores the firmware and operating system program in the on-chip random access memory, and controls the large CPU core to reset and release. The CPU big core reads the big core control instructions from the on-chip random access memory and executes the big core control instructions to complete the boot process for the CPU big core.

[0072] The control device for the SoC system provided in this application embodiment controls the CPU big core to generate control instructions and writes the control instructions into the register. The control register analyzes the control instructions, determines at least one target functional module associated with the control instructions, and generates corresponding enable signals to be sent to the control circuit corresponding to each target functional module. For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, generates control information, and sends it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control instructions. In this way, a control circuit is set up inside the subsystem of each functional module, and a register connected to the CPU big core is added to the SoC system. When the CPU big core issues an instruction, it writes the control instruction into the connected register. After the register parses the control instruction, it generates an enable signal and sends it to each control circuit. After the control circuit parses the enable signal, it generates control information and sends it to the corresponding target functional module, so that the control information sent to the corresponding target functional module automatically completes the configuration and executes the control instructions. This can reduce the configuration time of the CPU configuring functional modules one by one through the on-chip interconnect network, thereby improving the control efficiency of the SoC system. Please see Figure 5 , Figure 5This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 As shown, the electronic device 500 includes a processor 510, a memory 520, and a bus 530.

[0073] The memory 520 stores machine-readable instructions executable by the processor 510. When the electronic device 500 is running, the processor 510 and the memory 520 communicate via the bus 530. When the machine-readable instructions are executed by the processor 510, they can perform the operations described above. Figure 1 The steps of the SoC system control method in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0074] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 The steps of the SoC system control method in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0075] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0076] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0079] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A control method for a SoC system, characterized in that, This is applied to a System-on-a-Chip (SoC) system; the SoC system includes a CPU core, registers connected to the CPU core, and at least one functional module, each functional module having a corresponding control circuit within its subsystem; each control circuit is connected to the register; the control method includes: The CPU big core is controlled to generate control instructions, and the control instructions are written into the register; The register is controlled to analyze the control instruction, determine at least one target functional module associated with the control instruction, and generate a corresponding enable signal to be sent to the control circuit corresponding to each target functional module. For each target functional module, the control circuit receives and parses the corresponding enable signal, generates control information, and sends it to the corresponding target functional module so that each target functional module is configured according to the control information and executes the control command.

2. The control method according to claim 1, characterized in that, The control register analyzes the control instruction, determines at least one target functional module associated with the control instruction, and generates a corresponding enable signal to be sent to the control circuit corresponding to each target functional module, including: The register analyzes the control instruction to determine at least one target functional module associated with the control instruction and the corresponding operating mode of each target functional module; For each target functional module, a target number corresponding to the working mode is determined, and after generating a corresponding enable signal based on the target number, the enable signal is sent to the control circuit corresponding to each target functional module.

3. The control method according to claim 2, characterized in that, The step of generating the corresponding enable signal based on the target sequence number includes: The target sequence number is converted into a binary sequence of a preset number of bits, and the binary sequence is determined as the enable signal.

4. The control method according to claim 1, characterized in that, The generation of the corresponding enable signal and its transmission to the control circuit corresponding to each target functional module includes: Generate enable signals for each target functional module one by one, and send the corresponding control signals to each target functional module one by one; or, Simultaneously, enable signals are generated for each target functional module, and corresponding control signals are sent to each target functional module.

5. The control method according to claim 1, characterized in that, When the control instruction includes an initialization instruction, the control circuit for each target functional module controls the control circuit to receive and parse the corresponding enable signal, generate control information, and send it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control instruction, including: For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, generates initialization control information, and sends it to the corresponding target functional module, so that each target functional module triggers its internal circuit to automatically complete the initialization configuration of the target functional module according to the configuration information.

6. The control method according to claim 1, characterized in that, When the control command includes a working mode switching command, the control circuit for each target functional module controls the control circuit to receive and parse the corresponding enable signal, generate control information and send it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control command, including: For each target functional module's control circuit, the control circuit receives and parses the corresponding enable signal, determines the corresponding target operating mode, and sends the target operating mode to the corresponding target functional module, so that each target functional module automatically switches to the target operating mode according to the configuration information of the target operating mode.

7. The control method according to claim 1, characterized in that, The SoC system further includes a small CPU core; before controlling the large CPU core to generate control instructions and writing the control instructions into the register, the control method further includes: The small CPU core loads the firmware and operating system program of the large CPU core from the off-chip flash memory, stores the firmware and operating system program in the on-chip random access memory, and controls the large CPU core to reset and release. The CPU big core reads the big core control instructions from the on-chip random access memory and executes the big core control instructions to complete the boot process for the CPU big core.

8. A control device for a SoC system, characterized in that, This is applied to a System-on-a-Chip (SoC) system; the SoC system includes a CPU core, registers connected to the CPU core, and at least one functional module, each functional module having a corresponding control circuit within its subsystem; each control circuit is connected to the register; the control device includes: The instruction writing module is used to control the CPU big core to generate control instructions and write the control instructions into the register; An enable signal sending module is used to control the register to analyze the control instruction, determine at least one target functional module associated with the control instruction, and generate a corresponding enable signal to send to the control circuit corresponding to each target functional module. The configuration module is used to control the control circuit of each target functional module to receive and parse the corresponding enable signal, generate control information and send it to the corresponding target functional module, so that each target functional module is configured according to the control information and executes the control command.

9. An electronic device, characterized in that, include: The system includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the steps of the control method for the SoC system as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the control method for the SoC system according to any one of claims 1 to 7.

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