Method and system for writing data in power support component failure mode

Abstract

A method performed by a data storage device includes: receiving, by a controller of the data storage device, data from a host device; detecting, by a controller of the data storage device, a fault in a power support component of the data storage device; creating, by the controller, a single level cell (SLC) block comprising one or more groups of memory cells from the one or more multi-level cell blocks in persistent memory of the data storage device based on the value of the predefined data storage parameter; and storing, by the controller, the data in the SLC block.

Description

Cross Reference to Related Applications

[0001] This application is based on and claims priority to Indian Provisional Patent Application No. 202441040494, filed on May 24, 2024, and Indian Patent Application No. 202441040494, filed on August 13, 2024, in the Indian Patent Office, the disclosures of which are incorporated by reference in their entireties. TECHNICAL FIELD

[0002] The present disclosure relates generally to data storage devices. More specifically, the present disclosure relates to a method and system for writing data in a power support component failure mode. BACKGROUND

[0003] Data storage devices store data and instructions to be processed in a computer system. These data storage devices can include solid state drives (SSDs), hard disk drives (HDDs), and the like. Data storage devices include two types of memory, such as non-persistent memory and persistent memory. Non-persistent memory is a temporary storage device, and data is erased when the power of the data storage device is turned off. Persistent memory is a permanent storage device, and data is retained even when the power of the data storage device is turned off.

[0004] Reference Figure 1 , the storage device includes non-persistent memory 104 and persistent memory 106. Typically, the non-persistent memory 104 receives data to be stored in the data storage device from the host device 102. When the non-persistent memory 104 receives data from the host device 102, the data is sent to a multi-level cell block in the persistent memory 106 to store the data permanently in the data storage device. After filling all the storage cells in the storage cell group (WL 0, WL 1, …, WL N) with data, the multi-level cell block is processed. Thus, storage capacity waste and performance degradation of the persistent memory 106 can be avoided. Therefore, in a normal mode, when the data storage device is powered on and receives data equivalent to the total bit capacity of the storage cell group (WL 0, WL 1, …, WL N), the non-persistent memory 104 transfers the data to the persistent memory 106 unit once to program the multi-level cell. The total bit capacity refers to the total number of data bits that each storage cell group (WL 0, WL 1, …, WL N) can occupy. For example, the capacity of the multi-level cell can be 96k bits, and thus, when the non-persistent memory 104 receives 96k bits of data from the host device 102, the data is transferred to the persistent memory 106 for storage.

[0005] In certain cases, when the power to the data storage device is turned off, a power support component such as a capacitor can power the data storage device to store the data into the persistent memory 106 to achieve data reliability. Further, if the power support component fails, the data storage device enters a Forced Unit Access (FUA) mode to achieve data reliability as shown in Figure 2

[0006] In the FUA mode, when the non-persistent memory 204 receives data from the host device 202, the non-persistent memory 204 sends the data to the persistent memory 206 without waiting to receive data equivalent to the total bit capacity of a group of memory cells (WL 0, WL 1, …, WLN). Thus, in the FUA mode, if the number of data bits received from the host device 202 is less than the total bit capacity of a group of memory cells (WL 0, WL 1, …, WL N), the non-persistent memory 204 sends it to the group of memory cells (WL 0, WL 1, …, WL N) in the persistent memory 206, while the remaining memory cells in the group of memory cells are filled with dummy data. For example, assume that the capacity of each group of memory cells can be 96k. If only 4k of data is received from the host device 202 (as shown in the memory cell group MLC WL 1), the non-persistent memory 204 transfers the 4k data to the persistent memory 206, and the remaining 92k capacity of the memory cells can be filled with dummy data for processing the memory cell group MLC WL 1. Thus, in the FUA mode, the non-persistent memory 204 can not wait for data equivalent to the total bit capacity of a group of memory cells (WL 0, WL 1, …, WL N). Thus, in the FUA mode, while processing the multi-level cells, the memory cells with dummy data are also processed in addition to the memory cells filled with data. Thus, for processing the number of data bits that is less than the total capacity of a group of memory cells, the amount of time required is the same as the amount of time required to process data equivalent to the total bit capacity of a group of memory cells (WL 0, WL 1, …, WL N) because the dummy data in the memory cells are also processed along with the data. This causes a performance degradation of the data storage device and requires more time to process the number of data bits that is less than the total capacity of a group of memory cells compared to the total capacity of a group of memory cells. Further, the dummy data filled along with the data received from the host device 202 can cause a waste of storage capacity of the memory cells in the persistent memory 206. SUMMARY

[0007] ​According to an aspect of the disclosure, a method performed by a data storage device includes receiving, by a controller of the data storage device, data from a host device, detecting, by the controller of the data storage device, a failure in a power support component of the data storage device, creating, by the controller, a single level cell (SLC) block including one or more groups of storage cells in a persistent memory of the data storage device from one or more multi-level cell blocks based on values of predefined data storage parameters, and storing, by the controller, the data in the SLC block.

[0008] According to an aspect of the disclosure, a data storage device includes a persistent memory, a non-persistent memory, and a controller configured to receive data from a host device, detect a failure in a power support component of the data storage device, create, based on values of predefined data storage parameters, a single level cell (SLC) block including one or more groups of storage cells in the persistent memory of the data storage device from one or more multi-level cell blocks, and store the data in the SLC block.

[0009] The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent from specific descriptions given below by reference to the accompanying drawings.

[0011] The novel features of the present disclosure are set forth with particularity in the appended claims. However, a better understanding of the present disclosure, its advantages, and the applications thereof can be achieved from the following detailed description taken in conjunction with the accompanying drawings, in which one or more embodiments are shown and described. One or more embodiments are now described, by way of example only, with reference to the drawings, in which like reference numerals represent similar elements and in which:

[0012] Figure 1 An existing illustration (related art) for storing data in a power mode is shown;

[0013] Figure 2 An existing illustration for storing data in a power support component failure mode is shown;

[0014] Figure 3 An environment for writing data in a power support component failure mode according to one or more example embodiments of the disclosure is shown;

[0015] Figure 4 A detailed diagram of a data storage device for writing data in a power support component failure mode according to one or more example embodiments of the disclosure is shown;

[0016] Figures 5A to 5C An exemplary diagram for writing data in a power support component failure mode is shown in accordance with some embodiments of the present disclosure;

[0017] Figure 6 A flow diagram illustrating method operations for writing data in a power support component failure mode is shown in accordance with one or more example embodiments of the present disclosure; and

[0018] Figure 7 A block diagram of a computing system for writing data in a power support component failure mode is shown in accordance with one or more example embodiments of the present disclosure.

[0019] Those skilled in the art will appreciate that any flowchart herein represents a conceptual view of illustrative systems embodying the principles of the present disclosure. Similarly, it will be appreciated that any flowchart, flow diagram, state transition diagram, pseudocode, and / or the like represent various processes which can be substantially represented in computer readable medium and executed by a computer or processor, whether or not such computer or processor is explicitly shown. DETAILED DESCRIPTION

[0020] The terms "example embodiments," "embodiments," "one or more embodiments," "some embodiments,” and "one embodiment” mean “one or more (but not all) embodiments of the present disclosure,” unless expressly specified otherwise.

[0021] A list of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” mean “one or more,” unless expressly specified otherwise.

[0022] The description of example embodiments in which multiple components communicate with one another do not imply that such is the only manner in which the multiple components can interact. For example, the multiple components can interact in a substantially different manner from that which is explicitly described, unless expressly specified otherwise.

[0023] When a single device or article is described herein, it will be readily apparent that more than one device / article (whether or not they cooperate) can be used in place of a single device / article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device / article can be used in place of the more than one device or article or a different number of devices / articles can be used instead of the shown number of devices or programs. The functionality and / or the features of a device can be alternatively embodied by one or more other devices which are not explicitly described as having such

[0024] In the present disclosure, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the subject matter described herein that is described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0025] While the present disclosure can be modified in various ways and take on various alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the present disclosure to the particular forms disclosed, but on the contrary, this disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure.

[0026] The terms "comprise," "comprising," or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of components or steps does not include only those components or steps but can include other components or steps not expressly listed or inherent to such process, method, article, or apparatus. In other words, without limitation, one or more elements of a system or apparatus preceded by "comprising... a" does not, without more limitations, preclude the existence of other elements or additional elements in the system or apparatus.

[0027] The term "coupled" and its derivatives refer to any direct or indirect communication between two or more elements, whether or not those elements are in physical contact with one another. The term "or" is a disjunctive term meaning "and / or". The phrase "associated with," and its derivatives, refers to including, being included within, interconnection with, containing, being contained within, connected to or with, coupling to or with, communicable with, cooperating with, interlaced with, co-located with, in the vicinity of, bound to or with, having, having a property of, having a relationship to or with, or the like. The term "controller" refers to any device, system or part thereof that controls at least one operation. The functions associated with any particular controller can be centralized or distributed, whether locally or remotely. The phrase "at least one of" is used to mean one or more of the listed items can be used, alone or in combination, and that one or more of the listed items can be the only items used. For example, "at least one of A, B, and C" includes A, B, C, A and B, A and C, B and C, A and B and C, and any variations thereof. As an additional example, the expression "at least one of a, b, or c" can mean a only, b only, c only, a and b together, a and c together, b and c together, a, b, and c together, or any variation thereof. Similarly, the term "set" means one or more. Thus, a set of items can be a single item, or a collection of two or more items.

[0028] In the related art, in a power support component failure mode, a non-persistent memory enters a FUA mode to store data in a persistent memory of a data storage device. In the FUA mode, in addition to data received from a host device, dummy data can be filled in the persistent memory to process a group of storage cells in the persistent memory. Therefore, for processing a number of data bits that is less than a total capacity of the group of storage cells, an amount of time required is the same as an amount of time required to process data equivalent to a total bit capacity of the group of storage cells, because the dummy data in the storage cells is also processed with the data received from the host device. This causes a performance degradation of the data storage device, and requires more time to process the number of data bits that is less than the total capacity of the group of storage cells in comparison. In addition, the dummy data filled with the data received from the host device can cause a storage capacity waste of the storage cells in the persistent memory.

[0029] According to an example embodiment, a method and a data storage device for writing data in a power support component failure mode are provided. When a failure of a power support component of the data storage device is detected, the data storage device creates a single level cell (SLC) block for storing data received from a host device to a persistent memory of the data storage device. According to an example embodiment of the present disclosure, the data storage device creates the SLC block from a multi-level cell block existing in the persistent memory. The SLC block includes a group of storage cells, wherein each group of storage cells includes a plurality of storage cells. After the SLC block is created, the data received from the host device is stored in the SLC block. Therefore, since the SLC block occupies one bit in each storage cell, the non-persistent memory of the data storage device can transfer a number of bits of the received data to the persistent memory. In the persistent memory, since a total data storage capacity of the SLC block is low, a number of dummy data to be filled in the SLC block of the persistent memory is reduced. Therefore, in the present disclosure, a performance degradation of the data storage device can be improved while a storage capacity waste of the persistent memory is avoided.

[0030] Figure 3An environment 300 for writing data in a power support component failure mode is shown in accordance with one or more example embodiments. The environment 300 includes a data storage device 302 and a host device 304. The data storage device 302 stores data and / or instructions received from the host device 304. The data storage device 302 includes a solid state drive (SSD), a hard disk drive (HDD), and the like. However, the present disclosure is not limited thereto, and thus, other types of storage devices can be provided in accordance with another example embodiment. An SSD is a solid-state device that uses integrated circuit assemblies to store data permanently, typically using flash memory, and serves as a secondary storage in a computer storage hierarchy. An HDD is an electromechanical data storage device that uses magnetic storage to store and retrieve digital data. The host device 304 can be any computing device that communicates with the data storage device 302 over a network. The host device 304 can include, but is not limited to, a laptop computer, a desktop computer, a personal computer (PC), a notebook computer, a smartphone, a tablet computer, a server, and the like.

[0031] The data storage device 302 can include a controller 308, a non-persistent memory 310, and a persistent memory 312. The persistent memory 312 includes single level cell (SLC) blocks 314 and multi-level cell blocks 316. The SLC blocks 314 can refer to a version of single level cell memory that is capable of storing a single bit of information per storage cell. The multi-level cell (MLC) blocks can refer to a version of multi-level cell memory that is capable of storing multiple bits of information per storage cell.

[0032] For example, the MLC can include, but is not limited to, a triple level cell capable of storing three bits of information per storage cell, a quad level cell capable of storing four bits of information per storage cell, a quint level cell capable of storing five bits of information per storage cell, and the like. In an embodiment, the controller 308 can be an electronic component of the data storage device 302 that acts as a bridge between the host device 304, the non-persistent memory 310, and the persistent memory 312. The controller 308 can be an embedded processor that performs failure detection, creation of SLC blocks 314, and storing of data to the SLC blocks. However, the present disclosure is not limited thereto, and thus, the controller 308 can be configured to perform other operations in accordance with another example embodiment. The data storage device 302 stores data of the host device 304. In an implementation, the non-persistent memory 310 can include volatile memory, such as dynamic random access memory (DRAM), and the persistent memory can include non-volatile memory, such as NAND flash. In another implementation, the data storage device 302 can include the non-persistent memory 310 as a cache. However, the present disclosure is not limited thereto, and thus, any other memory type can be used in the data storage device 302 in accordance with another example embodiment.

[0033] The host device 304 and the data storage device 302 can be connected through an interface. The interface can include an internal interface or an external interface. The interface can be implemented by using various interface schemes, which are not limited to: an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a small computer small interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnect (PCI), a PCI express (PCIe), an NVMe, an IEEE 1394, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multimedia card (MMC) interface, an eMMC interface, a universal flash storage (UFS) interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

[0034] The controller 308 can be configured to store data in the data storage device 302 during a failure of a power support component of the data storage device 302. According to an example embodiment, the controller 308 can detect a failure in a power support component of the data storage device 302 while storing data received from the host device 304 to the data storage device 302. The power support component can refer to a component such as a capacitor that supplies power to the data storage device 302 in a power failure state to store data in the persistent memory 312 of the data storage device 302. The controller 308 can detect the failure in the power support component using known techniques and hardware components (e.g., registers, interrupters, etc.).

[0035] Further, the controller 308 can create an SLC block 314 including one or more groups of storage cells from one or more MLC blocks 316 in the persistent memory 312 of the data storage device 302. In an embodiment, the SLC block 314 can be created based on values of predefined data storage parameters. The predefined data storage parameters can include, for example, and without limitation, an erase cycle value of a total number of cells in the data storage device, a maximum endurance target value of the host device, an endurance of a total number of storage cells in one or more multi-level cell blocks to serve the host device, a maximum erase cycle, a size of each of the one or more multi-level cell blocks, an average erase cycle, and a total data value written to the persistent memory of the data storage device from the host device before a failure of the power support component, etc. Here, creating the SLC block 314 can involve determining a number of blocks to extract from the one or more MLC blocks 316, and extracting the determined number of blocks from the one or more MLC blocks 316 to create the SLC block 314.

[0036] Upon creating the SLC block 314, the controller 308 can store data received from the host device 304 via the non-persistent memory 310 in the SLC block 314 of the persistent memory 312. In an embodiment, the controller 308 can transfer the data from the SLC block 314 to one or more MLC blocks 316 based on a predefined SLC parameter. In an embodiment, the predefined SLC parameter can include, but is not limited to, a data capacity of the SLC block 314, a design of the SLC block 314, and a halt state of the SLC block 314.

[0037] Accordingly, the present disclosure provides the SLC block 314 for storing data received from the host device 304. Since the SLC block 314 is capable of storing a single bit of information per storage cell, the non-persistent memory 310 can send a smaller number of data bits received from the host device 304 to the persistent memory 312 even if the non-persistent memory 310 receives a smaller number of data bits from the host device 304. Accordingly, the use of dummy data in the persistent memory 312 can be avoided, or a smaller number of dummy data can be used, thereby avoiding wasting storage capacity of the storage cells of the persistent memory 312. Since the demand for dummy data in the persistent memory 312 is reduced, the additional time required to process the dummy data in the multi-level cell block 316 can be reduced. This enables an improvement in the performance of the data storage device 302 while processing and storing data in the data storage device 302 during a power support component failure mode.

[0038] Figure 4 A detailed diagram 400 of the data storage device 302 for writing data in a power support component failure mode according to an example embodiment of the present disclosure is shown. The data storage device 302 can include a controller 308 (also referred to as a “central processing unit,” “CPU,” and “processor”), a persistent memory 312, and a non-persistent memory 310.

[0039] In example embodiments, the persistent memory 312 and the non-persistent memory 310 can be communicatively coupled to the controller 308. The controller 308 can include at least one data processor for executing program components to perform user or system generated requests. The memory can be communicatively coupled to the controller 308. The memory stores instructions executable by the controller 308 which, when executed, can cause the controller 308 to write data in a power support component failure mode. In example embodiments, the persistent memory 312 can include one or more modules 404 and data 402. According to example embodiments of the present disclosure, the one or more modules 404 can be configured to perform operations for writing data in a power support component failure mode. For example, the one or more modules 404 can be configured to use the data 402 and perform operations for writing data in a power support component failure mode. In example embodiments, each of the one or more modules 404 can be hardware, which can be located outside of the persistent memory 312 and coupled with the data storage device 302. As used herein, the term module 404 can include, but is not limited to, an application specific integrated circuit (ASIC), an electronic circuit, a field-programmable gate array (FPGA), a programmable system on a chip (PSoC), a combinational logic circuit, and / or other suitable components that provide the described functionality.

[0040] According to example embodiments, the one or more modules 404 can be implemented by software or a combination of hardware and software. According to example embodiments, the one or more modules 404 will produce novel hardware or can be considered as a special purpose processor when configured with the described functionality defined in the present disclosure. However, the present disclosure is not limited thereto, and thus, the present disclosure can be implemented in another way according to various other example embodiments. In embodiments, an I / O interface is coupled with the controller 308 through which input signals or / and output signals are transferred. For example, the data storage device 302 can receive data from the host device 304 through the I / O interface. The I / O interface can include an internal interface or an external interface.

[0041] According to example embodiments, the modules 404 can include, for example, an input module 416, a detection module 418, an SLC creation module 420, an SLC storage module 422, and other modules 424. The above modules 404 can be represented as a single module or a combination of different modules. In one implementation, the data 402 can include, for example, input data 406, detection data 408, SLC creation data 410, SLC storage data 412, and other data 414.

[0042] In an example embodiment, the input module 416 can be configured to receive data from the host device 304 to store the data in the data storage device 302. In an embodiment, the input module 416 can reside in the persistent memory 312 of the data storage device 302. The data received from the host device 304 can be stored in the persistent memory 312 as input data 406. The data can be associated with any operation performed by the host device 304.

[0043] In an example embodiment, the detection module 418 can be configured to detect a failure in a power support component of the data storage device 302. The failure in the power support component can be detected using hardware components such as registers, interrupters, and the like. In an embodiment, the failure can be detected while receiving data from the host device 304 to store it in the data storage device 302. In another embodiment, the failure can be detected while sending the data from the non-persistent memory 310 to the persistent memory 312. In another embodiment, the failure can be detected while receiving the data from the host device 304 to the non-persistent memory 310. The detection of the failure in the power support component can be stored in the persistent memory 312 as detection data 408.

[0044] In an example embodiment, the SLC creation module 420 can be configured to create the SLC block 314 in the persistent memory 312 of the data storage device 302. Upon detecting the failure in the power support component of the data storage device, the controller 308 can create the SLC block 314 in the persistent memory 312 of the data storage device 302 from one or more MLC blocks 316. The SLC block 314 can be created based on values of predefined data storage parameters. The predefined data storage parameters can include, for example, an erase cycle value of a total number of cells in the data storage device 302, a maximum endurance target value of the host device 304, an endurance of a total number of storage cells in one or more multi-level cell blocks 316 serving the host device 304, a maximum erase cycle, a size of each of the one or more multi-level cell blocks 316, an average erase cycle, and a total data value written to the persistent memory 312 of the data storage device 302 from the host device 304 before the failure in the power support component occurs.

[0045] In an embodiment, the erase cycle value of a total number of cells in the data storage device 302 can refer to a sequence of events in which data written to the data storage device 302 can be erased and rewritten.

[0046] In an embodiment, the maximum endurance target value of the host device 304 refers to a maximum number of data bits that can be written to the data storage device 302 from the host device 304.

[0047] In an embodiment, the endurance of the total number of storage cells in one or more multi-level cell blocks 316 of the service host device 304 can refer to the total number of storage cells in one or more multi-level cell blocks 316 required to store data provided from the host device 304.

[0048] In an embodiment, the maximum erase cycle can refer to the maximum number of erase cycles that can be performed on the data storage device 302.

[0049] In an embodiment, the size of each of the one or more multi-level cell blocks 316 can refer to the data capacity of each of the one or more MLC blocks 316. In another embodiment, the size of each of the one or more multi-level cell blocks 316 can refer to the total number of storage cells in the one or more multi-level cell blocks 316.

[0050] In an embodiment, the average erase cycle can refer to the average number of erase cycles that can be performed on the data storage device 302.

[0051] In an embodiment, the total data value written to the persistent memory 312 of the data storage device 302 from the host device 304 before a failure of the power support component can refer to the total number of data bits written to the persistent memory 312 of the data storage device 302 from the host device 304 before the power support component failure is detected.

[0052] In an embodiment, the SLC creation module 420 can create the SLC block 314 by determining a number of blocks to extract from the one or more multi-level cell blocks 316 for creating the SLC block 314. The number of blocks for creating the SLC block 314 can be extracted based on the endurance of the total number of storage cells in the one or more multi-level cell blocks 316. The SLC creation module 420 can then extract the determined number of blocks from the one or more multi-level cell blocks 316. The SLC block 314 can be created from the number of blocks extracted from the one or more multi-level cell blocks 316.

[0053] For example, with reference to Figure 5A The multi-level cell block 502 can be populated with data received from the host device 304. The multi-level cell block 502 can include one or more groups of storage cells (MLC WL0, MLC WL1, …, MLC WL N). Each group of storage cells (MLC WL0, MLC WL1, …, MLC WL N) can include a plurality of storage cells. In a normal mode, while the data storage device 302 can be powered to store data, the data received from the host device 304 is stored in the one or more multi-level cell blocks 502. In an embodiment, upon creation of the SLC block 506 (as described in FIG. 5), the data stored in the one or more multi-level cell blocks 502 can be transferred to the SLC block 506. Figure 5BWhen the data is filled in the multi-level cell block 502, the data filled in the multi-level cell block 502 can be transferred to another multi-level cell block 504. One or more multi-level cell blocks 502 can be filled with valid data received from the host device 304 as well as invalid data. When the SLC block 506 is created, only valid data can be transferred from one or more multi-level cell blocks 502 to one or more multi-level cell blocks 504. Accordingly, when the data is transferred to one or more multi-level cell blocks 504, one or more multi-level cell blocks 502 can be erased.

[0054] Referring to FIG. 5B, Figure 5B Referring to FIG. 5B,

[0055] Referring to FIG. 5B, Figure 5C When a failure in the power support component is detected, the non-persistent memory 310 transfers the data received from the host device 304 to the SLC block 506 in the persistent memory 312. For example, it is assumed that the data capacity of the storage cell group SLC WL0 of the SLC block 506 can be 8 bits. In this case, when the host device 304 provides 7 bits of data, the non-persistent memory 310 transfers 7 bits of data to the persistent memory 312. In the persistent memory 312, in addition to 7 bits of data received from the host device 304, only one bit of dummy data can be added to fill and process the storage cell group SLC WL0. Accordingly, in the present disclosure, only one bit of data capacity of the storage cell group SLC WL0 in the SLC block 506 is wasted. Accordingly, the use of dummy data in the persistent memory 312 can be avoided, or a smaller number of dummy data can be used, thereby eliminating the waste of storage capacity of the storage cell of the persistent memory 312. The reduction of dummy data filled in the persistent memory 312 results in efficient performance of the data storage device 302, and as a result, the time taken to process the dummy data in the multi-level cell block 316 can be avoided. Accordingly, in the FUA mode, while processing the multi-level cell, in addition to the storage cell filled with data, the storage cell having dummy data is processed. Accordingly, since the number of dummy data used is reduced, the speed of processing the number of data bits and dummy data filled in the SLC block 314 can be increased. This results in an increase in the performance of the data storage device. Further, the time taken to process a smaller number of data bits not equivalent to the total capacity of the storage cell group can also be reduced.

[0056] Referring back to Figure 4In an embodiment, the number of blocks to be extracted from the one or more multi-level cell blocks 316 can be extracted by determining the count of SLC blocks 314. The count of SLC blocks 314 can refer to the number of blocks to be extracted from the MLC blocks 316.

[0057] In an example embodiment, the SLC creation module 420 can determine the count of SLC blocks 314 based on a function of the total number of storage blocks in the data storage device 302 and the predetermined number of one or more multi-level cell blocks required in the data storage device 302, as shown in equation (1):

[0058] The count of SLC blocks = the total number of storage blocks in the data storage device minus (-) the predetermined number of one or more multi-level cell blocks required in the data storage device … (1).

[0059] The predetermined number of one or more multi-level cell blocks required in the data storage device 302 is represented by equation (2) below:

[0060] The predetermined number of one or more multi-level cell blocks required in the data storage device = the remaining write capacity of the one or more multi-level cell blocks x WAF / (the remaining erase cycle x the size of the one or more multi-level cell blocks) … (2).

[0061] Here, “WAF” can refer to the number of data bits written to the data storage device 302 with respect to the number of data bits received from the host device 304.

[0062] The remaining write capacity of the one or more MLC blocks 316 can refer to the total number of empty storage cell groups that are not filled with data. The remaining write capacity of the one or more MLC blocks 316 can be a function of the total capacity of the one or more MLC blocks 316 and the total bits of data stored in the data storage device 302 before the failure of the power support component is detected, as shown in equation (3) below:

[0063] The remaining write capacity of the one or more multi-level cell blocks = the total capacity of the one or more multi-level cell blocks - the total bits of data stored in the data storage device before the failure of the power support component is detected … (3).

[0064] Here, the total capacity of the one or more MLC blocks 316 can refer to the number of data bits that the MLC blocks 316 can store. The total bits of data stored in the data storage device 302 before the failure of the power support component is detected can refer to the number of data bits filled in the MLC blocks 316 before the failure of the power support component is detected.

[0065] The remaining erase cycle can refer to the number of erase cycles left after subtracting the average erase cycle of the current time from the maximum erase cycle of the data storage device 302. The remaining erase cycle can be a function of the maximum erase cycle and the current average cycle, as shown in equation (4) below:

[0066] Remaining erase cycle = Maximum erase cycle - Current average erase cycle … (4).

[0067] In an example embodiment, the SLC storage module 422 can be configured to store data in the SLC block 314. The SLC storage module 422 can store data received from the non-persistent memory 310 into the SLC block 314 created in the persistent memory 312 of the data storage device 302.

[0068] In an embodiment, upon storing data into the SLC block 314, the data can be transferred / migrated from the SLC block 314 to one or more multi-level cell blocks 316 based on predefined SLC parameters. Referring back to Figure 5C , shows storing data received from the host device 304 in the SLC block 506 in the persistent memory 312. In an embodiment, the SLC block 506 can be merged / migrated with the multi-level cell block 508 to transfer data from the SLC block 506 to the multi-level cell block 508 based on predefined SLC parameters. Thus, the present disclosure can ensure the continuous availability of the SLC block 506 to store data received from the host device 304 in the power support component failure mode.

[0069] In an embodiment, the predefined SLC parameters can include, but are not limited to, the data capacity of the SLC block 506, the design of the SLC block 506, and the stop state of the SLC block 506. For the data capacity of the SLC block 506, consider reaching the total bit capacity of the group of storage cells (WL 0, WL 1, …, WL N) of the SLC block 506. Then, data from the SLC block 506 can be transferred to the MLC block 508. For the stop state of the SLC block 506, consider that the SLC block 506 can enter a stop state when the non-persistent memory 310 does not transfer data to the SLC block 506 within 2 ms. Then, the SLC block 506 can transfer data to the MLC block 508. For the design of the SLC block 506, the SLC block 506 can be designed to transfer data to the MLC block 508 every 5 ms or 10 ms, etc.

[0070] Other data 414 can store data generated by one or more modules 404, including temporary data and temporary files, used in the execution of the various functions of data storage device 302. One or more modules 404 can also include other modules 424 for carrying out miscellaneous functions of data storage device 302. Other data 414 can be stored in persistent storage 312. It is understood that one or more modules 404 can represent a single module or a combination of different modules.

[0071] Figure 6 A flow diagram illustrating a method of writing data in a power support component failure mode is shown in accordance with the example embodiments of this disclosure. As shown, method 600 can include one or more operations. Method 600 can be described in the general context of computer-executable instructions, which can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform particular functions or implement particular abstract data types. Figure 6 The order in which a method is described is not intended to be limiting, and

[0072] The order in which the method 600 is described is not intended to be limiting, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks can be deleted from the method without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

[0073] At operation 602, controller 308 can be configured to receive data from host device 304.

[0074] At operation 604, controller 308 can be configured to detect a failure in a power support component of data storage device 302 while storing the data received from host device 304 to data storage device 302. Controller 308 can use hardware components such as registers, interrupters, etc. to detect the failure.

[0075] At operation 606, controller 308 can be configured to create SLC block 314 upon detecting the failure in the power support component. SLC block 314 is created from one or more multi-level cell blocks 316 in persistent storage 312 of data storage device 302 based on a value of a predefined data storage parameter. SLC block 314 can be created by determining a number of blocks to extract from one or more multi-level cell blocks 316. Controller 308 can then extract the determined number of blocks from one or more multi-level cell blocks 316 to create SLC block 314.

[0076] At operation 608, the controller 308 can be configured to store data in the SLC block 314. After creating the SLC block 314, the controller can store data received from the host device 304 in the SLC block 314 of the persistent memory 312 in the data storage device 302. The controller 308 can transfer the data from the SLC block 314 to one or more MLC blocks 316 based on predefined SLC parameters. In an embodiment, the predefined SLC parameters can refer to a data capacity of the SLC block 314, a design of the SLC block 314, and a stop state of the SLC block 314.

[0077] Figure 7 A block diagram of a computer system 700 for implementing an example embodiment consistent with the present disclosure is shown. In an example embodiment, the computer system 700 can include the data storage device 302. Thus, the computer system 702 can be used to write data in a power support component failure mode. The computer system 702 and the data storage device 302 can be connected through an interface. The interface can include an internal interface or an external interface. The computer system 702 can include a central processing unit 712 (also referred to as “CPU,” “processor 712,” or controller). The processor 712 can include at least one data processor (one or more data processors). The processor 712 can include specialized processing units, such as an integrated system (bus) controller, a memory management control unit, a floating point unit, a graphics processing unit, a digital signal processing unit, and the like.

[0078] The processor 712 can be configured to communicate with one or more input / output (I / O) devices via the I / O interface 708. The I / O interface 708 can employ communication protocols / methods, such as, but not limited to, audio, analog, digital, mono, RCA, stereo, Institute of Electrical and Electronics Engineers (IEEE)-1394, serial bus, Universal Serial Bus (USB), infrared, PS / 2, BNC, coaxial, component, composite, Digital Video Interface (DVI), High-Definition Multimedia Interface (HDMI), radio frequency (RF) antenna, S-Video, VGA, IEEE 802.n / b / g / n / x, Bluetooth, cellular (such as Code Division Multiple Access (CDMA), High-Speed Packet Access (HSPA+), Global System for Mobile Communications (GSM), Long-Term Evolution (LTE), WiMax, and the like), and the like.

[0079] Using I / O interface 708, computer system 702 can communicate with one or more I / O devices. For example, input device 704 can be an antenna, keyboard, mouse, joystick, (infrared) remote control, camera, card reader, fax machine, dongle, biometric reader, microphone, touch screen, touchpad, trackball, stylus, scanner, storage device, transceiver, video device / source, etc. Output device 706 can be a printer, fax machine, video display (e.g., cathode ray tube (CRT), liquid crystal display (LCD), light-emitting diode (LED), plasma, plasma display panel (PDP), organic light-emitting diode display (OLED), etc.), audio speaker, etc.

[0080] Processor 712 can be configured to communicate with communication network 716 via network interface 714. Network interface 714 can communicate with communication network 716. Computer system 702 can communicate with data storage device 302 via communication network 716. Network interface 714 can employ a variety of connection protocols including, but not limited to, direct connection, Ethernet (e.g., twisted pair 10 / 100 / 1000 Base T), transmission control protocol / internet protocol (TCP / IP), token ringing, IEEE 802.11a / b / g / n / x, etc. Communication network 716 can include, but is not limited to, direct interconnection, local area network (LAN), wide area network (WAN), wireless network (e.g., using wireless application protocol), the Internet, etc. Network interface 714 can employ a variety of connection protocols including, but not limited to, direct connection, Ethernet (e.g., twisted pair 10 / 100 / 1000 Base T), transmission control protocol / internet protocol (TCP / IP), token ringing, IEEE 802.11a / b / g / n / x, etc.

[0081] Communication network 716 includes, but is not limited to, direct interconnection, electronic commerce network, peer-to-peer (P2P) network, local area network (LAN), wide area network (WAN), wireless network (e.g., using wireless application protocol), the Internet, Wi-Fi, etc. The first network and the second network can be private networks or shared networks, which represent an association of different types of networks that communicate with each other using various protocols (e.g., hypertext transfer protocol (HTTP), transmission control protocol / internet protocol (TCP / IP), wireless application protocol (WAP), etc.). Moreover, the first network and the second network can include various network devices, including routers, bridges, servers, computing devices, storage devices, etc.

[0082] In example embodiments, the processor 712 can be configured to communicate with a storage 724 (e.g., RAM, ROM, etc.) via a storage interface 718. The storage interface 718 can connect to the storage 724 using a variety of connection protocols, such as serial advanced technology attachment (SATA), integrated drive electronics (IDE), IEEE- 1394, universal serial bus (USB), Fibre Channel, small computer system interface (SCSI), etc., including but not limited to storage drives, removable disc drives, etc. The storage drives can further include drum, disk, tape, magneto-optical, optical, redundant array of independent disks (RAID), solid-state storage, solid state drives, etc.

[0083] The storage 724 can store collections of program or database components, including but not limited to user interfaces 734, operating systems 736, web browsers 732, etc. In example embodiments, the computer system 702 can store user / application data, such as data, variables, records, etc. described in the present disclosure. Such databases can be implemented as fault-tolerant, relational, scalable, secure databases, such as Oracle® or Sybase®.

[0084] The operating system 736 can facilitate management and operation of the computer system 500. Examples of operating systems include, but are not limited to, APPLE MACINTOSH R OS X, UNIX R、 UNIX-like systems distributions (e.g., BERKELEY SOFTWARE DISTRIBUTION TM (BSD), FREEBSD TM , NETBSD TM , OPENBSD TM , etc.), LINUX DISTRIBUTIONS TM (e.g., RED HAT TM , UBUNTU TM , KUBUNTU TM , etc.), IBM TM OS / 2, MICROSOFT TM WINDOWS TM (XP TM , VISTA TM / 7 / 8, 10, etc.), APPLE R IOS TM , GOOGLE R ANDROID TM , BLACKBERRY R OS, etc.

[0085] In an example embodiment, computer system 702 may implement the program components stored in web browser 732. Web browser 732 may be a hypertext viewing application, such as Microsoft. R INTERNET EXPLORER TM Google R CHROME TM0 MOZILLA R FIREFOX TM APPLE R SAFARI TM Secure web browsing can be provided using protocols such as Hypertext Transfer Protocol Secure (HTTPS), Secure Sockets Layer (SSL), and Transport Layer Security (TLS). Web browsers 732 can utilize technologies such as AJAX. TM DHTML TM、 ADOBE R FLASH TM JAVASCRIPT TM JAVA TM Facilities such as application programming interfaces (APIs) are provided. In an example embodiment, computer system 702 can implement program components stored on a mail server. The mail server can be an Internet mail server such as Microsoft Exchange. The mail server can use methods such as ASP. TM ACTIVEX TM、 ANSI TM C++ / C#, Microsoft R .NET TM CGI SCRIPTS TM JAVA TM JAVASCRIPT TM PERL TM PHP TM PYTHON TM WEBOBJECTS TM Mail servers can utilize various communication protocols, such as Internet Message Access Protocol (IMAP), Message Application Programming Interface (MAPI), and Microsoft... R Email clients can be stored in various formats, such as email exchange, Post Office Protocol (POP), and Simple Mail Transfer Protocol (SMTP). In an example embodiment, computer system 702 can implement program components for an email client. The email client can be an email viewing application, such as Apple's... R MAIL TM MICROSOFT R ENTOURAGE TMMICROSOFT R OUTLOOK TM MOZILLA R THUNDERBIRD TM and the like.

[0086] Further, in implementing embodiments of the present disclosure, one or more computer-readable storage media can be utilized. A computer-readable storage medium refers to any type of physical memory that can store information or data that is readable by a processor. Thus, a computer-readable storage medium can store instructions for execution by one or more processors including instructions for causing a processor to perform operations or stages according to embodiments described herein. The term "computer-readable medium" should be taken to include tangible articles and exclude carrier waves and transitory signals, i.e., not transitory. Examples include random access memory (RAM), read only memory (ROM), volatile memory, non-volatile memory, hard drives, compact discs read-only memory (CD-ROM), digital video disc (DVD), flash drives, magnetic disks, and any other known physical storage media.

[0087] According to example embodiments, a method and a data storage device for writing data in a power support component failure mode are provided. In the present disclosure, the data storage device creates SLC blocks from multi-level cell blocks in the persistent memory. The SLC blocks are created based on predefined data storage parameters. After the SLC blocks are created, data received from a host device is stored in the SLC blocks. Thus, the use of dummy data in the persistent memory 312 can be avoided, or a smaller number of dummy data can be used, thereby avoiding wasting storage capacity of the storage cells of the persistent memory 312. As the demand for dummy data in the persistent memory is reduced, the additional time required to process the dummy data in the multi-level cell blocks can be reduced. This enables to improve the performance of the data storage device 302 while processing and storing data in the data storage device during the power support component failure mode.

[0088] In the above-described example embodiments, components according to example embodiments of the present disclosure are referred to by using modules or units. A module or a unit can be implemented with various hardware devices, such as an integrated circuit, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), firmware that drives a hardware device, software such as an application, or a combination of hardware devices and software. In addition, a module or a unit can include a circuit implemented with a semiconductor element in an integrated circuit, or a circuit registered as intellectual property (IP).

[0089] Figure 6The illustrated operations show certain events occurring in a certain order. In alternative embodiments, certain operations can be performed in a different order, modified or removed. Moreover, operations can be added to the above described logic and still conform to the described embodiments. Further, operations described herein as sequential can be executed concurrently, or the specific operations can be handled by one or more generic processing units. Further, operations can be performed by a single processing unit or by distributed processing units.

[0090] Finally, the language used in the specification has been principally selected for readability and instructional purposes and can not have been selected to delineate or circumscribe the subject of the present application. Accordingly, the present disclosure is intended to be illustrative, and not restrictive, of the scope of the present application, which is, therefore, accordingly set forth in the attached claims.

[0091] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope being indicated by the appended claims.

Claims

1. A method performed by a data storage device, the method comprising: receiving, by a controller of the data storage device, data from a host device; detecting, by the controller of the data storage device, a failure in a power support component of the data storage device; creating, by the controller, a single level cell (SLC) block comprising one or more groups of storage cells in a persistent memory of the data storage device from one or more multi-level cell blocks based on values of predefined data storage parameters; and storing, by the controller, the data in the SLC block.

2. The method of claim 1, wherein the predefined data storage parameters comprise: an erase cycle value for a total number of cells in the data storage device, a maximum endurance target value for the host device, an endurance of a total number of storage cells in the one or more multi-level cell blocks serving the host device, a maximum erase cycle, a size of each of the one or more multi-level cell blocks, an average erase cycle, and a total data value written to the persistent memory of the data storage device from the host device before the failure in the power support component. creating, by the controller, the SLC block comprises:

3. The method of claim 1, wherein, determining, by the controller, a number of blocks to extract from the one or more multi-level cell blocks for creating the SLC block based on an endurance of a total number of storage cells in the one or more multi-level cell blocks; extracting, by the controller, the determined number of blocks from the one or more multi-level cell blocks; and creating, by the controller, the SLC block from the extracted one or more multi-level cell blocks. creating, by the controller, the SLC block further comprises determining a count of the SLC block based on a function of a total number of storage blocks in the data storage device and a predetermined number of the one or more multi-level cell blocks required in the data storage device.

4. The method of claim 1, wherein, the predetermined number of the one or more multi-level cell blocks required in the data storage device is determined based on at least one of:

5. The method of claim 4, wherein, a remaining write capacity of the one or more multi-level cell blocks, a write amplification factor (WAF) corresponding to the respective one or more multi-level cell blocks, a remaining erase cycle, and a size of the one or more multi-level cell blocks. transferring the data from the SLC block to the one or more multi-level cell blocks based on predefined SLC parameters.

6. The method of claim 1, further comprising: the predefined SLC parameters comprise a data capacity of the SLC block, a design of the SLC block, and a stop state of the SLC block.

7. The method of claim 6, wherein, 8. A data storage device comprising: a persistent memory; a non-persistent memory; and a controller configured to: receive data from a host device; detect a failure in a power support component of the data storage device; create, in the persistent memory of the data storage device, a single level cell (SLC) block comprising one or more groups of storage cells from one or more multi-level cell blocks based on values of predefined data storage parameters; and store the data in the SLC block. the predefined data storage parameters comprise: an erase cycle value for a total number of cells in the data storage device, a maximum endurance target value for the host device, 9. The data storage device of claim 8, wherein, an endurance of a total number of storage cells in the one or more multi-level cell blocks serving the host device, a maximum erase cycle, a size of each of the one or more multi-level cell blocks, an average erase cycle, and a total data value written to the persistent memory of the data storage device from the host device before the failure in the power support component. a maximum endurance target value for the host device, endurance of a total number of storage cells in the one or more multi-level cell blocks serving the host device, a maximum erase cycle, a size of each of the one or more multi-level cell blocks, an average erase cycle, and a total data value written from the host device to the persistent memory before a failure of the power support component.

10. The data storage device of claim 8, wherein, The controller is further configured to create the SLC block by: determining a number of blocks to extract from the one or more multi-level cell blocks for creating the SLC block based on endurance of a total number of storage cells in the one or more multi-level cell blocks; extracting the determined number of blocks from the one or more multi-level cell blocks; and creating the SLC block from the extracted one or more multi-level cell blocks. The controller is further configured to create the SLC block by determining a count of the SLC block based on at least one of a total number of storage blocks in the data storage device and a predetermined number of the one or more multi-level cell blocks required in the data storage device.

11. The data storage device of claim 8, wherein, The controller is further configured to determine the predetermined number of the one or more multi-level cell blocks required in the data storage device based on at least one of:

12. The data storage device of claim 11, wherein, a remaining write capacity of the one or more multi-level cell blocks, a write amplification factor (WAF) corresponding to the respective one or more multi-level cell blocks, a remaining erase cycle, and a size of the one or more multi-level cell blocks. The controller is further configured to transfer the data from the SLC block to the one or more multi-level cell blocks based on predefined SLC parameters.

13. The data storage device of claim 8, wherein, The predefined SLC parameters include a data capacity of the SLC block, a design of the SLC block, and a stop state of the SLC block.

14. The data storage device of claim 13, wherein, ​

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