System development method and device, computer equipment, storage medium and program product

Abstract

The invention relates to a system development method and device, computer equipment, a computer readable storage medium and a computer program product. Obtaining a system model constructed based on a first language; the first language is a semi-formalized modeling language; analyzing the system model to obtain an abstract instantiated syntax tree corresponding to the system model, and performing system analysis at least including system resource budget analysis based on the abstract instantiated syntax tree to obtain an analysis result; under the condition that the analysis result meets a preset condition, generating a target code of a second language matched with the system model based on the abstract instantiation syntax tree; the second language is a programming language. By adopting the method, the model development efficiency and quality can be improved.

Description

Technical Field

[0001] This application relates to the field of model-driven development technology, and in particular to a system development method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] Embedded application development today faces increasingly complex and ever-changing requirements, leading to ever more intricate systems. Traditional software development methods struggle to rapidly iterate and meet user needs. This has given rise to new approaches, such as Model-Driven Development (MDD). This business-relevant approach shifts system development from pure code coding to a higher-level, more abstract business model. This model is then converted into code or other components to drive partial or complete automated development.

[0003] In the practical application of model-driven development methods, there may be situations where the model designer is not familiar with programming-related knowledge, which may lead to quality problems in the code generated based on the designed business model. This may result in repeated code modifications or the need to repeatedly go through various processes such as system design and code conversion, resulting in low system development efficiency. Summary of the Invention

[0004] Therefore, it is necessary to provide a system development method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can improve system development efficiency and quality in response to the above-mentioned technical problems.

[0005] In one aspect, this application provides a system development method, comprising: obtaining a system model constructed based on a first language; the first language being a semi-formal modeling language; parsing the system model to obtain its corresponding abstract instantiation syntax tree; performing system analysis based on the abstract instantiation syntax tree, including at least system resource budget analysis, to obtain analysis results; and, if the analysis results meet preset conditions, generating target code in a second language that matches the system model based on the abstract instantiation syntax tree; the second language being a programming language.

[0006] In one embodiment, the system analysis based on the abstract instantiation syntax tree, which includes at least system resource budget analysis, to obtain the analysis results, includes: extracting thread-related information from the abstract instantiation syntax tree, performing system resource budget analysis based on the thread-related information, and obtaining the analysis results of the system analysis based at least on the results of the system resource budget analysis.

[0007] In one embodiment, the system resource budget analysis includes at least one of processor computing resource analysis, memory resource analysis, bus load analysis, and data flow latency analysis, wherein the processor computing resource analysis includes single-core utilization analysis and worst-case time response analysis.

[0008] In one embodiment, the method further includes: if the attribute value of the binding relationship between the thread representation and the processor core is a preset symbol, then generating multiple binding schemes based on binding constraints; the binding scheme indicates the binding relationship between the thread and the processor core; selecting a target binding scheme from the multiple binding schemes based on the desired optimization goal; updating the abstract instantiation syntax tree based on the target binding scheme; and using the updated abstract instantiation syntax tree to generate target code of the second language.

[0009] In one embodiment, the desired optimization objective includes at least one of the total power consumption of the processor core, the response time of the end-to-end data flow of the system model, and the processor utilization balance.

[0010] In one embodiment, obtaining the system model built based on the first language includes: obtaining a graphical representation related to the system to be developed; parsing the graphical representation, the internal attributes of the components, and the relationships between the components to obtain the modeling information of the system to be developed; and generating a system model of the system to be developed in the first language based on the modeling information.

[0011] On the other hand, this application also provides a system development apparatus, comprising: a model parser for obtaining a system model constructed based on a first language; the first language being a semi-formal modeling language; parsing the system model to obtain its corresponding abstract instantiation syntax tree; a system analysis module for performing system analysis based on the abstract instantiation syntax tree, including at least system resource budget analysis, to obtain analysis results; and a code generator for generating target code in a second language that matches the system model based on the abstract instantiation syntax tree, provided that the analysis results meet preset conditions; the second language being a programming language.

[0012] On the other hand, this application also provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described system development method.

[0013] In another aspect, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-described system development method.

[0014] On the other hand, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps in the above-described system development method.

[0015] The aforementioned system development methods, apparatus, computer equipment, computer-readable storage media, and computer program products parse the system model built based on the first language to obtain an abstract instantiated syntax tree. Then, leveraging this abstract instantiated syntax tree, system analysis, including at least system resource budget analysis, is performed in the early stages of system design. This allows for the timely identification of system design flaws before code conversion, improving system quality and ultimately enhancing the quality of the final generated code. This reduces the need for repeated code modifications or repeated system model building and code conversion due to early design defects, reducing development workload and improving system development efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a diagram illustrating the application environment of the system development apparatus in one embodiment;

[0018] Figure 2 This is a flowchart illustrating a system development method in one embodiment;

[0019] Figure 3 This is an example diagram illustrating the overall framework of a system development method in one embodiment;

[0020] Figure 4 This is an example diagram illustrating the overall framework of a system development method in a specific embodiment;

[0021] Figure 5 This is a flowchart of a system development method in one embodiment;

[0022] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0024] This application leverages the concept of model-driven development (MDT) to construct a system model of the business system and then convert it into target code to achieve system development. In MDT, the modeling language is used not only as a design language but also as a programming language, allowing the model to play a crucial role in software development. "Everything is a model" is the fundamental idea of ​​model-driven architecture. However, improving model quality remains a key challenge in MDT.

[0025] This application provides a system development method that conducts system analysis, including at least system resource budget analysis, in the early stages of system design. This allows for the timely identification of system design flaws before code conversion, improving system quality and ultimately enhancing the quality of the final generated code. This reduces the need for repeated code modifications or repeated system model building and code conversion due to early design defects, thus reducing development workload and improving system development efficiency.

[0026] Before describing the detailed scheme of this application, the first and second languages ​​involved will be explained:

[0027] The first language can be a semi-formal modeling language, such as AADL (Architecture Analysis and Design Language), SysML (Systems Modeling Language), or UML (Unified Modeling Language).

[0028] A second language, specifically a programming language, can be compiled and executed by a computer, such as C or C++.

[0029] In some cases, the system development method of this application can be specifically applied to embedded system development, such as edge computing, radar sensing, and vision sensing systems. Embedded systems are widely used in safety-critical fields such as aerospace, automotive control, and robotics. As these fields place increasing demands on computational accuracy, real-time response, and concurrent processing, embedded systems based on them become increasingly complex. Therefore, designing and describing complex embedded real-time systems with high reliability and high quality has become an important task in this field.

[0030] AADL is a semi-formal modeling language that supports model engineering design. Since its official release in 2004, the language has been improved and expanded based on industry experience. Its core documentation has been continuously revised and developed, evolving from AS5506 to the current AS5506D standard document. This document includes definitions of software components (such as processes, threads, and data), hardware components (such as processors, memory, and buses), and composite components (such as systems), as well as multiple (e.g., nine) standard attribute sets. Components are described using both component types and component implementations. Component types define the interface between the component and the outside world, such as features, patterns, and attributes; component implementations define the component's internal interface, such as sub-components, connections, and streams. It is a modeling language for embedded real-time systems, possessing advantages such as simple syntax, precise semantics, powerful functionality, and extensibility. It can model and describe the functional and non-functional attributes of embedded software. Therefore, using AADL as the modeling language for model-driven development is a preferred approach. That is, the first language of this application can specifically be AADL.

[0031] The system development method provided in this application can be applied to, for example... Figure 1 The system development apparatus 100 shown may include, exemplarily, a model parser 101, a system analysis module 102, and a code generator 103. In some embodiments, the system development apparatus 100 may be implemented on a computer device (such as a terminal or server); in other embodiments, the system development apparatus 100 may be implemented on a system including a terminal and a server (e.g., different modules of the system development apparatus 100 are deployed on different devices that can communicate with each other).

[0032] For example, the terminal can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc. Head-mounted devices can be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0033] In one exemplary embodiment, such as Figure 2 As shown, a system development method is provided, which can be applied to Figure 1Taking the system development device 100 as an example, the explanation includes the following steps 202 to 206. Wherein:

[0034] Step 202: Obtain the system model built based on the first language; the first language is a semi-formal modeling language.

[0035] The system model is a pre-built system architecture model with preset functions based on a first language. In some embodiments, the system model can be represented by a model file and an attribute set. In some scenarios, the first language may specifically be AADL, and the system model built based on AADL may specifically be an embedded model, which is represented by an AADL file and an attribute set.

[0036] An attribute set is a data collection describing the attributes of components supported by the first language. It can include standard attribute sets and custom attribute sets. For example, for a thread component in a model file (such as an AADL file), its corresponding attributes could be information indicating the thread type (e.g., a periodic thread) and the periodic time interval. A standard attribute set can be understood as the collection of attributes for each component officially defined by the first language. In practical applications, attributes for components involved in the system model can also be customized, i.e., custom attribute sets.

[0037] In some embodiments, the system model obtained by the system development apparatus 100 may be a model pre-built based on a first language. In other embodiments, the system development apparatus 100 further includes a graph parser for parsing the graphical representation related to the system to be built, thereby converting it into a system model described in the first language.

[0038] Step 204: Parse the system model to obtain its corresponding abstract instantiation syntax tree, and perform system analysis based on the abstract instantiation syntax tree, including at least system resource budget analysis, to obtain the analysis results.

[0039] Specifically, the model parser 101 can parse the system model after obtaining it, so as to convert the input system model into an abstract instantiation syntax tree. The abstract instantiation syntax tree will provide the system analysis module 102 and the code generator 103 with the necessary information of the system model.

[0040] In some embodiments, the model parser 101 includes a syntax parser and an instantiation module. Taking AADL as the first language as an example, the syntax parser can read the input AADL text as a token (character) stream, and then perform syntactic and lexical analysis according to the AADL standard syntax to generate the corresponding abstract syntax tree. The instantiation model can traverse the entire abstract syntax tree, process the information in the abstract syntax tree, and convert it into an abstract instantiated syntax tree.

[0041] Furthermore, the model parser 101 can input the parsed abstract instantiated syntax tree into the system analysis module 102 for system analysis. In some embodiments, the system analysis includes at least system resource budget analysis. System resources refer to the time resources, hardware and / or software resources required for system operation. System resource budget refers to the pre-quantified allocation and planning of system resources during the system design phase.

[0042] In some embodiments, system analysis can primarily be system architecture analysis, which includes at least system resource budget analysis. It can be understood that a system model is essentially a model file containing the system architecture; performing system architecture analysis means analyzing the system architecture described by the system model to determine whether the system architecture is reasonable. In other scenarios, system analysis may also include the analysis of hardware and software relationships, the analysis of the binding relationship between threads and processor cores, etc.

[0043] In some embodiments, the system analysis module 102 can perform system resource budget analysis based on the attribute information of each component in the system model and the relationships between the components, wherein the attribute information of each component in the system model and the relationships between the components can be extracted from the abstract instantiation syntax tree.

[0044] Step 206: If the analysis results meet the preset conditions, generate target code in a second language that matches the system model based on the abstract instantiated syntax tree; the second language is a programming language.

[0045] Among them, preset conditions are pre-set requirements, such as all indicators in the system analysis meeting preset requirements, such as being higher than or lower than preset thresholds; or certain specified indicators in the system analysis meeting preset requirements.

[0046] If the analysis results meet the preset conditions, it means that the designed system meets the requirements and has no design flaws, so the code conversion process can be directly carried out. In other words, if the analysis results meet the preset conditions, the abstract instantiated syntax tree can be input into the code generator 103, which will then generate and output target code in a second language that matches the system model.

[0047] In some embodiments, the system development device 100 may determine whether the analysis results meet preset conditions based on a set judgment logic. In other embodiments, the user may also determine whether the analysis results meet preset conditions. If the preset conditions are met, the system development device 100 is triggered to generate target code in a second language that matches the system model based on the abstract instantiated syntax tree; if the preset conditions are not met, modifications to the system model are triggered.

[0048] In some embodiments, mapping relationships between the first language and different second languages ​​can be set according to the differences in the code to be generated, so as to develop different code generators. Provided that the information provided by the abstract instantiation syntax tree is sufficiently complete, code generators adapted to different programming languages ​​(such as C, C++, etc.) can be developed.

[0049] Furthermore, the code generator 103 can traverse the abstract instantiated syntax tree and perform checks. If it finds elements that do not support code generation, it will display error messages and instruct the user to make adjustments based on these error messages, such as deleting elements that do not support code generation.

[0050] In some embodiments, generating target code in a second language that matches the system model includes: generating target code in a second language that matches the system model based on predefined mapping rules from a first language to a second language. Here, the mapping rules refer to the correspondence between semantically equivalent content described in the first language and content described in the second language. Mapping rules can be pre-constructed based on the language requirements of the first language and the second language, allowing the code generator 103 to convert content in the first language into semantically equivalent content in the second language. This enables the system model to be quickly and accurately converted into target code in the second language.

[0051] It is understandable that corresponding mapping rules can be constructed for different second languages ​​to be used for the conversion of system models. That is, a corresponding code generator 103 can be designed for each second language, which can realize the reuse of the aforementioned model parser 101 and system analysis module 102, and meet different business needs while saving resources.

[0052] In some embodiments, the code generator 103 may specifically traverse the abstract instantiation syntax tree to obtain relevant information about the system model, and generate corresponding target code based on this information and mapping rules. In some embodiments, the mapping rules may specifically be rules for converting each component into code in a programming language. Exemplarily, the mapping rules may include at least one of the following:

[0053] a. Convert system components into the outermost folder of the code project structure. Specifically, system components provide a collection of interoperable application software. Because this collection is an abstract concept, it will be the outermost folder in the generated code project structure, containing all the generated code.

[0054] b. Assign the processor component's attributes to the process bound to the corresponding processor and the threads within that process. Specifically, a processor component represents an abstract model of the hardware and software, responsible for scheduling and executing threads bound to that processor. The relevant attributes of the processor component will be inherited by the process bound to that processor and the threads within that process. Furthermore, because the processor component is an abstract concept, it will not be reflected in the generated code.

[0055] c. A process component represents a model of a virtual address space. A process contains processes and their sub-components (mainly threads and subroutines). Process components are primarily used to model a virtual address space containing concurrent tasks or active objects. The meaning of this model is consistent with the semantics in main.c in the C language. Each process component will generate a separate folder.

[0056] d. Thread components represent models of concurrent tasks or active objects (scheduling units that can execute concurrently with other threads), primarily based on the input-computation-output model of thread and port communication and execution. Thread components are mapped to C code function interfaces that create threads based on the information of the thread component, and the created threads execute according to the modeling information.

[0057] e. A subroutine component represents a description of a function interface or a sequence of function interface calls. The parameters of the function interface will be determined based on the characteristics of the subroutine component, and a pointer will be used to represent a parameter value that can be output.

[0058] f. Data components represent the modeling of data types. Based on the parameters of the data components, the corresponding data structure in C code will be generated. If the data type is a complex data type such as a structure, enumeration, or array, the tool will also generate corresponding data serialization and deserialization interfaces to facilitate data transmission.

[0059] It is understood that the above mapping rules are for illustrative purposes only and are not intended to be limiting. In actual applications, more, fewer, or different mapping rules can be set.

[0060] The aforementioned system development method parses the system model built on the first language to obtain an abstract instantiated syntax tree. Then, leveraging this abstract instantiated syntax tree, a system analysis, including at least a system resource budget analysis, is performed in the early stages of system design. This allows for the timely identification of system design flaws before code conversion, improving system quality and ultimately enhancing the quality of the final generated code. This reduces the need for repeated code modifications or repeated system model building and code conversion due to early design defects, thus reducing development workload and improving system development efficiency.

[0061] In some embodiments, the system development apparatus 100 can directly obtain a pre-selected, pre-built system model. In other embodiments, the system development apparatus 100 can provide a front-end page for building system models, allowing developers to build the system models themselves. In this case, the system development apparatus 100 may include a graph parser for parsing the graphical representation related to the system to be built, thereby converting it into a system model described in a first language.

[0062] For example, obtaining a system model built based on a first language includes: obtaining a graphical representation related to the system to be developed; parsing the graphical representation, the internal attributes of components, and the relationships between various components to obtain modeling information of the system to be developed; and generating a system model of the system to be developed in a first language based on the modeling information.

[0063] The system to be developed can be a system built based on business needs, specifically an embedded system. Graphical representation is the representation of components in a graphical form. When the first language is AADL, the graphical representation here can include standard AADL graphical representation and custom graphical representation. Relationships include at least one of the following: containment, inheritance, or connection. Containment means one component contains another; inheritance means one component can be created based on another; connection refers to the data flow relationship between components, such as data from component A being input into component B.

[0064] In some embodiments, users can design systems using graphical representations of components through a front-end interface. A graphical parser can then analyze this design to convert the system built using the graphical representation into a system model in the first language. It is understood that the graphical parser can support parsing the graphical representations of the AADL standard, where the graphical representations of the AADL standard need to be mapped according to the semantic logic defined in the AADL standard file. Furthermore, the graphical parser can also support graphical representations customized by the tool provider, but the tool provider needs to provide the customized graphical representation and the mapping relationship between the graphical representation and the AADL text.

[0065] For example, the graph parser may include a graph parsing module and a model text generation module. The graph parsing module parses the graphical representations of components on the front-end interface, the internal attributes of the components, and the relationships between the components, and inputs the obtained modeling information into the model text generation module. The model text generation module, based on the mapping relationship between the graphical representations and model text (such as AADL text), converts the obtained modeling information into a corresponding model file (such as an AADL file). This model file and the attribute set constitute the system model.

[0066] The above embodiments provide a function for visual system design, which can greatly reduce the threshold for users to develop systems. Furthermore, the graphical representation related to the system to be developed can be converted into a system model in the first language, making the generation of system models more convenient.

[0067] In some embodiments, the model parser 101 includes a syntax parser and an instantiation module. Parsing the system model to obtain its corresponding abstract instantiated syntax tree includes: the syntax parser parsing the components in the system model and the relationships between the components, constructing the abstract syntax tree based on the components and the relationships between the components, and the instantiation module instantiating the abstract syntax tree to obtain the abstract instantiated syntax tree.

[0068] The Abstract Syntax Tree (AST) is a tree-like representation of the abstract grammatical structure that is closer to that of a first language. In this embodiment, it can indicate the logical structure of the system model. The Abstract Instantiation Syntax Tree (AIT) is a tree-like representation obtained by instantiating the Abstract Syntax Tree.

[0069] Specifically, the parser can scan the model files (such as AADL files) and attribute sets in the system model, read the character (token) streams, perform lexical and syntactic analysis for syntax checking, and gradually build an initial abstract syntax tree based on the content that passes the syntax check. Further, after building the initial abstract syntax tree, the relationships between nodes in the initial abstract syntax tree can be determined based on the relationships between components. These relationships are then added to the initial abstract syntax tree using indexes, resulting in the final abstract syntax tree. Adding relationships to the initial abstract syntax tree using indexes can be done, for example, by adding indexes as flags within nodes to indicate the relationships between that node and other nodes.

[0070] Furthermore, the instantiation module can instantiate the abstract syntax tree to obtain an abstract instantiated syntax tree. During the instantiation process, the instantiation module traverses the entire abstract syntax tree, determines the root node of the abstract instantiated syntax tree from the final abstract syntax tree based on specified information, extracts the corresponding components from the abstract syntax tree according to the index in the root node to obtain the child nodes of the root node, and adds the attribute information of the child nodes. Then, it gradually determines the corresponding child nodes based on the index of the determined nodes and adds attribute information to construct the abstract instantiated syntax tree.

[0071] Understandably, in some implementations, during the construction of the abstract syntax tree and abstract instantiation syntax tree, certain checks are added based on business requirements to avoid introducing errors during parsing that could lead to code generation failure or poor code quality. If errors are detected in the system model itself (such as violating modeling rules or system incompleteness), the generation of the abstract instantiation syntax tree will fail, and the model parser 101 will display an error message. The user needs to revise the model based on the error information.

[0072] In the above embodiments, parsing the system model to obtain an abstract instantiation syntax tree can fully extract the effective information in the system model, which is helpful for subsequent system analysis and generates accurate target code.

[0073] In some embodiments, when designing the system model, the `Actual_Processor_Binding` attribute of a thread can be set. For example, the attribute value can be set to a value corresponding to a specific processor core, or set to a preset symbol (such as a placeholder). If the attribute value corresponds to a specific processor core, it indicates that the thread is bound to that processor core. If the attribute value is a preset symbol, it indicates that the thread is not yet bound to a processor core. In this case, thread binding optimization can be performed. This optimization includes the following steps: if the attribute representing the thread's binding relationship with the processor core is a preset symbol, multiple binding schemes are generated based on binding constraints; the binding scheme indicates the binding relationship between the thread and the processor core; based on the desired optimization objective, a target binding scheme is selected from the multiple binding schemes; the abstract instantiation syntax tree is updated based on the target binding scheme; the updated abstract instantiation is used to generate target code in a second language.

[0074] In some embodiments, the desired optimization objectives include at least one of the following: total power consumption of the processor cores, response time of the end-to-end flow of the system model, and processor utilization balance.

[0075] For the binding scheme, this application can calculate / obtain the following expected optimization objectives (also known as optimization metrics):

[0076] 1. Total Power Consumption: Assuming each processor core has idle power and active power, the power consumption is calculated linearly based on the processor core utilization as follows: .

[0077] in, This represents the final estimated power consumption (in watts, W) of the i-th processor core. This indicates the power consumption of the processor core when it is idle (without a task). This indicates the power consumption at full load (100% utilization). This indicates the utilization rate of the processor core (0-1). This indicates the additional power consumption required to increase the utilization rate from 0 to 1.

[0078] Among them, processor core utilization The calculation formula is: .

[0079] In the formula, WCET (Worst-Case Execution Time). The period is the cycle time. The overall goal is to reduce the total power consumption of all cores. This goal requires collecting thread time information and processor power models from the AADL model, mapping the thread runtime to the power model of the processor core to which the thread is bound, and thus obtaining a power consumption estimate. The linear model based on core utilization described above is just one method for calculating power consumption; there are also probabilistic models, thermally coupled models, DVFS (Dynamic Voltage and Frequency Scaling) CMOS, etc., which can be specified through AADL extended attributes. It should be noted that, in order to calculate the power consumption of processor cores, active / idle power models can be specified for the processor through extended custom attributes.

[0080] 2. Response Time (Lantency): This metric focuses on the latency of the end-to-end data flow (which can be determined based on the relationships between thread components). It requires collecting the sum of the response times of each task on all data paths in the system described by AADL to approximate the calculation. For a more accurate value, existing analysis tools (such as OSATE's stream latency analysis plugin) can be used to calculate the minimum latency.

[0081] 3. CPU Utilization Balance: This metric measures the degree of CPU load balancing. The utilization of each core can be calculated using the core utilization formula mentioned above. Then calculate the standard deviation between the maximum and minimum utilization rates. The balance objective is to minimize... ,in, This represents the maximum utilization rate of all cores in the system. This is the minimum utilization of all cores in the system. This balancing target can prevent some processor cores from being overloaded while others are idle.

[0082] The desired optimization objective in this application can be determined based on at least one of the above three factors. It is understood that other optimization metrics can be added in other application scenarios, and this application does not limit this.

[0083] In some embodiments, optimization can specifically be multi-objective optimization, that is, multi-objective optimization of the total power consumption of the processor cores, the response time of the end-to-end data flow of the system model, and the balance of processor utilization.

[0084] In the above embodiments, the impact of different thread binding schemes on the balance of total system power consumption, response time and CPU utilization can be systematically searched to obtain the optimal binding scheme.

[0085] Next, we will describe the specific optimization process in detail:

[0086] Specifically, when designing the system model, the attributes representing the binding relationship between each thread and the processor core (such as the Actual_Processor_Binding attribute) can be set as preset symbols (e.g., placeholders), and the range of available processor cores can be set through the Allowed_Processor_Binding attribute to limit the optimization. Thus, when the system analysis module 102 detects this preset symbol, it can perform thread binding optimization operations.

[0087] If the system analysis module 102 finds that the attribute value representing the binding relationship with the processor core is a preset symbol (e.g., a placeholder for the Actual_Processor_Binding attribute), it indicates that the attribute value of this attribute can be dynamically replaced for all threads in the abstract instantiation syntax tree. The system analysis module 102 can consider generating multiple binding schemes under binding constraints. These binding constraints refer to the range of processor cores that a thread can bind to, which can be specifically limited by the Allowed_Processor_Binding attribute. In some embodiments, the system analysis module 102 can enumerate all possible thread binding schemes based on the range of bindable processor cores to obtain multiple binding schemes. Each binding scheme defines the processor cores that each thread binds to.

[0088] The system analysis module 102 can construct optimization functions (such as multi-objective optimization functions) based on optimization metrics. The system analysis module 102 can traverse the abstract instantiation syntax tree to obtain thread-related information, such as the attributes of thread components (e.g., thread / process cycle time, WCET, Dispatch_Protocol, and related parameters) and the relationships between thread components (used to determine end-to-end flow). Based on the obtained thread-related information and the multi-objective optimization function, the system analysis module 102 can determine the target binding scheme from multiple binding schemes.

[0089] In some embodiments, the system analysis module 102 may specifically incorporate a multi-objective genetic algorithm to find the optimal / suboptimal mapping scheme in the solution space to optimize the desired objective. During the optimization search process, multiple binding schemes can be evaluated in parallel to accelerate the search process. For example, while meeting real-time requirements, the binding scheme with the lowest power consumption or the highest balance between processor utilization can be selected.

[0090] In other embodiments, for each binding scheme, the system analysis module can calculate the score corresponding to each optimization indicator under that binding scheme based on the aforementioned thread-related information. Then, it combines (e.g., weighted summation) the scores of multiple optimization indicators to obtain the comprehensive score of the binding scheme. Based on the comprehensive scores of each binding scheme, a target binding score can be selected, for example, choosing the binding scheme with the highest comprehensive score as the target binding scheme.

[0091] Furthermore, the attribute values ​​representing the binding relationship with the processor core in the abstract instantiation syntax tree can be updated based on the target binding scheme to obtain an updated abstract instantiation syntax tree. In addition, the scores of various optimization indicators corresponding to each binding scheme (such as the thread-to-processor core mapping, total power consumption, critical latency, and core utilization for each binding scheme) can be output in tabular form for secondary decision-making.

[0092] In the above embodiments, the binding relationship of threads can be automatically optimized based on the expected optimization goal, thereby improving the rationality and accuracy of the system design.

[0093] In addition to the aforementioned automatic optimization functions, this application also provides system analysis functions. In some embodiments, system analysis is performed based on an abstract instantiated syntax tree, including at least system resource budget analysis, to obtain analysis results, including: extracting thread-related information from the abstract instantiated syntax tree, performing system resource budget analysis based on the thread-related information, and obtaining the analysis results of the system analysis based at least on the results of the system resource budget analysis.

[0094] The thread-related information extracted from the abstract instantiation syntax tree can include the attribute information of each thread and the relationship between threads. Specifically, the thread attribute information can include: the thread's WCET (Worst-Case Execution Time), period time, stack, static data size, task priority, etc.

[0095] Specifically, the system analysis module 102 can perform system analysis based on information in the system model, such as system resource budget analysis. In some embodiments, the system analysis module 102 can also perform other analyses such as hardware / software relationship analysis and thread-processor core binding relationship analysis. In some embodiments, the system analysis module 102 can generate an analysis report based on the analysis results, and users can optimize the system based on the information in the analysis report.

[0096] In some embodiments, system resource budget analysis includes at least one of processor computing resource analysis, memory resource analysis, bus load analysis, and data flow latency analysis, wherein processor computing resource analysis includes single-core utilization analysis and worst-case time response analysis.

[0097] In some embodiments, the open-source AADL model analysis tool can also be used to analyze the model.

[0098] The following examples illustrate some aspects of system resource budget analysis:

[0099] For example, the current system has 3 threads, all bound to CPU core0, the system global communication cache is 32 KB, and the operating system / runtime overhead (estimated) is 16 KB. The extractable thread attribute information is as follows:

[0100]

[0101] The steps for performing processor computing resource analysis are as follows:

[0102] 1. Calculate single-core utilization:

[0103] Under the periodic task model, the total utilization rate U is: .

[0104] The calculation result is: U=0.95, and the total utilization rate is 0.95 (95%), which indicates that the current CPU load is very high, but it does not indicate whether the scheduling conditions can be met.

[0105] 2. Adopt a fixed priority (RMS, the shorter the period, the higher the priority) and use worst-case response time analysis (RTA):

[0106] The priority of the tasks corresponding to the threads is: T1>T2>T3.

[0107] RTA formula (for thread i):

[0108]

[0109] in, Let be the worst-case execution time of the task corresponding to thread i. This represents the worst-case execution time of the task corresponding to thread j. This represents the cycle time of the task corresponding to thread j. Let i be the set of all threads with a priority higher than thread i. This represents the response time corresponding to thread i. Within this, the maximum number of times a high-priority thread j can preempt (i.e., release) a task is calculated. This "rounding up" ensures that the worst-case scenario is considered.

[0110] Iterate until convergence or the timeout period is exceeded. Calculate T1: R1 = 20ms < 50ms; Calculate T2: R2 = 80ms < 100ms; Calculate T3: R3 = 190ms < 200ms.

[0111] Therefore, analysis shows that although the overall utilization of 0.95 exceeds the theoretical range limit of RMS (Liu-Layland bound ≈ 0.78 when there are three threads), the actual response time meets the deadline under this task combination and priority using precise RTA. Therefore, the system is still schedulable in the worst case on this single core (but with very little margin: CPU is almost saturated).

[0112] Perform memory resource analysis (RAM usage peak estimation):

[0113] Objective: Estimate the worst-case resident RAM required by the system to determine if 256 KB is sufficient.

[0114] 1. List memory usage by item (from property values ​​extracted from the abstract instantiation syntax tree).

[0115] For each thread / process, the following statistics should be collected:

[0116] Static data (static global / process-level data): .

[0117] Stack (independent stack for each thread): .

[0118] The dynamic heap that may be occupied during execution (the peak of heap allocation): .

[0119] Shared communication buffer (buffer allocated by producer / consumer): .

[0120] Operating system / runtime overhead: .

[0121] 2. Calculate the sum of all resources conservatively.

[0122] Conservative estimate (all threads exist simultaneously and occupy peak usage):

[0123]

[0124] Substituting the values, we can obtain .

[0125] Therefore, the analysis shows that the system requires approximately 126 KB under conservative estimates, which is less than the physical 256 KB, providing a safety margin.

[0126] In addition, it is understandable that other items can also be analyzed, such as bus load analysis and data flow delay analysis.

[0127] Bus load analysis is an analysis of bus load, which refers to the percentage of data actually transmitted on the bus within a specific time period relative to its theoretical maximum transmittable data capacity. It reflects the bus's busyness and bandwidth utilization. For example, the system analysis module 102 can also analyze bus load based on flow space (defined in the component, indicating the direction of data flow), end-to-end flow (defined in the relevant component implementation, describing a complete data path from the data source to the data endpoint), and the Actual_Connection_Binding attribute (which explicitly specifies which bus a port-to-port connection is physically bound to).

[0128] The analysis steps are as follows: 1. Locate all data streams flowing through the bus to be analyzed using flow specifications and end-to-end flow; 2. For each data stream, obtain the period value of its source and the data volume (data_volume) of the port, calculate the number of bits and transmission frequency of a single transmission of a single stream, and calculate the bandwidth occupied by a single transmission of the stream, that is, the load generated by a certain data stream on the bus = (total number of bits in the data frame / bus bandwidth) * transmission frequency; 3. Calculate the total bus load = (bandwidth of stream 1 + bandwidth of stream 2 + ... + bandwidth of stream n) / bus bandwidth.

[0129] Data stream latency can be obtained by accumulating the corresponding latency of each task on the end-to-end data stream (which can be determined based on the association between thread components). For details, please refer to the determination of response time in the aforementioned embodiments.

[0130] In the above embodiments, by performing at least a system resource budget analysis on the model system, it can be determined whether the system model meets the requirements and resource constraints; if the system model does not meet the requirements and resource constraints, the user can revise the model according to the requirements and resource constraints to improve the model quality.

[0131] In one specific embodiment, please refer to Figure 3 and Figure 4 The specific process of this model development method is as follows: A graphical description of the system model is constructed using standard graphical modules and custom graphical modules, where the custom graphical modules can be extended according to business scenarios. Then, a graphical parser parses the graphical description of the system model to obtain a model file (e.g., an AADL text description). Next, a model parser parses the model file to obtain an abstract instantiated syntax tree. The system analysis module can perform system analysis based on the abstract instantiated syntax tree to generate an analysis report, which indicates whether model modifications are needed. If no model modifications are needed, target code can be generated based on a code generator. It is understandable that different code generators can be designed for different second languages.

[0132] Further reference Figure 5 The solution of this application will now be described in detail in conjunction with specific application scenarios:

[0133] Step 1: Users can perform system modeling based on requirements and component models (such as radar perception system modeling) to obtain a graphical representation of the system model.

[0134] Step 2: Input the graphical representation of the system model into the graphical parser to generate the system model (e.g., an AADL text description).

[0135] Step 3: Input the system model into the model parser to generate the corresponding abstract instantiation syntax tree.

[0136] During the parsing process in steps 2 and 3, the system model will be checked. If the model itself has errors (such as violating modeling rules or being incomplete), it will cause the generation of the abstract instantiation syntax tree to fail and prompt an error. The user needs to revise the model according to the error message.

[0137] Step 4: After successfully generating the abstract instantiation syntax tree, system analysis is required based on requirements and resource constraints. Users can use the analysis report to determine whether the system model meets the requirements and resource constraints. If the system model does not meet the requirements and resource constraints, users can revise the model to improve its quality.

[0138] Step 5: Input the abstract instantiation syntax tree that meets the requirements and resource constraints into the code generator to generate code. If there are elements in the model file that do not support code generation, the code generation will fail and an error message will be displayed. The user needs to revise the model according to the error message and delete the elements that do not support code generation.

[0139] Step 6: Code generation successful.

[0140] This application allows for the customization of graphical component modules based on the scalability of the AADL modeling language, tailored to different application scenarios in embedded development. This enables modeling to meet user needs across various application scenarios. After customizing the graphical modules, logic supporting these modules needs to be added to the graphics parser, model parser, system analysis module, and code generator. This allows for improved system quality through simulation / model analysis in the early stages of system design, ultimately enhancing the quality of the generated code. In other words, this application can thoroughly analyze and verify system models for different application scenarios (e.g., memory resource analysis, bus load analysis, processor computing resource analysis, data flow latency analysis, etc.) before generating the corresponding code. This allows for the identification of resource constraint conflicts and system architecture anomalies in the early stages of system design, improving the efficiency of embedded development.

[0141] Furthermore, this application can systematically explore the impact of thread binding on system power consumption, response time, and load balancing, achieving multi-objective comprehensive optimization within the design space, thereby improving model quality. This invention can reduce repeated code modifications caused by early design flaws, thus reducing development workload and improving development efficiency.

[0142] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0143] Based on the same inventive concept, this application also provides a system development apparatus for implementing the system development method described above. The solution provided by this apparatus is similar to the solution described in the above method; therefore, the specific limitations in one or more system development apparatus embodiments provided below can be found in the limitations of the system development method described above, and will not be repeated here.

[0144] In one exemplary embodiment, such as Figure 1 As shown, a system development apparatus 100 is provided, including: a model parser 101, used to obtain a system model constructed based on a first language; the first language is a semi-formal modeling language; parsing the system model to obtain its corresponding abstract instantiation syntax tree; a system analysis module 102, used to perform system analysis based on the abstract instantiation syntax tree, including at least system resource budget analysis, and obtain analysis results; and a code generator 103, used to generate target code in a second language that matches the system model based on the abstract instantiation syntax tree, provided that the analysis results meet preset conditions; the second language is a programming language.

[0145] In some embodiments, the system analysis module 102 is specifically used to extract thread-related information from the abstract instantiated syntax tree, and perform system resource budget analysis based on the thread-related information, and at least obtain the analysis results of the system analysis based on the results of the system resource budget analysis.

[0146] In some embodiments, the system analysis module 102 is specifically used to perform at least one of processor computing resource analysis, memory resource analysis, bus load analysis, and data flow latency analysis, wherein processor computing resource analysis includes single-core utilization analysis and worst-case time response analysis.

[0147] In some embodiments, the system analysis module 102 is further configured to generate multiple binding schemes based on binding constraints if the attribute value of the binding relationship between the thread representation and the processor core is a preset symbol; the binding scheme indicates the binding relationship between the thread and the processor core; based on the desired optimization goal, select a target binding scheme from the multiple binding schemes; update the abstract instantiation syntax tree based on the target binding scheme; the updated abstract instantiation syntax tree is used to generate target code in the second language.

[0148] In some embodiments, the desired optimization objectives include at least one of the following: total power consumption of the processor cores, response time of the end-to-end data flow of the system model, and processor utilization balance.

[0149] In some embodiments, the system development apparatus 100 further includes a graph parser, which includes a graph parsing module and a model text generation module. The graph parser is used to obtain a graphical representation related to the system to be developed; to parse the graphical representation, the internal attributes of the components, and the relationships between the components to obtain modeling information of the system to be developed; and the model text generation module is used to generate a system model in a first language about the system to be developed based on the modeling information.

[0150] Each module in the aforementioned system development device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0151] In one exemplary embodiment, a computer device is provided on which a system development apparatus 100 is deployed. This computer device may be a server or a terminal, and its internal structure diagram may be as follows: Figure 6 As shown, this computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a system development methodology.

[0152] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0153] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0154] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0155] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0156] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0157] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0158] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0159] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A system development method, characterized in that, The method includes: Obtain a system model built based on a first language; the first language is a semi-formal modeling language; The system model is parsed to obtain its corresponding abstract instantiation syntax tree. Based on the abstract instantiation syntax tree, a system analysis is performed, including at least a system resource budget analysis, to obtain the analysis results. If the analysis results meet the preset conditions, target code in a second language that matches the system model is generated based on the abstract instantiated syntax tree; the second language is a programming language.

2. The method according to claim 1, characterized in that, The system analysis, based on the abstract instantiated syntax tree, includes at least system resource budget analysis, and the analysis results include: Thread-related information is extracted from the abstract instantiation syntax tree, and system resource budget analysis is performed based on the thread-related information. At least the system analysis results are obtained based on the results of the system resource budget analysis.

3. The method according to claim 1, characterized in that, The system resource budget analysis includes at least one of processor computing resource analysis, memory resource analysis, bus load analysis, and data flow latency analysis, wherein the processor computing resource analysis includes single-core utilization analysis and worst-case time response analysis.

4. The method according to claim 1, characterized in that, The method further includes: If the attribute value of the binding relationship between the thread representation and the processor core is a preset symbol, then multiple binding schemes are generated based on the binding constraints; the binding scheme indicates the binding relationship between the thread and the processor core. Based on the desired optimization objective, a target binding scheme is selected from the various binding schemes; The abstract instantiation syntax tree is updated based on the target binding scheme; the updated abstract instantiation syntax tree is used to generate the target code of the second language.

5. The method according to claim 4, characterized in that, The desired optimization objective includes at least one of the following: the total power consumption of the processor core, the response time of the end-to-end data flow of the system model, and the processor utilization balance.

6. The method according to any one of claims 1 to 5, characterized in that, The process of obtaining the system model built based on the first language includes: Obtain a graphical representation of the system to be developed; The graphical representation, the internal attributes of the components, and the relationships between the components are analyzed to obtain the modeling information of the system to be developed. Based on the modeling information, a system model in a first language is generated for the system to be developed.

7. A system development apparatus, characterized in that, The device includes: A model parser is used to obtain a system model built based on a first language; the first language is a semi-formal modeling language; the system model is parsed to obtain its corresponding abstract instantiation syntax tree; The system analysis module is used to perform system analysis based on the abstract instantiated syntax tree, including at least system resource budget analysis, and to obtain analysis results. A code generator is used to generate target code in a second language that matches the system model based on the abstract instantiated syntax tree, provided that the analysis results meet preset conditions; the second language is a programming language.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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